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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | d4e8164f | bellard | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | b346ff46 | bellard | #define DEBUG_DISAS
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23 | b346ff46 | bellard | |
24 | 33417e70 | bellard | #ifndef glue
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25 | 33417e70 | bellard | #define xglue(x, y) x ## y |
26 | 33417e70 | bellard | #define glue(x, y) xglue(x, y)
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27 | 33417e70 | bellard | #define stringify(s) tostring(s)
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28 | 33417e70 | bellard | #define tostring(s) #s |
29 | 33417e70 | bellard | #endif
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30 | 33417e70 | bellard | |
31 | 33417e70 | bellard | #if GCC_MAJOR < 3 |
32 | 33417e70 | bellard | #define __builtin_expect(x, n) (x)
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33 | 33417e70 | bellard | #endif
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34 | 33417e70 | bellard | |
35 | e2222c39 | bellard | #ifdef __i386__
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36 | e2222c39 | bellard | #define REGPARM(n) __attribute((regparm(n)))
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37 | e2222c39 | bellard | #else
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38 | e2222c39 | bellard | #define REGPARM(n)
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39 | e2222c39 | bellard | #endif
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40 | e2222c39 | bellard | |
41 | b346ff46 | bellard | /* is_jmp field values */
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42 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
43 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
44 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
45 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
46 | b346ff46 | bellard | |
47 | b346ff46 | bellard | struct TranslationBlock;
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48 | b346ff46 | bellard | |
49 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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50 | b346ff46 | bellard | #define MAX_OP_PER_INSTR 32 |
51 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
52 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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53 | b346ff46 | bellard | |
54 | b346ff46 | bellard | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
55 | b346ff46 | bellard | |
56 | b346ff46 | bellard | extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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57 | b346ff46 | bellard | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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58 | c27004ec | bellard | extern long gen_labels[OPC_BUF_SIZE]; |
59 | c27004ec | bellard | extern int nb_gen_labels; |
60 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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61 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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62 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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63 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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64 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
65 | b346ff46 | bellard | |
66 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
67 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
68 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
69 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
70 | 9886cc16 | bellard | |
71 | b346ff46 | bellard | #if defined(TARGET_I386)
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72 | b346ff46 | bellard | |
73 | 33417e70 | bellard | void optimize_flags_init(void); |
74 | d4e8164f | bellard | |
75 | b346ff46 | bellard | #endif
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76 | b346ff46 | bellard | |
77 | b346ff46 | bellard | extern FILE *logfile;
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78 | b346ff46 | bellard | extern int loglevel; |
79 | b346ff46 | bellard | |
80 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
81 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
82 | b346ff46 | bellard | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
83 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
84 | b346ff46 | bellard | int max_code_size, int *gen_code_size_ptr); |
85 | 66e85a21 | bellard | int cpu_restore_state(struct TranslationBlock *tb, |
86 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
87 | 58fe2f10 | bellard | void *puc);
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88 | 58fe2f10 | bellard | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
89 | 58fe2f10 | bellard | int max_code_size, int *gen_code_size_ptr); |
90 | 58fe2f10 | bellard | int cpu_restore_state_copy(struct TranslationBlock *tb, |
91 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
92 | 58fe2f10 | bellard | void *puc);
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93 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
94 | b346ff46 | bellard | void cpu_exec_init(void); |
95 | 2e12669a | bellard | int page_unprotect(unsigned long address, unsigned long pc, void *puc); |
96 | 2e12669a | bellard | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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97 | 2e12669a | bellard | int is_cpu_write_access);
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98 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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99 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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100 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
101 | 2e12669a | bellard | int tlb_set_page(CPUState *env, target_ulong vaddr,
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102 | 2e12669a | bellard | target_phys_addr_t paddr, int prot,
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103 | 4390df51 | bellard | int is_user, int is_softmmu); |
104 | d4e8164f | bellard | |
105 | d4e8164f | bellard | #define CODE_GEN_MAX_SIZE 65536 |
106 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
107 | d4e8164f | bellard | |
108 | d4e8164f | bellard | #define CODE_GEN_HASH_BITS 15 |
109 | d4e8164f | bellard | #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) |
110 | d4e8164f | bellard | |
111 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
112 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
113 | 4390df51 | bellard | |
114 | d4e8164f | bellard | /* maximum total translate dcode allocated */
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115 | 4390df51 | bellard | |
116 | 4390df51 | bellard | /* NOTE: the translated code area cannot be too big because on some
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117 | c4c7e3e6 | bellard | archs the range of "fast" function calls is limited. Here is a
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118 | 4390df51 | bellard | summary of the ranges:
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119 | 4390df51 | bellard | |
120 | 4390df51 | bellard | i386 : signed 32 bits
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121 | 4390df51 | bellard | arm : signed 26 bits
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122 | 4390df51 | bellard | ppc : signed 24 bits
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123 | 4390df51 | bellard | sparc : signed 32 bits
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124 | 4390df51 | bellard | alpha : signed 23 bits
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125 | 4390df51 | bellard | */
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126 | 4390df51 | bellard | |
127 | 4390df51 | bellard | #if defined(__alpha__)
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128 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
129 | b8076a74 | bellard | #elif defined(__ia64)
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130 | b8076a74 | bellard | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ |
131 | 4390df51 | bellard | #elif defined(__powerpc__)
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132 | c4c7e3e6 | bellard | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
133 | 4390df51 | bellard | #else
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134 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (8 * 1024 * 1024) |
135 | 4390df51 | bellard | #endif
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136 | 4390df51 | bellard | |
137 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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138 | d4e8164f | bellard | |
139 | 4390df51 | bellard | /* estimated block size for TB allocation */
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140 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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141 | 4390df51 | bellard | according to the host CPU */
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142 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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143 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
144 | 4390df51 | bellard | #else
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145 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
146 | 4390df51 | bellard | #endif
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147 | 4390df51 | bellard | |
148 | 4390df51 | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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149 | 4390df51 | bellard | |
150 | 4390df51 | bellard | #if defined(__powerpc__)
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151 | 4390df51 | bellard | #define USE_DIRECT_JUMP
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152 | 4390df51 | bellard | #endif
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153 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
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154 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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155 | d4e8164f | bellard | #endif
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156 | d4e8164f | bellard | |
157 | d4e8164f | bellard | typedef struct TranslationBlock { |
158 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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159 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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160 | d4e8164f | bellard | unsigned int flags; /* flags defining in which context the code was generated */ |
161 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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162 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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163 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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164 | bf088061 | bellard | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
165 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
166 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
167 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
168 | 58fe2f10 | bellard | |
169 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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170 | 4390df51 | bellard | struct TranslationBlock *hash_next; /* next matching tb for virtual address */ |
171 | 4390df51 | bellard | /* next matching tb for physical address. */
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172 | 4390df51 | bellard | struct TranslationBlock *phys_hash_next;
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173 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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174 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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175 | 4390df51 | bellard | struct TranslationBlock *page_next[2]; |
176 | 4390df51 | bellard | target_ulong page_addr[2];
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177 | 4390df51 | bellard | |
178 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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179 | d4e8164f | bellard | the code of this one. */
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180 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
181 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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182 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
183 | d4e8164f | bellard | #else
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184 | 95f7652d | bellard | uint32_t tb_next[2]; /* address of jump generated code */ |
185 | d4e8164f | bellard | #endif
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186 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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187 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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188 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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189 | d4e8164f | bellard | jmp_first */
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190 | d4e8164f | bellard | struct TranslationBlock *jmp_next[2]; |
191 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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192 | d4e8164f | bellard | } TranslationBlock; |
193 | d4e8164f | bellard | |
194 | c27004ec | bellard | static inline unsigned int tb_hash_func(target_ulong pc) |
195 | d4e8164f | bellard | { |
196 | d4e8164f | bellard | return pc & (CODE_GEN_HASH_SIZE - 1); |
197 | d4e8164f | bellard | } |
198 | d4e8164f | bellard | |
199 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
200 | 4390df51 | bellard | { |
201 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
202 | 4390df51 | bellard | } |
203 | 4390df51 | bellard | |
204 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
205 | 0124311e | bellard | void tb_flush(CPUState *env);
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206 | d4e8164f | bellard | void tb_link(TranslationBlock *tb);
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207 | 4390df51 | bellard | void tb_link_phys(TranslationBlock *tb,
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208 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
209 | d4e8164f | bellard | |
210 | d4e8164f | bellard | extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
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211 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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212 | d4e8164f | bellard | |
213 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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214 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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215 | d4e8164f | bellard | |
216 | d4e8164f | bellard | /* find a translation block in the translation cache. If not found,
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217 | d4e8164f | bellard | return NULL and the pointer to the last element of the list in pptb */
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218 | d4e8164f | bellard | static inline TranslationBlock *tb_find(TranslationBlock ***pptb, |
219 | 2e12669a | bellard | target_ulong pc, |
220 | 2e12669a | bellard | target_ulong cs_base, |
221 | d4e8164f | bellard | unsigned int flags) |
222 | d4e8164f | bellard | { |
223 | d4e8164f | bellard | TranslationBlock **ptb, *tb; |
224 | d4e8164f | bellard | unsigned int h; |
225 | d4e8164f | bellard | |
226 | d4e8164f | bellard | h = tb_hash_func(pc); |
227 | d4e8164f | bellard | ptb = &tb_hash[h]; |
228 | d4e8164f | bellard | for(;;) {
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229 | d4e8164f | bellard | tb = *ptb; |
230 | d4e8164f | bellard | if (!tb)
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231 | d4e8164f | bellard | break;
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232 | d4e8164f | bellard | if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
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233 | d4e8164f | bellard | return tb;
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234 | d4e8164f | bellard | ptb = &tb->hash_next; |
235 | d4e8164f | bellard | } |
236 | d4e8164f | bellard | *pptb = ptb; |
237 | d4e8164f | bellard | return NULL; |
238 | d4e8164f | bellard | } |
239 | d4e8164f | bellard | |
240 | d4e8164f | bellard | |
241 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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242 | 4390df51 | bellard | |
243 | 4390df51 | bellard | #if defined(__powerpc__)
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244 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
245 | d4e8164f | bellard | { |
246 | d4e8164f | bellard | uint32_t val, *ptr; |
247 | d4e8164f | bellard | |
248 | d4e8164f | bellard | /* patch the branch destination */
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249 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
250 | d4e8164f | bellard | val = *ptr; |
251 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
252 | d4e8164f | bellard | *ptr = val; |
253 | d4e8164f | bellard | /* flush icache */
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254 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
255 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
256 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
257 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
258 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
259 | d4e8164f | bellard | } |
260 | 4390df51 | bellard | #elif defined(__i386__)
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261 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
262 | 4390df51 | bellard | { |
263 | 4390df51 | bellard | /* patch the branch destination */
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264 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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265 | 4390df51 | bellard | /* no need to flush icache explicitely */
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266 | 4390df51 | bellard | } |
267 | 4390df51 | bellard | #endif
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268 | d4e8164f | bellard | |
269 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
270 | 4cbb86e1 | bellard | int n, unsigned long addr) |
271 | 4cbb86e1 | bellard | { |
272 | 4cbb86e1 | bellard | unsigned long offset; |
273 | 4cbb86e1 | bellard | |
274 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
275 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
276 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
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277 | 4cbb86e1 | bellard | if (offset != 0xffff) |
278 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
279 | 4cbb86e1 | bellard | } |
280 | 4cbb86e1 | bellard | |
281 | d4e8164f | bellard | #else
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282 | d4e8164f | bellard | |
283 | d4e8164f | bellard | /* set the jump target */
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284 | d4e8164f | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
285 | d4e8164f | bellard | int n, unsigned long addr) |
286 | d4e8164f | bellard | { |
287 | 95f7652d | bellard | tb->tb_next[n] = addr; |
288 | d4e8164f | bellard | } |
289 | d4e8164f | bellard | |
290 | d4e8164f | bellard | #endif
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291 | d4e8164f | bellard | |
292 | d4e8164f | bellard | static inline void tb_add_jump(TranslationBlock *tb, int n, |
293 | d4e8164f | bellard | TranslationBlock *tb_next) |
294 | d4e8164f | bellard | { |
295 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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296 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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297 | cf25629d | bellard | /* patch the native jump address */
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298 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
299 | cf25629d | bellard | |
300 | cf25629d | bellard | /* add in TB jmp circular list */
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301 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
302 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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303 | cf25629d | bellard | } |
304 | d4e8164f | bellard | } |
305 | d4e8164f | bellard | |
306 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
307 | a513fe19 | bellard | |
308 | d4e8164f | bellard | #ifndef offsetof
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309 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
310 | d4e8164f | bellard | #endif
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311 | d4e8164f | bellard | |
312 | d549f7d9 | bellard | #if defined(_WIN32)
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313 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
314 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
315 | d549f7d9 | bellard | #elif defined(__APPLE__)
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316 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
317 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
318 | d549f7d9 | bellard | #else
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319 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
320 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
321 | d549f7d9 | bellard | #endif
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322 | d549f7d9 | bellard | |
323 | b346ff46 | bellard | #if defined(__powerpc__)
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324 | b346ff46 | bellard | |
325 | 4390df51 | bellard | /* we patch the jump instruction directly */
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326 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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327 | b346ff46 | bellard | do {\
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328 | d549f7d9 | bellard | asm volatile (ASM_DATA_SECTION\ |
329 | d549f7d9 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\ |
330 | 9257a9e4 | bellard | ".long 1f\n"\
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331 | d549f7d9 | bellard | ASM_PREVIOUS_SECTION \ |
332 | d549f7d9 | bellard | "b " ASM_NAME(__op_jmp) #n "\n"\ |
333 | 9257a9e4 | bellard | "1:\n");\
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334 | 4390df51 | bellard | } while (0) |
335 | 4390df51 | bellard | |
336 | 4390df51 | bellard | #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
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337 | 4390df51 | bellard | |
338 | 4390df51 | bellard | /* we patch the jump instruction directly */
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339 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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340 | c27004ec | bellard | do {\
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341 | c27004ec | bellard | asm volatile (".section .data\n"\ |
342 | c27004ec | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\ |
343 | c27004ec | bellard | ".long 1f\n"\
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344 | c27004ec | bellard | ASM_PREVIOUS_SECTION \ |
345 | c27004ec | bellard | "jmp " ASM_NAME(__op_jmp) #n "\n"\ |
346 | c27004ec | bellard | "1:\n");\
|
347 | c27004ec | bellard | } while (0) |
348 | c27004ec | bellard | |
349 | b346ff46 | bellard | #else
|
350 | b346ff46 | bellard | |
351 | b346ff46 | bellard | /* jump to next block operations (more portable code, does not need
|
352 | b346ff46 | bellard | cache flushing, but slower because of indirect jump) */
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353 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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354 | b346ff46 | bellard | do {\
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355 | 2f62b397 | bellard | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ |
356 | ae063a68 | bellard | static void __attribute__((unused)) *__op_label ## n = &&label ## n;\ |
357 | b346ff46 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
358 | ae063a68 | bellard | label ## n: ;\ |
359 | ae063a68 | bellard | dummy_label ## n: ;\ |
360 | b346ff46 | bellard | } while (0) |
361 | b346ff46 | bellard | |
362 | ae063a68 | bellard | #endif
|
363 | ae063a68 | bellard | |
364 | ae063a68 | bellard | /* XXX: will be suppressed */
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365 | ae063a68 | bellard | #define JUMP_TB(opname, tbparam, n, eip)\
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366 | 4cbb86e1 | bellard | do {\
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367 | ae063a68 | bellard | GOTO_TB(opname, tbparam, n);\ |
368 | ae063a68 | bellard | T0 = (long)(tbparam) + (n);\
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369 | ae063a68 | bellard | EIP = (int32_t)eip;\ |
370 | ae063a68 | bellard | EXIT_TB();\ |
371 | 4cbb86e1 | bellard | } while (0) |
372 | 4cbb86e1 | bellard | |
373 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
374 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
375 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
376 | 33417e70 | bellard | |
377 | d4e8164f | bellard | #ifdef __powerpc__
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378 | d4e8164f | bellard | static inline int testandset (int *p) |
379 | d4e8164f | bellard | { |
380 | d4e8164f | bellard | int ret;
|
381 | d4e8164f | bellard | __asm__ __volatile__ ( |
382 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
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383 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
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384 | 02e1ec9b | bellard | " bne 1f\n"
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385 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
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386 | 02e1ec9b | bellard | " bne- 0b\n"
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387 | d4e8164f | bellard | "1: "
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388 | d4e8164f | bellard | : "=&r" (ret)
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389 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
390 | d4e8164f | bellard | : "cr0", "memory"); |
391 | d4e8164f | bellard | return ret;
|
392 | d4e8164f | bellard | } |
393 | d4e8164f | bellard | #endif
|
394 | d4e8164f | bellard | |
395 | d4e8164f | bellard | #ifdef __i386__
|
396 | d4e8164f | bellard | static inline int testandset (int *p) |
397 | d4e8164f | bellard | { |
398 | 4955a2cd | bellard | long int readval = 0; |
399 | d4e8164f | bellard | |
400 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
|
401 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
402 | 4955a2cd | bellard | : "r" (1) |
403 | 4955a2cd | bellard | : "cc");
|
404 | 4955a2cd | bellard | return readval;
|
405 | d4e8164f | bellard | } |
406 | d4e8164f | bellard | #endif
|
407 | d4e8164f | bellard | |
408 | bc51c5c9 | bellard | #ifdef __x86_64__
|
409 | bc51c5c9 | bellard | static inline int testandset (int *p) |
410 | bc51c5c9 | bellard | { |
411 | 4955a2cd | bellard | long int readval = 0; |
412 | bc51c5c9 | bellard | |
413 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
|
414 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
415 | 4955a2cd | bellard | : "r" (1) |
416 | 4955a2cd | bellard | : "cc");
|
417 | 4955a2cd | bellard | return readval;
|
418 | bc51c5c9 | bellard | } |
419 | bc51c5c9 | bellard | #endif
|
420 | bc51c5c9 | bellard | |
421 | d4e8164f | bellard | #ifdef __s390__
|
422 | d4e8164f | bellard | static inline int testandset (int *p) |
423 | d4e8164f | bellard | { |
424 | d4e8164f | bellard | int ret;
|
425 | d4e8164f | bellard | |
426 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
|
427 | d4e8164f | bellard | " jl 0b"
|
428 | d4e8164f | bellard | : "=&d" (ret)
|
429 | d4e8164f | bellard | : "r" (1), "a" (p), "0" (*p) |
430 | d4e8164f | bellard | : "cc", "memory" ); |
431 | d4e8164f | bellard | return ret;
|
432 | d4e8164f | bellard | } |
433 | d4e8164f | bellard | #endif
|
434 | d4e8164f | bellard | |
435 | d4e8164f | bellard | #ifdef __alpha__
|
436 | 2f87c607 | bellard | static inline int testandset (int *p) |
437 | d4e8164f | bellard | { |
438 | d4e8164f | bellard | int ret;
|
439 | d4e8164f | bellard | unsigned long one; |
440 | d4e8164f | bellard | |
441 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
|
442 | d4e8164f | bellard | " ldl_l %0,%1\n"
|
443 | d4e8164f | bellard | " stl_c %2,%1\n"
|
444 | d4e8164f | bellard | " beq %2,1f\n"
|
445 | d4e8164f | bellard | ".subsection 2\n"
|
446 | d4e8164f | bellard | "1: br 0b\n"
|
447 | d4e8164f | bellard | ".previous"
|
448 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
449 | d4e8164f | bellard | : "m" (*p));
|
450 | d4e8164f | bellard | return ret;
|
451 | d4e8164f | bellard | } |
452 | d4e8164f | bellard | #endif
|
453 | d4e8164f | bellard | |
454 | d4e8164f | bellard | #ifdef __sparc__
|
455 | d4e8164f | bellard | static inline int testandset (int *p) |
456 | d4e8164f | bellard | { |
457 | d4e8164f | bellard | int ret;
|
458 | d4e8164f | bellard | |
459 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
|
460 | d4e8164f | bellard | : "=r" (ret)
|
461 | d4e8164f | bellard | : "r" (p)
|
462 | d4e8164f | bellard | : "memory");
|
463 | d4e8164f | bellard | |
464 | d4e8164f | bellard | return (ret ? 1 : 0); |
465 | d4e8164f | bellard | } |
466 | d4e8164f | bellard | #endif
|
467 | d4e8164f | bellard | |
468 | a95c6790 | bellard | #ifdef __arm__
|
469 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
470 | a95c6790 | bellard | { |
471 | a95c6790 | bellard | register unsigned int ret; |
472 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
|
473 | a95c6790 | bellard | : "=r"(ret)
|
474 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
475 | a95c6790 | bellard | |
476 | a95c6790 | bellard | return ret;
|
477 | a95c6790 | bellard | } |
478 | a95c6790 | bellard | #endif
|
479 | a95c6790 | bellard | |
480 | 38e584a0 | bellard | #ifdef __mc68000
|
481 | 38e584a0 | bellard | static inline int testandset (int *p) |
482 | 38e584a0 | bellard | { |
483 | 38e584a0 | bellard | char ret;
|
484 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
|
485 | 38e584a0 | bellard | : "=r" (ret)
|
486 | 38e584a0 | bellard | : "m" (p)
|
487 | 38e584a0 | bellard | : "cc","memory"); |
488 | 4955a2cd | bellard | return ret;
|
489 | 38e584a0 | bellard | } |
490 | 38e584a0 | bellard | #endif
|
491 | 38e584a0 | bellard | |
492 | b8076a74 | bellard | #ifdef __ia64
|
493 | b8076a74 | bellard | #include <ia64intrin.h> |
494 | b8076a74 | bellard | |
495 | b8076a74 | bellard | static inline int testandset (int *p) |
496 | b8076a74 | bellard | { |
497 | b8076a74 | bellard | return __sync_lock_test_and_set (p, 1); |
498 | b8076a74 | bellard | } |
499 | b8076a74 | bellard | #endif
|
500 | b8076a74 | bellard | |
501 | d4e8164f | bellard | typedef int spinlock_t; |
502 | d4e8164f | bellard | |
503 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
504 | d4e8164f | bellard | |
505 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
|
506 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
507 | d4e8164f | bellard | { |
508 | d4e8164f | bellard | while (testandset(lock));
|
509 | d4e8164f | bellard | } |
510 | d4e8164f | bellard | |
511 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
512 | d4e8164f | bellard | { |
513 | d4e8164f | bellard | *lock = 0;
|
514 | d4e8164f | bellard | } |
515 | d4e8164f | bellard | |
516 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
517 | d4e8164f | bellard | { |
518 | d4e8164f | bellard | return !testandset(lock);
|
519 | d4e8164f | bellard | } |
520 | 3c1cf9fa | bellard | #else
|
521 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
522 | 3c1cf9fa | bellard | { |
523 | 3c1cf9fa | bellard | } |
524 | 3c1cf9fa | bellard | |
525 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
526 | 3c1cf9fa | bellard | { |
527 | 3c1cf9fa | bellard | } |
528 | 3c1cf9fa | bellard | |
529 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
530 | 3c1cf9fa | bellard | { |
531 | 3c1cf9fa | bellard | return 1; |
532 | 3c1cf9fa | bellard | } |
533 | 3c1cf9fa | bellard | #endif
|
534 | d4e8164f | bellard | |
535 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
536 | d4e8164f | bellard | |
537 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
538 | 6e59c1db | bellard | |
539 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
540 | 6e59c1db | bellard | |
541 | c27004ec | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, |
542 | 6e59c1db | bellard | void *retaddr);
|
543 | 6e59c1db | bellard | |
544 | 6e59c1db | bellard | #define ACCESS_TYPE 3 |
545 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
546 | 6e59c1db | bellard | #define env cpu_single_env
|
547 | 6e59c1db | bellard | |
548 | 6e59c1db | bellard | #define DATA_SIZE 1 |
549 | 6e59c1db | bellard | #include "softmmu_header.h" |
550 | 6e59c1db | bellard | |
551 | 6e59c1db | bellard | #define DATA_SIZE 2 |
552 | 6e59c1db | bellard | #include "softmmu_header.h" |
553 | 6e59c1db | bellard | |
554 | 6e59c1db | bellard | #define DATA_SIZE 4 |
555 | 6e59c1db | bellard | #include "softmmu_header.h" |
556 | 6e59c1db | bellard | |
557 | c27004ec | bellard | #define DATA_SIZE 8 |
558 | c27004ec | bellard | #include "softmmu_header.h" |
559 | c27004ec | bellard | |
560 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
561 | 6e59c1db | bellard | #undef MEMSUFFIX
|
562 | 6e59c1db | bellard | #undef env
|
563 | 6e59c1db | bellard | |
564 | 6e59c1db | bellard | #endif
|
565 | 4390df51 | bellard | |
566 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
567 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
568 | 4390df51 | bellard | { |
569 | 4390df51 | bellard | return addr;
|
570 | 4390df51 | bellard | } |
571 | 4390df51 | bellard | #else
|
572 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
573 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
574 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
575 | 4390df51 | bellard | /* XXX: i386 target specific */
|
576 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
577 | 4390df51 | bellard | { |
578 | c27004ec | bellard | int is_user, index, pd;
|
579 | 4390df51 | bellard | |
580 | 4390df51 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
581 | 3f5dcc34 | bellard | #if defined(TARGET_I386)
|
582 | 4390df51 | bellard | is_user = ((env->hflags & HF_CPL_MASK) == 3);
|
583 | 3f5dcc34 | bellard | #elif defined (TARGET_PPC)
|
584 | 3f5dcc34 | bellard | is_user = msr_pr; |
585 | e95c8d51 | bellard | #elif defined (TARGET_SPARC)
|
586 | e95c8d51 | bellard | is_user = (env->psrs == 0);
|
587 | 3f5dcc34 | bellard | #else
|
588 | 3f5dcc34 | bellard | #error "Unimplemented !" |
589 | 3f5dcc34 | bellard | #endif
|
590 | 4390df51 | bellard | if (__builtin_expect(env->tlb_read[is_user][index].address !=
|
591 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
592 | c27004ec | bellard | ldub_code(addr); |
593 | c27004ec | bellard | } |
594 | c27004ec | bellard | pd = env->tlb_read[is_user][index].address & ~TARGET_PAGE_MASK; |
595 | c27004ec | bellard | if (pd > IO_MEM_ROM) {
|
596 | c27004ec | bellard | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
|
597 | 4390df51 | bellard | } |
598 | 4390df51 | bellard | return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base; |
599 | 4390df51 | bellard | } |
600 | 4390df51 | bellard | #endif
|
601 | 9df217a3 | bellard | |
602 | 9df217a3 | bellard | |
603 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
604 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
|
605 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
|
606 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
607 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
608 | 9df217a3 | bellard | |
609 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
610 | 9df217a3 | bellard | { |
611 | 9df217a3 | bellard | return(env->kqemu_enabled &&
|
612 | 9df217a3 | bellard | (env->hflags & HF_CPL_MASK) == 3 &&
|
613 | 9df217a3 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK && |
614 | 9df217a3 | bellard | (env->cr[0] & CR0_PE_MASK) &&
|
615 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
616 | 9df217a3 | bellard | !(env->eflags & VM_MASK)); |
617 | 9df217a3 | bellard | } |
618 | 9df217a3 | bellard | |
619 | 9df217a3 | bellard | #endif |