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1 | 80cabfad | bellard | /*
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2 | 80cabfad | bellard | * QEMU 8259 interrupt controller emulation
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3 | 80cabfad | bellard | *
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4 | 80cabfad | bellard | * Copyright (c) 2003-2004 Fabrice Bellard
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5 | 80cabfad | bellard | *
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6 | 80cabfad | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 80cabfad | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 80cabfad | bellard | * in the Software without restriction, including without limitation the rights
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9 | 80cabfad | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 80cabfad | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 80cabfad | bellard | * furnished to do so, subject to the following conditions:
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12 | 80cabfad | bellard | *
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13 | 80cabfad | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 80cabfad | bellard | * all copies or substantial portions of the Software.
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15 | 80cabfad | bellard | *
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16 | 80cabfad | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 80cabfad | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 80cabfad | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 80cabfad | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 80cabfad | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 80cabfad | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 80cabfad | bellard | * THE SOFTWARE.
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23 | 80cabfad | bellard | */
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24 | 80cabfad | bellard | #include "vl.h" |
25 | 80cabfad | bellard | |
26 | 80cabfad | bellard | /* debug PIC */
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27 | 80cabfad | bellard | //#define DEBUG_PIC
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28 | 80cabfad | bellard | |
29 | b41a2cd1 | bellard | //#define DEBUG_IRQ_LATENCY
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30 | 4a0fb71e | bellard | //#define DEBUG_IRQ_COUNT
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31 | b41a2cd1 | bellard | |
32 | 80cabfad | bellard | typedef struct PicState { |
33 | 80cabfad | bellard | uint8_t last_irr; /* edge detection */
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34 | 80cabfad | bellard | uint8_t irr; /* interrupt request register */
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35 | 80cabfad | bellard | uint8_t imr; /* interrupt mask register */
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36 | 80cabfad | bellard | uint8_t isr; /* interrupt service register */
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37 | 80cabfad | bellard | uint8_t priority_add; /* highest irq priority */
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38 | 80cabfad | bellard | uint8_t irq_base; |
39 | 80cabfad | bellard | uint8_t read_reg_select; |
40 | 80cabfad | bellard | uint8_t poll; |
41 | 80cabfad | bellard | uint8_t special_mask; |
42 | 80cabfad | bellard | uint8_t init_state; |
43 | 80cabfad | bellard | uint8_t auto_eoi; |
44 | 80cabfad | bellard | uint8_t rotate_on_auto_eoi; |
45 | 80cabfad | bellard | uint8_t special_fully_nested_mode; |
46 | 80cabfad | bellard | uint8_t init4; /* true if 4 byte init */
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47 | 660de336 | bellard | uint8_t elcr; /* PIIX edge/trigger selection*/
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48 | 660de336 | bellard | uint8_t elcr_mask; |
49 | 80cabfad | bellard | } PicState; |
50 | 80cabfad | bellard | |
51 | 80cabfad | bellard | /* 0 is master pic, 1 is slave pic */
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52 | ba91cd80 | bellard | static PicState pics[2]; |
53 | 80cabfad | bellard | |
54 | 4a0fb71e | bellard | #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
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55 | 4a0fb71e | bellard | static int irq_level[16]; |
56 | 4a0fb71e | bellard | #endif
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57 | 4a0fb71e | bellard | #ifdef DEBUG_IRQ_COUNT
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58 | 4a0fb71e | bellard | static uint64_t irq_count[16]; |
59 | 4a0fb71e | bellard | #endif
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60 | 4a0fb71e | bellard | |
61 | 80cabfad | bellard | /* set irq level. If an edge is detected, then the IRR is set to 1 */
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62 | 80cabfad | bellard | static inline void pic_set_irq1(PicState *s, int irq, int level) |
63 | 80cabfad | bellard | { |
64 | 80cabfad | bellard | int mask;
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65 | 80cabfad | bellard | mask = 1 << irq;
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66 | 660de336 | bellard | if (s->elcr & mask) {
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67 | 660de336 | bellard | /* level triggered */
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68 | 660de336 | bellard | if (level) {
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69 | 80cabfad | bellard | s->irr |= mask; |
70 | 660de336 | bellard | s->last_irr |= mask; |
71 | 660de336 | bellard | } else {
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72 | 660de336 | bellard | s->irr &= ~mask; |
73 | 660de336 | bellard | s->last_irr &= ~mask; |
74 | 660de336 | bellard | } |
75 | 80cabfad | bellard | } else {
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76 | 660de336 | bellard | /* edge triggered */
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77 | 660de336 | bellard | if (level) {
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78 | 660de336 | bellard | if ((s->last_irr & mask) == 0) |
79 | 660de336 | bellard | s->irr |= mask; |
80 | 660de336 | bellard | s->last_irr |= mask; |
81 | 660de336 | bellard | } else {
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82 | 660de336 | bellard | s->last_irr &= ~mask; |
83 | 660de336 | bellard | } |
84 | 80cabfad | bellard | } |
85 | 80cabfad | bellard | } |
86 | 80cabfad | bellard | |
87 | 80cabfad | bellard | /* return the highest priority found in mask (highest = smallest
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88 | 80cabfad | bellard | number). Return 8 if no irq */
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89 | 80cabfad | bellard | static inline int get_priority(PicState *s, int mask) |
90 | 80cabfad | bellard | { |
91 | 80cabfad | bellard | int priority;
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92 | 80cabfad | bellard | if (mask == 0) |
93 | 80cabfad | bellard | return 8; |
94 | 80cabfad | bellard | priority = 0;
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95 | 80cabfad | bellard | while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) |
96 | 80cabfad | bellard | priority++; |
97 | 80cabfad | bellard | return priority;
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98 | 80cabfad | bellard | } |
99 | 80cabfad | bellard | |
100 | 80cabfad | bellard | /* return the pic wanted interrupt. return -1 if none */
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101 | 80cabfad | bellard | static int pic_get_irq(PicState *s) |
102 | 80cabfad | bellard | { |
103 | 80cabfad | bellard | int mask, cur_priority, priority;
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104 | 80cabfad | bellard | |
105 | 80cabfad | bellard | mask = s->irr & ~s->imr; |
106 | 80cabfad | bellard | priority = get_priority(s, mask); |
107 | 80cabfad | bellard | if (priority == 8) |
108 | 80cabfad | bellard | return -1; |
109 | 80cabfad | bellard | /* compute current priority. If special fully nested mode on the
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110 | 80cabfad | bellard | master, the IRQ coming from the slave is not taken into account
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111 | 80cabfad | bellard | for the priority computation. */
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112 | 80cabfad | bellard | mask = s->isr; |
113 | 80cabfad | bellard | if (s->special_fully_nested_mode && s == &pics[0]) |
114 | 80cabfad | bellard | mask &= ~(1 << 2); |
115 | 80cabfad | bellard | cur_priority = get_priority(s, mask); |
116 | 80cabfad | bellard | if (priority < cur_priority) {
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117 | 80cabfad | bellard | /* higher priority found: an irq should be generated */
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118 | 80cabfad | bellard | return (priority + s->priority_add) & 7; |
119 | 80cabfad | bellard | } else {
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120 | 80cabfad | bellard | return -1; |
121 | 80cabfad | bellard | } |
122 | 80cabfad | bellard | } |
123 | 80cabfad | bellard | |
124 | 80cabfad | bellard | /* raise irq to CPU if necessary. must be called every time the active
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125 | 80cabfad | bellard | irq may change */
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126 | b0a21b53 | bellard | static void pic_update_irq(void) |
127 | 80cabfad | bellard | { |
128 | 80cabfad | bellard | int irq2, irq;
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129 | 80cabfad | bellard | |
130 | 80cabfad | bellard | /* first look at slave pic */
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131 | 80cabfad | bellard | irq2 = pic_get_irq(&pics[1]);
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132 | 80cabfad | bellard | if (irq2 >= 0) { |
133 | 80cabfad | bellard | /* if irq request by slave pic, signal master PIC */
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134 | 80cabfad | bellard | pic_set_irq1(&pics[0], 2, 1); |
135 | 80cabfad | bellard | pic_set_irq1(&pics[0], 2, 0); |
136 | 80cabfad | bellard | } |
137 | 80cabfad | bellard | /* look at requested irq */
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138 | 80cabfad | bellard | irq = pic_get_irq(&pics[0]);
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139 | 80cabfad | bellard | if (irq >= 0) { |
140 | 80cabfad | bellard | #if defined(DEBUG_PIC)
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141 | 80cabfad | bellard | { |
142 | 80cabfad | bellard | int i;
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143 | 80cabfad | bellard | for(i = 0; i < 2; i++) { |
144 | 80cabfad | bellard | printf("pic%d: imr=%x irr=%x padd=%d\n",
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145 | 80cabfad | bellard | i, pics[i].imr, pics[i].irr, pics[i].priority_add); |
146 | 80cabfad | bellard | |
147 | 80cabfad | bellard | } |
148 | 80cabfad | bellard | } |
149 | 2444ca41 | bellard | printf("pic: cpu_interrupt\n");
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150 | 80cabfad | bellard | #endif
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151 | 80cabfad | bellard | cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
152 | 80cabfad | bellard | } |
153 | 80cabfad | bellard | } |
154 | 80cabfad | bellard | |
155 | 80cabfad | bellard | #ifdef DEBUG_IRQ_LATENCY
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156 | 80cabfad | bellard | int64_t irq_time[16];
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157 | 80cabfad | bellard | #endif
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158 | 80cabfad | bellard | |
159 | 80cabfad | bellard | void pic_set_irq(int irq, int level) |
160 | 80cabfad | bellard | { |
161 | 4a0fb71e | bellard | #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
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162 | 80cabfad | bellard | if (level != irq_level[irq]) {
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163 | 4a0fb71e | bellard | #if defined(DEBUG_PIC)
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164 | 80cabfad | bellard | printf("pic_set_irq: irq=%d level=%d\n", irq, level);
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165 | 4a0fb71e | bellard | #endif
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166 | 80cabfad | bellard | irq_level[irq] = level; |
167 | 4a0fb71e | bellard | #ifdef DEBUG_IRQ_COUNT
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168 | 4a0fb71e | bellard | if (level == 1) |
169 | 4a0fb71e | bellard | irq_count[irq]++; |
170 | 4a0fb71e | bellard | #endif
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171 | 80cabfad | bellard | } |
172 | 80cabfad | bellard | #endif
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173 | 80cabfad | bellard | #ifdef DEBUG_IRQ_LATENCY
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174 | 80cabfad | bellard | if (level) {
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175 | 2444ca41 | bellard | irq_time[irq] = qemu_get_clock(vm_clock); |
176 | 80cabfad | bellard | } |
177 | 80cabfad | bellard | #endif
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178 | 80cabfad | bellard | pic_set_irq1(&pics[irq >> 3], irq & 7, level); |
179 | 80cabfad | bellard | pic_update_irq(); |
180 | 80cabfad | bellard | } |
181 | 80cabfad | bellard | |
182 | 80cabfad | bellard | /* acknowledge interrupt 'irq' */
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183 | 80cabfad | bellard | static inline void pic_intack(PicState *s, int irq) |
184 | 80cabfad | bellard | { |
185 | 80cabfad | bellard | if (s->auto_eoi) {
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186 | 80cabfad | bellard | if (s->rotate_on_auto_eoi)
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187 | 80cabfad | bellard | s->priority_add = (irq + 1) & 7; |
188 | 80cabfad | bellard | } else {
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189 | 80cabfad | bellard | s->isr |= (1 << irq);
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190 | 80cabfad | bellard | } |
191 | 0ecf89aa | bellard | /* We don't clear a level sensitive interrupt here */
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192 | 0ecf89aa | bellard | if (!(s->elcr & (1 << irq))) |
193 | 0ecf89aa | bellard | s->irr &= ~(1 << irq);
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194 | 80cabfad | bellard | } |
195 | 80cabfad | bellard | |
196 | a541f297 | bellard | int cpu_get_pic_interrupt(CPUState *env)
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197 | 80cabfad | bellard | { |
198 | 80cabfad | bellard | int irq, irq2, intno;
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199 | 80cabfad | bellard | |
200 | 4f7631cf | bellard | #ifdef TARGET_X86_64
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201 | 4f7631cf | bellard | intno = apic_get_interrupt(env); |
202 | 4f7631cf | bellard | if (intno >= 0) { |
203 | 4f7631cf | bellard | /* set irq request if a PIC irq is still pending */
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204 | 4f7631cf | bellard | /* XXX: improve that */
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205 | 4f7631cf | bellard | pic_update_irq(); |
206 | 4f7631cf | bellard | return intno;
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207 | 4f7631cf | bellard | } |
208 | 4f7631cf | bellard | #endif
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209 | 15aeac38 | bellard | /* read the irq from the PIC */
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210 | 15aeac38 | bellard | |
211 | 15aeac38 | bellard | irq = pic_get_irq(&pics[0]);
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212 | 15aeac38 | bellard | if (irq >= 0) { |
213 | 15aeac38 | bellard | pic_intack(&pics[0], irq);
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214 | 15aeac38 | bellard | if (irq == 2) { |
215 | 15aeac38 | bellard | irq2 = pic_get_irq(&pics[1]);
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216 | 15aeac38 | bellard | if (irq2 >= 0) { |
217 | 15aeac38 | bellard | pic_intack(&pics[1], irq2);
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218 | 15aeac38 | bellard | } else {
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219 | 15aeac38 | bellard | /* spurious IRQ on slave controller */
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220 | 15aeac38 | bellard | irq2 = 7;
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221 | 15aeac38 | bellard | } |
222 | 15aeac38 | bellard | intno = pics[1].irq_base + irq2;
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223 | 15aeac38 | bellard | irq = irq2 + 8;
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224 | 15aeac38 | bellard | } else {
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225 | 15aeac38 | bellard | intno = pics[0].irq_base + irq;
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226 | 15aeac38 | bellard | } |
227 | 15aeac38 | bellard | } else {
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228 | 15aeac38 | bellard | /* spurious IRQ on host controller */
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229 | 15aeac38 | bellard | irq = 7;
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230 | 15aeac38 | bellard | intno = pics[0].irq_base + irq;
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231 | 15aeac38 | bellard | } |
232 | 15aeac38 | bellard | pic_update_irq(); |
233 | 15aeac38 | bellard | |
234 | 80cabfad | bellard | #ifdef DEBUG_IRQ_LATENCY
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235 | 80cabfad | bellard | printf("IRQ%d latency=%0.3fus\n",
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236 | 80cabfad | bellard | irq, |
237 | 2444ca41 | bellard | (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec); |
238 | 80cabfad | bellard | #endif
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239 | 80cabfad | bellard | #if defined(DEBUG_PIC)
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240 | 80cabfad | bellard | printf("pic_interrupt: irq=%d\n", irq);
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241 | 80cabfad | bellard | #endif
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242 | 80cabfad | bellard | return intno;
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243 | 80cabfad | bellard | } |
244 | 80cabfad | bellard | |
245 | d7d02e3c | bellard | static void pic_reset(void *opaque) |
246 | d7d02e3c | bellard | { |
247 | d7d02e3c | bellard | PicState *s = opaque; |
248 | d7d02e3c | bellard | int tmp;
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249 | d7d02e3c | bellard | |
250 | d7d02e3c | bellard | tmp = s->elcr_mask; |
251 | d7d02e3c | bellard | memset(s, 0, sizeof(PicState)); |
252 | d7d02e3c | bellard | s->elcr_mask = tmp; |
253 | d7d02e3c | bellard | } |
254 | d7d02e3c | bellard | |
255 | b41a2cd1 | bellard | static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
256 | 80cabfad | bellard | { |
257 | b41a2cd1 | bellard | PicState *s = opaque; |
258 | d7d02e3c | bellard | int priority, cmd, irq;
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259 | 80cabfad | bellard | |
260 | 80cabfad | bellard | #ifdef DEBUG_PIC
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261 | 80cabfad | bellard | printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
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262 | 80cabfad | bellard | #endif
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263 | 80cabfad | bellard | addr &= 1;
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264 | 80cabfad | bellard | if (addr == 0) { |
265 | 80cabfad | bellard | if (val & 0x10) { |
266 | 80cabfad | bellard | /* init */
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267 | d7d02e3c | bellard | pic_reset(s); |
268 | b54ad049 | bellard | /* deassert a pending interrupt */
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269 | b54ad049 | bellard | cpu_reset_interrupt(cpu_single_env, CPU_INTERRUPT_HARD); |
270 | 660de336 | bellard | |
271 | 80cabfad | bellard | s->init_state = 1;
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272 | 80cabfad | bellard | s->init4 = val & 1;
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273 | 80cabfad | bellard | if (val & 0x02) |
274 | 80cabfad | bellard | hw_error("single mode not supported");
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275 | 80cabfad | bellard | if (val & 0x08) |
276 | 80cabfad | bellard | hw_error("level sensitive irq not supported");
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277 | 80cabfad | bellard | } else if (val & 0x08) { |
278 | 80cabfad | bellard | if (val & 0x04) |
279 | 80cabfad | bellard | s->poll = 1;
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280 | 80cabfad | bellard | if (val & 0x02) |
281 | 80cabfad | bellard | s->read_reg_select = val & 1;
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282 | 80cabfad | bellard | if (val & 0x40) |
283 | 80cabfad | bellard | s->special_mask = (val >> 5) & 1; |
284 | 80cabfad | bellard | } else {
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285 | 80cabfad | bellard | cmd = val >> 5;
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286 | 80cabfad | bellard | switch(cmd) {
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287 | 80cabfad | bellard | case 0: |
288 | 80cabfad | bellard | case 4: |
289 | 80cabfad | bellard | s->rotate_on_auto_eoi = cmd >> 2;
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290 | 80cabfad | bellard | break;
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291 | 80cabfad | bellard | case 1: /* end of interrupt */ |
292 | 80cabfad | bellard | case 5: |
293 | 80cabfad | bellard | priority = get_priority(s, s->isr); |
294 | 80cabfad | bellard | if (priority != 8) { |
295 | 80cabfad | bellard | irq = (priority + s->priority_add) & 7;
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296 | 80cabfad | bellard | s->isr &= ~(1 << irq);
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297 | 80cabfad | bellard | if (cmd == 5) |
298 | 80cabfad | bellard | s->priority_add = (irq + 1) & 7; |
299 | 80cabfad | bellard | pic_update_irq(); |
300 | 80cabfad | bellard | } |
301 | 80cabfad | bellard | break;
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302 | 80cabfad | bellard | case 3: |
303 | 80cabfad | bellard | irq = val & 7;
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304 | 80cabfad | bellard | s->isr &= ~(1 << irq);
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305 | 80cabfad | bellard | pic_update_irq(); |
306 | 80cabfad | bellard | break;
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307 | 80cabfad | bellard | case 6: |
308 | 80cabfad | bellard | s->priority_add = (val + 1) & 7; |
309 | 80cabfad | bellard | pic_update_irq(); |
310 | 80cabfad | bellard | break;
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311 | 80cabfad | bellard | case 7: |
312 | 80cabfad | bellard | irq = val & 7;
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313 | 80cabfad | bellard | s->isr &= ~(1 << irq);
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314 | 80cabfad | bellard | s->priority_add = (irq + 1) & 7; |
315 | 80cabfad | bellard | pic_update_irq(); |
316 | 80cabfad | bellard | break;
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317 | 80cabfad | bellard | default:
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318 | 80cabfad | bellard | /* no operation */
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319 | 80cabfad | bellard | break;
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320 | 80cabfad | bellard | } |
321 | 80cabfad | bellard | } |
322 | 80cabfad | bellard | } else {
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323 | 80cabfad | bellard | switch(s->init_state) {
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324 | 80cabfad | bellard | case 0: |
325 | 80cabfad | bellard | /* normal mode */
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326 | 80cabfad | bellard | s->imr = val; |
327 | 80cabfad | bellard | pic_update_irq(); |
328 | 80cabfad | bellard | break;
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329 | 80cabfad | bellard | case 1: |
330 | 80cabfad | bellard | s->irq_base = val & 0xf8;
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331 | 80cabfad | bellard | s->init_state = 2;
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332 | 80cabfad | bellard | break;
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333 | 80cabfad | bellard | case 2: |
334 | 80cabfad | bellard | if (s->init4) {
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335 | 80cabfad | bellard | s->init_state = 3;
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336 | 80cabfad | bellard | } else {
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337 | 80cabfad | bellard | s->init_state = 0;
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338 | 80cabfad | bellard | } |
339 | 80cabfad | bellard | break;
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340 | 80cabfad | bellard | case 3: |
341 | 80cabfad | bellard | s->special_fully_nested_mode = (val >> 4) & 1; |
342 | 80cabfad | bellard | s->auto_eoi = (val >> 1) & 1; |
343 | 80cabfad | bellard | s->init_state = 0;
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344 | 80cabfad | bellard | break;
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345 | 80cabfad | bellard | } |
346 | 80cabfad | bellard | } |
347 | 80cabfad | bellard | } |
348 | 80cabfad | bellard | |
349 | 80cabfad | bellard | static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
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350 | 80cabfad | bellard | { |
351 | 80cabfad | bellard | int ret;
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352 | 80cabfad | bellard | |
353 | 80cabfad | bellard | ret = pic_get_irq(s); |
354 | 80cabfad | bellard | if (ret >= 0) { |
355 | 80cabfad | bellard | if (addr1 >> 7) { |
356 | 80cabfad | bellard | pics[0].isr &= ~(1 << 2); |
357 | 80cabfad | bellard | pics[0].irr &= ~(1 << 2); |
358 | 80cabfad | bellard | } |
359 | 80cabfad | bellard | s->irr &= ~(1 << ret);
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360 | 80cabfad | bellard | s->isr &= ~(1 << ret);
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361 | 80cabfad | bellard | if (addr1 >> 7 || ret != 2) |
362 | 80cabfad | bellard | pic_update_irq(); |
363 | 80cabfad | bellard | } else {
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364 | 80cabfad | bellard | ret = 0x07;
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365 | 80cabfad | bellard | pic_update_irq(); |
366 | 80cabfad | bellard | } |
367 | 80cabfad | bellard | |
368 | 80cabfad | bellard | return ret;
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369 | 80cabfad | bellard | } |
370 | 80cabfad | bellard | |
371 | b41a2cd1 | bellard | static uint32_t pic_ioport_read(void *opaque, uint32_t addr1) |
372 | 80cabfad | bellard | { |
373 | b41a2cd1 | bellard | PicState *s = opaque; |
374 | 80cabfad | bellard | unsigned int addr; |
375 | 80cabfad | bellard | int ret;
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376 | 80cabfad | bellard | |
377 | 80cabfad | bellard | addr = addr1; |
378 | 80cabfad | bellard | addr &= 1;
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379 | 80cabfad | bellard | if (s->poll) {
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380 | 80cabfad | bellard | ret = pic_poll_read(s, addr1); |
381 | 80cabfad | bellard | s->poll = 0;
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382 | 80cabfad | bellard | } else {
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383 | 80cabfad | bellard | if (addr == 0) { |
384 | 80cabfad | bellard | if (s->read_reg_select)
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385 | 80cabfad | bellard | ret = s->isr; |
386 | 80cabfad | bellard | else
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387 | 80cabfad | bellard | ret = s->irr; |
388 | 80cabfad | bellard | } else {
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389 | 80cabfad | bellard | ret = s->imr; |
390 | 80cabfad | bellard | } |
391 | 80cabfad | bellard | } |
392 | 80cabfad | bellard | #ifdef DEBUG_PIC
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393 | 80cabfad | bellard | printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
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394 | 80cabfad | bellard | #endif
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395 | 80cabfad | bellard | return ret;
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396 | 80cabfad | bellard | } |
397 | 80cabfad | bellard | |
398 | 80cabfad | bellard | /* memory mapped interrupt status */
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399 | 80cabfad | bellard | uint32_t pic_intack_read(CPUState *env) |
400 | 80cabfad | bellard | { |
401 | 80cabfad | bellard | int ret;
|
402 | 80cabfad | bellard | |
403 | 80cabfad | bellard | ret = pic_poll_read(&pics[0], 0x00); |
404 | 80cabfad | bellard | if (ret == 2) |
405 | 80cabfad | bellard | ret = pic_poll_read(&pics[1], 0x80) + 8; |
406 | 80cabfad | bellard | /* Prepare for ISR read */
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407 | 80cabfad | bellard | pics[0].read_reg_select = 1; |
408 | 80cabfad | bellard | |
409 | 80cabfad | bellard | return ret;
|
410 | 80cabfad | bellard | } |
411 | 80cabfad | bellard | |
412 | 660de336 | bellard | static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
413 | 660de336 | bellard | { |
414 | 660de336 | bellard | PicState *s = opaque; |
415 | 660de336 | bellard | s->elcr = val & s->elcr_mask; |
416 | 660de336 | bellard | } |
417 | 660de336 | bellard | |
418 | 660de336 | bellard | static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1) |
419 | 660de336 | bellard | { |
420 | 660de336 | bellard | PicState *s = opaque; |
421 | 660de336 | bellard | return s->elcr;
|
422 | 660de336 | bellard | } |
423 | 660de336 | bellard | |
424 | b0a21b53 | bellard | static void pic_save(QEMUFile *f, void *opaque) |
425 | b0a21b53 | bellard | { |
426 | b0a21b53 | bellard | PicState *s = opaque; |
427 | b0a21b53 | bellard | |
428 | b0a21b53 | bellard | qemu_put_8s(f, &s->last_irr); |
429 | b0a21b53 | bellard | qemu_put_8s(f, &s->irr); |
430 | b0a21b53 | bellard | qemu_put_8s(f, &s->imr); |
431 | b0a21b53 | bellard | qemu_put_8s(f, &s->isr); |
432 | b0a21b53 | bellard | qemu_put_8s(f, &s->priority_add); |
433 | b0a21b53 | bellard | qemu_put_8s(f, &s->irq_base); |
434 | b0a21b53 | bellard | qemu_put_8s(f, &s->read_reg_select); |
435 | b0a21b53 | bellard | qemu_put_8s(f, &s->poll); |
436 | b0a21b53 | bellard | qemu_put_8s(f, &s->special_mask); |
437 | b0a21b53 | bellard | qemu_put_8s(f, &s->init_state); |
438 | b0a21b53 | bellard | qemu_put_8s(f, &s->auto_eoi); |
439 | b0a21b53 | bellard | qemu_put_8s(f, &s->rotate_on_auto_eoi); |
440 | b0a21b53 | bellard | qemu_put_8s(f, &s->special_fully_nested_mode); |
441 | b0a21b53 | bellard | qemu_put_8s(f, &s->init4); |
442 | 660de336 | bellard | qemu_put_8s(f, &s->elcr); |
443 | b0a21b53 | bellard | } |
444 | b0a21b53 | bellard | |
445 | b0a21b53 | bellard | static int pic_load(QEMUFile *f, void *opaque, int version_id) |
446 | b0a21b53 | bellard | { |
447 | b0a21b53 | bellard | PicState *s = opaque; |
448 | b0a21b53 | bellard | |
449 | b0a21b53 | bellard | if (version_id != 1) |
450 | b0a21b53 | bellard | return -EINVAL;
|
451 | b0a21b53 | bellard | |
452 | b0a21b53 | bellard | qemu_get_8s(f, &s->last_irr); |
453 | b0a21b53 | bellard | qemu_get_8s(f, &s->irr); |
454 | b0a21b53 | bellard | qemu_get_8s(f, &s->imr); |
455 | b0a21b53 | bellard | qemu_get_8s(f, &s->isr); |
456 | b0a21b53 | bellard | qemu_get_8s(f, &s->priority_add); |
457 | b0a21b53 | bellard | qemu_get_8s(f, &s->irq_base); |
458 | b0a21b53 | bellard | qemu_get_8s(f, &s->read_reg_select); |
459 | b0a21b53 | bellard | qemu_get_8s(f, &s->poll); |
460 | b0a21b53 | bellard | qemu_get_8s(f, &s->special_mask); |
461 | b0a21b53 | bellard | qemu_get_8s(f, &s->init_state); |
462 | b0a21b53 | bellard | qemu_get_8s(f, &s->auto_eoi); |
463 | b0a21b53 | bellard | qemu_get_8s(f, &s->rotate_on_auto_eoi); |
464 | b0a21b53 | bellard | qemu_get_8s(f, &s->special_fully_nested_mode); |
465 | b0a21b53 | bellard | qemu_get_8s(f, &s->init4); |
466 | 660de336 | bellard | qemu_get_8s(f, &s->elcr); |
467 | b0a21b53 | bellard | return 0; |
468 | b0a21b53 | bellard | } |
469 | b0a21b53 | bellard | |
470 | b0a21b53 | bellard | /* XXX: add generic master/slave system */
|
471 | 660de336 | bellard | static void pic_init1(int io_addr, int elcr_addr, PicState *s) |
472 | b0a21b53 | bellard | { |
473 | b0a21b53 | bellard | register_ioport_write(io_addr, 2, 1, pic_ioport_write, s); |
474 | b0a21b53 | bellard | register_ioport_read(io_addr, 2, 1, pic_ioport_read, s); |
475 | 660de336 | bellard | if (elcr_addr >= 0) { |
476 | 660de336 | bellard | register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s); |
477 | 660de336 | bellard | register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s); |
478 | 660de336 | bellard | } |
479 | b0a21b53 | bellard | register_savevm("i8259", io_addr, 1, pic_save, pic_load, s); |
480 | d7d02e3c | bellard | qemu_register_reset(pic_reset, s); |
481 | b0a21b53 | bellard | } |
482 | b0a21b53 | bellard | |
483 | ba91cd80 | bellard | void pic_info(void) |
484 | ba91cd80 | bellard | { |
485 | ba91cd80 | bellard | int i;
|
486 | ba91cd80 | bellard | PicState *s; |
487 | ba91cd80 | bellard | |
488 | ba91cd80 | bellard | for(i=0;i<2;i++) { |
489 | ba91cd80 | bellard | s = &pics[i]; |
490 | 15aeac38 | bellard | term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
|
491 | 660de336 | bellard | i, s->irr, s->imr, s->isr, s->priority_add, |
492 | 15aeac38 | bellard | s->irq_base, s->read_reg_select, s->elcr, |
493 | 15aeac38 | bellard | s->special_fully_nested_mode); |
494 | ba91cd80 | bellard | } |
495 | ba91cd80 | bellard | } |
496 | ba91cd80 | bellard | |
497 | 4a0fb71e | bellard | void irq_info(void) |
498 | 4a0fb71e | bellard | { |
499 | 4a0fb71e | bellard | #ifndef DEBUG_IRQ_COUNT
|
500 | 4a0fb71e | bellard | term_printf("irq statistic code not compiled.\n");
|
501 | 4a0fb71e | bellard | #else
|
502 | 4a0fb71e | bellard | int i;
|
503 | 4a0fb71e | bellard | int64_t count; |
504 | 4a0fb71e | bellard | |
505 | 4a0fb71e | bellard | term_printf("IRQ statistics:\n");
|
506 | 4a0fb71e | bellard | for (i = 0; i < 16; i++) { |
507 | 4a0fb71e | bellard | count = irq_count[i]; |
508 | 4a0fb71e | bellard | if (count > 0) |
509 | 4a0fb71e | bellard | term_printf("%2d: %lld\n", i, count);
|
510 | 4a0fb71e | bellard | } |
511 | 4a0fb71e | bellard | #endif
|
512 | 4a0fb71e | bellard | } |
513 | ba91cd80 | bellard | |
514 | 80cabfad | bellard | void pic_init(void) |
515 | 80cabfad | bellard | { |
516 | 660de336 | bellard | pic_init1(0x20, 0x4d0, &pics[0]); |
517 | 660de336 | bellard | pic_init1(0xa0, 0x4d1, &pics[1]); |
518 | 660de336 | bellard | pics[0].elcr_mask = 0xf8; |
519 | 660de336 | bellard | pics[1].elcr_mask = 0xde; |
520 | 80cabfad | bellard | } |