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1 | 46ddf551 | bellard | /*
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2 | 46ddf551 | bellard | * vm86 linux syscall support
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3 | 46ddf551 | bellard | *
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4 | 46ddf551 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 46ddf551 | bellard | *
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6 | 46ddf551 | bellard | * This program is free software; you can redistribute it and/or modify
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7 | 46ddf551 | bellard | * it under the terms of the GNU General Public License as published by
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8 | 46ddf551 | bellard | * the Free Software Foundation; either version 2 of the License, or
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9 | 46ddf551 | bellard | * (at your option) any later version.
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10 | 46ddf551 | bellard | *
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11 | 46ddf551 | bellard | * This program is distributed in the hope that it will be useful,
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12 | 46ddf551 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 46ddf551 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | 46ddf551 | bellard | * GNU General Public License for more details.
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15 | 46ddf551 | bellard | *
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16 | 46ddf551 | bellard | * You should have received a copy of the GNU General Public License
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17 | 46ddf551 | bellard | * along with this program; if not, write to the Free Software
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18 | 46ddf551 | bellard | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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19 | 46ddf551 | bellard | */
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20 | 46ddf551 | bellard | #include <stdlib.h> |
21 | 46ddf551 | bellard | #include <stdio.h> |
22 | 46ddf551 | bellard | #include <stdarg.h> |
23 | 46ddf551 | bellard | #include <string.h> |
24 | 46ddf551 | bellard | #include <errno.h> |
25 | 46ddf551 | bellard | #include <unistd.h> |
26 | 46ddf551 | bellard | |
27 | 46ddf551 | bellard | #include "qemu.h" |
28 | 46ddf551 | bellard | |
29 | 46ddf551 | bellard | //#define DEBUG_VM86
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30 | 46ddf551 | bellard | |
31 | 46ddf551 | bellard | #define set_flags(X,new,mask) \
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32 | 46ddf551 | bellard | ((X) = ((X) & ~(mask)) | ((new) & (mask))) |
33 | 46ddf551 | bellard | |
34 | 46ddf551 | bellard | #define SAFE_MASK (0xDD5) |
35 | 46ddf551 | bellard | #define RETURN_MASK (0xDFF) |
36 | 46ddf551 | bellard | |
37 | 46ddf551 | bellard | static inline int is_revectored(int nr, struct target_revectored_struct *bitmap) |
38 | 46ddf551 | bellard | { |
39 | b333af06 | bellard | return (((uint8_t *)bitmap)[nr >> 3] >> (nr & 7)) & 1; |
40 | 46ddf551 | bellard | } |
41 | 46ddf551 | bellard | |
42 | 46ddf551 | bellard | static inline void vm_putw(uint8_t *segptr, unsigned int reg16, unsigned int val) |
43 | 46ddf551 | bellard | { |
44 | 84fa15d8 | bellard | stw(segptr + (reg16 & 0xffff), val);
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45 | 46ddf551 | bellard | } |
46 | 46ddf551 | bellard | |
47 | 46ddf551 | bellard | static inline void vm_putl(uint8_t *segptr, unsigned int reg16, unsigned int val) |
48 | 46ddf551 | bellard | { |
49 | 84fa15d8 | bellard | stl(segptr + (reg16 & 0xffff), val);
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50 | 46ddf551 | bellard | } |
51 | 46ddf551 | bellard | |
52 | 46ddf551 | bellard | static inline unsigned int vm_getw(uint8_t *segptr, unsigned int reg16) |
53 | 46ddf551 | bellard | { |
54 | 84fa15d8 | bellard | return lduw(segptr + (reg16 & 0xffff)); |
55 | 46ddf551 | bellard | } |
56 | 46ddf551 | bellard | |
57 | 46ddf551 | bellard | static inline unsigned int vm_getl(uint8_t *segptr, unsigned int reg16) |
58 | 46ddf551 | bellard | { |
59 | 84fa15d8 | bellard | return ldl(segptr + (reg16 & 0xffff)); |
60 | 46ddf551 | bellard | } |
61 | 46ddf551 | bellard | |
62 | 46ddf551 | bellard | void save_v86_state(CPUX86State *env)
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63 | 46ddf551 | bellard | { |
64 | 46ddf551 | bellard | TaskState *ts = env->opaque; |
65 | 46ddf551 | bellard | |
66 | 46ddf551 | bellard | /* put the VM86 registers in the userspace register structure */
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67 | 46ddf551 | bellard | ts->target_v86->regs.eax = tswap32(env->regs[R_EAX]); |
68 | 46ddf551 | bellard | ts->target_v86->regs.ebx = tswap32(env->regs[R_EBX]); |
69 | 46ddf551 | bellard | ts->target_v86->regs.ecx = tswap32(env->regs[R_ECX]); |
70 | 46ddf551 | bellard | ts->target_v86->regs.edx = tswap32(env->regs[R_EDX]); |
71 | 46ddf551 | bellard | ts->target_v86->regs.esi = tswap32(env->regs[R_ESI]); |
72 | 46ddf551 | bellard | ts->target_v86->regs.edi = tswap32(env->regs[R_EDI]); |
73 | 46ddf551 | bellard | ts->target_v86->regs.ebp = tswap32(env->regs[R_EBP]); |
74 | 46ddf551 | bellard | ts->target_v86->regs.esp = tswap32(env->regs[R_ESP]); |
75 | 46ddf551 | bellard | ts->target_v86->regs.eip = tswap32(env->eip); |
76 | c05bab77 | bellard | ts->target_v86->regs.cs = tswap16(env->segs[R_CS].selector); |
77 | c05bab77 | bellard | ts->target_v86->regs.ss = tswap16(env->segs[R_SS].selector); |
78 | c05bab77 | bellard | ts->target_v86->regs.ds = tswap16(env->segs[R_DS].selector); |
79 | c05bab77 | bellard | ts->target_v86->regs.es = tswap16(env->segs[R_ES].selector); |
80 | c05bab77 | bellard | ts->target_v86->regs.fs = tswap16(env->segs[R_FS].selector); |
81 | c05bab77 | bellard | ts->target_v86->regs.gs = tswap16(env->segs[R_GS].selector); |
82 | 46ddf551 | bellard | set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask); |
83 | 46ddf551 | bellard | ts->target_v86->regs.eflags = tswap32(env->eflags); |
84 | 46ddf551 | bellard | #ifdef DEBUG_VM86
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85 | 46ddf551 | bellard | fprintf(logfile, "save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
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86 | c05bab77 | bellard | env->eflags, env->segs[R_CS].selector, env->eip); |
87 | 46ddf551 | bellard | #endif
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88 | 46ddf551 | bellard | |
89 | 46ddf551 | bellard | /* restore 32 bit registers */
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90 | 46ddf551 | bellard | env->regs[R_EAX] = ts->vm86_saved_regs.eax; |
91 | 46ddf551 | bellard | env->regs[R_EBX] = ts->vm86_saved_regs.ebx; |
92 | 46ddf551 | bellard | env->regs[R_ECX] = ts->vm86_saved_regs.ecx; |
93 | 46ddf551 | bellard | env->regs[R_EDX] = ts->vm86_saved_regs.edx; |
94 | 46ddf551 | bellard | env->regs[R_ESI] = ts->vm86_saved_regs.esi; |
95 | 46ddf551 | bellard | env->regs[R_EDI] = ts->vm86_saved_regs.edi; |
96 | 46ddf551 | bellard | env->regs[R_EBP] = ts->vm86_saved_regs.ebp; |
97 | 46ddf551 | bellard | env->regs[R_ESP] = ts->vm86_saved_regs.esp; |
98 | 46ddf551 | bellard | env->eflags = ts->vm86_saved_regs.eflags; |
99 | 46ddf551 | bellard | env->eip = ts->vm86_saved_regs.eip; |
100 | 46ddf551 | bellard | |
101 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs); |
102 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss); |
103 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds); |
104 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es); |
105 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs); |
106 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs); |
107 | 46ddf551 | bellard | } |
108 | 46ddf551 | bellard | |
109 | 46ddf551 | bellard | /* return from vm86 mode to 32 bit. The vm86() syscall will return
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110 | 46ddf551 | bellard | 'retval' */
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111 | 46ddf551 | bellard | static inline void return_to_32bit(CPUX86State *env, int retval) |
112 | 46ddf551 | bellard | { |
113 | 46ddf551 | bellard | #ifdef DEBUG_VM86
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114 | 46ddf551 | bellard | fprintf(logfile, "return_to_32bit: ret=0x%x\n", retval);
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115 | 46ddf551 | bellard | #endif
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116 | 46ddf551 | bellard | save_v86_state(env); |
117 | 46ddf551 | bellard | env->regs[R_EAX] = retval; |
118 | 46ddf551 | bellard | } |
119 | 46ddf551 | bellard | |
120 | 46ddf551 | bellard | static inline int set_IF(CPUX86State *env) |
121 | 46ddf551 | bellard | { |
122 | 46ddf551 | bellard | TaskState *ts = env->opaque; |
123 | 46ddf551 | bellard | |
124 | 46ddf551 | bellard | ts->v86flags |= VIF_MASK; |
125 | 46ddf551 | bellard | if (ts->v86flags & VIP_MASK) {
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126 | 46ddf551 | bellard | return_to_32bit(env, TARGET_VM86_STI); |
127 | 46ddf551 | bellard | return 1; |
128 | 46ddf551 | bellard | } |
129 | 46ddf551 | bellard | return 0; |
130 | 46ddf551 | bellard | } |
131 | 46ddf551 | bellard | |
132 | 46ddf551 | bellard | static inline void clear_IF(CPUX86State *env) |
133 | 46ddf551 | bellard | { |
134 | 46ddf551 | bellard | TaskState *ts = env->opaque; |
135 | 46ddf551 | bellard | |
136 | 46ddf551 | bellard | ts->v86flags &= ~VIF_MASK; |
137 | 46ddf551 | bellard | } |
138 | 46ddf551 | bellard | |
139 | 46ddf551 | bellard | static inline void clear_TF(CPUX86State *env) |
140 | 46ddf551 | bellard | { |
141 | 46ddf551 | bellard | env->eflags &= ~TF_MASK; |
142 | 46ddf551 | bellard | } |
143 | 46ddf551 | bellard | |
144 | 226c9132 | bellard | static inline void clear_AC(CPUX86State *env) |
145 | 226c9132 | bellard | { |
146 | 226c9132 | bellard | env->eflags &= ~AC_MASK; |
147 | 226c9132 | bellard | } |
148 | 226c9132 | bellard | |
149 | 46ddf551 | bellard | static inline int set_vflags_long(unsigned long eflags, CPUX86State *env) |
150 | 46ddf551 | bellard | { |
151 | 46ddf551 | bellard | TaskState *ts = env->opaque; |
152 | 46ddf551 | bellard | |
153 | 46ddf551 | bellard | set_flags(ts->v86flags, eflags, ts->v86mask); |
154 | 46ddf551 | bellard | set_flags(env->eflags, eflags, SAFE_MASK); |
155 | 46ddf551 | bellard | if (eflags & IF_MASK)
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156 | 46ddf551 | bellard | return set_IF(env);
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157 | 226c9132 | bellard | else
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158 | 226c9132 | bellard | clear_IF(env); |
159 | 46ddf551 | bellard | return 0; |
160 | 46ddf551 | bellard | } |
161 | 46ddf551 | bellard | |
162 | 46ddf551 | bellard | static inline int set_vflags_short(unsigned short flags, CPUX86State *env) |
163 | 46ddf551 | bellard | { |
164 | 46ddf551 | bellard | TaskState *ts = env->opaque; |
165 | 46ddf551 | bellard | |
166 | 46ddf551 | bellard | set_flags(ts->v86flags, flags, ts->v86mask & 0xffff);
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167 | 46ddf551 | bellard | set_flags(env->eflags, flags, SAFE_MASK); |
168 | 46ddf551 | bellard | if (flags & IF_MASK)
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169 | 46ddf551 | bellard | return set_IF(env);
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170 | 226c9132 | bellard | else
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171 | 226c9132 | bellard | clear_IF(env); |
172 | 46ddf551 | bellard | return 0; |
173 | 46ddf551 | bellard | } |
174 | 46ddf551 | bellard | |
175 | 46ddf551 | bellard | static inline unsigned int get_vflags(CPUX86State *env) |
176 | 46ddf551 | bellard | { |
177 | 46ddf551 | bellard | TaskState *ts = env->opaque; |
178 | 46ddf551 | bellard | unsigned int flags; |
179 | 46ddf551 | bellard | |
180 | 46ddf551 | bellard | flags = env->eflags & RETURN_MASK; |
181 | 46ddf551 | bellard | if (ts->v86flags & VIF_MASK)
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182 | 46ddf551 | bellard | flags |= IF_MASK; |
183 | c05bab77 | bellard | flags |= IOPL_MASK; |
184 | 46ddf551 | bellard | return flags | (ts->v86flags & ts->v86mask);
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185 | 46ddf551 | bellard | } |
186 | 46ddf551 | bellard | |
187 | 46ddf551 | bellard | #define ADD16(reg, val) reg = (reg & ~0xffff) | ((reg + (val)) & 0xffff) |
188 | 46ddf551 | bellard | |
189 | 46ddf551 | bellard | /* handle VM86 interrupt (NOTE: the CPU core currently does not
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190 | 46ddf551 | bellard | support TSS interrupt revectoring, so this code is always executed) */
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191 | 447db213 | bellard | static void do_int(CPUX86State *env, int intno) |
192 | 46ddf551 | bellard | { |
193 | 46ddf551 | bellard | TaskState *ts = env->opaque; |
194 | 46ddf551 | bellard | uint32_t *int_ptr, segoffs; |
195 | 46ddf551 | bellard | uint8_t *ssp; |
196 | 46ddf551 | bellard | unsigned int sp; |
197 | 46ddf551 | bellard | |
198 | c05bab77 | bellard | if (env->segs[R_CS].selector == TARGET_BIOSSEG)
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199 | 46ddf551 | bellard | goto cannot_handle;
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200 | b333af06 | bellard | if (is_revectored(intno, &ts->vm86plus.int_revectored))
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201 | 46ddf551 | bellard | goto cannot_handle;
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202 | 46ddf551 | bellard | if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff, |
203 | b333af06 | bellard | &ts->vm86plus.int21_revectored)) |
204 | 46ddf551 | bellard | goto cannot_handle;
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205 | 46ddf551 | bellard | int_ptr = (uint32_t *)(intno << 2);
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206 | 46ddf551 | bellard | segoffs = tswap32(*int_ptr); |
207 | 46ddf551 | bellard | if ((segoffs >> 16) == TARGET_BIOSSEG) |
208 | 46ddf551 | bellard | goto cannot_handle;
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209 | 46ddf551 | bellard | #if defined(DEBUG_VM86)
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210 | 46ddf551 | bellard | fprintf(logfile, "VM86: emulating int 0x%x. CS:IP=%04x:%04x\n",
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211 | 46ddf551 | bellard | intno, segoffs >> 16, segoffs & 0xffff); |
212 | 46ddf551 | bellard | #endif
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213 | 46ddf551 | bellard | /* save old state */
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214 | c05bab77 | bellard | ssp = (uint8_t *)(env->segs[R_SS].selector << 4);
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215 | 46ddf551 | bellard | sp = env->regs[R_ESP] & 0xffff;
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216 | 46ddf551 | bellard | vm_putw(ssp, sp - 2, get_vflags(env));
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217 | c05bab77 | bellard | vm_putw(ssp, sp - 4, env->segs[R_CS].selector);
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218 | 46ddf551 | bellard | vm_putw(ssp, sp - 6, env->eip);
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219 | 46ddf551 | bellard | ADD16(env->regs[R_ESP], -6);
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220 | 46ddf551 | bellard | /* goto interrupt handler */
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221 | 46ddf551 | bellard | env->eip = segoffs & 0xffff;
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222 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_CS, segoffs >> 16);
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223 | 46ddf551 | bellard | clear_TF(env); |
224 | 46ddf551 | bellard | clear_IF(env); |
225 | 226c9132 | bellard | clear_AC(env); |
226 | 46ddf551 | bellard | return;
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227 | 46ddf551 | bellard | cannot_handle:
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228 | 46ddf551 | bellard | #if defined(DEBUG_VM86)
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229 | 46ddf551 | bellard | fprintf(logfile, "VM86: return to 32 bits int 0x%x\n", intno);
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230 | 46ddf551 | bellard | #endif
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231 | 46ddf551 | bellard | return_to_32bit(env, TARGET_VM86_INTx | (intno << 8));
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232 | 46ddf551 | bellard | } |
233 | 46ddf551 | bellard | |
234 | 447db213 | bellard | void handle_vm86_trap(CPUX86State *env, int trapno) |
235 | 447db213 | bellard | { |
236 | 447db213 | bellard | if (trapno == 1 || trapno == 3) { |
237 | 447db213 | bellard | return_to_32bit(env, TARGET_VM86_TRAP + (trapno << 8));
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238 | 447db213 | bellard | } else {
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239 | 447db213 | bellard | do_int(env, trapno); |
240 | 447db213 | bellard | } |
241 | 447db213 | bellard | } |
242 | 447db213 | bellard | |
243 | b333af06 | bellard | #define CHECK_IF_IN_TRAP() \
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244 | b333af06 | bellard | if ((ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) && \
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245 | b333af06 | bellard | (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_TFpendig)) \ |
246 | b333af06 | bellard | newflags |= TF_MASK |
247 | 46ddf551 | bellard | |
248 | 46ddf551 | bellard | #define VM86_FAULT_RETURN \
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249 | b333af06 | bellard | if ((ts->vm86plus.vm86plus.flags & TARGET_force_return_for_pic) && \
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250 | 46ddf551 | bellard | (ts->v86flags & (IF_MASK | VIF_MASK))) \ |
251 | 46ddf551 | bellard | return_to_32bit(env, TARGET_VM86_PICRETURN); \ |
252 | 46ddf551 | bellard | return
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253 | 46ddf551 | bellard | |
254 | 46ddf551 | bellard | void handle_vm86_fault(CPUX86State *env)
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255 | 46ddf551 | bellard | { |
256 | 46ddf551 | bellard | TaskState *ts = env->opaque; |
257 | 46ddf551 | bellard | uint8_t *csp, *pc, *ssp; |
258 | b333af06 | bellard | unsigned int ip, sp, newflags, newip, newcs, opcode, intno; |
259 | b333af06 | bellard | int data32, pref_done;
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260 | 46ddf551 | bellard | |
261 | c05bab77 | bellard | csp = (uint8_t *)(env->segs[R_CS].selector << 4);
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262 | 46ddf551 | bellard | ip = env->eip & 0xffff;
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263 | 46ddf551 | bellard | pc = csp + ip; |
264 | 46ddf551 | bellard | |
265 | c05bab77 | bellard | ssp = (uint8_t *)(env->segs[R_SS].selector << 4);
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266 | 46ddf551 | bellard | sp = env->regs[R_ESP] & 0xffff;
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267 | 46ddf551 | bellard | |
268 | 46ddf551 | bellard | #if defined(DEBUG_VM86)
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269 | 46ddf551 | bellard | fprintf(logfile, "VM86 exception %04x:%08x %02x %02x\n",
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270 | c05bab77 | bellard | env->segs[R_CS].selector, env->eip, pc[0], pc[1]); |
271 | 46ddf551 | bellard | #endif
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272 | 46ddf551 | bellard | |
273 | b333af06 | bellard | data32 = 0;
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274 | b333af06 | bellard | pref_done = 0;
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275 | b333af06 | bellard | do {
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276 | b333af06 | bellard | opcode = csp[ip]; |
277 | b333af06 | bellard | ADD16(ip, 1);
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278 | b333af06 | bellard | switch (opcode) {
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279 | b333af06 | bellard | case 0x66: /* 32-bit data */ data32=1; break; |
280 | b333af06 | bellard | case 0x67: /* 32-bit address */ break; |
281 | b333af06 | bellard | case 0x2e: /* CS */ break; |
282 | b333af06 | bellard | case 0x3e: /* DS */ break; |
283 | b333af06 | bellard | case 0x26: /* ES */ break; |
284 | b333af06 | bellard | case 0x36: /* SS */ break; |
285 | b333af06 | bellard | case 0x65: /* GS */ break; |
286 | b333af06 | bellard | case 0x64: /* FS */ break; |
287 | b333af06 | bellard | case 0xf2: /* repnz */ break; |
288 | b333af06 | bellard | case 0xf3: /* rep */ break; |
289 | b333af06 | bellard | default: pref_done = 1; |
290 | b333af06 | bellard | } |
291 | b333af06 | bellard | } while (!pref_done);
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292 | b333af06 | bellard | |
293 | 46ddf551 | bellard | /* VM86 mode */
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294 | b333af06 | bellard | switch(opcode) {
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295 | b333af06 | bellard | case 0x9c: /* pushf */ |
296 | b333af06 | bellard | if (data32) {
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297 | 46ddf551 | bellard | vm_putl(ssp, sp - 4, get_vflags(env));
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298 | b333af06 | bellard | ADD16(env->regs[R_ESP], -4);
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299 | b333af06 | bellard | } else {
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300 | b333af06 | bellard | vm_putw(ssp, sp - 2, get_vflags(env));
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301 | b333af06 | bellard | ADD16(env->regs[R_ESP], -2);
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302 | b333af06 | bellard | } |
303 | b333af06 | bellard | env->eip = ip; |
304 | b333af06 | bellard | VM86_FAULT_RETURN; |
305 | 46ddf551 | bellard | |
306 | b333af06 | bellard | case 0x9d: /* popf */ |
307 | b333af06 | bellard | if (data32) {
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308 | b333af06 | bellard | newflags = vm_getl(ssp, sp); |
309 | 46ddf551 | bellard | ADD16(env->regs[R_ESP], 4);
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310 | b333af06 | bellard | } else {
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311 | b333af06 | bellard | newflags = vm_getw(ssp, sp); |
312 | b333af06 | bellard | ADD16(env->regs[R_ESP], 2);
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313 | b333af06 | bellard | } |
314 | b333af06 | bellard | env->eip = ip; |
315 | b333af06 | bellard | CHECK_IF_IN_TRAP(); |
316 | b333af06 | bellard | if (data32) {
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317 | b333af06 | bellard | if (set_vflags_long(newflags, env))
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318 | 46ddf551 | bellard | return;
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319 | b333af06 | bellard | } else {
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320 | b333af06 | bellard | if (set_vflags_short(newflags, env))
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321 | 46ddf551 | bellard | return;
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322 | 46ddf551 | bellard | } |
323 | 46ddf551 | bellard | VM86_FAULT_RETURN; |
324 | 46ddf551 | bellard | |
325 | 46ddf551 | bellard | case 0xcd: /* int */ |
326 | b333af06 | bellard | intno = csp[ip]; |
327 | b333af06 | bellard | ADD16(ip, 1);
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328 | b333af06 | bellard | env->eip = ip; |
329 | b333af06 | bellard | if (ts->vm86plus.vm86plus.flags & TARGET_vm86dbg_active) {
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330 | b333af06 | bellard | if ( (ts->vm86plus.vm86plus.vm86dbg_intxxtab[intno >> 3] >> |
331 | b333af06 | bellard | (intno &7)) & 1) { |
332 | b333af06 | bellard | return_to_32bit(env, TARGET_VM86_INTx + (intno << 8));
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333 | b333af06 | bellard | return;
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334 | b333af06 | bellard | } |
335 | b333af06 | bellard | } |
336 | b333af06 | bellard | do_int(env, intno); |
337 | 46ddf551 | bellard | break;
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338 | 46ddf551 | bellard | |
339 | 46ddf551 | bellard | case 0xcf: /* iret */ |
340 | b333af06 | bellard | if (data32) {
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341 | b333af06 | bellard | newip = vm_getl(ssp, sp) & 0xffff;
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342 | b333af06 | bellard | newcs = vm_getl(ssp, sp + 4) & 0xffff; |
343 | b333af06 | bellard | newflags = vm_getl(ssp, sp + 8);
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344 | b333af06 | bellard | ADD16(env->regs[R_ESP], 12);
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345 | b333af06 | bellard | } else {
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346 | b333af06 | bellard | newip = vm_getw(ssp, sp); |
347 | b333af06 | bellard | newcs = vm_getw(ssp, sp + 2);
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348 | b333af06 | bellard | newflags = vm_getw(ssp, sp + 4);
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349 | b333af06 | bellard | ADD16(env->regs[R_ESP], 6);
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350 | b333af06 | bellard | } |
351 | b333af06 | bellard | env->eip = newip; |
352 | b333af06 | bellard | cpu_x86_load_seg(env, R_CS, newcs); |
353 | b333af06 | bellard | CHECK_IF_IN_TRAP(); |
354 | b333af06 | bellard | if (data32) {
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355 | b333af06 | bellard | if (set_vflags_long(newflags, env))
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356 | b333af06 | bellard | return;
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357 | b333af06 | bellard | } else {
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358 | b333af06 | bellard | if (set_vflags_short(newflags, env))
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359 | b333af06 | bellard | return;
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360 | b333af06 | bellard | } |
361 | 46ddf551 | bellard | VM86_FAULT_RETURN; |
362 | b333af06 | bellard | |
363 | 46ddf551 | bellard | case 0xfa: /* cli */ |
364 | b333af06 | bellard | env->eip = ip; |
365 | 46ddf551 | bellard | clear_IF(env); |
366 | 46ddf551 | bellard | VM86_FAULT_RETURN; |
367 | 46ddf551 | bellard | |
368 | 46ddf551 | bellard | case 0xfb: /* sti */ |
369 | b333af06 | bellard | env->eip = ip; |
370 | 46ddf551 | bellard | if (set_IF(env))
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371 | 46ddf551 | bellard | return;
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372 | 46ddf551 | bellard | VM86_FAULT_RETURN; |
373 | 46ddf551 | bellard | |
374 | 46ddf551 | bellard | default:
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375 | 46ddf551 | bellard | /* real VM86 GPF exception */
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376 | 46ddf551 | bellard | return_to_32bit(env, TARGET_VM86_UNKNOWN); |
377 | 46ddf551 | bellard | break;
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378 | 46ddf551 | bellard | } |
379 | 46ddf551 | bellard | } |
380 | 46ddf551 | bellard | |
381 | 46ddf551 | bellard | int do_vm86(CPUX86State *env, long subfunction, |
382 | 46ddf551 | bellard | struct target_vm86plus_struct * target_v86)
|
383 | 46ddf551 | bellard | { |
384 | 46ddf551 | bellard | TaskState *ts = env->opaque; |
385 | 46ddf551 | bellard | int ret;
|
386 | 46ddf551 | bellard | |
387 | 46ddf551 | bellard | switch (subfunction) {
|
388 | 46ddf551 | bellard | case TARGET_VM86_REQUEST_IRQ:
|
389 | 46ddf551 | bellard | case TARGET_VM86_FREE_IRQ:
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390 | 46ddf551 | bellard | case TARGET_VM86_GET_IRQ_BITS:
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391 | 46ddf551 | bellard | case TARGET_VM86_GET_AND_RESET_IRQ:
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392 | 46ddf551 | bellard | gemu_log("qemu: unsupported vm86 subfunction (%ld)\n", subfunction);
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393 | 46ddf551 | bellard | ret = -EINVAL; |
394 | 46ddf551 | bellard | goto out;
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395 | 46ddf551 | bellard | case TARGET_VM86_PLUS_INSTALL_CHECK:
|
396 | 46ddf551 | bellard | /* NOTE: on old vm86 stuff this will return the error
|
397 | 46ddf551 | bellard | from verify_area(), because the subfunction is
|
398 | 46ddf551 | bellard | interpreted as (invalid) address to vm86_struct.
|
399 | 46ddf551 | bellard | So the installation check works.
|
400 | 46ddf551 | bellard | */
|
401 | 46ddf551 | bellard | ret = 0;
|
402 | 46ddf551 | bellard | goto out;
|
403 | 46ddf551 | bellard | } |
404 | 46ddf551 | bellard | |
405 | 46ddf551 | bellard | ts->target_v86 = target_v86; |
406 | 46ddf551 | bellard | /* save current CPU regs */
|
407 | 46ddf551 | bellard | ts->vm86_saved_regs.eax = 0; /* default vm86 syscall return code */ |
408 | 46ddf551 | bellard | ts->vm86_saved_regs.ebx = env->regs[R_EBX]; |
409 | 46ddf551 | bellard | ts->vm86_saved_regs.ecx = env->regs[R_ECX]; |
410 | 46ddf551 | bellard | ts->vm86_saved_regs.edx = env->regs[R_EDX]; |
411 | 46ddf551 | bellard | ts->vm86_saved_regs.esi = env->regs[R_ESI]; |
412 | 46ddf551 | bellard | ts->vm86_saved_regs.edi = env->regs[R_EDI]; |
413 | 46ddf551 | bellard | ts->vm86_saved_regs.ebp = env->regs[R_EBP]; |
414 | 46ddf551 | bellard | ts->vm86_saved_regs.esp = env->regs[R_ESP]; |
415 | 46ddf551 | bellard | ts->vm86_saved_regs.eflags = env->eflags; |
416 | 46ddf551 | bellard | ts->vm86_saved_regs.eip = env->eip; |
417 | c05bab77 | bellard | ts->vm86_saved_regs.cs = env->segs[R_CS].selector; |
418 | c05bab77 | bellard | ts->vm86_saved_regs.ss = env->segs[R_SS].selector; |
419 | c05bab77 | bellard | ts->vm86_saved_regs.ds = env->segs[R_DS].selector; |
420 | c05bab77 | bellard | ts->vm86_saved_regs.es = env->segs[R_ES].selector; |
421 | c05bab77 | bellard | ts->vm86_saved_regs.fs = env->segs[R_FS].selector; |
422 | c05bab77 | bellard | ts->vm86_saved_regs.gs = env->segs[R_GS].selector; |
423 | 46ddf551 | bellard | |
424 | 46ddf551 | bellard | /* build vm86 CPU state */
|
425 | 46ddf551 | bellard | ts->v86flags = tswap32(target_v86->regs.eflags); |
426 | 46ddf551 | bellard | env->eflags = (env->eflags & ~SAFE_MASK) | |
427 | 46ddf551 | bellard | (tswap32(target_v86->regs.eflags) & SAFE_MASK) | VM_MASK; |
428 | b333af06 | bellard | |
429 | b333af06 | bellard | ts->vm86plus.cpu_type = tswapl(target_v86->cpu_type); |
430 | b333af06 | bellard | switch (ts->vm86plus.cpu_type) {
|
431 | b333af06 | bellard | case TARGET_CPU_286:
|
432 | b333af06 | bellard | ts->v86mask = 0;
|
433 | b333af06 | bellard | break;
|
434 | b333af06 | bellard | case TARGET_CPU_386:
|
435 | b333af06 | bellard | ts->v86mask = NT_MASK | IOPL_MASK; |
436 | b333af06 | bellard | break;
|
437 | b333af06 | bellard | case TARGET_CPU_486:
|
438 | b333af06 | bellard | ts->v86mask = AC_MASK | NT_MASK | IOPL_MASK; |
439 | b333af06 | bellard | break;
|
440 | b333af06 | bellard | default:
|
441 | b333af06 | bellard | ts->v86mask = ID_MASK | AC_MASK | NT_MASK | IOPL_MASK; |
442 | b333af06 | bellard | break;
|
443 | b333af06 | bellard | } |
444 | 46ddf551 | bellard | |
445 | 46ddf551 | bellard | env->regs[R_EBX] = tswap32(target_v86->regs.ebx); |
446 | 46ddf551 | bellard | env->regs[R_ECX] = tswap32(target_v86->regs.ecx); |
447 | 46ddf551 | bellard | env->regs[R_EDX] = tswap32(target_v86->regs.edx); |
448 | 46ddf551 | bellard | env->regs[R_ESI] = tswap32(target_v86->regs.esi); |
449 | 46ddf551 | bellard | env->regs[R_EDI] = tswap32(target_v86->regs.edi); |
450 | 46ddf551 | bellard | env->regs[R_EBP] = tswap32(target_v86->regs.ebp); |
451 | 46ddf551 | bellard | env->regs[R_ESP] = tswap32(target_v86->regs.esp); |
452 | 46ddf551 | bellard | env->eip = tswap32(target_v86->regs.eip); |
453 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_CS, tswap16(target_v86->regs.cs)); |
454 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_SS, tswap16(target_v86->regs.ss)); |
455 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_DS, tswap16(target_v86->regs.ds)); |
456 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_ES, tswap16(target_v86->regs.es)); |
457 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_FS, tswap16(target_v86->regs.fs)); |
458 | 46ddf551 | bellard | cpu_x86_load_seg(env, R_GS, tswap16(target_v86->regs.gs)); |
459 | 46ddf551 | bellard | ret = tswap32(target_v86->regs.eax); /* eax will be restored at
|
460 | 46ddf551 | bellard | the end of the syscall */
|
461 | b333af06 | bellard | memcpy(&ts->vm86plus.int_revectored, |
462 | b333af06 | bellard | &target_v86->int_revectored, 32);
|
463 | b333af06 | bellard | memcpy(&ts->vm86plus.int21_revectored, |
464 | b333af06 | bellard | &target_v86->int21_revectored, 32);
|
465 | b333af06 | bellard | ts->vm86plus.vm86plus.flags = tswapl(target_v86->vm86plus.flags); |
466 | b333af06 | bellard | memcpy(&ts->vm86plus.vm86plus.vm86dbg_intxxtab, |
467 | b333af06 | bellard | target_v86->vm86plus.vm86dbg_intxxtab, 32);
|
468 | b333af06 | bellard | |
469 | 46ddf551 | bellard | #ifdef DEBUG_VM86
|
470 | c05bab77 | bellard | fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n",
|
471 | c05bab77 | bellard | env->segs[R_CS].selector, env->eip); |
472 | 46ddf551 | bellard | #endif
|
473 | 46ddf551 | bellard | /* now the virtual CPU is ready for vm86 execution ! */
|
474 | 46ddf551 | bellard | out:
|
475 | 46ddf551 | bellard | return ret;
|
476 | 46ddf551 | bellard | } |