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1 | 2c0262af | bellard | /*
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2 | 2c0262af | bellard | * ARM micro operations
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3 | 2c0262af | bellard | *
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4 | 2c0262af | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | b7bcbe95 | bellard | * Copyright (c) 2005 CodeSourcery, LLC
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6 | 2c0262af | bellard | *
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7 | 2c0262af | bellard | * This library is free software; you can redistribute it and/or
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8 | 2c0262af | bellard | * modify it under the terms of the GNU Lesser General Public
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9 | 2c0262af | bellard | * License as published by the Free Software Foundation; either
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10 | 2c0262af | bellard | * version 2 of the License, or (at your option) any later version.
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11 | 2c0262af | bellard | *
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12 | 2c0262af | bellard | * This library is distributed in the hope that it will be useful,
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13 | 2c0262af | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | 2c0262af | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | 2c0262af | bellard | * Lesser General Public License for more details.
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16 | 2c0262af | bellard | *
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17 | 2c0262af | bellard | * You should have received a copy of the GNU Lesser General Public
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18 | 2c0262af | bellard | * License along with this library; if not, write to the Free Software
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19 | 2c0262af | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | 2c0262af | bellard | */
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21 | 2c0262af | bellard | #include "exec.h" |
22 | 2c0262af | bellard | |
23 | 2c0262af | bellard | #define REGNAME r0
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24 | 2c0262af | bellard | #define REG (env->regs[0]) |
25 | 2c0262af | bellard | #include "op_template.h" |
26 | 2c0262af | bellard | |
27 | 2c0262af | bellard | #define REGNAME r1
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28 | 2c0262af | bellard | #define REG (env->regs[1]) |
29 | 2c0262af | bellard | #include "op_template.h" |
30 | 2c0262af | bellard | |
31 | 2c0262af | bellard | #define REGNAME r2
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32 | 2c0262af | bellard | #define REG (env->regs[2]) |
33 | 2c0262af | bellard | #include "op_template.h" |
34 | 2c0262af | bellard | |
35 | 2c0262af | bellard | #define REGNAME r3
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36 | 2c0262af | bellard | #define REG (env->regs[3]) |
37 | 2c0262af | bellard | #include "op_template.h" |
38 | 2c0262af | bellard | |
39 | 2c0262af | bellard | #define REGNAME r4
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40 | 2c0262af | bellard | #define REG (env->regs[4]) |
41 | 2c0262af | bellard | #include "op_template.h" |
42 | 2c0262af | bellard | |
43 | 2c0262af | bellard | #define REGNAME r5
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44 | 2c0262af | bellard | #define REG (env->regs[5]) |
45 | 2c0262af | bellard | #include "op_template.h" |
46 | 2c0262af | bellard | |
47 | 2c0262af | bellard | #define REGNAME r6
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48 | 2c0262af | bellard | #define REG (env->regs[6]) |
49 | 2c0262af | bellard | #include "op_template.h" |
50 | 2c0262af | bellard | |
51 | 2c0262af | bellard | #define REGNAME r7
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52 | 2c0262af | bellard | #define REG (env->regs[7]) |
53 | 2c0262af | bellard | #include "op_template.h" |
54 | 2c0262af | bellard | |
55 | 2c0262af | bellard | #define REGNAME r8
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56 | 2c0262af | bellard | #define REG (env->regs[8]) |
57 | 2c0262af | bellard | #include "op_template.h" |
58 | 2c0262af | bellard | |
59 | 2c0262af | bellard | #define REGNAME r9
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60 | 2c0262af | bellard | #define REG (env->regs[9]) |
61 | 2c0262af | bellard | #include "op_template.h" |
62 | 2c0262af | bellard | |
63 | 2c0262af | bellard | #define REGNAME r10
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64 | 2c0262af | bellard | #define REG (env->regs[10]) |
65 | 2c0262af | bellard | #include "op_template.h" |
66 | 2c0262af | bellard | |
67 | 2c0262af | bellard | #define REGNAME r11
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68 | 2c0262af | bellard | #define REG (env->regs[11]) |
69 | 2c0262af | bellard | #include "op_template.h" |
70 | 2c0262af | bellard | |
71 | 2c0262af | bellard | #define REGNAME r12
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72 | 2c0262af | bellard | #define REG (env->regs[12]) |
73 | 2c0262af | bellard | #include "op_template.h" |
74 | 2c0262af | bellard | |
75 | 2c0262af | bellard | #define REGNAME r13
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76 | 2c0262af | bellard | #define REG (env->regs[13]) |
77 | 2c0262af | bellard | #include "op_template.h" |
78 | 2c0262af | bellard | |
79 | 2c0262af | bellard | #define REGNAME r14
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80 | 2c0262af | bellard | #define REG (env->regs[14]) |
81 | 2c0262af | bellard | #include "op_template.h" |
82 | 2c0262af | bellard | |
83 | 2c0262af | bellard | #define REGNAME r15
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84 | 2c0262af | bellard | #define REG (env->regs[15]) |
85 | 99c475ab | bellard | #define SET_REG(x) REG = x & ~(uint32_t)1 |
86 | 2c0262af | bellard | #include "op_template.h" |
87 | 2c0262af | bellard | |
88 | 99c475ab | bellard | void OPPROTO op_bx_T0(void) |
89 | 99c475ab | bellard | { |
90 | 99c475ab | bellard | env->regs[15] = T0 & ~(uint32_t)1; |
91 | 99c475ab | bellard | env->thumb = (T0 & 1) != 0; |
92 | 99c475ab | bellard | } |
93 | 99c475ab | bellard | |
94 | 2c0262af | bellard | void OPPROTO op_movl_T0_0(void) |
95 | 2c0262af | bellard | { |
96 | 2c0262af | bellard | T0 = 0;
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97 | 2c0262af | bellard | } |
98 | 2c0262af | bellard | |
99 | 2c0262af | bellard | void OPPROTO op_movl_T0_im(void) |
100 | 2c0262af | bellard | { |
101 | 2c0262af | bellard | T0 = PARAM1; |
102 | 2c0262af | bellard | } |
103 | 2c0262af | bellard | |
104 | 2c0262af | bellard | void OPPROTO op_movl_T1_im(void) |
105 | 2c0262af | bellard | { |
106 | 2c0262af | bellard | T1 = PARAM1; |
107 | 2c0262af | bellard | } |
108 | 2c0262af | bellard | |
109 | 7ff4d218 | bellard | void OPPROTO op_mov_CF_T1(void) |
110 | 7ff4d218 | bellard | { |
111 | 7ff4d218 | bellard | env->CF = ((uint32_t)T1) >> 31;
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112 | 7ff4d218 | bellard | } |
113 | 7ff4d218 | bellard | |
114 | 2c0262af | bellard | void OPPROTO op_movl_T2_im(void) |
115 | 2c0262af | bellard | { |
116 | 2c0262af | bellard | T2 = PARAM1; |
117 | 2c0262af | bellard | } |
118 | 2c0262af | bellard | |
119 | 2c0262af | bellard | void OPPROTO op_addl_T1_im(void) |
120 | 2c0262af | bellard | { |
121 | 2c0262af | bellard | T1 += PARAM1; |
122 | 2c0262af | bellard | } |
123 | 2c0262af | bellard | |
124 | 2c0262af | bellard | void OPPROTO op_addl_T1_T2(void) |
125 | 2c0262af | bellard | { |
126 | 2c0262af | bellard | T1 += T2; |
127 | 2c0262af | bellard | } |
128 | 2c0262af | bellard | |
129 | 2c0262af | bellard | void OPPROTO op_subl_T1_T2(void) |
130 | 2c0262af | bellard | { |
131 | 2c0262af | bellard | T1 -= T2; |
132 | 2c0262af | bellard | } |
133 | 2c0262af | bellard | |
134 | 2c0262af | bellard | void OPPROTO op_addl_T0_T1(void) |
135 | 2c0262af | bellard | { |
136 | 2c0262af | bellard | T0 += T1; |
137 | 2c0262af | bellard | } |
138 | 2c0262af | bellard | |
139 | 2c0262af | bellard | void OPPROTO op_addl_T0_T1_cc(void) |
140 | 2c0262af | bellard | { |
141 | 2c0262af | bellard | unsigned int src1; |
142 | 2c0262af | bellard | src1 = T0; |
143 | 2c0262af | bellard | T0 += T1; |
144 | 2c0262af | bellard | env->NZF = T0; |
145 | 2c0262af | bellard | env->CF = T0 < src1; |
146 | 2c0262af | bellard | env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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147 | 2c0262af | bellard | } |
148 | 2c0262af | bellard | |
149 | 2c0262af | bellard | void OPPROTO op_adcl_T0_T1(void) |
150 | 2c0262af | bellard | { |
151 | 2c0262af | bellard | T0 += T1 + env->CF; |
152 | 2c0262af | bellard | } |
153 | 2c0262af | bellard | |
154 | 2c0262af | bellard | void OPPROTO op_adcl_T0_T1_cc(void) |
155 | 2c0262af | bellard | { |
156 | 2c0262af | bellard | unsigned int src1; |
157 | 2c0262af | bellard | src1 = T0; |
158 | 2c0262af | bellard | if (!env->CF) {
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159 | 2c0262af | bellard | T0 += T1; |
160 | 2c0262af | bellard | env->CF = T0 < src1; |
161 | 2c0262af | bellard | } else {
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162 | 2c0262af | bellard | T0 += T1 + 1;
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163 | 2c0262af | bellard | env->CF = T0 <= src1; |
164 | 2c0262af | bellard | } |
165 | 2c0262af | bellard | env->VF = (src1 ^ T1 ^ -1) & (src1 ^ T0);
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166 | 2c0262af | bellard | env->NZF = T0; |
167 | 2c0262af | bellard | FORCE_RET(); |
168 | 2c0262af | bellard | } |
169 | 2c0262af | bellard | |
170 | 2c0262af | bellard | #define OPSUB(sub, sbc, res, T0, T1) \
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171 | 2c0262af | bellard | \ |
172 | 2c0262af | bellard | void OPPROTO op_ ## sub ## l_T0_T1(void) \ |
173 | 2c0262af | bellard | { \ |
174 | 2c0262af | bellard | res = T0 - T1; \ |
175 | 2c0262af | bellard | } \ |
176 | 2c0262af | bellard | \ |
177 | 2c0262af | bellard | void OPPROTO op_ ## sub ## l_T0_T1_cc(void) \ |
178 | 2c0262af | bellard | { \ |
179 | 2c0262af | bellard | unsigned int src1; \ |
180 | 2c0262af | bellard | src1 = T0; \ |
181 | 2c0262af | bellard | T0 -= T1; \ |
182 | 2c0262af | bellard | env->NZF = T0; \ |
183 | 2c0262af | bellard | env->CF = src1 >= T1; \ |
184 | 2c0262af | bellard | env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
185 | 2c0262af | bellard | res = T0; \ |
186 | 2c0262af | bellard | } \ |
187 | 2c0262af | bellard | \ |
188 | 2c0262af | bellard | void OPPROTO op_ ## sbc ## l_T0_T1(void) \ |
189 | 2c0262af | bellard | { \ |
190 | 2c0262af | bellard | res = T0 - T1 + env->CF - 1; \
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191 | 2c0262af | bellard | } \ |
192 | 2c0262af | bellard | \ |
193 | 2c0262af | bellard | void OPPROTO op_ ## sbc ## l_T0_T1_cc(void) \ |
194 | 2c0262af | bellard | { \ |
195 | 2c0262af | bellard | unsigned int src1; \ |
196 | 2c0262af | bellard | src1 = T0; \ |
197 | 2c0262af | bellard | if (!env->CF) { \
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198 | 2c0262af | bellard | T0 = T0 - T1 - 1; \
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199 | 78573df6 | bellard | env->CF = src1 > T1; \ |
200 | 2c0262af | bellard | } else { \
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201 | 2c0262af | bellard | T0 = T0 - T1; \ |
202 | 78573df6 | bellard | env->CF = src1 >= T1; \ |
203 | 2c0262af | bellard | } \ |
204 | 2c0262af | bellard | env->VF = (src1 ^ T1) & (src1 ^ T0); \ |
205 | 2c0262af | bellard | env->NZF = T0; \ |
206 | 2c0262af | bellard | res = T0; \ |
207 | 2c0262af | bellard | FORCE_RET(); \ |
208 | 2c0262af | bellard | } |
209 | 2c0262af | bellard | |
210 | 2c0262af | bellard | OPSUB(sub, sbc, T0, T0, T1) |
211 | 2c0262af | bellard | |
212 | 2c0262af | bellard | OPSUB(rsb, rsc, T0, T1, T0) |
213 | 2c0262af | bellard | |
214 | 2c0262af | bellard | void OPPROTO op_andl_T0_T1(void) |
215 | 2c0262af | bellard | { |
216 | 2c0262af | bellard | T0 &= T1; |
217 | 2c0262af | bellard | } |
218 | 2c0262af | bellard | |
219 | 2c0262af | bellard | void OPPROTO op_xorl_T0_T1(void) |
220 | 2c0262af | bellard | { |
221 | 2c0262af | bellard | T0 ^= T1; |
222 | 2c0262af | bellard | } |
223 | 2c0262af | bellard | |
224 | 2c0262af | bellard | void OPPROTO op_orl_T0_T1(void) |
225 | 2c0262af | bellard | { |
226 | 2c0262af | bellard | T0 |= T1; |
227 | 2c0262af | bellard | } |
228 | 2c0262af | bellard | |
229 | 2c0262af | bellard | void OPPROTO op_bicl_T0_T1(void) |
230 | 2c0262af | bellard | { |
231 | 2c0262af | bellard | T0 &= ~T1; |
232 | 2c0262af | bellard | } |
233 | 2c0262af | bellard | |
234 | 2c0262af | bellard | void OPPROTO op_notl_T1(void) |
235 | 2c0262af | bellard | { |
236 | 2c0262af | bellard | T1 = ~T1; |
237 | 2c0262af | bellard | } |
238 | 2c0262af | bellard | |
239 | 2c0262af | bellard | void OPPROTO op_logic_T0_cc(void) |
240 | 2c0262af | bellard | { |
241 | 2c0262af | bellard | env->NZF = T0; |
242 | 2c0262af | bellard | } |
243 | 2c0262af | bellard | |
244 | 2c0262af | bellard | void OPPROTO op_logic_T1_cc(void) |
245 | 2c0262af | bellard | { |
246 | 2c0262af | bellard | env->NZF = T1; |
247 | 2c0262af | bellard | } |
248 | 2c0262af | bellard | |
249 | 2c0262af | bellard | #define EIP (env->regs[15]) |
250 | 2c0262af | bellard | |
251 | 2c0262af | bellard | void OPPROTO op_test_eq(void) |
252 | 2c0262af | bellard | { |
253 | 2c0262af | bellard | if (env->NZF == 0) |
254 | 2c0262af | bellard | JUMP_TB(op_test_eq, PARAM1, 0, PARAM2);
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255 | 2c0262af | bellard | FORCE_RET(); |
256 | 2c0262af | bellard | } |
257 | 2c0262af | bellard | |
258 | 2c0262af | bellard | void OPPROTO op_test_ne(void) |
259 | 2c0262af | bellard | { |
260 | 2c0262af | bellard | if (env->NZF != 0) |
261 | 2c0262af | bellard | JUMP_TB(op_test_ne, PARAM1, 0, PARAM2);
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262 | 2c0262af | bellard | FORCE_RET(); |
263 | 2c0262af | bellard | } |
264 | 2c0262af | bellard | |
265 | 2c0262af | bellard | void OPPROTO op_test_cs(void) |
266 | 2c0262af | bellard | { |
267 | 2c0262af | bellard | if (env->CF != 0) |
268 | 2c0262af | bellard | JUMP_TB(op_test_cs, PARAM1, 0, PARAM2);
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269 | 2c0262af | bellard | FORCE_RET(); |
270 | 2c0262af | bellard | } |
271 | 2c0262af | bellard | |
272 | 2c0262af | bellard | void OPPROTO op_test_cc(void) |
273 | 2c0262af | bellard | { |
274 | 2c0262af | bellard | if (env->CF == 0) |
275 | 2c0262af | bellard | JUMP_TB(op_test_cc, PARAM1, 0, PARAM2);
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276 | 2c0262af | bellard | FORCE_RET(); |
277 | 2c0262af | bellard | } |
278 | 2c0262af | bellard | |
279 | 2c0262af | bellard | void OPPROTO op_test_mi(void) |
280 | 2c0262af | bellard | { |
281 | 2c0262af | bellard | if ((env->NZF & 0x80000000) != 0) |
282 | 2c0262af | bellard | JUMP_TB(op_test_mi, PARAM1, 0, PARAM2);
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283 | 2c0262af | bellard | FORCE_RET(); |
284 | 2c0262af | bellard | } |
285 | 2c0262af | bellard | |
286 | 2c0262af | bellard | void OPPROTO op_test_pl(void) |
287 | 2c0262af | bellard | { |
288 | 2c0262af | bellard | if ((env->NZF & 0x80000000) == 0) |
289 | 2c0262af | bellard | JUMP_TB(op_test_pl, PARAM1, 0, PARAM2);
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290 | 2c0262af | bellard | FORCE_RET(); |
291 | 2c0262af | bellard | } |
292 | 2c0262af | bellard | |
293 | 2c0262af | bellard | void OPPROTO op_test_vs(void) |
294 | 2c0262af | bellard | { |
295 | 2c0262af | bellard | if ((env->VF & 0x80000000) != 0) |
296 | 2c0262af | bellard | JUMP_TB(op_test_vs, PARAM1, 0, PARAM2);
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297 | 2c0262af | bellard | FORCE_RET(); |
298 | 2c0262af | bellard | } |
299 | 2c0262af | bellard | |
300 | 2c0262af | bellard | void OPPROTO op_test_vc(void) |
301 | 2c0262af | bellard | { |
302 | 2c0262af | bellard | if ((env->VF & 0x80000000) == 0) |
303 | 2c0262af | bellard | JUMP_TB(op_test_vc, PARAM1, 0, PARAM2);
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304 | 2c0262af | bellard | FORCE_RET(); |
305 | 2c0262af | bellard | } |
306 | 2c0262af | bellard | |
307 | 2c0262af | bellard | void OPPROTO op_test_hi(void) |
308 | 2c0262af | bellard | { |
309 | 2c0262af | bellard | if (env->CF != 0 && env->NZF != 0) |
310 | 2c0262af | bellard | JUMP_TB(op_test_hi, PARAM1, 0, PARAM2);
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311 | 2c0262af | bellard | FORCE_RET(); |
312 | 2c0262af | bellard | } |
313 | 2c0262af | bellard | |
314 | 2c0262af | bellard | void OPPROTO op_test_ls(void) |
315 | 2c0262af | bellard | { |
316 | 2c0262af | bellard | if (env->CF == 0 || env->NZF == 0) |
317 | 2c0262af | bellard | JUMP_TB(op_test_ls, PARAM1, 0, PARAM2);
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318 | 2c0262af | bellard | FORCE_RET(); |
319 | 2c0262af | bellard | } |
320 | 2c0262af | bellard | |
321 | 2c0262af | bellard | void OPPROTO op_test_ge(void) |
322 | 2c0262af | bellard | { |
323 | 2c0262af | bellard | if (((env->VF ^ env->NZF) & 0x80000000) == 0) |
324 | 2c0262af | bellard | JUMP_TB(op_test_ge, PARAM1, 0, PARAM2);
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325 | 2c0262af | bellard | FORCE_RET(); |
326 | 2c0262af | bellard | } |
327 | 2c0262af | bellard | |
328 | 2c0262af | bellard | void OPPROTO op_test_lt(void) |
329 | 2c0262af | bellard | { |
330 | 2c0262af | bellard | if (((env->VF ^ env->NZF) & 0x80000000) != 0) |
331 | 2c0262af | bellard | JUMP_TB(op_test_lt, PARAM1, 0, PARAM2);
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332 | 2c0262af | bellard | FORCE_RET(); |
333 | 2c0262af | bellard | } |
334 | 2c0262af | bellard | |
335 | 2c0262af | bellard | void OPPROTO op_test_gt(void) |
336 | 2c0262af | bellard | { |
337 | 2c0262af | bellard | if (env->NZF != 0 && ((env->VF ^ env->NZF) & 0x80000000) == 0) |
338 | 2c0262af | bellard | JUMP_TB(op_test_gt, PARAM1, 0, PARAM2);
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339 | 2c0262af | bellard | FORCE_RET(); |
340 | 2c0262af | bellard | } |
341 | 2c0262af | bellard | |
342 | 2c0262af | bellard | void OPPROTO op_test_le(void) |
343 | 2c0262af | bellard | { |
344 | 2c0262af | bellard | if (env->NZF == 0 || ((env->VF ^ env->NZF) & 0x80000000) != 0) |
345 | 2c0262af | bellard | JUMP_TB(op_test_le, PARAM1, 0, PARAM2);
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346 | 2c0262af | bellard | FORCE_RET(); |
347 | 2c0262af | bellard | } |
348 | 2c0262af | bellard | |
349 | 2c0262af | bellard | void OPPROTO op_jmp(void) |
350 | 2c0262af | bellard | { |
351 | 2c0262af | bellard | JUMP_TB(op_jmp, PARAM1, 1, PARAM2);
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352 | 2c0262af | bellard | } |
353 | 2c0262af | bellard | |
354 | 2c0262af | bellard | void OPPROTO op_exit_tb(void) |
355 | 2c0262af | bellard | { |
356 | 2c0262af | bellard | EXIT_TB(); |
357 | 2c0262af | bellard | } |
358 | 2c0262af | bellard | |
359 | 2c0262af | bellard | void OPPROTO op_movl_T0_psr(void) |
360 | 2c0262af | bellard | { |
361 | 2c0262af | bellard | T0 = compute_cpsr(); |
362 | 2c0262af | bellard | } |
363 | 2c0262af | bellard | |
364 | 2c0262af | bellard | /* NOTE: N = 1 and Z = 1 cannot be stored currently */
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365 | 2c0262af | bellard | void OPPROTO op_movl_psr_T0(void) |
366 | 2c0262af | bellard | { |
367 | 2c0262af | bellard | unsigned int psr; |
368 | 2c0262af | bellard | psr = T0; |
369 | 2c0262af | bellard | env->CF = (psr >> 29) & 1; |
370 | 2c0262af | bellard | env->NZF = (psr & 0xc0000000) ^ 0x40000000; |
371 | 2c0262af | bellard | env->VF = (psr << 3) & 0x80000000; |
372 | 2c0262af | bellard | /* for user mode we do not update other state info */
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373 | 2c0262af | bellard | } |
374 | 2c0262af | bellard | |
375 | 2c0262af | bellard | void OPPROTO op_mul_T0_T1(void) |
376 | 2c0262af | bellard | { |
377 | 2c0262af | bellard | T0 = T0 * T1; |
378 | 2c0262af | bellard | } |
379 | 2c0262af | bellard | |
380 | 2c0262af | bellard | /* 64 bit unsigned mul */
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381 | 2c0262af | bellard | void OPPROTO op_mull_T0_T1(void) |
382 | 2c0262af | bellard | { |
383 | 2c0262af | bellard | uint64_t res; |
384 | 2e134c9c | bellard | res = (uint64_t)T0 * (uint64_t)T1; |
385 | 2c0262af | bellard | T1 = res >> 32;
|
386 | 2c0262af | bellard | T0 = res; |
387 | 2c0262af | bellard | } |
388 | 2c0262af | bellard | |
389 | 2c0262af | bellard | /* 64 bit signed mul */
|
390 | 2c0262af | bellard | void OPPROTO op_imull_T0_T1(void) |
391 | 2c0262af | bellard | { |
392 | 2c0262af | bellard | uint64_t res; |
393 | 163a7cb6 | bellard | res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
394 | 2c0262af | bellard | T1 = res >> 32;
|
395 | 2c0262af | bellard | T0 = res; |
396 | 2c0262af | bellard | } |
397 | 2c0262af | bellard | |
398 | 99c475ab | bellard | /* 48 bit signed mul, top 32 bits */
|
399 | 99c475ab | bellard | void OPPROTO op_imulw_T0_T1(void) |
400 | 99c475ab | bellard | { |
401 | 99c475ab | bellard | uint64_t res; |
402 | 99c475ab | bellard | res = (int64_t)((int32_t)T0) * (int64_t)((int32_t)T1); |
403 | 99c475ab | bellard | T0 = res >> 16;
|
404 | 99c475ab | bellard | } |
405 | 99c475ab | bellard | |
406 | 2c0262af | bellard | void OPPROTO op_addq_T0_T1(void) |
407 | 2c0262af | bellard | { |
408 | 2c0262af | bellard | uint64_t res; |
409 | 2c0262af | bellard | res = ((uint64_t)T1 << 32) | T0;
|
410 | 2c0262af | bellard | res += ((uint64_t)(env->regs[PARAM2]) << 32) | (env->regs[PARAM1]);
|
411 | 2c0262af | bellard | T1 = res >> 32;
|
412 | 2c0262af | bellard | T0 = res; |
413 | 2c0262af | bellard | } |
414 | 2c0262af | bellard | |
415 | 99c475ab | bellard | void OPPROTO op_addq_lo_T0_T1(void) |
416 | 99c475ab | bellard | { |
417 | 99c475ab | bellard | uint64_t res; |
418 | 99c475ab | bellard | res = ((uint64_t)T1 << 32) | T0;
|
419 | 99c475ab | bellard | res += (uint64_t)(env->regs[PARAM1]); |
420 | 99c475ab | bellard | T1 = res >> 32;
|
421 | 99c475ab | bellard | T0 = res; |
422 | 99c475ab | bellard | } |
423 | 99c475ab | bellard | |
424 | 2c0262af | bellard | void OPPROTO op_logicq_cc(void) |
425 | 2c0262af | bellard | { |
426 | 2c0262af | bellard | env->NZF = (T1 & 0x80000000) | ((T0 | T1) != 0); |
427 | 2c0262af | bellard | } |
428 | 2c0262af | bellard | |
429 | 2c0262af | bellard | /* memory access */
|
430 | 2c0262af | bellard | |
431 | 2c0262af | bellard | void OPPROTO op_ldub_T0_T1(void) |
432 | 2c0262af | bellard | { |
433 | 2c0262af | bellard | T0 = ldub((void *)T1);
|
434 | 2c0262af | bellard | } |
435 | 2c0262af | bellard | |
436 | 2c0262af | bellard | void OPPROTO op_ldsb_T0_T1(void) |
437 | 2c0262af | bellard | { |
438 | 2c0262af | bellard | T0 = ldsb((void *)T1);
|
439 | 2c0262af | bellard | } |
440 | 2c0262af | bellard | |
441 | 2c0262af | bellard | void OPPROTO op_lduw_T0_T1(void) |
442 | 2c0262af | bellard | { |
443 | 2c0262af | bellard | T0 = lduw((void *)T1);
|
444 | 2c0262af | bellard | } |
445 | 2c0262af | bellard | |
446 | 2c0262af | bellard | void OPPROTO op_ldsw_T0_T1(void) |
447 | 2c0262af | bellard | { |
448 | 2c0262af | bellard | T0 = ldsw((void *)T1);
|
449 | 2c0262af | bellard | } |
450 | 2c0262af | bellard | |
451 | 2c0262af | bellard | void OPPROTO op_ldl_T0_T1(void) |
452 | 2c0262af | bellard | { |
453 | 2c0262af | bellard | T0 = ldl((void *)T1);
|
454 | 2c0262af | bellard | } |
455 | 2c0262af | bellard | |
456 | 2c0262af | bellard | void OPPROTO op_stb_T0_T1(void) |
457 | 2c0262af | bellard | { |
458 | 2c0262af | bellard | stb((void *)T1, T0);
|
459 | 2c0262af | bellard | } |
460 | 2c0262af | bellard | |
461 | 2c0262af | bellard | void OPPROTO op_stw_T0_T1(void) |
462 | 2c0262af | bellard | { |
463 | 2c0262af | bellard | stw((void *)T1, T0);
|
464 | 2c0262af | bellard | } |
465 | 2c0262af | bellard | |
466 | 2c0262af | bellard | void OPPROTO op_stl_T0_T1(void) |
467 | 2c0262af | bellard | { |
468 | 2c0262af | bellard | stl((void *)T1, T0);
|
469 | 2c0262af | bellard | } |
470 | 2c0262af | bellard | |
471 | 2c0262af | bellard | void OPPROTO op_swpb_T0_T1(void) |
472 | 2c0262af | bellard | { |
473 | 2c0262af | bellard | int tmp;
|
474 | 2c0262af | bellard | |
475 | 2c0262af | bellard | cpu_lock(); |
476 | 2c0262af | bellard | tmp = ldub((void *)T1);
|
477 | 2c0262af | bellard | stb((void *)T1, T0);
|
478 | 2c0262af | bellard | T0 = tmp; |
479 | 2c0262af | bellard | cpu_unlock(); |
480 | 2c0262af | bellard | } |
481 | 2c0262af | bellard | |
482 | 2c0262af | bellard | void OPPROTO op_swpl_T0_T1(void) |
483 | 2c0262af | bellard | { |
484 | 2c0262af | bellard | int tmp;
|
485 | 2c0262af | bellard | |
486 | 2c0262af | bellard | cpu_lock(); |
487 | 2c0262af | bellard | tmp = ldl((void *)T1);
|
488 | 2c0262af | bellard | stl((void *)T1, T0);
|
489 | 2c0262af | bellard | T0 = tmp; |
490 | 2c0262af | bellard | cpu_unlock(); |
491 | 2c0262af | bellard | } |
492 | 2c0262af | bellard | |
493 | 2c0262af | bellard | /* shifts */
|
494 | 2c0262af | bellard | |
495 | 2c0262af | bellard | /* T1 based */
|
496 | 1e8d4eec | bellard | |
497 | 2c0262af | bellard | void OPPROTO op_shll_T1_im(void) |
498 | 2c0262af | bellard | { |
499 | 2c0262af | bellard | T1 = T1 << PARAM1; |
500 | 2c0262af | bellard | } |
501 | 2c0262af | bellard | |
502 | 2c0262af | bellard | void OPPROTO op_shrl_T1_im(void) |
503 | 2c0262af | bellard | { |
504 | 2c0262af | bellard | T1 = (uint32_t)T1 >> PARAM1; |
505 | 2c0262af | bellard | } |
506 | 2c0262af | bellard | |
507 | 1e8d4eec | bellard | void OPPROTO op_shrl_T1_0(void) |
508 | 1e8d4eec | bellard | { |
509 | 1e8d4eec | bellard | T1 = 0;
|
510 | 1e8d4eec | bellard | } |
511 | 1e8d4eec | bellard | |
512 | 2c0262af | bellard | void OPPROTO op_sarl_T1_im(void) |
513 | 2c0262af | bellard | { |
514 | 2c0262af | bellard | T1 = (int32_t)T1 >> PARAM1; |
515 | 2c0262af | bellard | } |
516 | 2c0262af | bellard | |
517 | 1e8d4eec | bellard | void OPPROTO op_sarl_T1_0(void) |
518 | 1e8d4eec | bellard | { |
519 | 1e8d4eec | bellard | T1 = (int32_t)T1 >> 31;
|
520 | 1e8d4eec | bellard | } |
521 | 1e8d4eec | bellard | |
522 | 2c0262af | bellard | void OPPROTO op_rorl_T1_im(void) |
523 | 2c0262af | bellard | { |
524 | 2c0262af | bellard | int shift;
|
525 | 2c0262af | bellard | shift = PARAM1; |
526 | 2c0262af | bellard | T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
527 | 2c0262af | bellard | } |
528 | 2c0262af | bellard | |
529 | 88920f34 | bellard | void OPPROTO op_rrxl_T1(void) |
530 | 88920f34 | bellard | { |
531 | 88920f34 | bellard | T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); |
532 | 88920f34 | bellard | } |
533 | 88920f34 | bellard | |
534 | 2c0262af | bellard | /* T1 based, set C flag */
|
535 | 2c0262af | bellard | void OPPROTO op_shll_T1_im_cc(void) |
536 | 2c0262af | bellard | { |
537 | 2c0262af | bellard | env->CF = (T1 >> (32 - PARAM1)) & 1; |
538 | 2c0262af | bellard | T1 = T1 << PARAM1; |
539 | 2c0262af | bellard | } |
540 | 2c0262af | bellard | |
541 | 2c0262af | bellard | void OPPROTO op_shrl_T1_im_cc(void) |
542 | 2c0262af | bellard | { |
543 | 2c0262af | bellard | env->CF = (T1 >> (PARAM1 - 1)) & 1; |
544 | 2c0262af | bellard | T1 = (uint32_t)T1 >> PARAM1; |
545 | 2c0262af | bellard | } |
546 | 2c0262af | bellard | |
547 | 1e8d4eec | bellard | void OPPROTO op_shrl_T1_0_cc(void) |
548 | 1e8d4eec | bellard | { |
549 | 1e8d4eec | bellard | env->CF = (T1 >> 31) & 1; |
550 | 1e8d4eec | bellard | T1 = 0;
|
551 | 1e8d4eec | bellard | } |
552 | 1e8d4eec | bellard | |
553 | 2c0262af | bellard | void OPPROTO op_sarl_T1_im_cc(void) |
554 | 2c0262af | bellard | { |
555 | 2c0262af | bellard | env->CF = (T1 >> (PARAM1 - 1)) & 1; |
556 | 2c0262af | bellard | T1 = (int32_t)T1 >> PARAM1; |
557 | 2c0262af | bellard | } |
558 | 2c0262af | bellard | |
559 | 1e8d4eec | bellard | void OPPROTO op_sarl_T1_0_cc(void) |
560 | 1e8d4eec | bellard | { |
561 | 1e8d4eec | bellard | env->CF = (T1 >> 31) & 1; |
562 | 1e8d4eec | bellard | T1 = (int32_t)T1 >> 31;
|
563 | 1e8d4eec | bellard | } |
564 | 1e8d4eec | bellard | |
565 | 2c0262af | bellard | void OPPROTO op_rorl_T1_im_cc(void) |
566 | 2c0262af | bellard | { |
567 | 2c0262af | bellard | int shift;
|
568 | 2c0262af | bellard | shift = PARAM1; |
569 | 2c0262af | bellard | env->CF = (T1 >> (shift - 1)) & 1; |
570 | 2c0262af | bellard | T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
571 | 2c0262af | bellard | } |
572 | 2c0262af | bellard | |
573 | 88920f34 | bellard | void OPPROTO op_rrxl_T1_cc(void) |
574 | 88920f34 | bellard | { |
575 | 88920f34 | bellard | uint32_t c; |
576 | 88920f34 | bellard | c = T1 & 1;
|
577 | 88920f34 | bellard | T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31); |
578 | 88920f34 | bellard | env->CF = c; |
579 | 88920f34 | bellard | } |
580 | 88920f34 | bellard | |
581 | 2c0262af | bellard | /* T2 based */
|
582 | 2c0262af | bellard | void OPPROTO op_shll_T2_im(void) |
583 | 2c0262af | bellard | { |
584 | 2c0262af | bellard | T2 = T2 << PARAM1; |
585 | 2c0262af | bellard | } |
586 | 2c0262af | bellard | |
587 | 2c0262af | bellard | void OPPROTO op_shrl_T2_im(void) |
588 | 2c0262af | bellard | { |
589 | 2c0262af | bellard | T2 = (uint32_t)T2 >> PARAM1; |
590 | 2c0262af | bellard | } |
591 | 2c0262af | bellard | |
592 | 1e8d4eec | bellard | void OPPROTO op_shrl_T2_0(void) |
593 | 1e8d4eec | bellard | { |
594 | 1e8d4eec | bellard | T2 = 0;
|
595 | 1e8d4eec | bellard | } |
596 | 1e8d4eec | bellard | |
597 | 2c0262af | bellard | void OPPROTO op_sarl_T2_im(void) |
598 | 2c0262af | bellard | { |
599 | 2c0262af | bellard | T2 = (int32_t)T2 >> PARAM1; |
600 | 2c0262af | bellard | } |
601 | 2c0262af | bellard | |
602 | 1e8d4eec | bellard | void OPPROTO op_sarl_T2_0(void) |
603 | 1e8d4eec | bellard | { |
604 | 1e8d4eec | bellard | T2 = (int32_t)T2 >> 31;
|
605 | 1e8d4eec | bellard | } |
606 | 1e8d4eec | bellard | |
607 | 2c0262af | bellard | void OPPROTO op_rorl_T2_im(void) |
608 | 2c0262af | bellard | { |
609 | 2c0262af | bellard | int shift;
|
610 | 2c0262af | bellard | shift = PARAM1; |
611 | 2c0262af | bellard | T2 = ((uint32_t)T2 >> shift) | (T2 << (32 - shift));
|
612 | 2c0262af | bellard | } |
613 | 2c0262af | bellard | |
614 | 1e8d4eec | bellard | void OPPROTO op_rrxl_T2(void) |
615 | 1e8d4eec | bellard | { |
616 | 1e8d4eec | bellard | T2 = ((uint32_t)T2 >> 1) | ((uint32_t)env->CF << 31); |
617 | 1e8d4eec | bellard | } |
618 | 1e8d4eec | bellard | |
619 | 2c0262af | bellard | /* T1 based, use T0 as shift count */
|
620 | 2c0262af | bellard | |
621 | 2c0262af | bellard | void OPPROTO op_shll_T1_T0(void) |
622 | 2c0262af | bellard | { |
623 | 2c0262af | bellard | int shift;
|
624 | 2c0262af | bellard | shift = T0 & 0xff;
|
625 | 2c0262af | bellard | if (shift >= 32) |
626 | 2c0262af | bellard | T1 = 0;
|
627 | 2c0262af | bellard | else
|
628 | 2c0262af | bellard | T1 = T1 << shift; |
629 | 2c0262af | bellard | FORCE_RET(); |
630 | 2c0262af | bellard | } |
631 | 2c0262af | bellard | |
632 | 2c0262af | bellard | void OPPROTO op_shrl_T1_T0(void) |
633 | 2c0262af | bellard | { |
634 | 2c0262af | bellard | int shift;
|
635 | 2c0262af | bellard | shift = T0 & 0xff;
|
636 | 2c0262af | bellard | if (shift >= 32) |
637 | 2c0262af | bellard | T1 = 0;
|
638 | 2c0262af | bellard | else
|
639 | 2c0262af | bellard | T1 = (uint32_t)T1 >> shift; |
640 | 2c0262af | bellard | FORCE_RET(); |
641 | 2c0262af | bellard | } |
642 | 2c0262af | bellard | |
643 | 2c0262af | bellard | void OPPROTO op_sarl_T1_T0(void) |
644 | 2c0262af | bellard | { |
645 | 2c0262af | bellard | int shift;
|
646 | 2c0262af | bellard | shift = T0 & 0xff;
|
647 | 2c0262af | bellard | if (shift >= 32) |
648 | 2c0262af | bellard | shift = 31;
|
649 | 2c0262af | bellard | T1 = (int32_t)T1 >> shift; |
650 | 2c0262af | bellard | } |
651 | 2c0262af | bellard | |
652 | 2c0262af | bellard | void OPPROTO op_rorl_T1_T0(void) |
653 | 2c0262af | bellard | { |
654 | 2c0262af | bellard | int shift;
|
655 | 2c0262af | bellard | shift = T0 & 0x1f;
|
656 | 2c0262af | bellard | if (shift) {
|
657 | 2c0262af | bellard | T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
658 | 2c0262af | bellard | } |
659 | 2c0262af | bellard | FORCE_RET(); |
660 | 2c0262af | bellard | } |
661 | 2c0262af | bellard | |
662 | 2c0262af | bellard | /* T1 based, use T0 as shift count and compute CF */
|
663 | 2c0262af | bellard | |
664 | 2c0262af | bellard | void OPPROTO op_shll_T1_T0_cc(void) |
665 | 2c0262af | bellard | { |
666 | 2c0262af | bellard | int shift;
|
667 | 2c0262af | bellard | shift = T0 & 0xff;
|
668 | 2c0262af | bellard | if (shift >= 32) { |
669 | 2c0262af | bellard | if (shift == 32) |
670 | 2c0262af | bellard | env->CF = T1 & 1;
|
671 | 2c0262af | bellard | else
|
672 | 2c0262af | bellard | env->CF = 0;
|
673 | 2c0262af | bellard | T1 = 0;
|
674 | 2c0262af | bellard | } else if (shift != 0) { |
675 | 2c0262af | bellard | env->CF = (T1 >> (32 - shift)) & 1; |
676 | 2c0262af | bellard | T1 = T1 << shift; |
677 | 2c0262af | bellard | } |
678 | 2c0262af | bellard | FORCE_RET(); |
679 | 2c0262af | bellard | } |
680 | 2c0262af | bellard | |
681 | 2c0262af | bellard | void OPPROTO op_shrl_T1_T0_cc(void) |
682 | 2c0262af | bellard | { |
683 | 2c0262af | bellard | int shift;
|
684 | 2c0262af | bellard | shift = T0 & 0xff;
|
685 | 2c0262af | bellard | if (shift >= 32) { |
686 | 2c0262af | bellard | if (shift == 32) |
687 | 2c0262af | bellard | env->CF = (T1 >> 31) & 1; |
688 | 2c0262af | bellard | else
|
689 | 2c0262af | bellard | env->CF = 0;
|
690 | 2c0262af | bellard | T1 = 0;
|
691 | 2c0262af | bellard | } else if (shift != 0) { |
692 | 2c0262af | bellard | env->CF = (T1 >> (shift - 1)) & 1; |
693 | 2c0262af | bellard | T1 = (uint32_t)T1 >> shift; |
694 | 2c0262af | bellard | } |
695 | 2c0262af | bellard | FORCE_RET(); |
696 | 2c0262af | bellard | } |
697 | 2c0262af | bellard | |
698 | 2c0262af | bellard | void OPPROTO op_sarl_T1_T0_cc(void) |
699 | 2c0262af | bellard | { |
700 | 2c0262af | bellard | int shift;
|
701 | 2c0262af | bellard | shift = T0 & 0xff;
|
702 | 2c0262af | bellard | if (shift >= 32) { |
703 | 2c0262af | bellard | env->CF = (T1 >> 31) & 1; |
704 | 2c0262af | bellard | T1 = (int32_t)T1 >> 31;
|
705 | 2c0262af | bellard | } else {
|
706 | 2c0262af | bellard | env->CF = (T1 >> (shift - 1)) & 1; |
707 | 2c0262af | bellard | T1 = (int32_t)T1 >> shift; |
708 | 2c0262af | bellard | } |
709 | 2c0262af | bellard | FORCE_RET(); |
710 | 2c0262af | bellard | } |
711 | 2c0262af | bellard | |
712 | 2c0262af | bellard | void OPPROTO op_rorl_T1_T0_cc(void) |
713 | 2c0262af | bellard | { |
714 | 2c0262af | bellard | int shift1, shift;
|
715 | 2c0262af | bellard | shift1 = T0 & 0xff;
|
716 | 2c0262af | bellard | shift = shift1 & 0x1f;
|
717 | 2c0262af | bellard | if (shift == 0) { |
718 | 2c0262af | bellard | if (shift1 != 0) |
719 | 2c0262af | bellard | env->CF = (T1 >> 31) & 1; |
720 | 2c0262af | bellard | } else {
|
721 | 2c0262af | bellard | env->CF = (T1 >> (shift - 1)) & 1; |
722 | 2c0262af | bellard | T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
|
723 | 2c0262af | bellard | } |
724 | 2c0262af | bellard | FORCE_RET(); |
725 | 2c0262af | bellard | } |
726 | 2c0262af | bellard | |
727 | 99c475ab | bellard | /* misc */
|
728 | 99c475ab | bellard | void OPPROTO op_clz_T0(void) |
729 | 99c475ab | bellard | { |
730 | 99c475ab | bellard | int count;
|
731 | 99c475ab | bellard | for (count = 32; T0 > 0; count--) |
732 | 99c475ab | bellard | T0 = T0 >> 1;
|
733 | 99c475ab | bellard | T0 = count; |
734 | 99c475ab | bellard | FORCE_RET(); |
735 | 99c475ab | bellard | } |
736 | 99c475ab | bellard | |
737 | 99c475ab | bellard | void OPPROTO op_sarl_T0_im(void) |
738 | 99c475ab | bellard | { |
739 | 99c475ab | bellard | T0 = (int32_t)T0 >> PARAM1; |
740 | 99c475ab | bellard | } |
741 | 99c475ab | bellard | |
742 | 99c475ab | bellard | /* 16->32 Sign extend */
|
743 | 99c475ab | bellard | void OPPROTO op_sxl_T0(void) |
744 | 99c475ab | bellard | { |
745 | 99c475ab | bellard | T0 = (int16_t)T0; |
746 | 99c475ab | bellard | } |
747 | 99c475ab | bellard | |
748 | 99c475ab | bellard | void OPPROTO op_sxl_T1(void) |
749 | 99c475ab | bellard | { |
750 | 99c475ab | bellard | T1 = (int16_t)T1; |
751 | 99c475ab | bellard | } |
752 | 99c475ab | bellard | |
753 | 99c475ab | bellard | #define SIGNBIT (uint32_t)0x80000000 |
754 | 99c475ab | bellard | /* saturating arithmetic */
|
755 | 99c475ab | bellard | void OPPROTO op_addl_T0_T1_setq(void) |
756 | 99c475ab | bellard | { |
757 | 99c475ab | bellard | uint32_t res; |
758 | 99c475ab | bellard | |
759 | 99c475ab | bellard | res = T0 + T1; |
760 | 99c475ab | bellard | if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT))
|
761 | 99c475ab | bellard | env->QF = 1;
|
762 | 99c475ab | bellard | |
763 | 99c475ab | bellard | T0 = res; |
764 | 99c475ab | bellard | FORCE_RET(); |
765 | 99c475ab | bellard | } |
766 | 99c475ab | bellard | |
767 | 99c475ab | bellard | void OPPROTO op_addl_T0_T1_saturate(void) |
768 | 99c475ab | bellard | { |
769 | 99c475ab | bellard | uint32_t res; |
770 | 99c475ab | bellard | |
771 | 99c475ab | bellard | res = T0 + T1; |
772 | 99c475ab | bellard | if (((res ^ T0) & SIGNBIT) && !((T0 ^ T1) & SIGNBIT)) {
|
773 | 99c475ab | bellard | env->QF = 1;
|
774 | 99c475ab | bellard | if (T0 & SIGNBIT)
|
775 | 99c475ab | bellard | T0 = 0x80000000;
|
776 | 99c475ab | bellard | else
|
777 | 99c475ab | bellard | T0 = 0x7fffffff;
|
778 | 99c475ab | bellard | } |
779 | 99c475ab | bellard | else
|
780 | 99c475ab | bellard | T0 = res; |
781 | 99c475ab | bellard | |
782 | 99c475ab | bellard | FORCE_RET(); |
783 | 99c475ab | bellard | } |
784 | 99c475ab | bellard | |
785 | 99c475ab | bellard | void OPPROTO op_subl_T0_T1_saturate(void) |
786 | 99c475ab | bellard | { |
787 | 99c475ab | bellard | uint32_t res; |
788 | 99c475ab | bellard | |
789 | 99c475ab | bellard | res = T0 - T1; |
790 | 99c475ab | bellard | if (((res ^ T0) & SIGNBIT) && ((T0 ^ T1) & SIGNBIT)) {
|
791 | 99c475ab | bellard | env->QF = 1;
|
792 | 99c475ab | bellard | if (T0 & SIGNBIT)
|
793 | 99c475ab | bellard | T0 = 0x8000000;
|
794 | 99c475ab | bellard | else
|
795 | 99c475ab | bellard | T0 = 0x7fffffff;
|
796 | 99c475ab | bellard | } |
797 | 99c475ab | bellard | else
|
798 | 99c475ab | bellard | T0 = res; |
799 | 99c475ab | bellard | |
800 | 99c475ab | bellard | FORCE_RET(); |
801 | 99c475ab | bellard | } |
802 | 99c475ab | bellard | |
803 | 99c475ab | bellard | /* thumb shift by immediate */
|
804 | 99c475ab | bellard | void OPPROTO op_shll_T0_im_thumb(void) |
805 | 99c475ab | bellard | { |
806 | 99c475ab | bellard | int shift;
|
807 | 99c475ab | bellard | shift = PARAM1; |
808 | 99c475ab | bellard | if (shift != 0) { |
809 | 99c475ab | bellard | env->CF = (T1 >> (32 - shift)) & 1; |
810 | 99c475ab | bellard | T0 = T0 << shift; |
811 | 99c475ab | bellard | } |
812 | 99c475ab | bellard | env->NZF = T0; |
813 | 99c475ab | bellard | FORCE_RET(); |
814 | 99c475ab | bellard | } |
815 | 99c475ab | bellard | |
816 | 99c475ab | bellard | void OPPROTO op_shrl_T0_im_thumb(void) |
817 | 99c475ab | bellard | { |
818 | 99c475ab | bellard | int shift;
|
819 | 99c475ab | bellard | |
820 | 99c475ab | bellard | shift = PARAM1; |
821 | 99c475ab | bellard | if (shift == 0) { |
822 | 99c475ab | bellard | env->CF = 0;
|
823 | 99c475ab | bellard | T0 = 0;
|
824 | 99c475ab | bellard | } else {
|
825 | 99c475ab | bellard | env->CF = (T0 >> (shift - 1)) & 1; |
826 | 99c475ab | bellard | T0 = T0 >> shift; |
827 | 99c475ab | bellard | } |
828 | 99c475ab | bellard | FORCE_RET(); |
829 | 99c475ab | bellard | } |
830 | 99c475ab | bellard | |
831 | 99c475ab | bellard | void OPPROTO op_sarl_T0_im_thumb(void) |
832 | 99c475ab | bellard | { |
833 | 99c475ab | bellard | int shift;
|
834 | 99c475ab | bellard | |
835 | 99c475ab | bellard | shift = PARAM1; |
836 | 99c475ab | bellard | if (shift == 0) { |
837 | 99c475ab | bellard | T0 = ((int32_t)T0) >> 31;
|
838 | 99c475ab | bellard | env->CF = T0 & 1;
|
839 | 99c475ab | bellard | } else {
|
840 | 99c475ab | bellard | env->CF = (T0 >> (shift - 1)) & 1; |
841 | 99c475ab | bellard | T0 = ((int32_t)T0) >> shift; |
842 | 99c475ab | bellard | } |
843 | 99c475ab | bellard | env->NZF = T0; |
844 | 99c475ab | bellard | FORCE_RET(); |
845 | 99c475ab | bellard | } |
846 | 99c475ab | bellard | |
847 | 2c0262af | bellard | /* exceptions */
|
848 | 2c0262af | bellard | |
849 | 2c0262af | bellard | void OPPROTO op_swi(void) |
850 | 2c0262af | bellard | { |
851 | 2c0262af | bellard | env->exception_index = EXCP_SWI; |
852 | 2c0262af | bellard | cpu_loop_exit(); |
853 | 2c0262af | bellard | } |
854 | 2c0262af | bellard | |
855 | 2c0262af | bellard | void OPPROTO op_undef_insn(void) |
856 | 2c0262af | bellard | { |
857 | 2c0262af | bellard | env->exception_index = EXCP_UDEF; |
858 | 2c0262af | bellard | cpu_loop_exit(); |
859 | 2c0262af | bellard | } |
860 | 2c0262af | bellard | |
861 | 1fddef4b | bellard | void OPPROTO op_debug(void) |
862 | 1fddef4b | bellard | { |
863 | 1fddef4b | bellard | env->exception_index = EXCP_DEBUG; |
864 | 1fddef4b | bellard | cpu_loop_exit(); |
865 | 1fddef4b | bellard | } |
866 | 1fddef4b | bellard | |
867 | b7bcbe95 | bellard | /* VFP support. We follow the convention used for VFP instrunctions:
|
868 | b7bcbe95 | bellard | Single precition routines have a "s" suffix, double precision a
|
869 | b7bcbe95 | bellard | "d" suffix. */
|
870 | 2c0262af | bellard | |
871 | b7bcbe95 | bellard | #define VFP_OP(name, p) void OPPROTO op_vfp_##name##p(void) |
872 | 2c0262af | bellard | |
873 | 53cd6637 | bellard | #define VFP_BINOP(name) \
|
874 | b7bcbe95 | bellard | VFP_OP(name, s) \ |
875 | b7bcbe95 | bellard | { \ |
876 | 53cd6637 | bellard | FT0s = float32_ ## name (FT0s, FT1s, &env->vfp.fp_status); \ |
877 | b7bcbe95 | bellard | } \ |
878 | b7bcbe95 | bellard | VFP_OP(name, d) \ |
879 | b7bcbe95 | bellard | { \ |
880 | 53cd6637 | bellard | FT0d = float64_ ## name (FT0d, FT1d, &env->vfp.fp_status); \ |
881 | b7bcbe95 | bellard | } |
882 | 53cd6637 | bellard | VFP_BINOP(add) |
883 | 53cd6637 | bellard | VFP_BINOP(sub) |
884 | 53cd6637 | bellard | VFP_BINOP(mul) |
885 | 53cd6637 | bellard | VFP_BINOP(div) |
886 | b7bcbe95 | bellard | #undef VFP_BINOP
|
887 | b7bcbe95 | bellard | |
888 | b7bcbe95 | bellard | #define VFP_HELPER(name) \
|
889 | b7bcbe95 | bellard | VFP_OP(name, s) \ |
890 | b7bcbe95 | bellard | { \ |
891 | b7bcbe95 | bellard | do_vfp_##name##s(); \ |
892 | b7bcbe95 | bellard | } \ |
893 | b7bcbe95 | bellard | VFP_OP(name, d) \ |
894 | b7bcbe95 | bellard | { \ |
895 | b7bcbe95 | bellard | do_vfp_##name##d(); \ |
896 | b7bcbe95 | bellard | } |
897 | b7bcbe95 | bellard | VFP_HELPER(abs) |
898 | b7bcbe95 | bellard | VFP_HELPER(sqrt) |
899 | b7bcbe95 | bellard | VFP_HELPER(cmp) |
900 | b7bcbe95 | bellard | VFP_HELPER(cmpe) |
901 | b7bcbe95 | bellard | #undef VFP_HELPER
|
902 | b7bcbe95 | bellard | |
903 | b7bcbe95 | bellard | /* XXX: Will this do the right thing for NANs. Should invert the signbit
|
904 | b7bcbe95 | bellard | without looking at the rest of the value. */
|
905 | b7bcbe95 | bellard | VFP_OP(neg, s) |
906 | b7bcbe95 | bellard | { |
907 | 53cd6637 | bellard | FT0s = float32_chs(FT0s); |
908 | b7bcbe95 | bellard | } |
909 | b7bcbe95 | bellard | |
910 | b7bcbe95 | bellard | VFP_OP(neg, d) |
911 | b7bcbe95 | bellard | { |
912 | 53cd6637 | bellard | FT0d = float64_chs(FT0d); |
913 | b7bcbe95 | bellard | } |
914 | b7bcbe95 | bellard | |
915 | b7bcbe95 | bellard | VFP_OP(F1_ld0, s) |
916 | b7bcbe95 | bellard | { |
917 | 53cd6637 | bellard | union {
|
918 | 53cd6637 | bellard | uint32_t i; |
919 | 53cd6637 | bellard | float32 s; |
920 | 53cd6637 | bellard | } v; |
921 | 53cd6637 | bellard | v.i = 0;
|
922 | 53cd6637 | bellard | FT1s = v.s; |
923 | b7bcbe95 | bellard | } |
924 | b7bcbe95 | bellard | |
925 | b7bcbe95 | bellard | VFP_OP(F1_ld0, d) |
926 | b7bcbe95 | bellard | { |
927 | 53cd6637 | bellard | union {
|
928 | 53cd6637 | bellard | uint64_t i; |
929 | 53cd6637 | bellard | float64 d; |
930 | 53cd6637 | bellard | } v; |
931 | 53cd6637 | bellard | v.i = 0;
|
932 | 53cd6637 | bellard | FT1d = v.d; |
933 | b7bcbe95 | bellard | } |
934 | b7bcbe95 | bellard | |
935 | b7bcbe95 | bellard | /* Helper routines to perform bitwise copies between float and int. */
|
936 | 53cd6637 | bellard | static inline float32 vfp_itos(uint32_t i) |
937 | b7bcbe95 | bellard | { |
938 | b7bcbe95 | bellard | union {
|
939 | b7bcbe95 | bellard | uint32_t i; |
940 | 53cd6637 | bellard | float32 s; |
941 | b7bcbe95 | bellard | } v; |
942 | b7bcbe95 | bellard | |
943 | b7bcbe95 | bellard | v.i = i; |
944 | b7bcbe95 | bellard | return v.s;
|
945 | b7bcbe95 | bellard | } |
946 | b7bcbe95 | bellard | |
947 | 53cd6637 | bellard | static inline uint32_t vfp_stoi(float32 s) |
948 | b7bcbe95 | bellard | { |
949 | b7bcbe95 | bellard | union {
|
950 | b7bcbe95 | bellard | uint32_t i; |
951 | 53cd6637 | bellard | float32 s; |
952 | b7bcbe95 | bellard | } v; |
953 | b7bcbe95 | bellard | |
954 | b7bcbe95 | bellard | v.s = s; |
955 | b7bcbe95 | bellard | return v.i;
|
956 | b7bcbe95 | bellard | } |
957 | b7bcbe95 | bellard | |
958 | b7bcbe95 | bellard | /* Integer to float conversion. */
|
959 | b7bcbe95 | bellard | VFP_OP(uito, s) |
960 | b7bcbe95 | bellard | { |
961 | 53cd6637 | bellard | FT0s = uint32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status); |
962 | b7bcbe95 | bellard | } |
963 | b7bcbe95 | bellard | |
964 | b7bcbe95 | bellard | VFP_OP(uito, d) |
965 | b7bcbe95 | bellard | { |
966 | 53cd6637 | bellard | FT0d = uint32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status); |
967 | b7bcbe95 | bellard | } |
968 | b7bcbe95 | bellard | |
969 | b7bcbe95 | bellard | VFP_OP(sito, s) |
970 | b7bcbe95 | bellard | { |
971 | 53cd6637 | bellard | FT0s = int32_to_float32(vfp_stoi(FT0s), &env->vfp.fp_status); |
972 | b7bcbe95 | bellard | } |
973 | b7bcbe95 | bellard | |
974 | b7bcbe95 | bellard | VFP_OP(sito, d) |
975 | b7bcbe95 | bellard | { |
976 | 53cd6637 | bellard | FT0d = int32_to_float64(vfp_stoi(FT0s), &env->vfp.fp_status); |
977 | b7bcbe95 | bellard | } |
978 | b7bcbe95 | bellard | |
979 | b7bcbe95 | bellard | /* Float to integer conversion. */
|
980 | b7bcbe95 | bellard | VFP_OP(toui, s) |
981 | b7bcbe95 | bellard | { |
982 | 53cd6637 | bellard | FT0s = vfp_itos(float32_to_uint32(FT0s, &env->vfp.fp_status)); |
983 | b7bcbe95 | bellard | } |
984 | b7bcbe95 | bellard | |
985 | b7bcbe95 | bellard | VFP_OP(toui, d) |
986 | b7bcbe95 | bellard | { |
987 | 53cd6637 | bellard | FT0s = vfp_itos(float64_to_uint32(FT0d, &env->vfp.fp_status)); |
988 | b7bcbe95 | bellard | } |
989 | b7bcbe95 | bellard | |
990 | b7bcbe95 | bellard | VFP_OP(tosi, s) |
991 | b7bcbe95 | bellard | { |
992 | 53cd6637 | bellard | FT0s = vfp_itos(float32_to_int32(FT0s, &env->vfp.fp_status)); |
993 | b7bcbe95 | bellard | } |
994 | b7bcbe95 | bellard | |
995 | b7bcbe95 | bellard | VFP_OP(tosi, d) |
996 | b7bcbe95 | bellard | { |
997 | 53cd6637 | bellard | FT0s = vfp_itos(float64_to_int32(FT0d, &env->vfp.fp_status)); |
998 | b7bcbe95 | bellard | } |
999 | b7bcbe95 | bellard | |
1000 | b7bcbe95 | bellard | /* TODO: Set rounding mode properly. */
|
1001 | b7bcbe95 | bellard | VFP_OP(touiz, s) |
1002 | b7bcbe95 | bellard | { |
1003 | 53cd6637 | bellard | FT0s = vfp_itos(float32_to_uint32_round_to_zero(FT0s, &env->vfp.fp_status)); |
1004 | b7bcbe95 | bellard | } |
1005 | b7bcbe95 | bellard | |
1006 | b7bcbe95 | bellard | VFP_OP(touiz, d) |
1007 | b7bcbe95 | bellard | { |
1008 | 53cd6637 | bellard | FT0s = vfp_itos(float64_to_uint32_round_to_zero(FT0d, &env->vfp.fp_status)); |
1009 | b7bcbe95 | bellard | } |
1010 | b7bcbe95 | bellard | |
1011 | b7bcbe95 | bellard | VFP_OP(tosiz, s) |
1012 | b7bcbe95 | bellard | { |
1013 | 53cd6637 | bellard | FT0s = vfp_itos(float32_to_int32_round_to_zero(FT0s, &env->vfp.fp_status)); |
1014 | b7bcbe95 | bellard | } |
1015 | b7bcbe95 | bellard | |
1016 | b7bcbe95 | bellard | VFP_OP(tosiz, d) |
1017 | 2c0262af | bellard | { |
1018 | 53cd6637 | bellard | FT0s = vfp_itos(float64_to_int32_round_to_zero(FT0d, &env->vfp.fp_status)); |
1019 | 2c0262af | bellard | } |
1020 | 2c0262af | bellard | |
1021 | b7bcbe95 | bellard | /* floating point conversion */
|
1022 | b7bcbe95 | bellard | VFP_OP(fcvtd, s) |
1023 | 2c0262af | bellard | { |
1024 | 53cd6637 | bellard | FT0d = float32_to_float64(FT0s, &env->vfp.fp_status); |
1025 | 2c0262af | bellard | } |
1026 | 2c0262af | bellard | |
1027 | b7bcbe95 | bellard | VFP_OP(fcvts, d) |
1028 | b7bcbe95 | bellard | { |
1029 | 53cd6637 | bellard | FT0s = float64_to_float32(FT0d, &env->vfp.fp_status); |
1030 | b7bcbe95 | bellard | } |
1031 | b7bcbe95 | bellard | |
1032 | b7bcbe95 | bellard | /* Get and Put values from registers. */
|
1033 | b7bcbe95 | bellard | VFP_OP(getreg_F0, d) |
1034 | b7bcbe95 | bellard | { |
1035 | 53cd6637 | bellard | FT0d = *(float64 *)((char *) env + PARAM1);
|
1036 | b7bcbe95 | bellard | } |
1037 | b7bcbe95 | bellard | |
1038 | b7bcbe95 | bellard | VFP_OP(getreg_F0, s) |
1039 | b7bcbe95 | bellard | { |
1040 | 53cd6637 | bellard | FT0s = *(float32 *)((char *) env + PARAM1);
|
1041 | b7bcbe95 | bellard | } |
1042 | b7bcbe95 | bellard | |
1043 | b7bcbe95 | bellard | VFP_OP(getreg_F1, d) |
1044 | b7bcbe95 | bellard | { |
1045 | 53cd6637 | bellard | FT1d = *(float64 *)((char *) env + PARAM1);
|
1046 | b7bcbe95 | bellard | } |
1047 | b7bcbe95 | bellard | |
1048 | b7bcbe95 | bellard | VFP_OP(getreg_F1, s) |
1049 | b7bcbe95 | bellard | { |
1050 | 53cd6637 | bellard | FT1s = *(float32 *)((char *) env + PARAM1);
|
1051 | b7bcbe95 | bellard | } |
1052 | b7bcbe95 | bellard | |
1053 | b7bcbe95 | bellard | VFP_OP(setreg_F0, d) |
1054 | b7bcbe95 | bellard | { |
1055 | 53cd6637 | bellard | *(float64 *)((char *) env + PARAM1) = FT0d;
|
1056 | b7bcbe95 | bellard | } |
1057 | b7bcbe95 | bellard | |
1058 | b7bcbe95 | bellard | VFP_OP(setreg_F0, s) |
1059 | b7bcbe95 | bellard | { |
1060 | 53cd6637 | bellard | *(float32 *)((char *) env + PARAM1) = FT0s;
|
1061 | b7bcbe95 | bellard | } |
1062 | b7bcbe95 | bellard | |
1063 | b7bcbe95 | bellard | void OPPROTO op_vfp_movl_T0_fpscr(void) |
1064 | b7bcbe95 | bellard | { |
1065 | b7bcbe95 | bellard | do_vfp_get_fpscr (); |
1066 | b7bcbe95 | bellard | } |
1067 | b7bcbe95 | bellard | |
1068 | b7bcbe95 | bellard | void OPPROTO op_vfp_movl_T0_fpscr_flags(void) |
1069 | b7bcbe95 | bellard | { |
1070 | b7bcbe95 | bellard | T0 = env->vfp.fpscr & (0xf << 28); |
1071 | b7bcbe95 | bellard | } |
1072 | b7bcbe95 | bellard | |
1073 | b7bcbe95 | bellard | void OPPROTO op_vfp_movl_fpscr_T0(void) |
1074 | b7bcbe95 | bellard | { |
1075 | b7bcbe95 | bellard | do_vfp_set_fpscr(); |
1076 | b7bcbe95 | bellard | } |
1077 | b7bcbe95 | bellard | |
1078 | b7bcbe95 | bellard | /* Move between FT0s to T0 */
|
1079 | b7bcbe95 | bellard | void OPPROTO op_vfp_mrs(void) |
1080 | b7bcbe95 | bellard | { |
1081 | b7bcbe95 | bellard | T0 = vfp_stoi(FT0s); |
1082 | b7bcbe95 | bellard | } |
1083 | b7bcbe95 | bellard | |
1084 | b7bcbe95 | bellard | void OPPROTO op_vfp_msr(void) |
1085 | b7bcbe95 | bellard | { |
1086 | b7bcbe95 | bellard | FT0s = vfp_itos(T0); |
1087 | b7bcbe95 | bellard | } |
1088 | b7bcbe95 | bellard | |
1089 | b7bcbe95 | bellard | /* Move between FT0d and {T0,T1} */
|
1090 | b7bcbe95 | bellard | void OPPROTO op_vfp_mrrd(void) |
1091 | b7bcbe95 | bellard | { |
1092 | b7bcbe95 | bellard | CPU_DoubleU u; |
1093 | b7bcbe95 | bellard | |
1094 | b7bcbe95 | bellard | u.d = FT0d; |
1095 | b7bcbe95 | bellard | T0 = u.l.lower; |
1096 | b7bcbe95 | bellard | T1 = u.l.upper; |
1097 | b7bcbe95 | bellard | } |
1098 | b7bcbe95 | bellard | |
1099 | b7bcbe95 | bellard | void OPPROTO op_vfp_mdrr(void) |
1100 | b7bcbe95 | bellard | { |
1101 | b7bcbe95 | bellard | CPU_DoubleU u; |
1102 | b7bcbe95 | bellard | |
1103 | b7bcbe95 | bellard | u.l.lower = T0; |
1104 | b7bcbe95 | bellard | u.l.upper = T1; |
1105 | b7bcbe95 | bellard | FT0d = u.d; |
1106 | b7bcbe95 | bellard | } |
1107 | b7bcbe95 | bellard | |
1108 | b7bcbe95 | bellard | /* Floating point load/store. Address is in T1 */
|
1109 | b7bcbe95 | bellard | void OPPROTO op_vfp_lds(void) |
1110 | b7bcbe95 | bellard | { |
1111 | b7bcbe95 | bellard | FT0s = ldfl((void *)T1);
|
1112 | b7bcbe95 | bellard | } |
1113 | b7bcbe95 | bellard | |
1114 | b7bcbe95 | bellard | void OPPROTO op_vfp_ldd(void) |
1115 | b7bcbe95 | bellard | { |
1116 | b7bcbe95 | bellard | FT0d = ldfq((void *)T1);
|
1117 | b7bcbe95 | bellard | } |
1118 | b7bcbe95 | bellard | |
1119 | b7bcbe95 | bellard | void OPPROTO op_vfp_sts(void) |
1120 | b7bcbe95 | bellard | { |
1121 | b7bcbe95 | bellard | stfl((void *)T1, FT0s);
|
1122 | b7bcbe95 | bellard | } |
1123 | b7bcbe95 | bellard | |
1124 | b7bcbe95 | bellard | void OPPROTO op_vfp_std(void) |
1125 | b7bcbe95 | bellard | { |
1126 | b7bcbe95 | bellard | stfq((void *)T1, FT0d);
|
1127 | b7bcbe95 | bellard | } |