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Revision 8935a442

         } while (0)
     #define MAX_CPU     32
     #define MAX_SRC     256
     #define MAX_TMR     4
     #define MAX_IPI     4
     #define MAX_MSI     8
     #define MAX_IRQ     (MAX_SRC + MAX_IPI + MAX_TMR)
     #define VID         0x03 /* MPIC version ID */
     /* OpenPIC capability flags */
-...
     #define OPENPIC_SUMMARY_REG_START   0x3800
     #define OPENPIC_SUMMARY_REG_SIZE    0x800
     #define OPENPIC_SRC_REG_START        0x10000
     #define OPENPIC_SRC_REG_SIZE         (MAX_SRC * 0x20)
     #define OPENPIC_SRC_REG_SIZE         (OPENPIC_MAX_SRC * 0x20)
     #define OPENPIC_CPU_REG_START        0x20000
     #define OPENPIC_CPU_REG_SIZE         0x100 + ((MAX_CPU - 1) * 0x1000)
-...
     #define RAVEN_MAX_CPU      2
     #define RAVEN_MAX_EXT     48
     #define RAVEN_MAX_IRQ     64
     #define RAVEN_MAX_TMR      MAX_TMR
     #define RAVEN_MAX_IPI      MAX_IPI
     #define RAVEN_MAX_TMR      OPENPIC_MAX_TMR
     #define RAVEN_MAX_IPI      OPENPIC_MAX_IPI
     /* Interrupt definitions */
     #define RAVEN_FE_IRQ     (RAVEN_MAX_EXT)     /* Internal functional IRQ */
-...
         /* Round up to the nearest 64 IRQs so that the queue length
          * won't change when moving between 32 and 64 bit hosts.
          */
         unsigned long queue[BITS_TO_LONGS((MAX_IRQ + 63) & ~63)];
         unsigned long queue[BITS_TO_LONGS((OPENPIC_MAX_IRQ + 63) & ~63)];
         int next;
         int priority;
     } IRQQueue;
-...
         uint32_t spve; /* Spurious vector register */
         uint32_t tfrr; /* Timer frequency reporting register */
         /* Source registers */
         IRQSource src[MAX_IRQ];
         IRQSource src[OPENPIC_MAX_IRQ];
         /* Local registers per output pin */
         IRQDest dst[MAX_CPU];
         uint32_t nb_cpus;
-...
         struct {
             uint32_t tccr;  /* Global timer current count register */
             uint32_t tbcr;  /* Global timer base count register */
         } timers[MAX_TMR];
         } timers[OPENPIC_MAX_TMR];
         /* Shared MSI registers */
         struct {
             uint32_t msir;   /* Shared Message Signaled Interrupt Register */
-...
         OpenPICState *opp = opaque;
         IRQSource *src;
         if (n_IRQ >= MAX_IRQ) {
         if (n_IRQ >= OPENPIC_MAX_IRQ) {
             fprintf(stderr, "%s: IRQ %d out of range\n", __func__, n_IRQ);
             abort();
+        }
-...
             opp->dst[i].servicing.next = -1;
+        }
         /* Initialise timers */
         for (i = 0; i < MAX_TMR; i++) {
         for (i = 0; i < OPENPIC_MAX_TMR; i++) {
             opp->timers[i].tccr = 0;
             opp->timers[i].tbcr = TBCR_CI;
+        }
-...
             IRQ_resetbit(&dst->raised, irq);
+        }
         if ((irq >= opp->irq_ipi0) &&  (irq < (opp->irq_ipi0 + MAX_IPI))) {
         if ((irq >= opp->irq_ipi0) &&  (irq < (opp->irq_ipi0 + OPENPIC_MAX_IPI))) {
             src->destmask &= ~(1 << cpu);
             if (src->destmask && !src->level) {
                 /* trigger on CPUs that didn't know about it yet */
-...
                             sizeof(opp->dst[i].outputs_active));
+        }
         for (i = 0; i < MAX_TMR; i++) {
         for (i = 0; i < OPENPIC_MAX_TMR; i++) {
             qemu_put_be32s(f, &opp->timers[i].tccr);
             qemu_put_be32s(f, &opp->timers[i].tbcr);
+        }
-...
                             sizeof(opp->dst[i].outputs_active));
+        }
         for (i = 0; i < MAX_TMR; i++) {
         for (i = 0; i < OPENPIC_MAX_TMR; i++) {
             qemu_get_be32s(f, &opp->timers[i].tccr);
             qemu_get_be32s(f, &opp->timers[i].tbcr);
+        }
-...
     static void fsl_common_init(OpenPICState *opp)
+    {
         int i;
         int virq = MAX_SRC;
         int virq = OPENPIC_MAX_SRC;
         opp->vid = VID_REVISION_1_2;
         opp->vir = VIR_GENERIC;
-...
         opp->tfrr_reset = 0;
         opp->ivpr_reset = IVPR_MASK_MASK;
         opp->idr_reset = 1 << 0;
         opp->max_irq = MAX_IRQ;
         opp->max_irq = OPENPIC_MAX_IRQ;
         opp->irq_ipi0 = virq;
         virq += MAX_IPI;
         virq += OPENPIC_MAX_IPI;
         opp->irq_tim0 = virq;
         virq += MAX_TMR;
         virq += OPENPIC_MAX_TMR;
         assert(virq <= MAX_IRQ);
         assert(virq <= OPENPIC_MAX_IRQ);
         opp->irq_msi = 224;
-...
+        }
         /* Internal interrupts, including message and MSI */
         for (i = 16; i < MAX_SRC; i++) {
         for (i = 16; i < OPENPIC_MAX_SRC; i++) {
             opp->src[i].type = IRQ_TYPE_FSLINT;
             opp->src[i].level = true;
+        }
         /* timers and IPIs */
         for (i = MAX_SRC; i < virq; i++) {
         for (i = OPENPIC_MAX_SRC; i < virq; i++) {
             opp->src[i].type = IRQ_TYPE_FSLSPECIAL;
             opp->src[i].level = false;
+        }

     #if !defined(__OPENPIC_H__)
     #define __OPENPIC_H__
     #include "qemu-common.h"
     #include "hw/qdev.h"
     /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
     enum {
         OPENPIC_OUTPUT_INT = 0, /* IRQ                       */
-...
     #define OPENPIC_MODEL_FSL_MPIC_20 1
     #define OPENPIC_MODEL_FSL_MPIC_42 2
     #define OPENPIC_MAX_SRC     256
     #define OPENPIC_MAX_TMR     4
     #define OPENPIC_MAX_IPI     4
     #define OPENPIC_MAX_IRQ     (OPENPIC_MAX_SRC + OPENPIC_MAX_IPI + \
                                  OPENPIC_MAX_TMR)
     DeviceState *kvm_openpic_create(BusState *bus, int model);
     #endif /* __OPENPIC_H__ */

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Revision 8935a442