Revision 89e957e7 linux-user/main.c
b/linux-user/main.c | ||
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119 | 119 |
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120 | 120 |
uint64_t gdt_table[6]; |
121 | 121 |
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//#define DEBUG_VM86 |
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static inline int is_revectored(int nr, struct target_revectored_struct *bitmap) |
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{ |
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return (tswap32(bitmap->__map[nr >> 5]) >> (nr & 0x1f)) & 1; |
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} |
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128 |
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static inline uint8_t *seg_to_linear(unsigned int seg, unsigned int reg) |
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{ |
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return (uint8_t *)((seg << 4) + (reg & 0xffff)); |
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} |
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static inline void pushw(CPUX86State *env, int val) |
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{ |
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env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | |
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((env->regs[R_ESP] - 2) & 0xffff); |
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*(uint16_t *)seg_to_linear(env->segs[R_SS], env->regs[R_ESP]) = val; |
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} |
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static inline unsigned int get_vflags(CPUX86State *env) |
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{ |
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unsigned int eflags; |
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eflags = env->eflags & ~(VM_MASK | RF_MASK | IF_MASK); |
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if (eflags & VIF_MASK) |
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eflags |= IF_MASK; |
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return eflags; |
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} |
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void save_v86_state(CPUX86State *env) |
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{ |
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TaskState *ts = env->opaque; |
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#ifdef DEBUG_VM86 |
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printf("save_v86_state\n"); |
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#endif |
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/* put the VM86 registers in the userspace register structure */ |
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ts->target_v86->regs.eax = tswap32(env->regs[R_EAX]); |
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ts->target_v86->regs.ebx = tswap32(env->regs[R_EBX]); |
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ts->target_v86->regs.ecx = tswap32(env->regs[R_ECX]); |
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ts->target_v86->regs.edx = tswap32(env->regs[R_EDX]); |
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ts->target_v86->regs.esi = tswap32(env->regs[R_ESI]); |
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ts->target_v86->regs.edi = tswap32(env->regs[R_EDI]); |
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ts->target_v86->regs.ebp = tswap32(env->regs[R_EBP]); |
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ts->target_v86->regs.esp = tswap32(env->regs[R_ESP]); |
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ts->target_v86->regs.eip = tswap32(env->eip); |
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ts->target_v86->regs.cs = tswap16(env->segs[R_CS]); |
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ts->target_v86->regs.ss = tswap16(env->segs[R_SS]); |
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ts->target_v86->regs.ds = tswap16(env->segs[R_DS]); |
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ts->target_v86->regs.es = tswap16(env->segs[R_ES]); |
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ts->target_v86->regs.fs = tswap16(env->segs[R_FS]); |
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ts->target_v86->regs.gs = tswap16(env->segs[R_GS]); |
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ts->target_v86->regs.eflags = tswap32(env->eflags); |
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/* restore 32 bit registers */ |
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env->regs[R_EAX] = ts->vm86_saved_regs.eax; |
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env->regs[R_EBX] = ts->vm86_saved_regs.ebx; |
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env->regs[R_ECX] = ts->vm86_saved_regs.ecx; |
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env->regs[R_EDX] = ts->vm86_saved_regs.edx; |
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env->regs[R_ESI] = ts->vm86_saved_regs.esi; |
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env->regs[R_EDI] = ts->vm86_saved_regs.edi; |
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env->regs[R_EBP] = ts->vm86_saved_regs.ebp; |
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env->regs[R_ESP] = ts->vm86_saved_regs.esp; |
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env->eflags = ts->vm86_saved_regs.eflags; |
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env->eip = ts->vm86_saved_regs.eip; |
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cpu_x86_load_seg(env, R_CS, ts->vm86_saved_regs.cs); |
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cpu_x86_load_seg(env, R_SS, ts->vm86_saved_regs.ss); |
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cpu_x86_load_seg(env, R_DS, ts->vm86_saved_regs.ds); |
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cpu_x86_load_seg(env, R_ES, ts->vm86_saved_regs.es); |
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cpu_x86_load_seg(env, R_FS, ts->vm86_saved_regs.fs); |
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cpu_x86_load_seg(env, R_GS, ts->vm86_saved_regs.gs); |
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} |
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/* return from vm86 mode to 32 bit. The vm86() syscall will return |
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'retval' */ |
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static inline void return_to_32bit(CPUX86State *env, int retval) |
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{ |
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#ifdef DEBUG_VM86 |
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printf("return_to_32bit: ret=0x%x\n", retval); |
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#endif |
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save_v86_state(env); |
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env->regs[R_EAX] = retval; |
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} |
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/* handle VM86 interrupt (NOTE: the CPU core currently does not |
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support TSS interrupt revectoring, so this code is always executed) */ |
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static void do_int(CPUX86State *env, int intno) |
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{ |
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TaskState *ts = env->opaque; |
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uint32_t *int_ptr, segoffs; |
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if (env->segs[R_CS] == TARGET_BIOSSEG) |
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goto cannot_handle; /* XXX: I am not sure this is really useful */ |
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if (is_revectored(intno, &ts->target_v86->int_revectored)) |
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goto cannot_handle; |
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if (intno == 0x21 && is_revectored((env->regs[R_EAX] >> 8) & 0xff, |
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&ts->target_v86->int21_revectored)) |
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goto cannot_handle; |
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int_ptr = (uint32_t *)(intno << 2); |
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segoffs = tswap32(*int_ptr); |
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if ((segoffs >> 16) == TARGET_BIOSSEG) |
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goto cannot_handle; |
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#ifdef DEBUG_VM86 |
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printf("VM86: emulating int 0x%x. CS:IP=%04x:%04x\n", |
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intno, segoffs >> 16, segoffs & 0xffff); |
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#endif |
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/* save old state */ |
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pushw(env, get_vflags(env)); |
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pushw(env, env->segs[R_CS]); |
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pushw(env, env->eip); |
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/* goto interrupt handler */ |
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env->eip = segoffs & 0xffff; |
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cpu_x86_load_seg(env, R_CS, segoffs >> 16); |
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env->eflags &= ~(VIF_MASK | TF_MASK); |
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return; |
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cannot_handle: |
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#ifdef DEBUG_VM86 |
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printf("VM86: return to 32 bits int 0x%x\n", intno); |
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#endif |
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return_to_32bit(env, TARGET_VM86_INTx | (intno << 8)); |
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} |
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void cpu_loop(struct CPUX86State *env) |
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void cpu_loop(CPUX86State *env) |
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245 | 123 |
{ |
246 | 124 |
int trapnr; |
247 | 125 |
uint8_t *pc; |
... | ... | |
249 | 127 |
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250 | 128 |
for(;;) { |
251 | 129 |
trapnr = cpu_x86_exec(env); |
252 |
pc = env->seg_cache[R_CS].base + env->eip; |
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switch(trapnr) { |
254 | 131 |
case EXCP0D_GPF: |
255 | 132 |
if (env->eflags & VM_MASK) { |
256 |
#ifdef DEBUG_VM86 |
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printf("VM86 exception %04x:%08x %02x %02x\n", |
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env->segs[R_CS], env->eip, pc[0], pc[1]); |
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#endif |
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/* VM86 mode */ |
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switch(pc[0]) { |
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case 0xcd: /* int */ |
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env->eip += 2; |
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do_int(env, pc[1]); |
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break; |
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case 0x66: |
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switch(pc[1]) { |
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case 0xfb: /* sti */ |
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case 0x9d: /* popf */ |
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case 0xcf: /* iret */ |
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env->eip += 2; |
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return_to_32bit(env, TARGET_VM86_STI); |
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break; |
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default: |
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goto vm86_gpf; |
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} |
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break; |
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case 0xfb: /* sti */ |
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case 0x9d: /* popf */ |
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case 0xcf: /* iret */ |
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env->eip++; |
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return_to_32bit(env, TARGET_VM86_STI); |
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break; |
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default: |
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vm86_gpf: |
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/* real VM86 GPF exception */ |
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return_to_32bit(env, TARGET_VM86_UNKNOWN); |
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break; |
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} |
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handle_vm86_fault(env); |
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290 | 134 |
} else { |
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pc = env->seg_cache[R_CS].base + env->eip; |
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291 | 136 |
if (pc[0] == 0xcd && pc[1] == 0x80) { |
292 | 137 |
/* syscall */ |
293 | 138 |
env->eip += 2; |
... | ... | |
354 | 199 |
/* just indicate that signals should be handled asap */ |
355 | 200 |
break; |
356 | 201 |
default: |
202 |
pc = env->seg_cache[R_CS].base + env->eip; |
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357 | 203 |
fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n", |
358 | 204 |
(long)pc, trapnr); |
359 | 205 |
abort(); |
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