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1 | e6e5906b | pbrook | /*
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2 | e6e5906b | pbrook | * m68k virtual CPU header
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3 | 5fafdf24 | ths | *
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4 | 0633879f | pbrook | * Copyright (c) 2005-2007 CodeSourcery
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5 | e6e5906b | pbrook | * Written by Paul Brook
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6 | e6e5906b | pbrook | *
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7 | e6e5906b | pbrook | * This library is free software; you can redistribute it and/or
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8 | e6e5906b | pbrook | * modify it under the terms of the GNU Lesser General Public
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9 | e6e5906b | pbrook | * License as published by the Free Software Foundation; either
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10 | e6e5906b | pbrook | * version 2 of the License, or (at your option) any later version.
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11 | e6e5906b | pbrook | *
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12 | e6e5906b | pbrook | * This library is distributed in the hope that it will be useful,
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13 | e6e5906b | pbrook | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 | e6e5906b | pbrook | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 | e6e5906b | pbrook | * General Public License for more details.
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16 | e6e5906b | pbrook | *
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17 | e6e5906b | pbrook | * You should have received a copy of the GNU Lesser General Public
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18 | e6e5906b | pbrook | * License along with this library; if not, write to the Free Software
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19 | e6e5906b | pbrook | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20 | e6e5906b | pbrook | */
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21 | e6e5906b | pbrook | #ifndef CPU_M68K_H
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22 | e6e5906b | pbrook | #define CPU_M68K_H
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23 | e6e5906b | pbrook | |
24 | e6e5906b | pbrook | #define TARGET_LONG_BITS 32 |
25 | e6e5906b | pbrook | |
26 | e6e5906b | pbrook | #include "cpu-defs.h" |
27 | e6e5906b | pbrook | |
28 | e6e5906b | pbrook | #include "softfloat.h" |
29 | e6e5906b | pbrook | |
30 | e6e5906b | pbrook | #define MAX_QREGS 32 |
31 | e6e5906b | pbrook | |
32 | e6e5906b | pbrook | #define TARGET_HAS_ICE 1 |
33 | e6e5906b | pbrook | |
34 | 9042c0e2 | ths | #define ELF_MACHINE EM_68K
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35 | 9042c0e2 | ths | |
36 | e6e5906b | pbrook | #define EXCP_ACCESS 2 /* Access (MMU) error. */ |
37 | e6e5906b | pbrook | #define EXCP_ADDRESS 3 /* Address error. */ |
38 | e6e5906b | pbrook | #define EXCP_ILLEGAL 4 /* Illegal instruction. */ |
39 | e6e5906b | pbrook | #define EXCP_DIV0 5 /* Divide by zero */ |
40 | e6e5906b | pbrook | #define EXCP_PRIVILEGE 8 /* Privilege violation. */ |
41 | e6e5906b | pbrook | #define EXCP_TRACE 9 |
42 | e6e5906b | pbrook | #define EXCP_LINEA 10 /* Unimplemented line-A (MAC) opcode. */ |
43 | e6e5906b | pbrook | #define EXCP_LINEF 11 /* Unimplemented line-F (FPU) opcode. */ |
44 | e6e5906b | pbrook | #define EXCP_DEBUGNBP 12 /* Non-breakpoint debug interrupt. */ |
45 | e6e5906b | pbrook | #define EXCP_DEBEGBP 13 /* Breakpoint debug interrupt. */ |
46 | e6e5906b | pbrook | #define EXCP_FORMAT 14 /* RTE format error. */ |
47 | e6e5906b | pbrook | #define EXCP_UNINITIALIZED 15 |
48 | e6e5906b | pbrook | #define EXCP_TRAP0 32 /* User trap #0. */ |
49 | e6e5906b | pbrook | #define EXCP_TRAP15 47 /* User trap #15. */ |
50 | e6e5906b | pbrook | #define EXCP_UNSUPPORTED 61 |
51 | e6e5906b | pbrook | #define EXCP_ICE 13 |
52 | e6e5906b | pbrook | |
53 | 0633879f | pbrook | #define EXCP_RTE 0x100 |
54 | a87295e8 | pbrook | #define EXCP_HALT_INSN 0x101 |
55 | 0633879f | pbrook | |
56 | e6e5906b | pbrook | typedef struct CPUM68KState { |
57 | e6e5906b | pbrook | uint32_t dregs[8];
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58 | e6e5906b | pbrook | uint32_t aregs[8];
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59 | e6e5906b | pbrook | uint32_t pc; |
60 | e6e5906b | pbrook | uint32_t sr; |
61 | e6e5906b | pbrook | |
62 | 20dcee94 | pbrook | /* SSP and USP. The current_sp is stored in aregs[7], the other here. */
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63 | 20dcee94 | pbrook | int current_sp;
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64 | 20dcee94 | pbrook | uint32_t sp[2];
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65 | 20dcee94 | pbrook | |
66 | e6e5906b | pbrook | /* Condition flags. */
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67 | e6e5906b | pbrook | uint32_t cc_op; |
68 | e6e5906b | pbrook | uint32_t cc_dest; |
69 | e6e5906b | pbrook | uint32_t cc_src; |
70 | e6e5906b | pbrook | uint32_t cc_x; |
71 | e6e5906b | pbrook | |
72 | e6e5906b | pbrook | float64 fregs[8];
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73 | e6e5906b | pbrook | float64 fp_result; |
74 | e6e5906b | pbrook | uint32_t fpcr; |
75 | e6e5906b | pbrook | uint32_t fpsr; |
76 | e6e5906b | pbrook | float_status fp_status; |
77 | e6e5906b | pbrook | |
78 | acf930aa | pbrook | uint64_t mactmp; |
79 | acf930aa | pbrook | /* EMAC Hardware deals with 48-bit values composed of one 32-bit and
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80 | acf930aa | pbrook | two 8-bit parts. We store a single 64-bit value and
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81 | acf930aa | pbrook | rearrange/extend this when changing modes. */
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82 | acf930aa | pbrook | uint64_t macc[4];
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83 | acf930aa | pbrook | uint32_t macsr; |
84 | acf930aa | pbrook | uint32_t mac_mask; |
85 | acf930aa | pbrook | |
86 | e6e5906b | pbrook | /* Temporary storage for DIV helpers. */
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87 | e6e5906b | pbrook | uint32_t div1; |
88 | e6e5906b | pbrook | uint32_t div2; |
89 | 3b46e624 | ths | |
90 | e6e5906b | pbrook | /* MMU status. */
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91 | e6e5906b | pbrook | struct {
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92 | e6e5906b | pbrook | uint32_t ar; |
93 | e6e5906b | pbrook | } mmu; |
94 | 0633879f | pbrook | |
95 | 0633879f | pbrook | /* Control registers. */
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96 | 0633879f | pbrook | uint32_t vbr; |
97 | 0633879f | pbrook | uint32_t mbar; |
98 | 0633879f | pbrook | uint32_t rambar0; |
99 | 20dcee94 | pbrook | uint32_t cacr; |
100 | 0633879f | pbrook | |
101 | 0402f767 | pbrook | uint32_t features; |
102 | 0402f767 | pbrook | |
103 | e6e5906b | pbrook | /* ??? remove this. */
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104 | e6e5906b | pbrook | uint32_t t1; |
105 | e6e5906b | pbrook | |
106 | e6e5906b | pbrook | /* exception/interrupt handling */
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107 | e6e5906b | pbrook | jmp_buf jmp_env; |
108 | e6e5906b | pbrook | int exception_index;
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109 | e6e5906b | pbrook | int interrupt_request;
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110 | e6e5906b | pbrook | int user_mode_only;
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111 | 0633879f | pbrook | int halted;
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112 | 0633879f | pbrook | |
113 | 0633879f | pbrook | int pending_vector;
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114 | 0633879f | pbrook | int pending_level;
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115 | e6e5906b | pbrook | |
116 | e6e5906b | pbrook | uint32_t qregs[MAX_QREGS]; |
117 | e6e5906b | pbrook | |
118 | e6e5906b | pbrook | CPU_COMMON |
119 | e6e5906b | pbrook | } CPUM68KState; |
120 | e6e5906b | pbrook | |
121 | e6e5906b | pbrook | CPUM68KState *cpu_m68k_init(void);
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122 | e6e5906b | pbrook | int cpu_m68k_exec(CPUM68KState *s);
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123 | e6e5906b | pbrook | void cpu_m68k_close(CPUM68KState *s);
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124 | 0633879f | pbrook | void do_interrupt(int is_hw); |
125 | e6e5906b | pbrook | /* you can call this signal handler from your SIGBUS and SIGSEGV
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126 | e6e5906b | pbrook | signal handlers to inform the virtual CPU of exceptions. non zero
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127 | e6e5906b | pbrook | is returned if the signal was handled by the virtual CPU. */
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128 | 5fafdf24 | ths | int cpu_m68k_signal_handler(int host_signum, void *pinfo, |
129 | e6e5906b | pbrook | void *puc);
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130 | e6e5906b | pbrook | void cpu_m68k_flush_flags(CPUM68KState *, int); |
131 | e6e5906b | pbrook | |
132 | e6e5906b | pbrook | enum {
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133 | e6e5906b | pbrook | CC_OP_DYNAMIC, /* Use env->cc_op */
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134 | e6e5906b | pbrook | CC_OP_FLAGS, /* CC_DEST = CVZN, CC_SRC = unused */
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135 | e6e5906b | pbrook | CC_OP_LOGIC, /* CC_DEST = result, CC_SRC = unused */
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136 | e6e5906b | pbrook | CC_OP_ADD, /* CC_DEST = result, CC_SRC = source */
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137 | e6e5906b | pbrook | CC_OP_SUB, /* CC_DEST = result, CC_SRC = source */
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138 | e6e5906b | pbrook | CC_OP_CMPB, /* CC_DEST = result, CC_SRC = source */
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139 | e6e5906b | pbrook | CC_OP_CMPW, /* CC_DEST = result, CC_SRC = source */
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140 | e6e5906b | pbrook | CC_OP_ADDX, /* CC_DEST = result, CC_SRC = source */
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141 | e6e5906b | pbrook | CC_OP_SUBX, /* CC_DEST = result, CC_SRC = source */
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142 | e6e5906b | pbrook | CC_OP_SHL, /* CC_DEST = source, CC_SRC = shift */
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143 | e6e5906b | pbrook | CC_OP_SHR, /* CC_DEST = source, CC_SRC = shift */
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144 | e6e5906b | pbrook | CC_OP_SAR, /* CC_DEST = source, CC_SRC = shift */
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145 | e6e5906b | pbrook | }; |
146 | e6e5906b | pbrook | |
147 | e6e5906b | pbrook | #define CCF_C 0x01 |
148 | e6e5906b | pbrook | #define CCF_V 0x02 |
149 | e6e5906b | pbrook | #define CCF_Z 0x04 |
150 | e6e5906b | pbrook | #define CCF_N 0x08 |
151 | 0633879f | pbrook | #define CCF_X 0x10 |
152 | 0633879f | pbrook | |
153 | 0633879f | pbrook | #define SR_I_SHIFT 8 |
154 | 0633879f | pbrook | #define SR_I 0x0700 |
155 | 0633879f | pbrook | #define SR_M 0x1000 |
156 | 0633879f | pbrook | #define SR_S 0x2000 |
157 | 0633879f | pbrook | #define SR_T 0x8000 |
158 | e6e5906b | pbrook | |
159 | 20dcee94 | pbrook | #define M68K_SSP 0 |
160 | 20dcee94 | pbrook | #define M68K_USP 1 |
161 | 20dcee94 | pbrook | |
162 | 20dcee94 | pbrook | /* CACR fields are implementation defined, but some bits are common. */
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163 | 20dcee94 | pbrook | #define M68K_CACR_EUSP 0x10 |
164 | 20dcee94 | pbrook | |
165 | acf930aa | pbrook | #define MACSR_PAV0 0x100 |
166 | acf930aa | pbrook | #define MACSR_OMC 0x080 |
167 | acf930aa | pbrook | #define MACSR_SU 0x040 |
168 | acf930aa | pbrook | #define MACSR_FI 0x020 |
169 | acf930aa | pbrook | #define MACSR_RT 0x010 |
170 | acf930aa | pbrook | #define MACSR_N 0x008 |
171 | acf930aa | pbrook | #define MACSR_Z 0x004 |
172 | acf930aa | pbrook | #define MACSR_V 0x002 |
173 | acf930aa | pbrook | #define MACSR_EV 0x001 |
174 | acf930aa | pbrook | |
175 | e6e5906b | pbrook | typedef struct m68k_def_t m68k_def_t; |
176 | e6e5906b | pbrook | |
177 | 0633879f | pbrook | int cpu_m68k_set_model(CPUM68KState *env, const char * name); |
178 | 0633879f | pbrook | |
179 | 0633879f | pbrook | void m68k_set_irq_level(CPUM68KState *env, int level, uint8_t vector); |
180 | acf930aa | pbrook | void m68k_set_macsr(CPUM68KState *env, uint32_t val);
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181 | 20dcee94 | pbrook | void m68k_switch_sp(CPUM68KState *env);
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182 | e6e5906b | pbrook | |
183 | e6e5906b | pbrook | #define M68K_FPCR_PREC (1 << 6) |
184 | e6e5906b | pbrook | |
185 | a87295e8 | pbrook | void do_m68k_semihosting(CPUM68KState *env, int nr); |
186 | a87295e8 | pbrook | |
187 | d315c888 | pbrook | /* There are 4 ColdFire core ISA revisions: A, A+, B and C.
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188 | d315c888 | pbrook | Each feature covers the subset of instructions common to the
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189 | d315c888 | pbrook | ISA revisions mentioned. */
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190 | d315c888 | pbrook | |
191 | 0402f767 | pbrook | enum m68k_features {
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192 | 0402f767 | pbrook | M68K_FEATURE_CF_ISA_A, |
193 | d315c888 | pbrook | M68K_FEATURE_CF_ISA_B, /* (ISA B or C). */
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194 | d315c888 | pbrook | M68K_FEATURE_CF_ISA_APLUSC, /* BIT/BITREV, FF1, STRLDSR (ISA A+ or C). */
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195 | d315c888 | pbrook | M68K_FEATURE_BRAL, /* Long unconditional branch. (ISA A+ or B). */
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196 | 0402f767 | pbrook | M68K_FEATURE_CF_FPU, |
197 | 0402f767 | pbrook | M68K_FEATURE_CF_MAC, |
198 | 0402f767 | pbrook | M68K_FEATURE_CF_EMAC, |
199 | d315c888 | pbrook | M68K_FEATURE_CF_EMAC_B, /* Revision B EMAC (dual accumulate). */
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200 | d315c888 | pbrook | M68K_FEATURE_USP, /* User Stack Pointer. (ISA A+, B or C). */
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201 | e6dbd3b3 | pbrook | M68K_FEATURE_EXT_FULL, /* 68020+ full extension word. */
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202 | e6dbd3b3 | pbrook | M68K_FEATURE_WORD_INDEX /* word sized address index registers. */
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203 | 0402f767 | pbrook | }; |
204 | 0402f767 | pbrook | |
205 | 0402f767 | pbrook | static inline int m68k_feature(CPUM68KState *env, int feature) |
206 | 0402f767 | pbrook | { |
207 | 0402f767 | pbrook | return (env->features & (1u << feature)) != 0; |
208 | 0402f767 | pbrook | } |
209 | 0402f767 | pbrook | |
210 | 0402f767 | pbrook | void register_m68k_insns (CPUM68KState *env);
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211 | 0402f767 | pbrook | |
212 | e6e5906b | pbrook | #ifdef CONFIG_USER_ONLY
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213 | e6e5906b | pbrook | /* Linux uses 8k pages. */
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214 | e6e5906b | pbrook | #define TARGET_PAGE_BITS 13 |
215 | e6e5906b | pbrook | #else
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216 | 5fafdf24 | ths | /* Smallest TLB entry size is 1k. */
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217 | e6e5906b | pbrook | #define TARGET_PAGE_BITS 10 |
218 | e6e5906b | pbrook | #endif
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219 | 9467d44c | ths | |
220 | 9467d44c | ths | #define CPUState CPUM68KState
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221 | 9467d44c | ths | #define cpu_init cpu_m68k_init
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222 | 9467d44c | ths | #define cpu_exec cpu_m68k_exec
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223 | 9467d44c | ths | #define cpu_gen_code cpu_m68k_gen_code
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224 | 9467d44c | ths | #define cpu_signal_handler cpu_m68k_signal_handler
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225 | 9467d44c | ths | |
226 | e6e5906b | pbrook | #include "cpu-all.h" |
227 | e6e5906b | pbrook | |
228 | e6e5906b | pbrook | #endif |