root / target-sh4 / op.c @ 89fc88da
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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 emulation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | fdf9b3e8 | bellard | * License along with this library; if not, write to the Free Software
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18 | fdf9b3e8 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | fdf9b3e8 | bellard | */
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20 | fdf9b3e8 | bellard | #include "exec.h" |
21 | fdf9b3e8 | bellard | |
22 | fdf9b3e8 | bellard | static inline void set_flag(uint32_t flag) |
23 | fdf9b3e8 | bellard | { |
24 | fdf9b3e8 | bellard | env->flags |= flag; |
25 | fdf9b3e8 | bellard | } |
26 | fdf9b3e8 | bellard | |
27 | fdf9b3e8 | bellard | static inline void clr_flag(uint32_t flag) |
28 | fdf9b3e8 | bellard | { |
29 | fdf9b3e8 | bellard | env->flags &= ~flag; |
30 | fdf9b3e8 | bellard | } |
31 | fdf9b3e8 | bellard | |
32 | fdf9b3e8 | bellard | static inline void set_t(void) |
33 | fdf9b3e8 | bellard | { |
34 | fdf9b3e8 | bellard | env->sr |= SR_T; |
35 | fdf9b3e8 | bellard | } |
36 | fdf9b3e8 | bellard | |
37 | fdf9b3e8 | bellard | static inline void clr_t(void) |
38 | fdf9b3e8 | bellard | { |
39 | fdf9b3e8 | bellard | env->sr &= ~SR_T; |
40 | fdf9b3e8 | bellard | } |
41 | fdf9b3e8 | bellard | |
42 | fdf9b3e8 | bellard | static inline void cond_t(int cond) |
43 | fdf9b3e8 | bellard | { |
44 | fdf9b3e8 | bellard | if (cond)
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45 | fdf9b3e8 | bellard | set_t(); |
46 | fdf9b3e8 | bellard | else
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47 | fdf9b3e8 | bellard | clr_t(); |
48 | fdf9b3e8 | bellard | } |
49 | fdf9b3e8 | bellard | |
50 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_T0(void) |
51 | fdf9b3e8 | bellard | { |
52 | fdf9b3e8 | bellard | T0 = (uint32_t) PARAM1; |
53 | fdf9b3e8 | bellard | RETURN(); |
54 | fdf9b3e8 | bellard | } |
55 | fdf9b3e8 | bellard | |
56 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_T1(void) |
57 | fdf9b3e8 | bellard | { |
58 | fdf9b3e8 | bellard | T0 = (uint32_t) PARAM1; |
59 | fdf9b3e8 | bellard | RETURN(); |
60 | fdf9b3e8 | bellard | } |
61 | fdf9b3e8 | bellard | |
62 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_T2(void) |
63 | fdf9b3e8 | bellard | { |
64 | fdf9b3e8 | bellard | T0 = (uint32_t) PARAM1; |
65 | fdf9b3e8 | bellard | RETURN(); |
66 | fdf9b3e8 | bellard | } |
67 | fdf9b3e8 | bellard | |
68 | fdf9b3e8 | bellard | void OPPROTO op_cmp_eq_imm_T0(void) |
69 | fdf9b3e8 | bellard | { |
70 | fdf9b3e8 | bellard | cond_t((int32_t) T0 == (int32_t) PARAM1); |
71 | fdf9b3e8 | bellard | RETURN(); |
72 | fdf9b3e8 | bellard | } |
73 | fdf9b3e8 | bellard | |
74 | fdf9b3e8 | bellard | void OPPROTO op_cmd_eq_T0_T1(void) |
75 | fdf9b3e8 | bellard | { |
76 | fdf9b3e8 | bellard | cond_t(T0 == T1); |
77 | fdf9b3e8 | bellard | RETURN(); |
78 | fdf9b3e8 | bellard | } |
79 | fdf9b3e8 | bellard | |
80 | fdf9b3e8 | bellard | void OPPROTO op_cmd_hs_T0_T1(void) |
81 | fdf9b3e8 | bellard | { |
82 | fdf9b3e8 | bellard | cond_t((uint32_t) T0 <= (uint32_t) T1); |
83 | fdf9b3e8 | bellard | RETURN(); |
84 | fdf9b3e8 | bellard | } |
85 | fdf9b3e8 | bellard | |
86 | fdf9b3e8 | bellard | void OPPROTO op_cmd_ge_T0_T1(void) |
87 | fdf9b3e8 | bellard | { |
88 | fdf9b3e8 | bellard | cond_t((int32_t) T0 <= (int32_t) T1); |
89 | fdf9b3e8 | bellard | RETURN(); |
90 | fdf9b3e8 | bellard | } |
91 | fdf9b3e8 | bellard | |
92 | fdf9b3e8 | bellard | void OPPROTO op_cmd_hi_T0_T1(void) |
93 | fdf9b3e8 | bellard | { |
94 | fdf9b3e8 | bellard | cond_t((uint32_t) T0 < (uint32_t) T1); |
95 | fdf9b3e8 | bellard | RETURN(); |
96 | fdf9b3e8 | bellard | } |
97 | fdf9b3e8 | bellard | |
98 | fdf9b3e8 | bellard | void OPPROTO op_cmd_gt_T0_T1(void) |
99 | fdf9b3e8 | bellard | { |
100 | fdf9b3e8 | bellard | cond_t((int32_t) T0 < (int32_t) T1); |
101 | fdf9b3e8 | bellard | RETURN(); |
102 | fdf9b3e8 | bellard | } |
103 | fdf9b3e8 | bellard | |
104 | fdf9b3e8 | bellard | void OPPROTO op_not_T0(void) |
105 | fdf9b3e8 | bellard | { |
106 | fdf9b3e8 | bellard | T0 = ~T0; |
107 | fdf9b3e8 | bellard | RETURN(); |
108 | fdf9b3e8 | bellard | } |
109 | fdf9b3e8 | bellard | |
110 | fdf9b3e8 | bellard | void OPPROTO op_bf_s(void) |
111 | fdf9b3e8 | bellard | { |
112 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1; |
113 | 9c2a9ea1 | pbrook | set_flag(DELAY_SLOT_CONDITIONAL | ((~env->sr) & SR_T)); |
114 | fdf9b3e8 | bellard | RETURN(); |
115 | fdf9b3e8 | bellard | } |
116 | fdf9b3e8 | bellard | |
117 | fdf9b3e8 | bellard | void OPPROTO op_bt_s(void) |
118 | fdf9b3e8 | bellard | { |
119 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1; |
120 | 9c2a9ea1 | pbrook | set_flag(DELAY_SLOT_CONDITIONAL | (env->sr & SR_T)); |
121 | fdf9b3e8 | bellard | RETURN(); |
122 | fdf9b3e8 | bellard | } |
123 | fdf9b3e8 | bellard | |
124 | fdf9b3e8 | bellard | void OPPROTO op_bra(void) |
125 | fdf9b3e8 | bellard | { |
126 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1; |
127 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
128 | fdf9b3e8 | bellard | RETURN(); |
129 | fdf9b3e8 | bellard | } |
130 | fdf9b3e8 | bellard | |
131 | fdf9b3e8 | bellard | void OPPROTO op_braf_T0(void) |
132 | fdf9b3e8 | bellard | { |
133 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1 + T0; |
134 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
135 | fdf9b3e8 | bellard | RETURN(); |
136 | fdf9b3e8 | bellard | } |
137 | fdf9b3e8 | bellard | |
138 | fdf9b3e8 | bellard | void OPPROTO op_bsr(void) |
139 | fdf9b3e8 | bellard | { |
140 | fdf9b3e8 | bellard | env->pr = PARAM1; |
141 | fdf9b3e8 | bellard | env->delayed_pc = PARAM2; |
142 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
143 | fdf9b3e8 | bellard | RETURN(); |
144 | fdf9b3e8 | bellard | } |
145 | fdf9b3e8 | bellard | |
146 | fdf9b3e8 | bellard | void OPPROTO op_bsrf_T0(void) |
147 | fdf9b3e8 | bellard | { |
148 | fdf9b3e8 | bellard | env->pr = PARAM1; |
149 | fdf9b3e8 | bellard | env->delayed_pc = PARAM1 + T0; |
150 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
151 | fdf9b3e8 | bellard | RETURN(); |
152 | fdf9b3e8 | bellard | } |
153 | fdf9b3e8 | bellard | |
154 | fdf9b3e8 | bellard | void OPPROTO op_jsr_T0(void) |
155 | fdf9b3e8 | bellard | { |
156 | fdf9b3e8 | bellard | env->pr = PARAM1; |
157 | fdf9b3e8 | bellard | env->delayed_pc = T0; |
158 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
159 | fdf9b3e8 | bellard | RETURN(); |
160 | fdf9b3e8 | bellard | } |
161 | fdf9b3e8 | bellard | |
162 | fdf9b3e8 | bellard | void OPPROTO op_rts(void) |
163 | fdf9b3e8 | bellard | { |
164 | fdf9b3e8 | bellard | env->delayed_pc = env->pr; |
165 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
166 | fdf9b3e8 | bellard | RETURN(); |
167 | fdf9b3e8 | bellard | } |
168 | fdf9b3e8 | bellard | |
169 | fdf9b3e8 | bellard | void OPPROTO op_clr_delay_slot(void) |
170 | fdf9b3e8 | bellard | { |
171 | fdf9b3e8 | bellard | clr_flag(DELAY_SLOT); |
172 | fdf9b3e8 | bellard | RETURN(); |
173 | fdf9b3e8 | bellard | } |
174 | fdf9b3e8 | bellard | |
175 | fdf9b3e8 | bellard | void OPPROTO op_clr_delay_slot_conditional(void) |
176 | fdf9b3e8 | bellard | { |
177 | fdf9b3e8 | bellard | clr_flag(DELAY_SLOT_CONDITIONAL); |
178 | fdf9b3e8 | bellard | RETURN(); |
179 | fdf9b3e8 | bellard | } |
180 | fdf9b3e8 | bellard | |
181 | fdf9b3e8 | bellard | void OPPROTO op_exit_tb(void) |
182 | fdf9b3e8 | bellard | { |
183 | fdf9b3e8 | bellard | EXIT_TB(); |
184 | fdf9b3e8 | bellard | RETURN(); |
185 | fdf9b3e8 | bellard | } |
186 | fdf9b3e8 | bellard | |
187 | fdf9b3e8 | bellard | void OPPROTO op_addl_imm_T0(void) |
188 | fdf9b3e8 | bellard | { |
189 | fdf9b3e8 | bellard | T0 += PARAM1; |
190 | fdf9b3e8 | bellard | RETURN(); |
191 | fdf9b3e8 | bellard | } |
192 | fdf9b3e8 | bellard | |
193 | fdf9b3e8 | bellard | void OPPROTO op_addl_imm_T1(void) |
194 | fdf9b3e8 | bellard | { |
195 | fdf9b3e8 | bellard | T1 += PARAM1; |
196 | fdf9b3e8 | bellard | RETURN(); |
197 | fdf9b3e8 | bellard | } |
198 | fdf9b3e8 | bellard | |
199 | fdf9b3e8 | bellard | void OPPROTO op_clrmac(void) |
200 | fdf9b3e8 | bellard | { |
201 | fdf9b3e8 | bellard | env->mach = env->macl = 0;
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202 | fdf9b3e8 | bellard | RETURN(); |
203 | fdf9b3e8 | bellard | } |
204 | fdf9b3e8 | bellard | |
205 | fdf9b3e8 | bellard | void OPPROTO op_clrs(void) |
206 | fdf9b3e8 | bellard | { |
207 | fdf9b3e8 | bellard | env->sr &= ~SR_S; |
208 | fdf9b3e8 | bellard | RETURN(); |
209 | fdf9b3e8 | bellard | } |
210 | fdf9b3e8 | bellard | |
211 | fdf9b3e8 | bellard | void OPPROTO op_clrt(void) |
212 | fdf9b3e8 | bellard | { |
213 | fdf9b3e8 | bellard | env->sr &= ~SR_T; |
214 | fdf9b3e8 | bellard | RETURN(); |
215 | fdf9b3e8 | bellard | } |
216 | fdf9b3e8 | bellard | |
217 | fdf9b3e8 | bellard | void OPPROTO op_sets(void) |
218 | fdf9b3e8 | bellard | { |
219 | fdf9b3e8 | bellard | env->sr |= SR_S; |
220 | fdf9b3e8 | bellard | RETURN(); |
221 | fdf9b3e8 | bellard | } |
222 | fdf9b3e8 | bellard | |
223 | fdf9b3e8 | bellard | void OPPROTO op_sett(void) |
224 | fdf9b3e8 | bellard | { |
225 | fdf9b3e8 | bellard | env->sr |= SR_T; |
226 | fdf9b3e8 | bellard | RETURN(); |
227 | fdf9b3e8 | bellard | } |
228 | fdf9b3e8 | bellard | |
229 | eda9b09b | bellard | void OPPROTO op_frchg(void) |
230 | eda9b09b | bellard | { |
231 | eda9b09b | bellard | env->fpscr ^= FPSCR_FR; |
232 | eda9b09b | bellard | RETURN(); |
233 | eda9b09b | bellard | } |
234 | eda9b09b | bellard | |
235 | eda9b09b | bellard | void OPPROTO op_fschg(void) |
236 | eda9b09b | bellard | { |
237 | eda9b09b | bellard | env->fpscr ^= FPSCR_SZ; |
238 | eda9b09b | bellard | RETURN(); |
239 | eda9b09b | bellard | } |
240 | eda9b09b | bellard | |
241 | fdf9b3e8 | bellard | void OPPROTO op_rte(void) |
242 | fdf9b3e8 | bellard | { |
243 | fdf9b3e8 | bellard | env->sr = env->ssr; |
244 | fdf9b3e8 | bellard | env->delayed_pc = env->spc; |
245 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
246 | fdf9b3e8 | bellard | RETURN(); |
247 | fdf9b3e8 | bellard | } |
248 | fdf9b3e8 | bellard | |
249 | fdf9b3e8 | bellard | void OPPROTO op_swapb_T0(void) |
250 | fdf9b3e8 | bellard | { |
251 | fdf9b3e8 | bellard | T0 = (T0 & 0xffff0000) | ((T0 & 0xff) << 8) | ((T0 >> 8) & 0xff); |
252 | fdf9b3e8 | bellard | RETURN(); |
253 | fdf9b3e8 | bellard | } |
254 | fdf9b3e8 | bellard | |
255 | fdf9b3e8 | bellard | void OPPROTO op_swapw_T0(void) |
256 | fdf9b3e8 | bellard | { |
257 | fdf9b3e8 | bellard | T0 = ((T0 & 0xffff) << 16) | ((T0 >> 16) & 0xffff); |
258 | fdf9b3e8 | bellard | RETURN(); |
259 | fdf9b3e8 | bellard | } |
260 | fdf9b3e8 | bellard | |
261 | fdf9b3e8 | bellard | void OPPROTO op_xtrct_T0_T1(void) |
262 | fdf9b3e8 | bellard | { |
263 | fdf9b3e8 | bellard | T1 = ((T0 & 0xffff) << 16) | ((T1 >> 16) & 0xffff); |
264 | fdf9b3e8 | bellard | RETURN(); |
265 | fdf9b3e8 | bellard | } |
266 | fdf9b3e8 | bellard | |
267 | fdf9b3e8 | bellard | void OPPROTO op_addc_T0_T1(void) |
268 | fdf9b3e8 | bellard | { |
269 | fdf9b3e8 | bellard | helper_addc_T0_T1(); |
270 | fdf9b3e8 | bellard | RETURN(); |
271 | fdf9b3e8 | bellard | } |
272 | fdf9b3e8 | bellard | |
273 | fdf9b3e8 | bellard | void OPPROTO op_addv_T0_T1(void) |
274 | fdf9b3e8 | bellard | { |
275 | fdf9b3e8 | bellard | helper_addv_T0_T1(); |
276 | fdf9b3e8 | bellard | RETURN(); |
277 | fdf9b3e8 | bellard | } |
278 | fdf9b3e8 | bellard | |
279 | fdf9b3e8 | bellard | void OPPROTO op_cmp_eq_T0_T1(void) |
280 | fdf9b3e8 | bellard | { |
281 | fdf9b3e8 | bellard | cond_t(T1 == T0); |
282 | fdf9b3e8 | bellard | RETURN(); |
283 | fdf9b3e8 | bellard | } |
284 | fdf9b3e8 | bellard | |
285 | fdf9b3e8 | bellard | void OPPROTO op_cmp_ge_T0_T1(void) |
286 | fdf9b3e8 | bellard | { |
287 | fdf9b3e8 | bellard | cond_t((int32_t) T1 >= (int32_t) T0); |
288 | fdf9b3e8 | bellard | RETURN(); |
289 | fdf9b3e8 | bellard | } |
290 | fdf9b3e8 | bellard | |
291 | fdf9b3e8 | bellard | void OPPROTO op_cmp_gt_T0_T1(void) |
292 | fdf9b3e8 | bellard | { |
293 | fdf9b3e8 | bellard | cond_t((int32_t) T1 > (int32_t) T0); |
294 | fdf9b3e8 | bellard | RETURN(); |
295 | fdf9b3e8 | bellard | } |
296 | fdf9b3e8 | bellard | |
297 | fdf9b3e8 | bellard | void OPPROTO op_cmp_hi_T0_T1(void) |
298 | fdf9b3e8 | bellard | { |
299 | fdf9b3e8 | bellard | cond_t((uint32_t) T1 > (uint32_t) T0); |
300 | fdf9b3e8 | bellard | RETURN(); |
301 | fdf9b3e8 | bellard | } |
302 | fdf9b3e8 | bellard | |
303 | fdf9b3e8 | bellard | void OPPROTO op_cmp_hs_T0_T1(void) |
304 | fdf9b3e8 | bellard | { |
305 | fdf9b3e8 | bellard | cond_t((uint32_t) T1 >= (uint32_t) T0); |
306 | fdf9b3e8 | bellard | RETURN(); |
307 | fdf9b3e8 | bellard | } |
308 | fdf9b3e8 | bellard | |
309 | fdf9b3e8 | bellard | void OPPROTO op_cmp_str_T0_T1(void) |
310 | fdf9b3e8 | bellard | { |
311 | fdf9b3e8 | bellard | cond_t((T0 & 0x000000ff) == (T1 & 0x000000ff) || |
312 | fdf9b3e8 | bellard | (T0 & 0x0000ff00) == (T1 & 0x0000ff00) || |
313 | fdf9b3e8 | bellard | (T0 & 0x00ff0000) == (T1 & 0x00ff0000) || |
314 | fdf9b3e8 | bellard | (T0 & 0xff000000) == (T1 & 0xff000000)); |
315 | fdf9b3e8 | bellard | RETURN(); |
316 | fdf9b3e8 | bellard | } |
317 | fdf9b3e8 | bellard | |
318 | fdf9b3e8 | bellard | void OPPROTO op_tst_T0_T1(void) |
319 | fdf9b3e8 | bellard | { |
320 | fdf9b3e8 | bellard | cond_t((T1 & T0) == 0);
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321 | fdf9b3e8 | bellard | RETURN(); |
322 | fdf9b3e8 | bellard | } |
323 | fdf9b3e8 | bellard | |
324 | fdf9b3e8 | bellard | void OPPROTO op_div0s_T0_T1(void) |
325 | fdf9b3e8 | bellard | { |
326 | fdf9b3e8 | bellard | if (T1 & 0x80000000) |
327 | fdf9b3e8 | bellard | env->sr |= SR_Q; |
328 | fdf9b3e8 | bellard | else
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329 | fdf9b3e8 | bellard | env->sr &= ~SR_Q; |
330 | fdf9b3e8 | bellard | if (T0 & 0x80000000) |
331 | fdf9b3e8 | bellard | env->sr |= SR_M; |
332 | fdf9b3e8 | bellard | else
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333 | fdf9b3e8 | bellard | env->sr &= ~SR_M; |
334 | fdf9b3e8 | bellard | cond_t((T1 ^ T0) & 0x80000000);
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335 | fdf9b3e8 | bellard | RETURN(); |
336 | fdf9b3e8 | bellard | } |
337 | fdf9b3e8 | bellard | |
338 | fdf9b3e8 | bellard | void OPPROTO op_div0u(void) |
339 | fdf9b3e8 | bellard | { |
340 | fdf9b3e8 | bellard | env->sr &= ~(SR_M | SR_Q | SR_T); |
341 | fdf9b3e8 | bellard | RETURN(); |
342 | fdf9b3e8 | bellard | } |
343 | fdf9b3e8 | bellard | |
344 | fdf9b3e8 | bellard | void OPPROTO op_div1_T0_T1(void) |
345 | fdf9b3e8 | bellard | { |
346 | fdf9b3e8 | bellard | helper_div1_T0_T1(); |
347 | fdf9b3e8 | bellard | RETURN(); |
348 | fdf9b3e8 | bellard | } |
349 | fdf9b3e8 | bellard | |
350 | fdf9b3e8 | bellard | void OPPROTO op_dmulsl_T0_T1(void) |
351 | fdf9b3e8 | bellard | { |
352 | fdf9b3e8 | bellard | helper_dmulsl_T0_T1(); |
353 | fdf9b3e8 | bellard | RETURN(); |
354 | fdf9b3e8 | bellard | } |
355 | fdf9b3e8 | bellard | |
356 | fdf9b3e8 | bellard | void OPPROTO op_dmulul_T0_T1(void) |
357 | fdf9b3e8 | bellard | { |
358 | fdf9b3e8 | bellard | helper_dmulul_T0_T1(); |
359 | fdf9b3e8 | bellard | RETURN(); |
360 | fdf9b3e8 | bellard | } |
361 | fdf9b3e8 | bellard | |
362 | fdf9b3e8 | bellard | void OPPROTO op_macl_T0_T1(void) |
363 | fdf9b3e8 | bellard | { |
364 | fdf9b3e8 | bellard | helper_macl_T0_T1(); |
365 | fdf9b3e8 | bellard | RETURN(); |
366 | fdf9b3e8 | bellard | } |
367 | fdf9b3e8 | bellard | |
368 | fdf9b3e8 | bellard | void OPPROTO op_macw_T0_T1(void) |
369 | fdf9b3e8 | bellard | { |
370 | fdf9b3e8 | bellard | helper_macw_T0_T1(); |
371 | fdf9b3e8 | bellard | RETURN(); |
372 | fdf9b3e8 | bellard | } |
373 | fdf9b3e8 | bellard | |
374 | fdf9b3e8 | bellard | void OPPROTO op_mull_T0_T1(void) |
375 | fdf9b3e8 | bellard | { |
376 | fdf9b3e8 | bellard | env->macl = (T0 * T1) & 0xffffffff;
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377 | fdf9b3e8 | bellard | RETURN(); |
378 | fdf9b3e8 | bellard | } |
379 | fdf9b3e8 | bellard | |
380 | fdf9b3e8 | bellard | void OPPROTO op_mulsw_T0_T1(void) |
381 | fdf9b3e8 | bellard | { |
382 | fdf9b3e8 | bellard | env->macl = (int32_t) T0 *(int32_t) T1; |
383 | fdf9b3e8 | bellard | RETURN(); |
384 | fdf9b3e8 | bellard | } |
385 | fdf9b3e8 | bellard | |
386 | fdf9b3e8 | bellard | void OPPROTO op_muluw_T0_T1(void) |
387 | fdf9b3e8 | bellard | { |
388 | fdf9b3e8 | bellard | env->macl = (uint32_t) T0 *(uint32_t) T1; |
389 | fdf9b3e8 | bellard | RETURN(); |
390 | fdf9b3e8 | bellard | } |
391 | fdf9b3e8 | bellard | |
392 | fdf9b3e8 | bellard | void OPPROTO op_neg_T0(void) |
393 | fdf9b3e8 | bellard | { |
394 | fdf9b3e8 | bellard | T0 = -T0; |
395 | fdf9b3e8 | bellard | RETURN(); |
396 | fdf9b3e8 | bellard | } |
397 | fdf9b3e8 | bellard | |
398 | fdf9b3e8 | bellard | void OPPROTO op_negc_T0(void) |
399 | fdf9b3e8 | bellard | { |
400 | fdf9b3e8 | bellard | helper_negc_T0(); |
401 | fdf9b3e8 | bellard | RETURN(); |
402 | fdf9b3e8 | bellard | } |
403 | fdf9b3e8 | bellard | |
404 | fdf9b3e8 | bellard | void OPPROTO op_shad_T0_T1(void) |
405 | fdf9b3e8 | bellard | { |
406 | fdf9b3e8 | bellard | if ((T0 & 0x80000000) == 0) |
407 | fdf9b3e8 | bellard | T1 <<= (T0 & 0x1f);
|
408 | fdf9b3e8 | bellard | else if ((T0 & 0x1f) == 0) |
409 | fdf9b3e8 | bellard | T1 = 0;
|
410 | fdf9b3e8 | bellard | else
|
411 | fdf9b3e8 | bellard | T1 = ((int32_t) T1) >> ((~T0 & 0x1f) + 1); |
412 | fdf9b3e8 | bellard | RETURN(); |
413 | fdf9b3e8 | bellard | } |
414 | fdf9b3e8 | bellard | |
415 | fdf9b3e8 | bellard | void OPPROTO op_shld_T0_T1(void) |
416 | fdf9b3e8 | bellard | { |
417 | fdf9b3e8 | bellard | if ((T0 & 0x80000000) == 0) |
418 | fdf9b3e8 | bellard | T1 <<= (T0 & 0x1f);
|
419 | fdf9b3e8 | bellard | else if ((T0 & 0x1f) == 0) |
420 | fdf9b3e8 | bellard | T1 = 0;
|
421 | fdf9b3e8 | bellard | else
|
422 | fdf9b3e8 | bellard | T1 = ((uint32_t) T1) >> ((~T0 & 0x1f) + 1); |
423 | fdf9b3e8 | bellard | RETURN(); |
424 | fdf9b3e8 | bellard | } |
425 | fdf9b3e8 | bellard | |
426 | fdf9b3e8 | bellard | void OPPROTO op_subc_T0_T1(void) |
427 | fdf9b3e8 | bellard | { |
428 | fdf9b3e8 | bellard | helper_subc_T0_T1(); |
429 | fdf9b3e8 | bellard | RETURN(); |
430 | fdf9b3e8 | bellard | } |
431 | fdf9b3e8 | bellard | |
432 | fdf9b3e8 | bellard | void OPPROTO op_subv_T0_T1(void) |
433 | fdf9b3e8 | bellard | { |
434 | fdf9b3e8 | bellard | helper_subv_T0_T1(); |
435 | fdf9b3e8 | bellard | RETURN(); |
436 | fdf9b3e8 | bellard | } |
437 | fdf9b3e8 | bellard | |
438 | fdf9b3e8 | bellard | void OPPROTO op_trapa(void) |
439 | fdf9b3e8 | bellard | { |
440 | fdf9b3e8 | bellard | env->tra = PARAM1 * 2;
|
441 | fdf9b3e8 | bellard | env->exception_index = 0x160;
|
442 | fdf9b3e8 | bellard | do_raise_exception(); |
443 | fdf9b3e8 | bellard | RETURN(); |
444 | fdf9b3e8 | bellard | } |
445 | fdf9b3e8 | bellard | |
446 | fdf9b3e8 | bellard | void OPPROTO op_cmp_pl_T0(void) |
447 | fdf9b3e8 | bellard | { |
448 | fdf9b3e8 | bellard | cond_t((int32_t) T0 > 0);
|
449 | fdf9b3e8 | bellard | RETURN(); |
450 | fdf9b3e8 | bellard | } |
451 | fdf9b3e8 | bellard | |
452 | fdf9b3e8 | bellard | void OPPROTO op_cmp_pz_T0(void) |
453 | fdf9b3e8 | bellard | { |
454 | fdf9b3e8 | bellard | cond_t((int32_t) T0 >= 0);
|
455 | fdf9b3e8 | bellard | RETURN(); |
456 | fdf9b3e8 | bellard | } |
457 | fdf9b3e8 | bellard | |
458 | fdf9b3e8 | bellard | void OPPROTO op_jmp_T0(void) |
459 | fdf9b3e8 | bellard | { |
460 | fdf9b3e8 | bellard | env->delayed_pc = T0; |
461 | fdf9b3e8 | bellard | set_flag(DELAY_SLOT); |
462 | fdf9b3e8 | bellard | RETURN(); |
463 | fdf9b3e8 | bellard | } |
464 | fdf9b3e8 | bellard | |
465 | fdf9b3e8 | bellard | void OPPROTO op_movl_rN_rN(void) |
466 | fdf9b3e8 | bellard | { |
467 | fdf9b3e8 | bellard | env->gregs[PARAM2] = env->gregs[PARAM1]; |
468 | fdf9b3e8 | bellard | RETURN(); |
469 | fdf9b3e8 | bellard | } |
470 | fdf9b3e8 | bellard | |
471 | fdf9b3e8 | bellard | void OPPROTO op_ldcl_rMplus_rN_bank(void) |
472 | fdf9b3e8 | bellard | { |
473 | fdf9b3e8 | bellard | env->gregs[PARAM2] = env->gregs[PARAM1]; |
474 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 4;
|
475 | fdf9b3e8 | bellard | RETURN(); |
476 | fdf9b3e8 | bellard | } |
477 | fdf9b3e8 | bellard | |
478 | eda9b09b | bellard | void OPPROTO op_ldc_T0_sr(void) |
479 | eda9b09b | bellard | { |
480 | eda9b09b | bellard | env->sr = T0 & 0x700083f3;
|
481 | eda9b09b | bellard | RETURN(); |
482 | eda9b09b | bellard | } |
483 | eda9b09b | bellard | |
484 | eda9b09b | bellard | void OPPROTO op_stc_sr_T0(void) |
485 | eda9b09b | bellard | { |
486 | eda9b09b | bellard | T0 = env->sr; |
487 | eda9b09b | bellard | RETURN(); |
488 | eda9b09b | bellard | } |
489 | eda9b09b | bellard | |
490 | fdf9b3e8 | bellard | #define LDSTOPS(target,load,store) \
|
491 | fdf9b3e8 | bellard | void OPPROTO op_##load##_T0_##target (void) \ |
492 | fdf9b3e8 | bellard | { env ->target = T0; RETURN(); \ |
493 | fdf9b3e8 | bellard | } \ |
494 | fdf9b3e8 | bellard | void OPPROTO op_##store##_##target##_T0 (void) \ |
495 | fdf9b3e8 | bellard | { T0 = env->target; RETURN(); \ |
496 | fdf9b3e8 | bellard | } \ |
497 | fdf9b3e8 | bellard | |
498 | fdf9b3e8 | bellard | LDSTOPS(gbr, ldc, stc) |
499 | fdf9b3e8 | bellard | LDSTOPS(vbr, ldc, stc) |
500 | fdf9b3e8 | bellard | LDSTOPS(ssr, ldc, stc) |
501 | fdf9b3e8 | bellard | LDSTOPS(spc, ldc, stc) |
502 | fdf9b3e8 | bellard | LDSTOPS(sgr, ldc, stc) |
503 | fdf9b3e8 | bellard | LDSTOPS(dbr, ldc, stc) |
504 | fdf9b3e8 | bellard | LDSTOPS(mach, lds, sts) |
505 | fdf9b3e8 | bellard | LDSTOPS(macl, lds, sts) |
506 | fdf9b3e8 | bellard | LDSTOPS(pr, lds, sts) |
507 | eda9b09b | bellard | LDSTOPS(fpul, lds, sts) |
508 | eda9b09b | bellard | |
509 | eda9b09b | bellard | void OPPROTO op_lds_T0_fpscr(void) |
510 | eda9b09b | bellard | { |
511 | eda9b09b | bellard | env->fpscr = T0 & 0x003fffff;
|
512 | ea6cf6be | ths | env->fp_status.float_rounding_mode = T0 & 0x01 ?
|
513 | ea6cf6be | ths | float_round_to_zero : float_round_nearest_even; |
514 | ea6cf6be | ths | |
515 | eda9b09b | bellard | RETURN(); |
516 | eda9b09b | bellard | } |
517 | eda9b09b | bellard | |
518 | eda9b09b | bellard | void OPPROTO op_sts_fpscr_T0(void) |
519 | eda9b09b | bellard | { |
520 | eda9b09b | bellard | T0 = env->fpscr & 0x003fffff;
|
521 | eda9b09b | bellard | RETURN(); |
522 | eda9b09b | bellard | } |
523 | fdf9b3e8 | bellard | |
524 | fdf9b3e8 | bellard | void OPPROTO op_movt_rN(void) |
525 | fdf9b3e8 | bellard | { |
526 | fdf9b3e8 | bellard | env->gregs[PARAM1] = env->sr & SR_T; |
527 | fdf9b3e8 | bellard | RETURN(); |
528 | fdf9b3e8 | bellard | } |
529 | fdf9b3e8 | bellard | |
530 | fdf9b3e8 | bellard | void OPPROTO op_rotcl_Rn(void) |
531 | fdf9b3e8 | bellard | { |
532 | fdf9b3e8 | bellard | helper_rotcl(&env->gregs[PARAM1]); |
533 | fdf9b3e8 | bellard | RETURN(); |
534 | fdf9b3e8 | bellard | } |
535 | fdf9b3e8 | bellard | |
536 | fdf9b3e8 | bellard | void OPPROTO op_rotcr_Rn(void) |
537 | fdf9b3e8 | bellard | { |
538 | fdf9b3e8 | bellard | helper_rotcr(&env->gregs[PARAM1]); |
539 | fdf9b3e8 | bellard | RETURN(); |
540 | fdf9b3e8 | bellard | } |
541 | fdf9b3e8 | bellard | |
542 | fdf9b3e8 | bellard | void OPPROTO op_rotl_Rn(void) |
543 | fdf9b3e8 | bellard | { |
544 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 0x80000000);
|
545 | fdf9b3e8 | bellard | env->gregs[PARAM1] = (env->gregs[PARAM1] << 1) | (env->sr & SR_T);
|
546 | fdf9b3e8 | bellard | RETURN(); |
547 | fdf9b3e8 | bellard | } |
548 | fdf9b3e8 | bellard | |
549 | fdf9b3e8 | bellard | void OPPROTO op_rotr_Rn(void) |
550 | fdf9b3e8 | bellard | { |
551 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 1);
|
552 | fdf9b3e8 | bellard | env->gregs[PARAM1] = (env->gregs[PARAM1] >> 1) |
|
553 | fdf9b3e8 | bellard | ((env->sr & SR_T) ? 0x80000000 : 0); |
554 | fdf9b3e8 | bellard | RETURN(); |
555 | fdf9b3e8 | bellard | } |
556 | fdf9b3e8 | bellard | |
557 | fdf9b3e8 | bellard | void OPPROTO op_shal_Rn(void) |
558 | fdf9b3e8 | bellard | { |
559 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 0x80000000);
|
560 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 1;
|
561 | fdf9b3e8 | bellard | RETURN(); |
562 | fdf9b3e8 | bellard | } |
563 | fdf9b3e8 | bellard | |
564 | fdf9b3e8 | bellard | void OPPROTO op_shar_Rn(void) |
565 | fdf9b3e8 | bellard | { |
566 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 1);
|
567 | a5d251bd | ths | env->gregs[PARAM1] >>= 1;
|
568 | fdf9b3e8 | bellard | RETURN(); |
569 | fdf9b3e8 | bellard | } |
570 | fdf9b3e8 | bellard | |
571 | fdf9b3e8 | bellard | void OPPROTO op_shlr_Rn(void) |
572 | fdf9b3e8 | bellard | { |
573 | fdf9b3e8 | bellard | cond_t(env->gregs[PARAM1] & 1);
|
574 | a5d251bd | ths | env->gregs[PARAM1] >>= 1;
|
575 | fdf9b3e8 | bellard | RETURN(); |
576 | fdf9b3e8 | bellard | } |
577 | fdf9b3e8 | bellard | |
578 | fdf9b3e8 | bellard | void OPPROTO op_shll2_Rn(void) |
579 | fdf9b3e8 | bellard | { |
580 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 2;
|
581 | fdf9b3e8 | bellard | RETURN(); |
582 | fdf9b3e8 | bellard | } |
583 | fdf9b3e8 | bellard | |
584 | fdf9b3e8 | bellard | void OPPROTO op_shll8_Rn(void) |
585 | fdf9b3e8 | bellard | { |
586 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 8;
|
587 | fdf9b3e8 | bellard | RETURN(); |
588 | fdf9b3e8 | bellard | } |
589 | fdf9b3e8 | bellard | |
590 | fdf9b3e8 | bellard | void OPPROTO op_shll16_Rn(void) |
591 | fdf9b3e8 | bellard | { |
592 | fdf9b3e8 | bellard | env->gregs[PARAM1] <<= 16;
|
593 | fdf9b3e8 | bellard | RETURN(); |
594 | fdf9b3e8 | bellard | } |
595 | fdf9b3e8 | bellard | |
596 | fdf9b3e8 | bellard | void OPPROTO op_shlr2_Rn(void) |
597 | fdf9b3e8 | bellard | { |
598 | a5d251bd | ths | env->gregs[PARAM1] >>= 2;
|
599 | fdf9b3e8 | bellard | RETURN(); |
600 | fdf9b3e8 | bellard | } |
601 | fdf9b3e8 | bellard | |
602 | fdf9b3e8 | bellard | void OPPROTO op_shlr8_Rn(void) |
603 | fdf9b3e8 | bellard | { |
604 | a5d251bd | ths | env->gregs[PARAM1] >>= 8;
|
605 | fdf9b3e8 | bellard | RETURN(); |
606 | fdf9b3e8 | bellard | } |
607 | fdf9b3e8 | bellard | |
608 | fdf9b3e8 | bellard | void OPPROTO op_shlr16_Rn(void) |
609 | fdf9b3e8 | bellard | { |
610 | a5d251bd | ths | env->gregs[PARAM1] >>= 16;
|
611 | fdf9b3e8 | bellard | RETURN(); |
612 | fdf9b3e8 | bellard | } |
613 | fdf9b3e8 | bellard | |
614 | fdf9b3e8 | bellard | void OPPROTO op_tasb_rN(void) |
615 | fdf9b3e8 | bellard | { |
616 | fdf9b3e8 | bellard | cond_t(*(int8_t *) env->gregs[PARAM1] == 0);
|
617 | fdf9b3e8 | bellard | *(int8_t *) env->gregs[PARAM1] |= 0x80;
|
618 | fdf9b3e8 | bellard | RETURN(); |
619 | fdf9b3e8 | bellard | } |
620 | fdf9b3e8 | bellard | |
621 | fdf9b3e8 | bellard | void OPPROTO op_movl_T0_rN(void) |
622 | fdf9b3e8 | bellard | { |
623 | fdf9b3e8 | bellard | env->gregs[PARAM1] = T0; |
624 | fdf9b3e8 | bellard | RETURN(); |
625 | fdf9b3e8 | bellard | } |
626 | fdf9b3e8 | bellard | |
627 | fdf9b3e8 | bellard | void OPPROTO op_movl_T1_rN(void) |
628 | fdf9b3e8 | bellard | { |
629 | fdf9b3e8 | bellard | env->gregs[PARAM1] = T1; |
630 | fdf9b3e8 | bellard | RETURN(); |
631 | fdf9b3e8 | bellard | } |
632 | fdf9b3e8 | bellard | |
633 | fdf9b3e8 | bellard | void OPPROTO op_movb_rN_T0(void) |
634 | fdf9b3e8 | bellard | { |
635 | fdf9b3e8 | bellard | T0 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
|
636 | fdf9b3e8 | bellard | RETURN(); |
637 | fdf9b3e8 | bellard | } |
638 | fdf9b3e8 | bellard | |
639 | fdf9b3e8 | bellard | void OPPROTO op_movub_rN_T0(void) |
640 | fdf9b3e8 | bellard | { |
641 | fdf9b3e8 | bellard | T0 = env->gregs[PARAM1] & 0xff;
|
642 | fdf9b3e8 | bellard | RETURN(); |
643 | fdf9b3e8 | bellard | } |
644 | fdf9b3e8 | bellard | |
645 | fdf9b3e8 | bellard | void OPPROTO op_movw_rN_T0(void) |
646 | fdf9b3e8 | bellard | { |
647 | fdf9b3e8 | bellard | T0 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
|
648 | fdf9b3e8 | bellard | RETURN(); |
649 | fdf9b3e8 | bellard | } |
650 | fdf9b3e8 | bellard | |
651 | fdf9b3e8 | bellard | void OPPROTO op_movuw_rN_T0(void) |
652 | fdf9b3e8 | bellard | { |
653 | fdf9b3e8 | bellard | T0 = env->gregs[PARAM1] & 0xffff;
|
654 | fdf9b3e8 | bellard | RETURN(); |
655 | fdf9b3e8 | bellard | } |
656 | fdf9b3e8 | bellard | |
657 | fdf9b3e8 | bellard | void OPPROTO op_movl_rN_T0(void) |
658 | fdf9b3e8 | bellard | { |
659 | fdf9b3e8 | bellard | T0 = env->gregs[PARAM1]; |
660 | fdf9b3e8 | bellard | RETURN(); |
661 | fdf9b3e8 | bellard | } |
662 | fdf9b3e8 | bellard | |
663 | fdf9b3e8 | bellard | void OPPROTO op_movb_rN_T1(void) |
664 | fdf9b3e8 | bellard | { |
665 | fdf9b3e8 | bellard | T1 = (int32_t) (int8_t) (env->gregs[PARAM1] & 0xff);
|
666 | fdf9b3e8 | bellard | RETURN(); |
667 | fdf9b3e8 | bellard | } |
668 | fdf9b3e8 | bellard | |
669 | fdf9b3e8 | bellard | void OPPROTO op_movub_rN_T1(void) |
670 | fdf9b3e8 | bellard | { |
671 | fdf9b3e8 | bellard | T1 = env->gregs[PARAM1] & 0xff;
|
672 | fdf9b3e8 | bellard | RETURN(); |
673 | fdf9b3e8 | bellard | } |
674 | fdf9b3e8 | bellard | |
675 | fdf9b3e8 | bellard | void OPPROTO op_movw_rN_T1(void) |
676 | fdf9b3e8 | bellard | { |
677 | fdf9b3e8 | bellard | T1 = (int32_t) (int16_t) (env->gregs[PARAM1] & 0xffff);
|
678 | fdf9b3e8 | bellard | RETURN(); |
679 | fdf9b3e8 | bellard | } |
680 | fdf9b3e8 | bellard | |
681 | fdf9b3e8 | bellard | void OPPROTO op_movuw_rN_T1(void) |
682 | fdf9b3e8 | bellard | { |
683 | fdf9b3e8 | bellard | T1 = env->gregs[PARAM1] & 0xffff;
|
684 | fdf9b3e8 | bellard | RETURN(); |
685 | fdf9b3e8 | bellard | } |
686 | fdf9b3e8 | bellard | |
687 | fdf9b3e8 | bellard | void OPPROTO op_movl_rN_T1(void) |
688 | fdf9b3e8 | bellard | { |
689 | fdf9b3e8 | bellard | T1 = env->gregs[PARAM1]; |
690 | fdf9b3e8 | bellard | RETURN(); |
691 | fdf9b3e8 | bellard | } |
692 | fdf9b3e8 | bellard | |
693 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_rN(void) |
694 | fdf9b3e8 | bellard | { |
695 | fdf9b3e8 | bellard | env->gregs[PARAM2] = PARAM1; |
696 | fdf9b3e8 | bellard | RETURN(); |
697 | fdf9b3e8 | bellard | } |
698 | fdf9b3e8 | bellard | |
699 | eda9b09b | bellard | void OPPROTO op_fmov_frN_FT0(void) |
700 | eda9b09b | bellard | { |
701 | e04ea3dc | ths | FT0 = env->fregs[PARAM1]; |
702 | eda9b09b | bellard | RETURN(); |
703 | eda9b09b | bellard | } |
704 | eda9b09b | bellard | |
705 | eda9b09b | bellard | void OPPROTO op_fmov_drN_DT0(void) |
706 | eda9b09b | bellard | { |
707 | e04ea3dc | ths | CPU_DoubleU d; |
708 | e04ea3dc | ths | |
709 | e04ea3dc | ths | d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
710 | e04ea3dc | ths | d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
711 | e04ea3dc | ths | DT0 = d.d; |
712 | eda9b09b | bellard | RETURN(); |
713 | eda9b09b | bellard | } |
714 | eda9b09b | bellard | |
715 | ea6cf6be | ths | void OPPROTO op_fmov_frN_FT1(void) |
716 | ea6cf6be | ths | { |
717 | e04ea3dc | ths | FT1 = env->fregs[PARAM1]; |
718 | ea6cf6be | ths | RETURN(); |
719 | ea6cf6be | ths | } |
720 | ea6cf6be | ths | |
721 | ea6cf6be | ths | void OPPROTO op_fmov_drN_DT1(void) |
722 | ea6cf6be | ths | { |
723 | e04ea3dc | ths | CPU_DoubleU d; |
724 | e04ea3dc | ths | |
725 | e04ea3dc | ths | d.l.upper = *(uint32_t *)&env->fregs[PARAM1]; |
726 | e04ea3dc | ths | d.l.lower = *(uint32_t *)&env->fregs[PARAM1 + 1];
|
727 | e04ea3dc | ths | DT1 = d.d; |
728 | ea6cf6be | ths | RETURN(); |
729 | ea6cf6be | ths | } |
730 | ea6cf6be | ths | |
731 | eda9b09b | bellard | void OPPROTO op_fmov_FT0_frN(void) |
732 | eda9b09b | bellard | { |
733 | e04ea3dc | ths | env->fregs[PARAM1] = FT0; |
734 | eda9b09b | bellard | RETURN(); |
735 | eda9b09b | bellard | } |
736 | eda9b09b | bellard | |
737 | eda9b09b | bellard | void OPPROTO op_fmov_DT0_drN(void) |
738 | eda9b09b | bellard | { |
739 | e04ea3dc | ths | CPU_DoubleU d; |
740 | e04ea3dc | ths | |
741 | e04ea3dc | ths | d.d = DT0; |
742 | e04ea3dc | ths | *(uint32_t *)&env->fregs[PARAM1] = d.l.upper; |
743 | e04ea3dc | ths | *(uint32_t *)&env->fregs[PARAM1 + 1] = d.l.lower;
|
744 | eda9b09b | bellard | RETURN(); |
745 | eda9b09b | bellard | } |
746 | eda9b09b | bellard | |
747 | ea6cf6be | ths | void OPPROTO op_fadd_FT(void) |
748 | ea6cf6be | ths | { |
749 | ea6cf6be | ths | FT0 = float32_add(FT0, FT1, &env->fp_status); |
750 | ea6cf6be | ths | RETURN(); |
751 | ea6cf6be | ths | } |
752 | ea6cf6be | ths | |
753 | ea6cf6be | ths | void OPPROTO op_fadd_DT(void) |
754 | ea6cf6be | ths | { |
755 | ea6cf6be | ths | DT0 = float64_add(DT0, DT1, &env->fp_status); |
756 | ea6cf6be | ths | RETURN(); |
757 | ea6cf6be | ths | } |
758 | ea6cf6be | ths | |
759 | ea6cf6be | ths | void OPPROTO op_fsub_FT(void) |
760 | ea6cf6be | ths | { |
761 | ea6cf6be | ths | FT0 = float32_sub(FT0, FT1, &env->fp_status); |
762 | ea6cf6be | ths | RETURN(); |
763 | ea6cf6be | ths | } |
764 | ea6cf6be | ths | |
765 | ea6cf6be | ths | void OPPROTO op_fsub_DT(void) |
766 | ea6cf6be | ths | { |
767 | ea6cf6be | ths | DT0 = float64_sub(DT0, DT1, &env->fp_status); |
768 | ea6cf6be | ths | RETURN(); |
769 | ea6cf6be | ths | } |
770 | ea6cf6be | ths | |
771 | ea6cf6be | ths | void OPPROTO op_fmul_FT(void) |
772 | ea6cf6be | ths | { |
773 | ea6cf6be | ths | FT0 = float32_mul(FT0, FT1, &env->fp_status); |
774 | ea6cf6be | ths | RETURN(); |
775 | ea6cf6be | ths | } |
776 | ea6cf6be | ths | |
777 | ea6cf6be | ths | void OPPROTO op_fmul_DT(void) |
778 | ea6cf6be | ths | { |
779 | ea6cf6be | ths | DT0 = float64_mul(DT0, DT1, &env->fp_status); |
780 | ea6cf6be | ths | RETURN(); |
781 | ea6cf6be | ths | } |
782 | ea6cf6be | ths | |
783 | ea6cf6be | ths | void OPPROTO op_fdiv_FT(void) |
784 | ea6cf6be | ths | { |
785 | ea6cf6be | ths | FT0 = float32_div(FT0, FT1, &env->fp_status); |
786 | ea6cf6be | ths | RETURN(); |
787 | ea6cf6be | ths | } |
788 | ea6cf6be | ths | |
789 | ea6cf6be | ths | void OPPROTO op_fdiv_DT(void) |
790 | ea6cf6be | ths | { |
791 | ea6cf6be | ths | DT0 = float64_div(DT0, DT1, &env->fp_status); |
792 | ea6cf6be | ths | RETURN(); |
793 | ea6cf6be | ths | } |
794 | ea6cf6be | ths | |
795 | ea6cf6be | ths | void OPPROTO op_float_FT(void) |
796 | ea6cf6be | ths | { |
797 | ea6cf6be | ths | FT0 = int32_to_float32(env->fpul, &env->fp_status); |
798 | ea6cf6be | ths | RETURN(); |
799 | ea6cf6be | ths | } |
800 | ea6cf6be | ths | |
801 | ea6cf6be | ths | void OPPROTO op_float_DT(void) |
802 | ea6cf6be | ths | { |
803 | ea6cf6be | ths | DT0 = int32_to_float64(env->fpul, &env->fp_status); |
804 | ea6cf6be | ths | RETURN(); |
805 | ea6cf6be | ths | } |
806 | ea6cf6be | ths | |
807 | ea6cf6be | ths | void OPPROTO op_ftrc_FT(void) |
808 | ea6cf6be | ths | { |
809 | ea6cf6be | ths | env->fpul = float32_to_int32_round_to_zero(FT0, &env->fp_status); |
810 | ea6cf6be | ths | RETURN(); |
811 | ea6cf6be | ths | } |
812 | ea6cf6be | ths | |
813 | ea6cf6be | ths | void OPPROTO op_ftrc_DT(void) |
814 | ea6cf6be | ths | { |
815 | ea6cf6be | ths | env->fpul = float64_to_int32_round_to_zero(DT0, &env->fp_status); |
816 | ea6cf6be | ths | RETURN(); |
817 | ea6cf6be | ths | } |
818 | ea6cf6be | ths | |
819 | ea6cf6be | ths | void OPPROTO op_fmov_T0_frN(void) |
820 | ea6cf6be | ths | { |
821 | ea6cf6be | ths | *(unsigned int *)&env->fregs[PARAM1] = T0; |
822 | ea6cf6be | ths | RETURN(); |
823 | ea6cf6be | ths | } |
824 | ea6cf6be | ths | |
825 | fdf9b3e8 | bellard | void OPPROTO op_dec1_rN(void) |
826 | fdf9b3e8 | bellard | { |
827 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= 1;
|
828 | fdf9b3e8 | bellard | RETURN(); |
829 | fdf9b3e8 | bellard | } |
830 | fdf9b3e8 | bellard | |
831 | fdf9b3e8 | bellard | void OPPROTO op_dec2_rN(void) |
832 | fdf9b3e8 | bellard | { |
833 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= 2;
|
834 | fdf9b3e8 | bellard | RETURN(); |
835 | fdf9b3e8 | bellard | } |
836 | fdf9b3e8 | bellard | |
837 | fdf9b3e8 | bellard | void OPPROTO op_dec4_rN(void) |
838 | fdf9b3e8 | bellard | { |
839 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= 4;
|
840 | fdf9b3e8 | bellard | RETURN(); |
841 | fdf9b3e8 | bellard | } |
842 | fdf9b3e8 | bellard | |
843 | eda9b09b | bellard | void OPPROTO op_dec8_rN(void) |
844 | eda9b09b | bellard | { |
845 | 0a618140 | ths | env->gregs[PARAM1] -= 8;
|
846 | eda9b09b | bellard | RETURN(); |
847 | eda9b09b | bellard | } |
848 | eda9b09b | bellard | |
849 | fdf9b3e8 | bellard | void OPPROTO op_inc1_rN(void) |
850 | fdf9b3e8 | bellard | { |
851 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 1;
|
852 | fdf9b3e8 | bellard | RETURN(); |
853 | fdf9b3e8 | bellard | } |
854 | fdf9b3e8 | bellard | |
855 | fdf9b3e8 | bellard | void OPPROTO op_inc2_rN(void) |
856 | fdf9b3e8 | bellard | { |
857 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 2;
|
858 | fdf9b3e8 | bellard | RETURN(); |
859 | fdf9b3e8 | bellard | } |
860 | fdf9b3e8 | bellard | |
861 | fdf9b3e8 | bellard | void OPPROTO op_inc4_rN(void) |
862 | fdf9b3e8 | bellard | { |
863 | fdf9b3e8 | bellard | env->gregs[PARAM1] += 4;
|
864 | fdf9b3e8 | bellard | RETURN(); |
865 | fdf9b3e8 | bellard | } |
866 | fdf9b3e8 | bellard | |
867 | eda9b09b | bellard | void OPPROTO op_inc8_rN(void) |
868 | eda9b09b | bellard | { |
869 | 0a618140 | ths | env->gregs[PARAM1] += 8;
|
870 | eda9b09b | bellard | RETURN(); |
871 | eda9b09b | bellard | } |
872 | eda9b09b | bellard | |
873 | fdf9b3e8 | bellard | void OPPROTO op_add_T0_rN(void) |
874 | fdf9b3e8 | bellard | { |
875 | fdf9b3e8 | bellard | env->gregs[PARAM1] += T0; |
876 | fdf9b3e8 | bellard | RETURN(); |
877 | fdf9b3e8 | bellard | } |
878 | fdf9b3e8 | bellard | |
879 | fdf9b3e8 | bellard | void OPPROTO op_sub_T0_rN(void) |
880 | fdf9b3e8 | bellard | { |
881 | fdf9b3e8 | bellard | env->gregs[PARAM1] -= T0; |
882 | fdf9b3e8 | bellard | RETURN(); |
883 | fdf9b3e8 | bellard | } |
884 | fdf9b3e8 | bellard | |
885 | fdf9b3e8 | bellard | void OPPROTO op_and_T0_rN(void) |
886 | fdf9b3e8 | bellard | { |
887 | fdf9b3e8 | bellard | env->gregs[PARAM1] &= T0; |
888 | fdf9b3e8 | bellard | RETURN(); |
889 | fdf9b3e8 | bellard | } |
890 | fdf9b3e8 | bellard | |
891 | fdf9b3e8 | bellard | void OPPROTO op_or_T0_rN(void) |
892 | fdf9b3e8 | bellard | { |
893 | fdf9b3e8 | bellard | env->gregs[PARAM1] |= T0; |
894 | fdf9b3e8 | bellard | RETURN(); |
895 | fdf9b3e8 | bellard | } |
896 | fdf9b3e8 | bellard | |
897 | fdf9b3e8 | bellard | void OPPROTO op_xor_T0_rN(void) |
898 | fdf9b3e8 | bellard | { |
899 | fdf9b3e8 | bellard | env->gregs[PARAM1] ^= T0; |
900 | fdf9b3e8 | bellard | RETURN(); |
901 | fdf9b3e8 | bellard | } |
902 | fdf9b3e8 | bellard | |
903 | fdf9b3e8 | bellard | void OPPROTO op_add_rN_T0(void) |
904 | fdf9b3e8 | bellard | { |
905 | fdf9b3e8 | bellard | T0 += env->gregs[PARAM1]; |
906 | fdf9b3e8 | bellard | RETURN(); |
907 | fdf9b3e8 | bellard | } |
908 | fdf9b3e8 | bellard | |
909 | fdf9b3e8 | bellard | void OPPROTO op_add_rN_T1(void) |
910 | fdf9b3e8 | bellard | { |
911 | fdf9b3e8 | bellard | T1 += env->gregs[PARAM1]; |
912 | fdf9b3e8 | bellard | RETURN(); |
913 | fdf9b3e8 | bellard | } |
914 | fdf9b3e8 | bellard | |
915 | fdf9b3e8 | bellard | void OPPROTO op_add_imm_rN(void) |
916 | fdf9b3e8 | bellard | { |
917 | fdf9b3e8 | bellard | env->gregs[PARAM2] += PARAM1; |
918 | fdf9b3e8 | bellard | RETURN(); |
919 | fdf9b3e8 | bellard | } |
920 | fdf9b3e8 | bellard | |
921 | fdf9b3e8 | bellard | void OPPROTO op_and_imm_rN(void) |
922 | fdf9b3e8 | bellard | { |
923 | fdf9b3e8 | bellard | env->gregs[PARAM2] &= PARAM1; |
924 | fdf9b3e8 | bellard | RETURN(); |
925 | fdf9b3e8 | bellard | } |
926 | fdf9b3e8 | bellard | |
927 | fdf9b3e8 | bellard | void OPPROTO op_or_imm_rN(void) |
928 | fdf9b3e8 | bellard | { |
929 | fdf9b3e8 | bellard | env->gregs[PARAM2] |= PARAM1; |
930 | fdf9b3e8 | bellard | RETURN(); |
931 | fdf9b3e8 | bellard | } |
932 | fdf9b3e8 | bellard | |
933 | fdf9b3e8 | bellard | void OPPROTO op_xor_imm_rN(void) |
934 | fdf9b3e8 | bellard | { |
935 | fdf9b3e8 | bellard | env->gregs[PARAM2] ^= PARAM1; |
936 | fdf9b3e8 | bellard | RETURN(); |
937 | fdf9b3e8 | bellard | } |
938 | fdf9b3e8 | bellard | |
939 | fdf9b3e8 | bellard | void OPPROTO op_dt_rN(void) |
940 | fdf9b3e8 | bellard | { |
941 | fdf9b3e8 | bellard | cond_t((--env->gregs[PARAM1]) == 0);
|
942 | fdf9b3e8 | bellard | RETURN(); |
943 | fdf9b3e8 | bellard | } |
944 | fdf9b3e8 | bellard | |
945 | fdf9b3e8 | bellard | void OPPROTO op_tst_imm_rN(void) |
946 | fdf9b3e8 | bellard | { |
947 | fdf9b3e8 | bellard | cond_t((env->gregs[PARAM2] & PARAM1) == 0);
|
948 | fdf9b3e8 | bellard | RETURN(); |
949 | fdf9b3e8 | bellard | } |
950 | fdf9b3e8 | bellard | |
951 | fdf9b3e8 | bellard | void OPPROTO op_movl_T0_T1(void) |
952 | fdf9b3e8 | bellard | { |
953 | fdf9b3e8 | bellard | T1 = T0; |
954 | fdf9b3e8 | bellard | RETURN(); |
955 | fdf9b3e8 | bellard | } |
956 | fdf9b3e8 | bellard | |
957 | eda9b09b | bellard | void OPPROTO op_movl_fpul_FT0(void) |
958 | eda9b09b | bellard | { |
959 | eda9b09b | bellard | FT0 = *(float32 *)&env->fpul; |
960 | eda9b09b | bellard | RETURN(); |
961 | eda9b09b | bellard | } |
962 | eda9b09b | bellard | |
963 | eda9b09b | bellard | void OPPROTO op_movl_FT0_fpul(void) |
964 | eda9b09b | bellard | { |
965 | eda9b09b | bellard | *(float32 *)&env->fpul = FT0; |
966 | eda9b09b | bellard | RETURN(); |
967 | eda9b09b | bellard | } |
968 | eda9b09b | bellard | |
969 | fdf9b3e8 | bellard | void OPPROTO op_goto_tb0(void) |
970 | fdf9b3e8 | bellard | { |
971 | fdf9b3e8 | bellard | GOTO_TB(op_goto_tb0, PARAM1, 0);
|
972 | fdf9b3e8 | bellard | RETURN(); |
973 | fdf9b3e8 | bellard | } |
974 | fdf9b3e8 | bellard | |
975 | fdf9b3e8 | bellard | void OPPROTO op_goto_tb1(void) |
976 | fdf9b3e8 | bellard | { |
977 | fdf9b3e8 | bellard | GOTO_TB(op_goto_tb1, PARAM1, 1);
|
978 | fdf9b3e8 | bellard | RETURN(); |
979 | fdf9b3e8 | bellard | } |
980 | fdf9b3e8 | bellard | |
981 | fdf9b3e8 | bellard | void OPPROTO op_movl_imm_PC(void) |
982 | fdf9b3e8 | bellard | { |
983 | fdf9b3e8 | bellard | env->pc = PARAM1; |
984 | fdf9b3e8 | bellard | RETURN(); |
985 | fdf9b3e8 | bellard | } |
986 | fdf9b3e8 | bellard | |
987 | fdf9b3e8 | bellard | void OPPROTO op_jT(void) |
988 | fdf9b3e8 | bellard | { |
989 | fdf9b3e8 | bellard | if (env->sr & SR_T)
|
990 | fdf9b3e8 | bellard | GOTO_LABEL_PARAM(1);
|
991 | fdf9b3e8 | bellard | RETURN(); |
992 | fdf9b3e8 | bellard | } |
993 | fdf9b3e8 | bellard | |
994 | 9c2a9ea1 | pbrook | void OPPROTO op_jdelayed(void) |
995 | fdf9b3e8 | bellard | { |
996 | 9c2a9ea1 | pbrook | uint32_t flags; |
997 | 9c2a9ea1 | pbrook | flags = env->flags; |
998 | 9c2a9ea1 | pbrook | env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
999 | 9c2a9ea1 | pbrook | if (flags & DELAY_SLOT)
|
1000 | fdf9b3e8 | bellard | GOTO_LABEL_PARAM(1);
|
1001 | fdf9b3e8 | bellard | RETURN(); |
1002 | fdf9b3e8 | bellard | } |
1003 | fdf9b3e8 | bellard | |
1004 | fdf9b3e8 | bellard | void OPPROTO op_movl_delayed_pc_PC(void) |
1005 | fdf9b3e8 | bellard | { |
1006 | fdf9b3e8 | bellard | env->pc = env->delayed_pc; |
1007 | fdf9b3e8 | bellard | RETURN(); |
1008 | fdf9b3e8 | bellard | } |
1009 | fdf9b3e8 | bellard | |
1010 | fdf9b3e8 | bellard | void OPPROTO op_addl_GBR_T0(void) |
1011 | fdf9b3e8 | bellard | { |
1012 | fdf9b3e8 | bellard | T0 += env->gbr; |
1013 | fdf9b3e8 | bellard | RETURN(); |
1014 | fdf9b3e8 | bellard | } |
1015 | fdf9b3e8 | bellard | |
1016 | fdf9b3e8 | bellard | void OPPROTO op_and_imm_T0(void) |
1017 | fdf9b3e8 | bellard | { |
1018 | fdf9b3e8 | bellard | T0 &= PARAM1; |
1019 | fdf9b3e8 | bellard | RETURN(); |
1020 | fdf9b3e8 | bellard | } |
1021 | fdf9b3e8 | bellard | |
1022 | fdf9b3e8 | bellard | void OPPROTO op_or_imm_T0(void) |
1023 | fdf9b3e8 | bellard | { |
1024 | fdf9b3e8 | bellard | T0 |= PARAM1; |
1025 | fdf9b3e8 | bellard | RETURN(); |
1026 | fdf9b3e8 | bellard | } |
1027 | fdf9b3e8 | bellard | |
1028 | fdf9b3e8 | bellard | void OPPROTO op_xor_imm_T0(void) |
1029 | fdf9b3e8 | bellard | { |
1030 | fdf9b3e8 | bellard | T0 ^= PARAM1; |
1031 | fdf9b3e8 | bellard | RETURN(); |
1032 | fdf9b3e8 | bellard | } |
1033 | fdf9b3e8 | bellard | |
1034 | fdf9b3e8 | bellard | void OPPROTO op_tst_imm_T0(void) |
1035 | fdf9b3e8 | bellard | { |
1036 | fdf9b3e8 | bellard | cond_t((T0 & PARAM1) == 0);
|
1037 | fdf9b3e8 | bellard | RETURN(); |
1038 | fdf9b3e8 | bellard | } |
1039 | fdf9b3e8 | bellard | |
1040 | fdf9b3e8 | bellard | void OPPROTO op_raise_illegal_instruction(void) |
1041 | fdf9b3e8 | bellard | { |
1042 | fdf9b3e8 | bellard | env->exception_index = 0x180;
|
1043 | fdf9b3e8 | bellard | do_raise_exception(); |
1044 | fdf9b3e8 | bellard | RETURN(); |
1045 | fdf9b3e8 | bellard | } |
1046 | fdf9b3e8 | bellard | |
1047 | fdf9b3e8 | bellard | void OPPROTO op_raise_slot_illegal_instruction(void) |
1048 | fdf9b3e8 | bellard | { |
1049 | fdf9b3e8 | bellard | env->exception_index = 0x1a0;
|
1050 | fdf9b3e8 | bellard | do_raise_exception(); |
1051 | fdf9b3e8 | bellard | RETURN(); |
1052 | fdf9b3e8 | bellard | } |
1053 | fdf9b3e8 | bellard | |
1054 | fdf9b3e8 | bellard | void OPPROTO op_debug(void) |
1055 | fdf9b3e8 | bellard | { |
1056 | fdf9b3e8 | bellard | env->exception_index = EXCP_DEBUG; |
1057 | fdf9b3e8 | bellard | cpu_loop_exit(); |
1058 | fdf9b3e8 | bellard | } |
1059 | fdf9b3e8 | bellard | |
1060 | fdf9b3e8 | bellard | /* Load and store */
|
1061 | fdf9b3e8 | bellard | #define MEMSUFFIX _raw
|
1062 | fdf9b3e8 | bellard | #include "op_mem.c" |
1063 | fdf9b3e8 | bellard | #undef MEMSUFFIX
|
1064 | fdf9b3e8 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1065 | fdf9b3e8 | bellard | #define MEMSUFFIX _user
|
1066 | fdf9b3e8 | bellard | #include "op_mem.c" |
1067 | fdf9b3e8 | bellard | #undef MEMSUFFIX
|
1068 | fdf9b3e8 | bellard | |
1069 | fdf9b3e8 | bellard | #define MEMSUFFIX _kernel
|
1070 | fdf9b3e8 | bellard | #include "op_mem.c" |
1071 | fdf9b3e8 | bellard | #undef MEMSUFFIX
|
1072 | fdf9b3e8 | bellard | #endif |