root / vl.h @ 89fc88da
History | View | Annotate | Download (54.9 kB)
1 | fc01f7e7 | bellard | /*
|
---|---|---|---|
2 | fc01f7e7 | bellard | * QEMU System Emulator header
|
3 | 5fafdf24 | ths | *
|
4 | fc01f7e7 | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | 5fafdf24 | ths | *
|
6 | fc01f7e7 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | fc01f7e7 | bellard | * of this software and associated documentation files (the "Software"), to deal
|
8 | fc01f7e7 | bellard | * in the Software without restriction, including without limitation the rights
|
9 | fc01f7e7 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | fc01f7e7 | bellard | * copies of the Software, and to permit persons to whom the Software is
|
11 | fc01f7e7 | bellard | * furnished to do so, subject to the following conditions:
|
12 | fc01f7e7 | bellard | *
|
13 | fc01f7e7 | bellard | * The above copyright notice and this permission notice shall be included in
|
14 | fc01f7e7 | bellard | * all copies or substantial portions of the Software.
|
15 | fc01f7e7 | bellard | *
|
16 | fc01f7e7 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | fc01f7e7 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | fc01f7e7 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | fc01f7e7 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | fc01f7e7 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | fc01f7e7 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | fc01f7e7 | bellard | * THE SOFTWARE.
|
23 | fc01f7e7 | bellard | */
|
24 | fc01f7e7 | bellard | #ifndef VL_H
|
25 | fc01f7e7 | bellard | #define VL_H
|
26 | fc01f7e7 | bellard | |
27 | 67b915a5 | bellard | /* we put basic includes here to avoid repeating them in device drivers */
|
28 | 67b915a5 | bellard | #include <stdlib.h> |
29 | 67b915a5 | bellard | #include <stdio.h> |
30 | 67b915a5 | bellard | #include <stdarg.h> |
31 | 67b915a5 | bellard | #include <string.h> |
32 | 67b915a5 | bellard | #include <inttypes.h> |
33 | 85571bc7 | bellard | #include <limits.h> |
34 | 8a7ddc38 | bellard | #include <time.h> |
35 | 67b915a5 | bellard | #include <ctype.h> |
36 | 67b915a5 | bellard | #include <errno.h> |
37 | 67b915a5 | bellard | #include <unistd.h> |
38 | 67b915a5 | bellard | #include <fcntl.h> |
39 | 7d3505c5 | bellard | #include <sys/stat.h> |
40 | 67b915a5 | bellard | |
41 | 67b915a5 | bellard | #ifndef O_LARGEFILE
|
42 | 67b915a5 | bellard | #define O_LARGEFILE 0 |
43 | 67b915a5 | bellard | #endif
|
44 | 40c3bac3 | bellard | #ifndef O_BINARY
|
45 | 40c3bac3 | bellard | #define O_BINARY 0 |
46 | 40c3bac3 | bellard | #endif
|
47 | 67b915a5 | bellard | |
48 | 71c2fd5c | ths | #ifndef ENOMEDIUM
|
49 | 71c2fd5c | ths | #define ENOMEDIUM ENODEV
|
50 | 71c2fd5c | ths | #endif
|
51 | 2e9671da | ths | |
52 | 67b915a5 | bellard | #ifdef _WIN32
|
53 | a18e524a | bellard | #include <windows.h> |
54 | ac62f715 | pbrook | #define fsync _commit
|
55 | 57d1a2b6 | bellard | #define lseek _lseeki64
|
56 | 57d1a2b6 | bellard | #define ENOTSUP 4096 |
57 | beac80cd | bellard | extern int qemu_ftruncate64(int, int64_t); |
58 | beac80cd | bellard | #define ftruncate qemu_ftruncate64
|
59 | beac80cd | bellard | |
60 | 57d1a2b6 | bellard | |
61 | 57d1a2b6 | bellard | static inline char *realpath(const char *path, char *resolved_path) |
62 | 57d1a2b6 | bellard | { |
63 | 57d1a2b6 | bellard | _fullpath(resolved_path, path, _MAX_PATH); |
64 | 57d1a2b6 | bellard | return resolved_path;
|
65 | 57d1a2b6 | bellard | } |
66 | ec3757de | bellard | |
67 | ec3757de | bellard | #define PRId64 "I64d" |
68 | 26a76461 | bellard | #define PRIx64 "I64x" |
69 | 26a76461 | bellard | #define PRIu64 "I64u" |
70 | 26a76461 | bellard | #define PRIo64 "I64o" |
71 | 67b915a5 | bellard | #endif
|
72 | 8a7ddc38 | bellard | |
73 | ea2384d3 | bellard | #ifdef QEMU_TOOL
|
74 | ea2384d3 | bellard | |
75 | ea2384d3 | bellard | /* we use QEMU_TOOL in the command line tools which do not depend on
|
76 | ea2384d3 | bellard | the target CPU type */
|
77 | ea2384d3 | bellard | #include "config-host.h" |
78 | ea2384d3 | bellard | #include <setjmp.h> |
79 | ea2384d3 | bellard | #include "osdep.h" |
80 | ea2384d3 | bellard | #include "bswap.h" |
81 | ea2384d3 | bellard | |
82 | ea2384d3 | bellard | #else
|
83 | ea2384d3 | bellard | |
84 | 4f209290 | pbrook | #include "audio/audio.h" |
85 | 16f62432 | bellard | #include "cpu.h" |
86 | 16f62432 | bellard | |
87 | ea2384d3 | bellard | #endif /* !defined(QEMU_TOOL) */ |
88 | ea2384d3 | bellard | |
89 | 67b915a5 | bellard | #ifndef glue
|
90 | 67b915a5 | bellard | #define xglue(x, y) x ## y |
91 | 67b915a5 | bellard | #define glue(x, y) xglue(x, y)
|
92 | 67b915a5 | bellard | #define stringify(s) tostring(s)
|
93 | 67b915a5 | bellard | #define tostring(s) #s |
94 | 67b915a5 | bellard | #endif
|
95 | 67b915a5 | bellard | |
96 | 2e03286b | balrog | #ifndef likely
|
97 | 2e03286b | balrog | #if __GNUC__ < 3 |
98 | 2e03286b | balrog | #define __builtin_expect(x, n) (x)
|
99 | 2e03286b | balrog | #endif
|
100 | 2e03286b | balrog | |
101 | 2e03286b | balrog | #define likely(x) __builtin_expect(!!(x), 1) |
102 | 2e03286b | balrog | #define unlikely(x) __builtin_expect(!!(x), 0) |
103 | 2e03286b | balrog | #endif
|
104 | 2e03286b | balrog | |
105 | 24236869 | bellard | #ifndef MIN
|
106 | 24236869 | bellard | #define MIN(a, b) (((a) < (b)) ? (a) : (b))
|
107 | 24236869 | bellard | #endif
|
108 | 24236869 | bellard | #ifndef MAX
|
109 | 24236869 | bellard | #define MAX(a, b) (((a) > (b)) ? (a) : (b))
|
110 | 24236869 | bellard | #endif
|
111 | 24236869 | bellard | |
112 | 29f640e2 | j_mayer | #ifndef always_inline
|
113 | 8a84de23 | j_mayer | #if (__GNUC__ < 3) || defined(__APPLE__) |
114 | 29f640e2 | j_mayer | #define always_inline inline |
115 | 29f640e2 | j_mayer | #else
|
116 | 29f640e2 | j_mayer | #define always_inline __attribute__ (( always_inline )) inline |
117 | 29f640e2 | j_mayer | #endif
|
118 | 29f640e2 | j_mayer | #endif
|
119 | 29f640e2 | j_mayer | |
120 | 18607dcb | bellard | /* cutils.c */
|
121 | 18607dcb | bellard | void pstrcpy(char *buf, int buf_size, const char *str); |
122 | 18607dcb | bellard | char *pstrcat(char *buf, int buf_size, const char *s); |
123 | 18607dcb | bellard | int strstart(const char *str, const char *val, const char **ptr); |
124 | 18607dcb | bellard | int stristart(const char *str, const char *val, const char **ptr); |
125 | 18607dcb | bellard | |
126 | 33e3963e | bellard | /* vl.c */
|
127 | 80cabfad | bellard | uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c); |
128 | 313aa567 | bellard | |
129 | 80cabfad | bellard | void hw_error(const char *fmt, ...); |
130 | 80cabfad | bellard | |
131 | 80cabfad | bellard | extern const char *bios_dir; |
132 | 1192dad8 | j_mayer | extern const char *bios_name; |
133 | 80cabfad | bellard | |
134 | 8a7ddc38 | bellard | extern int vm_running; |
135 | c35734b2 | ths | extern const char *qemu_name; |
136 | 8a7ddc38 | bellard | |
137 | 0bd48850 | bellard | typedef struct vm_change_state_entry VMChangeStateEntry; |
138 | 0bd48850 | bellard | typedef void VMChangeStateHandler(void *opaque, int running); |
139 | 8a7ddc38 | bellard | typedef void VMStopHandler(void *opaque, int reason); |
140 | 8a7ddc38 | bellard | |
141 | 0bd48850 | bellard | VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb, |
142 | 0bd48850 | bellard | void *opaque);
|
143 | 0bd48850 | bellard | void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
|
144 | 0bd48850 | bellard | |
145 | 8a7ddc38 | bellard | int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque); |
146 | 8a7ddc38 | bellard | void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque); |
147 | 8a7ddc38 | bellard | |
148 | 8a7ddc38 | bellard | void vm_start(void); |
149 | 8a7ddc38 | bellard | void vm_stop(int reason); |
150 | 8a7ddc38 | bellard | |
151 | bb0c6722 | bellard | typedef void QEMUResetHandler(void *opaque); |
152 | bb0c6722 | bellard | |
153 | bb0c6722 | bellard | void qemu_register_reset(QEMUResetHandler *func, void *opaque); |
154 | bb0c6722 | bellard | void qemu_system_reset_request(void); |
155 | bb0c6722 | bellard | void qemu_system_shutdown_request(void); |
156 | 3475187d | bellard | void qemu_system_powerdown_request(void); |
157 | 3475187d | bellard | #if !defined(TARGET_SPARC)
|
158 | 3475187d | bellard | // Please implement a power failure function to signal the OS
|
159 | 3475187d | bellard | #define qemu_system_powerdown() do{}while(0) |
160 | 3475187d | bellard | #else
|
161 | 3475187d | bellard | void qemu_system_powerdown(void); |
162 | 3475187d | bellard | #endif
|
163 | bb0c6722 | bellard | |
164 | ea2384d3 | bellard | void main_loop_wait(int timeout); |
165 | ea2384d3 | bellard | |
166 | 0ced6589 | bellard | extern int ram_size; |
167 | 0ced6589 | bellard | extern int bios_size; |
168 | ee22c2f7 | bellard | extern int rtc_utc; |
169 | 1f04275e | bellard | extern int cirrus_vga_enabled; |
170 | d34cab9f | ths | extern int vmsvga_enabled; |
171 | 28b9b5af | bellard | extern int graphic_width; |
172 | 28b9b5af | bellard | extern int graphic_height; |
173 | 28b9b5af | bellard | extern int graphic_depth; |
174 | 3d11d0eb | bellard | extern const char *keyboard_layout; |
175 | d993e026 | bellard | extern int kqemu_allowed; |
176 | a09db21f | bellard | extern int win2k_install_hack; |
177 | 3780e197 | ths | extern int alt_grab; |
178 | bb36d470 | bellard | extern int usb_enabled; |
179 | 6a00d601 | bellard | extern int smp_cpus; |
180 | 9467cd46 | balrog | extern int cursor_hide; |
181 | a171fe39 | balrog | extern int graphic_rotate; |
182 | 667accab | ths | extern int no_quit; |
183 | 8e71621f | pbrook | extern int semihosting_enabled; |
184 | 3c07f8e8 | pbrook | extern int autostart; |
185 | 2b8f2d41 | balrog | extern int old_param; |
186 | 47d5d01a | ths | extern const char *bootp_filename; |
187 | 0ced6589 | bellard | |
188 | 9ae02555 | ths | #define MAX_OPTION_ROMS 16 |
189 | 9ae02555 | ths | extern const char *option_rom[MAX_OPTION_ROMS]; |
190 | 9ae02555 | ths | extern int nb_option_roms; |
191 | 9ae02555 | ths | |
192 | 66508601 | blueswir1 | #ifdef TARGET_SPARC
|
193 | 66508601 | blueswir1 | #define MAX_PROM_ENVS 128 |
194 | 66508601 | blueswir1 | extern const char *prom_envs[MAX_PROM_ENVS]; |
195 | 66508601 | blueswir1 | extern unsigned int nb_prom_envs; |
196 | 66508601 | blueswir1 | #endif
|
197 | 66508601 | blueswir1 | |
198 | 0ced6589 | bellard | /* XXX: make it dynamic */
|
199 | 970ac5a3 | bellard | #define MAX_BIOS_SIZE (4 * 1024 * 1024) |
200 | 75956cf0 | pbrook | #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
|
201 | d5295253 | bellard | #define BIOS_SIZE ((512 + 32) * 1024) |
202 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
|
203 | 567daa49 | ths | #define BIOS_SIZE (4 * 1024 * 1024) |
204 | 0ced6589 | bellard | #endif
|
205 | aaaa7df6 | bellard | |
206 | 63066f4f | bellard | /* keyboard/mouse support */
|
207 | 63066f4f | bellard | |
208 | 63066f4f | bellard | #define MOUSE_EVENT_LBUTTON 0x01 |
209 | 63066f4f | bellard | #define MOUSE_EVENT_RBUTTON 0x02 |
210 | 63066f4f | bellard | #define MOUSE_EVENT_MBUTTON 0x04 |
211 | 63066f4f | bellard | |
212 | 63066f4f | bellard | typedef void QEMUPutKBDEvent(void *opaque, int keycode); |
213 | 63066f4f | bellard | typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state); |
214 | 63066f4f | bellard | |
215 | 455204eb | ths | typedef struct QEMUPutMouseEntry { |
216 | 455204eb | ths | QEMUPutMouseEvent *qemu_put_mouse_event; |
217 | 455204eb | ths | void *qemu_put_mouse_event_opaque;
|
218 | 455204eb | ths | int qemu_put_mouse_event_absolute;
|
219 | 455204eb | ths | char *qemu_put_mouse_event_name;
|
220 | 455204eb | ths | |
221 | 455204eb | ths | /* used internally by qemu for handling mice */
|
222 | 455204eb | ths | struct QEMUPutMouseEntry *next;
|
223 | 455204eb | ths | } QEMUPutMouseEntry; |
224 | 455204eb | ths | |
225 | 63066f4f | bellard | void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque); |
226 | 455204eb | ths | QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func, |
227 | 455204eb | ths | void *opaque, int absolute, |
228 | 455204eb | ths | const char *name); |
229 | 455204eb | ths | void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
|
230 | 63066f4f | bellard | |
231 | 63066f4f | bellard | void kbd_put_keycode(int keycode); |
232 | 63066f4f | bellard | void kbd_mouse_event(int dx, int dy, int dz, int buttons_state); |
233 | 09b26c5e | bellard | int kbd_mouse_is_absolute(void); |
234 | 63066f4f | bellard | |
235 | 455204eb | ths | void do_info_mice(void); |
236 | 455204eb | ths | void do_mouse_set(int index); |
237 | 455204eb | ths | |
238 | 82c643ff | bellard | /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
|
239 | 82c643ff | bellard | constants) */
|
240 | 82c643ff | bellard | #define QEMU_KEY_ESC1(c) ((c) | 0xe100) |
241 | 82c643ff | bellard | #define QEMU_KEY_BACKSPACE 0x007f |
242 | 82c643ff | bellard | #define QEMU_KEY_UP QEMU_KEY_ESC1('A') |
243 | 82c643ff | bellard | #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B') |
244 | 82c643ff | bellard | #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C') |
245 | 82c643ff | bellard | #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D') |
246 | 82c643ff | bellard | #define QEMU_KEY_HOME QEMU_KEY_ESC1(1) |
247 | 82c643ff | bellard | #define QEMU_KEY_END QEMU_KEY_ESC1(4) |
248 | 82c643ff | bellard | #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5) |
249 | 82c643ff | bellard | #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6) |
250 | 82c643ff | bellard | #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3) |
251 | 82c643ff | bellard | |
252 | 82c643ff | bellard | #define QEMU_KEY_CTRL_UP 0xe400 |
253 | 82c643ff | bellard | #define QEMU_KEY_CTRL_DOWN 0xe401 |
254 | 82c643ff | bellard | #define QEMU_KEY_CTRL_LEFT 0xe402 |
255 | 82c643ff | bellard | #define QEMU_KEY_CTRL_RIGHT 0xe403 |
256 | 82c643ff | bellard | #define QEMU_KEY_CTRL_HOME 0xe404 |
257 | 82c643ff | bellard | #define QEMU_KEY_CTRL_END 0xe405 |
258 | 82c643ff | bellard | #define QEMU_KEY_CTRL_PAGEUP 0xe406 |
259 | 82c643ff | bellard | #define QEMU_KEY_CTRL_PAGEDOWN 0xe407 |
260 | 82c643ff | bellard | |
261 | 82c643ff | bellard | void kbd_put_keysym(int keysym); |
262 | 82c643ff | bellard | |
263 | c20709aa | bellard | /* async I/O support */
|
264 | c20709aa | bellard | |
265 | c20709aa | bellard | typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size); |
266 | c20709aa | bellard | typedef int IOCanRWHandler(void *opaque); |
267 | 7c9d8e07 | bellard | typedef void IOHandler(void *opaque); |
268 | c20709aa | bellard | |
269 | 5fafdf24 | ths | int qemu_set_fd_handler2(int fd, |
270 | 5fafdf24 | ths | IOCanRWHandler *fd_read_poll, |
271 | 5fafdf24 | ths | IOHandler *fd_read, |
272 | 5fafdf24 | ths | IOHandler *fd_write, |
273 | 7c9d8e07 | bellard | void *opaque);
|
274 | 7c9d8e07 | bellard | int qemu_set_fd_handler(int fd, |
275 | 5fafdf24 | ths | IOHandler *fd_read, |
276 | 7c9d8e07 | bellard | IOHandler *fd_write, |
277 | 7c9d8e07 | bellard | void *opaque);
|
278 | c20709aa | bellard | |
279 | f331110f | bellard | /* Polling handling */
|
280 | f331110f | bellard | |
281 | f331110f | bellard | /* return TRUE if no sleep should be done afterwards */
|
282 | f331110f | bellard | typedef int PollingFunc(void *opaque); |
283 | f331110f | bellard | |
284 | f331110f | bellard | int qemu_add_polling_cb(PollingFunc *func, void *opaque); |
285 | f331110f | bellard | void qemu_del_polling_cb(PollingFunc *func, void *opaque); |
286 | f331110f | bellard | |
287 | a18e524a | bellard | #ifdef _WIN32
|
288 | a18e524a | bellard | /* Wait objects handling */
|
289 | a18e524a | bellard | typedef void WaitObjectFunc(void *opaque); |
290 | a18e524a | bellard | |
291 | a18e524a | bellard | int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); |
292 | a18e524a | bellard | void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); |
293 | a18e524a | bellard | #endif
|
294 | a18e524a | bellard | |
295 | 86e94dea | ths | typedef struct QEMUBH QEMUBH; |
296 | 86e94dea | ths | |
297 | 82c643ff | bellard | /* character device */
|
298 | 82c643ff | bellard | |
299 | 82c643ff | bellard | #define CHR_EVENT_BREAK 0 /* serial break char */ |
300 | ea2384d3 | bellard | #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */ |
301 | 86e94dea | ths | #define CHR_EVENT_RESET 2 /* new connection established */ |
302 | 2122c51a | bellard | |
303 | 2122c51a | bellard | |
304 | 2122c51a | bellard | #define CHR_IOCTL_SERIAL_SET_PARAMS 1 |
305 | 2122c51a | bellard | typedef struct { |
306 | 2122c51a | bellard | int speed;
|
307 | 2122c51a | bellard | int parity;
|
308 | 2122c51a | bellard | int data_bits;
|
309 | 2122c51a | bellard | int stop_bits;
|
310 | 2122c51a | bellard | } QEMUSerialSetParams; |
311 | 2122c51a | bellard | |
312 | 2122c51a | bellard | #define CHR_IOCTL_SERIAL_SET_BREAK 2 |
313 | 2122c51a | bellard | |
314 | 2122c51a | bellard | #define CHR_IOCTL_PP_READ_DATA 3 |
315 | 2122c51a | bellard | #define CHR_IOCTL_PP_WRITE_DATA 4 |
316 | 2122c51a | bellard | #define CHR_IOCTL_PP_READ_CONTROL 5 |
317 | 2122c51a | bellard | #define CHR_IOCTL_PP_WRITE_CONTROL 6 |
318 | 2122c51a | bellard | #define CHR_IOCTL_PP_READ_STATUS 7 |
319 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_READ_ADDR 8 |
320 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_READ 9 |
321 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10 |
322 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_WRITE 11 |
323 | 2122c51a | bellard | |
324 | 82c643ff | bellard | typedef void IOEventHandler(void *opaque, int event); |
325 | 82c643ff | bellard | |
326 | 82c643ff | bellard | typedef struct CharDriverState { |
327 | 82c643ff | bellard | int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len); |
328 | e5b0bc44 | pbrook | void (*chr_update_read_handler)(struct CharDriverState *s); |
329 | 2122c51a | bellard | int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg); |
330 | 82c643ff | bellard | IOEventHandler *chr_event; |
331 | e5b0bc44 | pbrook | IOCanRWHandler *chr_can_read; |
332 | e5b0bc44 | pbrook | IOReadHandler *chr_read; |
333 | e5b0bc44 | pbrook | void *handler_opaque;
|
334 | eb45f5fe | bellard | void (*chr_send_event)(struct CharDriverState *chr, int event); |
335 | f331110f | bellard | void (*chr_close)(struct CharDriverState *chr); |
336 | 82c643ff | bellard | void *opaque;
|
337 | 20d8a3ed | ths | int focus;
|
338 | 86e94dea | ths | QEMUBH *bh; |
339 | 82c643ff | bellard | } CharDriverState; |
340 | 82c643ff | bellard | |
341 | 5856de80 | ths | CharDriverState *qemu_chr_open(const char *filename); |
342 | 82c643ff | bellard | void qemu_chr_printf(CharDriverState *s, const char *fmt, ...); |
343 | 82c643ff | bellard | int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len); |
344 | ea2384d3 | bellard | void qemu_chr_send_event(CharDriverState *s, int event); |
345 | 5fafdf24 | ths | void qemu_chr_add_handlers(CharDriverState *s,
|
346 | 5fafdf24 | ths | IOCanRWHandler *fd_can_read, |
347 | e5b0bc44 | pbrook | IOReadHandler *fd_read, |
348 | e5b0bc44 | pbrook | IOEventHandler *fd_event, |
349 | e5b0bc44 | pbrook | void *opaque);
|
350 | 2122c51a | bellard | int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg); |
351 | 86e94dea | ths | void qemu_chr_reset(CharDriverState *s);
|
352 | e5b0bc44 | pbrook | int qemu_chr_can_read(CharDriverState *s);
|
353 | e5b0bc44 | pbrook | void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len); |
354 | f8d179e3 | bellard | |
355 | 82c643ff | bellard | /* consoles */
|
356 | 82c643ff | bellard | |
357 | 82c643ff | bellard | typedef struct DisplayState DisplayState; |
358 | 82c643ff | bellard | typedef struct TextConsole TextConsole; |
359 | 82c643ff | bellard | |
360 | 95219897 | pbrook | typedef void (*vga_hw_update_ptr)(void *); |
361 | 95219897 | pbrook | typedef void (*vga_hw_invalidate_ptr)(void *); |
362 | 95219897 | pbrook | typedef void (*vga_hw_screen_dump_ptr)(void *, const char *); |
363 | 95219897 | pbrook | |
364 | 95219897 | pbrook | TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update, |
365 | 95219897 | pbrook | vga_hw_invalidate_ptr invalidate, |
366 | 95219897 | pbrook | vga_hw_screen_dump_ptr screen_dump, |
367 | 95219897 | pbrook | void *opaque);
|
368 | 95219897 | pbrook | void vga_hw_update(void); |
369 | 95219897 | pbrook | void vga_hw_invalidate(void); |
370 | 95219897 | pbrook | void vga_hw_screen_dump(const char *filename); |
371 | 95219897 | pbrook | |
372 | 95219897 | pbrook | int is_graphic_console(void); |
373 | af3a9031 | ths | CharDriverState *text_console_init(DisplayState *ds, const char *p); |
374 | 82c643ff | bellard | void console_select(unsigned int index); |
375 | 82c643ff | bellard | |
376 | 8d11df9e | bellard | /* serial ports */
|
377 | 8d11df9e | bellard | |
378 | 8d11df9e | bellard | #define MAX_SERIAL_PORTS 4 |
379 | 8d11df9e | bellard | |
380 | 8d11df9e | bellard | extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
|
381 | 8d11df9e | bellard | |
382 | 6508fe59 | bellard | /* parallel ports */
|
383 | 6508fe59 | bellard | |
384 | 6508fe59 | bellard | #define MAX_PARALLEL_PORTS 3 |
385 | 6508fe59 | bellard | |
386 | 6508fe59 | bellard | extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
|
387 | 6508fe59 | bellard | |
388 | 5867c88a | ths | struct ParallelIOArg {
|
389 | 5867c88a | ths | void *buffer;
|
390 | 5867c88a | ths | int count;
|
391 | 5867c88a | ths | }; |
392 | 5867c88a | ths | |
393 | 7c9d8e07 | bellard | /* VLANs support */
|
394 | 7c9d8e07 | bellard | |
395 | 7c9d8e07 | bellard | typedef struct VLANClientState VLANClientState; |
396 | 7c9d8e07 | bellard | |
397 | 7c9d8e07 | bellard | struct VLANClientState {
|
398 | 7c9d8e07 | bellard | IOReadHandler *fd_read; |
399 | d861b05e | pbrook | /* Packets may still be sent if this returns zero. It's used to
|
400 | d861b05e | pbrook | rate-limit the slirp code. */
|
401 | d861b05e | pbrook | IOCanRWHandler *fd_can_read; |
402 | 7c9d8e07 | bellard | void *opaque;
|
403 | 7c9d8e07 | bellard | struct VLANClientState *next;
|
404 | 7c9d8e07 | bellard | struct VLANState *vlan;
|
405 | 7c9d8e07 | bellard | char info_str[256]; |
406 | 7c9d8e07 | bellard | }; |
407 | 7c9d8e07 | bellard | |
408 | 7c9d8e07 | bellard | typedef struct VLANState { |
409 | 7c9d8e07 | bellard | int id;
|
410 | 7c9d8e07 | bellard | VLANClientState *first_client; |
411 | 7c9d8e07 | bellard | struct VLANState *next;
|
412 | 833c7174 | blueswir1 | unsigned int nb_guest_devs, nb_host_devs; |
413 | 7c9d8e07 | bellard | } VLANState; |
414 | 7c9d8e07 | bellard | |
415 | 7c9d8e07 | bellard | VLANState *qemu_find_vlan(int id);
|
416 | 7c9d8e07 | bellard | VLANClientState *qemu_new_vlan_client(VLANState *vlan, |
417 | d861b05e | pbrook | IOReadHandler *fd_read, |
418 | d861b05e | pbrook | IOCanRWHandler *fd_can_read, |
419 | d861b05e | pbrook | void *opaque);
|
420 | d861b05e | pbrook | int qemu_can_send_packet(VLANClientState *vc);
|
421 | 7c9d8e07 | bellard | void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size); |
422 | d861b05e | pbrook | void qemu_handler_true(void *opaque); |
423 | 7c9d8e07 | bellard | |
424 | 7c9d8e07 | bellard | void do_info_network(void); |
425 | 7c9d8e07 | bellard | |
426 | 7fb843f8 | bellard | /* TAP win32 */
|
427 | 7fb843f8 | bellard | int tap_win32_init(VLANState *vlan, const char *ifname); |
428 | 7fb843f8 | bellard | |
429 | 7c9d8e07 | bellard | /* NIC info */
|
430 | c4b1fcc0 | bellard | |
431 | c4b1fcc0 | bellard | #define MAX_NICS 8 |
432 | c4b1fcc0 | bellard | |
433 | 7c9d8e07 | bellard | typedef struct NICInfo { |
434 | c4b1fcc0 | bellard | uint8_t macaddr[6];
|
435 | a41b2ff2 | pbrook | const char *model; |
436 | 7c9d8e07 | bellard | VLANState *vlan; |
437 | 7c9d8e07 | bellard | } NICInfo; |
438 | c4b1fcc0 | bellard | |
439 | c4b1fcc0 | bellard | extern int nb_nics; |
440 | 7c9d8e07 | bellard | extern NICInfo nd_table[MAX_NICS];
|
441 | 8a7ddc38 | bellard | |
442 | 8a7ddc38 | bellard | /* timers */
|
443 | 8a7ddc38 | bellard | |
444 | 8a7ddc38 | bellard | typedef struct QEMUClock QEMUClock; |
445 | 8a7ddc38 | bellard | typedef struct QEMUTimer QEMUTimer; |
446 | 8a7ddc38 | bellard | typedef void QEMUTimerCB(void *opaque); |
447 | 8a7ddc38 | bellard | |
448 | 8a7ddc38 | bellard | /* The real time clock should be used only for stuff which does not
|
449 | 8a7ddc38 | bellard | change the virtual machine state, as it is run even if the virtual
|
450 | 69b91039 | bellard | machine is stopped. The real time clock has a frequency of 1000
|
451 | 8a7ddc38 | bellard | Hz. */
|
452 | 8a7ddc38 | bellard | extern QEMUClock *rt_clock;
|
453 | 8a7ddc38 | bellard | |
454 | e80cfcfc | bellard | /* The virtual clock is only run during the emulation. It is stopped
|
455 | 8a7ddc38 | bellard | when the virtual machine is stopped. Virtual timers use a high
|
456 | 8a7ddc38 | bellard | precision clock, usually cpu cycles (use ticks_per_sec). */
|
457 | 8a7ddc38 | bellard | extern QEMUClock *vm_clock;
|
458 | 8a7ddc38 | bellard | |
459 | 8a7ddc38 | bellard | int64_t qemu_get_clock(QEMUClock *clock); |
460 | 8a7ddc38 | bellard | |
461 | 8a7ddc38 | bellard | QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
|
462 | 8a7ddc38 | bellard | void qemu_free_timer(QEMUTimer *ts);
|
463 | 8a7ddc38 | bellard | void qemu_del_timer(QEMUTimer *ts);
|
464 | 8a7ddc38 | bellard | void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
|
465 | 8a7ddc38 | bellard | int qemu_timer_pending(QEMUTimer *ts);
|
466 | 8a7ddc38 | bellard | |
467 | 8a7ddc38 | bellard | extern int64_t ticks_per_sec;
|
468 | 8a7ddc38 | bellard | |
469 | 1dce7c3c | bellard | int64_t cpu_get_ticks(void);
|
470 | 8a7ddc38 | bellard | void cpu_enable_ticks(void); |
471 | 8a7ddc38 | bellard | void cpu_disable_ticks(void); |
472 | 8a7ddc38 | bellard | |
473 | 8a7ddc38 | bellard | /* VM Load/Save */
|
474 | 8a7ddc38 | bellard | |
475 | faea38e7 | bellard | typedef struct QEMUFile QEMUFile; |
476 | 8a7ddc38 | bellard | |
477 | faea38e7 | bellard | QEMUFile *qemu_fopen(const char *filename, const char *mode); |
478 | faea38e7 | bellard | void qemu_fflush(QEMUFile *f);
|
479 | faea38e7 | bellard | void qemu_fclose(QEMUFile *f);
|
480 | 8a7ddc38 | bellard | void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size); |
481 | 8a7ddc38 | bellard | void qemu_put_byte(QEMUFile *f, int v); |
482 | 8a7ddc38 | bellard | void qemu_put_be16(QEMUFile *f, unsigned int v); |
483 | 8a7ddc38 | bellard | void qemu_put_be32(QEMUFile *f, unsigned int v); |
484 | 8a7ddc38 | bellard | void qemu_put_be64(QEMUFile *f, uint64_t v);
|
485 | 8a7ddc38 | bellard | int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size); |
486 | 8a7ddc38 | bellard | int qemu_get_byte(QEMUFile *f);
|
487 | 8a7ddc38 | bellard | unsigned int qemu_get_be16(QEMUFile *f); |
488 | 8a7ddc38 | bellard | unsigned int qemu_get_be32(QEMUFile *f); |
489 | 8a7ddc38 | bellard | uint64_t qemu_get_be64(QEMUFile *f); |
490 | 8a7ddc38 | bellard | |
491 | 8a7ddc38 | bellard | static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv) |
492 | 8a7ddc38 | bellard | { |
493 | 8a7ddc38 | bellard | qemu_put_be64(f, *pv); |
494 | 8a7ddc38 | bellard | } |
495 | 8a7ddc38 | bellard | |
496 | 8a7ddc38 | bellard | static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv) |
497 | 8a7ddc38 | bellard | { |
498 | 8a7ddc38 | bellard | qemu_put_be32(f, *pv); |
499 | 8a7ddc38 | bellard | } |
500 | 8a7ddc38 | bellard | |
501 | 8a7ddc38 | bellard | static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv) |
502 | 8a7ddc38 | bellard | { |
503 | 8a7ddc38 | bellard | qemu_put_be16(f, *pv); |
504 | 8a7ddc38 | bellard | } |
505 | 8a7ddc38 | bellard | |
506 | 8a7ddc38 | bellard | static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv) |
507 | 8a7ddc38 | bellard | { |
508 | 8a7ddc38 | bellard | qemu_put_byte(f, *pv); |
509 | 8a7ddc38 | bellard | } |
510 | 8a7ddc38 | bellard | |
511 | 8a7ddc38 | bellard | static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv) |
512 | 8a7ddc38 | bellard | { |
513 | 8a7ddc38 | bellard | *pv = qemu_get_be64(f); |
514 | 8a7ddc38 | bellard | } |
515 | 8a7ddc38 | bellard | |
516 | 8a7ddc38 | bellard | static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv) |
517 | 8a7ddc38 | bellard | { |
518 | 8a7ddc38 | bellard | *pv = qemu_get_be32(f); |
519 | 8a7ddc38 | bellard | } |
520 | 8a7ddc38 | bellard | |
521 | 8a7ddc38 | bellard | static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv) |
522 | 8a7ddc38 | bellard | { |
523 | 8a7ddc38 | bellard | *pv = qemu_get_be16(f); |
524 | 8a7ddc38 | bellard | } |
525 | 8a7ddc38 | bellard | |
526 | 8a7ddc38 | bellard | static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv) |
527 | 8a7ddc38 | bellard | { |
528 | 8a7ddc38 | bellard | *pv = qemu_get_byte(f); |
529 | 8a7ddc38 | bellard | } |
530 | 8a7ddc38 | bellard | |
531 | c27004ec | bellard | #if TARGET_LONG_BITS == 64 |
532 | c27004ec | bellard | #define qemu_put_betl qemu_put_be64
|
533 | c27004ec | bellard | #define qemu_get_betl qemu_get_be64
|
534 | c27004ec | bellard | #define qemu_put_betls qemu_put_be64s
|
535 | c27004ec | bellard | #define qemu_get_betls qemu_get_be64s
|
536 | c27004ec | bellard | #else
|
537 | c27004ec | bellard | #define qemu_put_betl qemu_put_be32
|
538 | c27004ec | bellard | #define qemu_get_betl qemu_get_be32
|
539 | c27004ec | bellard | #define qemu_put_betls qemu_put_be32s
|
540 | c27004ec | bellard | #define qemu_get_betls qemu_get_be32s
|
541 | c27004ec | bellard | #endif
|
542 | c27004ec | bellard | |
543 | 8a7ddc38 | bellard | int64_t qemu_ftell(QEMUFile *f); |
544 | 8a7ddc38 | bellard | int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
|
545 | 8a7ddc38 | bellard | |
546 | 8a7ddc38 | bellard | typedef void SaveStateHandler(QEMUFile *f, void *opaque); |
547 | 8a7ddc38 | bellard | typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id); |
548 | 8a7ddc38 | bellard | |
549 | 5fafdf24 | ths | int register_savevm(const char *idstr, |
550 | 5fafdf24 | ths | int instance_id,
|
551 | 8a7ddc38 | bellard | int version_id,
|
552 | 8a7ddc38 | bellard | SaveStateHandler *save_state, |
553 | 8a7ddc38 | bellard | LoadStateHandler *load_state, |
554 | 8a7ddc38 | bellard | void *opaque);
|
555 | 8a7ddc38 | bellard | void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
|
556 | 8a7ddc38 | bellard | void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
|
557 | c4b1fcc0 | bellard | |
558 | 6a00d601 | bellard | void cpu_save(QEMUFile *f, void *opaque); |
559 | 6a00d601 | bellard | int cpu_load(QEMUFile *f, void *opaque, int version_id); |
560 | 6a00d601 | bellard | |
561 | faea38e7 | bellard | void do_savevm(const char *name); |
562 | faea38e7 | bellard | void do_loadvm(const char *name); |
563 | faea38e7 | bellard | void do_delvm(const char *name); |
564 | faea38e7 | bellard | void do_info_snapshots(void); |
565 | faea38e7 | bellard | |
566 | 83f64091 | bellard | /* bottom halves */
|
567 | 83f64091 | bellard | typedef void QEMUBHFunc(void *opaque); |
568 | 83f64091 | bellard | |
569 | 83f64091 | bellard | QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
|
570 | 83f64091 | bellard | void qemu_bh_schedule(QEMUBH *bh);
|
571 | 83f64091 | bellard | void qemu_bh_cancel(QEMUBH *bh);
|
572 | 83f64091 | bellard | void qemu_bh_delete(QEMUBH *bh);
|
573 | 6eb5733a | bellard | int qemu_bh_poll(void); |
574 | 83f64091 | bellard | |
575 | fc01f7e7 | bellard | /* block.c */
|
576 | fc01f7e7 | bellard | typedef struct BlockDriverState BlockDriverState; |
577 | ea2384d3 | bellard | typedef struct BlockDriver BlockDriver; |
578 | ea2384d3 | bellard | |
579 | ea2384d3 | bellard | extern BlockDriver bdrv_raw;
|
580 | 19cb3738 | bellard | extern BlockDriver bdrv_host_device;
|
581 | ea2384d3 | bellard | extern BlockDriver bdrv_cow;
|
582 | ea2384d3 | bellard | extern BlockDriver bdrv_qcow;
|
583 | ea2384d3 | bellard | extern BlockDriver bdrv_vmdk;
|
584 | 3c56521b | bellard | extern BlockDriver bdrv_cloop;
|
585 | 585d0ed9 | bellard | extern BlockDriver bdrv_dmg;
|
586 | a8753c34 | bellard | extern BlockDriver bdrv_bochs;
|
587 | 6a0f9e82 | bellard | extern BlockDriver bdrv_vpc;
|
588 | de167e41 | bellard | extern BlockDriver bdrv_vvfat;
|
589 | faea38e7 | bellard | extern BlockDriver bdrv_qcow2;
|
590 | 6ada7453 | ths | extern BlockDriver bdrv_parallels;
|
591 | faea38e7 | bellard | |
592 | faea38e7 | bellard | typedef struct BlockDriverInfo { |
593 | faea38e7 | bellard | /* in bytes, 0 if irrelevant */
|
594 | 5fafdf24 | ths | int cluster_size;
|
595 | faea38e7 | bellard | /* offset at which the VM state can be saved (0 if not possible) */
|
596 | 5fafdf24 | ths | int64_t vm_state_offset; |
597 | faea38e7 | bellard | } BlockDriverInfo; |
598 | faea38e7 | bellard | |
599 | faea38e7 | bellard | typedef struct QEMUSnapshotInfo { |
600 | faea38e7 | bellard | char id_str[128]; /* unique snapshot id */ |
601 | faea38e7 | bellard | /* the following fields are informative. They are not needed for
|
602 | faea38e7 | bellard | the consistency of the snapshot */
|
603 | faea38e7 | bellard | char name[256]; /* user choosen name */ |
604 | faea38e7 | bellard | uint32_t vm_state_size; /* VM state info size */
|
605 | faea38e7 | bellard | uint32_t date_sec; /* UTC date of the snapshot */
|
606 | faea38e7 | bellard | uint32_t date_nsec; |
607 | faea38e7 | bellard | uint64_t vm_clock_nsec; /* VM clock relative to boot */
|
608 | faea38e7 | bellard | } QEMUSnapshotInfo; |
609 | ea2384d3 | bellard | |
610 | 83f64091 | bellard | #define BDRV_O_RDONLY 0x0000 |
611 | 83f64091 | bellard | #define BDRV_O_RDWR 0x0002 |
612 | 83f64091 | bellard | #define BDRV_O_ACCESS 0x0003 |
613 | 83f64091 | bellard | #define BDRV_O_CREAT 0x0004 /* create an empty file */ |
614 | 83f64091 | bellard | #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */ |
615 | 83f64091 | bellard | #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to |
616 | 83f64091 | bellard | use a disk image format on top of
|
617 | 83f64091 | bellard | it (default for
|
618 | 83f64091 | bellard | bdrv_file_open()) */
|
619 | 83f64091 | bellard | |
620 | ea2384d3 | bellard | void bdrv_init(void); |
621 | ea2384d3 | bellard | BlockDriver *bdrv_find_format(const char *format_name); |
622 | 5fafdf24 | ths | int bdrv_create(BlockDriver *drv,
|
623 | ea2384d3 | bellard | const char *filename, int64_t size_in_sectors, |
624 | ea2384d3 | bellard | const char *backing_file, int flags); |
625 | c4b1fcc0 | bellard | BlockDriverState *bdrv_new(const char *device_name); |
626 | c4b1fcc0 | bellard | void bdrv_delete(BlockDriverState *bs);
|
627 | 83f64091 | bellard | int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags); |
628 | 83f64091 | bellard | int bdrv_open(BlockDriverState *bs, const char *filename, int flags); |
629 | 83f64091 | bellard | int bdrv_open2(BlockDriverState *bs, const char *filename, int flags, |
630 | ea2384d3 | bellard | BlockDriver *drv); |
631 | fc01f7e7 | bellard | void bdrv_close(BlockDriverState *bs);
|
632 | 5fafdf24 | ths | int bdrv_read(BlockDriverState *bs, int64_t sector_num,
|
633 | fc01f7e7 | bellard | uint8_t *buf, int nb_sectors);
|
634 | 5fafdf24 | ths | int bdrv_write(BlockDriverState *bs, int64_t sector_num,
|
635 | fc01f7e7 | bellard | const uint8_t *buf, int nb_sectors); |
636 | 5fafdf24 | ths | int bdrv_pread(BlockDriverState *bs, int64_t offset,
|
637 | 83f64091 | bellard | void *buf, int count); |
638 | 5fafdf24 | ths | int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
|
639 | 83f64091 | bellard | const void *buf, int count); |
640 | 83f64091 | bellard | int bdrv_truncate(BlockDriverState *bs, int64_t offset);
|
641 | 83f64091 | bellard | int64_t bdrv_getlength(BlockDriverState *bs); |
642 | fc01f7e7 | bellard | void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
|
643 | 33e3963e | bellard | int bdrv_commit(BlockDriverState *bs);
|
644 | 77fef8c1 | bellard | void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size); |
645 | 83f64091 | bellard | /* async block I/O */
|
646 | 83f64091 | bellard | typedef struct BlockDriverAIOCB BlockDriverAIOCB; |
647 | 83f64091 | bellard | typedef void BlockDriverCompletionFunc(void *opaque, int ret); |
648 | 83f64091 | bellard | |
649 | ce1a14dc | pbrook | BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num, |
650 | ce1a14dc | pbrook | uint8_t *buf, int nb_sectors,
|
651 | ce1a14dc | pbrook | BlockDriverCompletionFunc *cb, void *opaque);
|
652 | ce1a14dc | pbrook | BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num, |
653 | ce1a14dc | pbrook | const uint8_t *buf, int nb_sectors, |
654 | ce1a14dc | pbrook | BlockDriverCompletionFunc *cb, void *opaque);
|
655 | 83f64091 | bellard | void bdrv_aio_cancel(BlockDriverAIOCB *acb);
|
656 | 83f64091 | bellard | |
657 | 83f64091 | bellard | void qemu_aio_init(void); |
658 | 83f64091 | bellard | void qemu_aio_poll(void); |
659 | 6192bc37 | pbrook | void qemu_aio_flush(void); |
660 | 83f64091 | bellard | void qemu_aio_wait_start(void); |
661 | 83f64091 | bellard | void qemu_aio_wait(void); |
662 | 83f64091 | bellard | void qemu_aio_wait_end(void); |
663 | 83f64091 | bellard | |
664 | 2bac6019 | balrog | int qemu_key_check(BlockDriverState *bs, const char *name); |
665 | 2bac6019 | balrog | |
666 | 7a6cba61 | pbrook | /* Ensure contents are flushed to disk. */
|
667 | 7a6cba61 | pbrook | void bdrv_flush(BlockDriverState *bs);
|
668 | 33e3963e | bellard | |
669 | c4b1fcc0 | bellard | #define BDRV_TYPE_HD 0 |
670 | c4b1fcc0 | bellard | #define BDRV_TYPE_CDROM 1 |
671 | c4b1fcc0 | bellard | #define BDRV_TYPE_FLOPPY 2 |
672 | 4dbb0f50 | ths | #define BIOS_ATA_TRANSLATION_AUTO 0 |
673 | 4dbb0f50 | ths | #define BIOS_ATA_TRANSLATION_NONE 1 |
674 | 4dbb0f50 | ths | #define BIOS_ATA_TRANSLATION_LBA 2 |
675 | 4dbb0f50 | ths | #define BIOS_ATA_TRANSLATION_LARGE 3 |
676 | 4dbb0f50 | ths | #define BIOS_ATA_TRANSLATION_RECHS 4 |
677 | c4b1fcc0 | bellard | |
678 | 5fafdf24 | ths | void bdrv_set_geometry_hint(BlockDriverState *bs,
|
679 | c4b1fcc0 | bellard | int cyls, int heads, int secs); |
680 | c4b1fcc0 | bellard | void bdrv_set_type_hint(BlockDriverState *bs, int type); |
681 | 46d4767d | bellard | void bdrv_set_translation_hint(BlockDriverState *bs, int translation); |
682 | 5fafdf24 | ths | void bdrv_get_geometry_hint(BlockDriverState *bs,
|
683 | c4b1fcc0 | bellard | int *pcyls, int *pheads, int *psecs); |
684 | c4b1fcc0 | bellard | int bdrv_get_type_hint(BlockDriverState *bs);
|
685 | 46d4767d | bellard | int bdrv_get_translation_hint(BlockDriverState *bs);
|
686 | c4b1fcc0 | bellard | int bdrv_is_removable(BlockDriverState *bs);
|
687 | c4b1fcc0 | bellard | int bdrv_is_read_only(BlockDriverState *bs);
|
688 | c4b1fcc0 | bellard | int bdrv_is_inserted(BlockDriverState *bs);
|
689 | 19cb3738 | bellard | int bdrv_media_changed(BlockDriverState *bs);
|
690 | c4b1fcc0 | bellard | int bdrv_is_locked(BlockDriverState *bs);
|
691 | c4b1fcc0 | bellard | void bdrv_set_locked(BlockDriverState *bs, int locked); |
692 | 19cb3738 | bellard | void bdrv_eject(BlockDriverState *bs, int eject_flag); |
693 | 5fafdf24 | ths | void bdrv_set_change_cb(BlockDriverState *bs,
|
694 | c4b1fcc0 | bellard | void (*change_cb)(void *opaque), void *opaque); |
695 | ea2384d3 | bellard | void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size); |
696 | c4b1fcc0 | bellard | void bdrv_info(void); |
697 | c4b1fcc0 | bellard | BlockDriverState *bdrv_find(const char *name); |
698 | 82c643ff | bellard | void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque); |
699 | ea2384d3 | bellard | int bdrv_is_encrypted(BlockDriverState *bs);
|
700 | ea2384d3 | bellard | int bdrv_set_key(BlockDriverState *bs, const char *key); |
701 | 5fafdf24 | ths | void bdrv_iterate_format(void (*it)(void *opaque, const char *name), |
702 | ea2384d3 | bellard | void *opaque);
|
703 | ea2384d3 | bellard | const char *bdrv_get_device_name(BlockDriverState *bs); |
704 | 5fafdf24 | ths | int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
|
705 | faea38e7 | bellard | const uint8_t *buf, int nb_sectors); |
706 | faea38e7 | bellard | int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
|
707 | c4b1fcc0 | bellard | |
708 | 5fafdf24 | ths | void bdrv_get_backing_filename(BlockDriverState *bs,
|
709 | 83f64091 | bellard | char *filename, int filename_size); |
710 | 5fafdf24 | ths | int bdrv_snapshot_create(BlockDriverState *bs,
|
711 | faea38e7 | bellard | QEMUSnapshotInfo *sn_info); |
712 | 5fafdf24 | ths | int bdrv_snapshot_goto(BlockDriverState *bs,
|
713 | faea38e7 | bellard | const char *snapshot_id); |
714 | faea38e7 | bellard | int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id); |
715 | 5fafdf24 | ths | int bdrv_snapshot_list(BlockDriverState *bs,
|
716 | faea38e7 | bellard | QEMUSnapshotInfo **psn_info); |
717 | faea38e7 | bellard | char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn); |
718 | faea38e7 | bellard | |
719 | faea38e7 | bellard | char *get_human_readable_size(char *buf, int buf_size, int64_t size); |
720 | 83f64091 | bellard | int path_is_absolute(const char *path); |
721 | 83f64091 | bellard | void path_combine(char *dest, int dest_size, |
722 | 83f64091 | bellard | const char *base_path, |
723 | 83f64091 | bellard | const char *filename); |
724 | ea2384d3 | bellard | |
725 | ea2384d3 | bellard | #ifndef QEMU_TOOL
|
726 | 54fa5af5 | bellard | |
727 | 5fafdf24 | ths | typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, |
728 | 54fa5af5 | bellard | int boot_device,
|
729 | 54fa5af5 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
730 | 54fa5af5 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
731 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model); |
732 | 54fa5af5 | bellard | |
733 | 54fa5af5 | bellard | typedef struct QEMUMachine { |
734 | 54fa5af5 | bellard | const char *name; |
735 | 54fa5af5 | bellard | const char *desc; |
736 | 54fa5af5 | bellard | QEMUMachineInitFunc *init; |
737 | 54fa5af5 | bellard | struct QEMUMachine *next;
|
738 | 54fa5af5 | bellard | } QEMUMachine; |
739 | 54fa5af5 | bellard | |
740 | 54fa5af5 | bellard | int qemu_register_machine(QEMUMachine *m);
|
741 | 54fa5af5 | bellard | |
742 | 54fa5af5 | bellard | typedef void SetIRQFunc(void *opaque, int irq_num, int level); |
743 | 54fa5af5 | bellard | |
744 | d537cf6c | pbrook | #include "hw/irq.h" |
745 | d537cf6c | pbrook | |
746 | 26aa7d72 | bellard | /* ISA bus */
|
747 | 26aa7d72 | bellard | |
748 | 26aa7d72 | bellard | extern target_phys_addr_t isa_mem_base;
|
749 | 26aa7d72 | bellard | |
750 | 26aa7d72 | bellard | typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data); |
751 | 26aa7d72 | bellard | typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address); |
752 | 26aa7d72 | bellard | |
753 | 5fafdf24 | ths | int register_ioport_read(int start, int length, int size, |
754 | 26aa7d72 | bellard | IOPortReadFunc *func, void *opaque);
|
755 | 5fafdf24 | ths | int register_ioport_write(int start, int length, int size, |
756 | 26aa7d72 | bellard | IOPortWriteFunc *func, void *opaque);
|
757 | 69b91039 | bellard | void isa_unassign_ioport(int start, int length); |
758 | 69b91039 | bellard | |
759 | aef445bd | pbrook | void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
|
760 | aef445bd | pbrook | |
761 | 69b91039 | bellard | /* PCI bus */
|
762 | 69b91039 | bellard | |
763 | 69b91039 | bellard | extern target_phys_addr_t pci_mem_base;
|
764 | 69b91039 | bellard | |
765 | 46e50e9d | bellard | typedef struct PCIBus PCIBus; |
766 | 69b91039 | bellard | typedef struct PCIDevice PCIDevice; |
767 | 69b91039 | bellard | |
768 | 5fafdf24 | ths | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
769 | 69b91039 | bellard | uint32_t address, uint32_t data, int len);
|
770 | 5fafdf24 | ths | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
|
771 | 69b91039 | bellard | uint32_t address, int len);
|
772 | 5fafdf24 | ths | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
773 | 69b91039 | bellard | uint32_t addr, uint32_t size, int type);
|
774 | 69b91039 | bellard | |
775 | 69b91039 | bellard | #define PCI_ADDRESS_SPACE_MEM 0x00 |
776 | 69b91039 | bellard | #define PCI_ADDRESS_SPACE_IO 0x01 |
777 | 69b91039 | bellard | #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 |
778 | 69b91039 | bellard | |
779 | 69b91039 | bellard | typedef struct PCIIORegion { |
780 | 5768f5ac | bellard | uint32_t addr; /* current PCI mapping address. -1 means not mapped */
|
781 | 69b91039 | bellard | uint32_t size; |
782 | 69b91039 | bellard | uint8_t type; |
783 | 69b91039 | bellard | PCIMapIORegionFunc *map_func; |
784 | 69b91039 | bellard | } PCIIORegion; |
785 | 69b91039 | bellard | |
786 | 8a8696a3 | bellard | #define PCI_ROM_SLOT 6 |
787 | 8a8696a3 | bellard | #define PCI_NUM_REGIONS 7 |
788 | 502a5395 | pbrook | |
789 | 502a5395 | pbrook | #define PCI_DEVICES_MAX 64 |
790 | 502a5395 | pbrook | |
791 | 502a5395 | pbrook | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
792 | 502a5395 | pbrook | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
793 | 502a5395 | pbrook | #define PCI_COMMAND 0x04 /* 16 bits */ |
794 | 502a5395 | pbrook | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
795 | 502a5395 | pbrook | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
796 | 502a5395 | pbrook | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
797 | 502a5395 | pbrook | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
798 | 502a5395 | pbrook | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
799 | 502a5395 | pbrook | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
800 | 502a5395 | pbrook | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
801 | 502a5395 | pbrook | |
802 | 69b91039 | bellard | struct PCIDevice {
|
803 | 69b91039 | bellard | /* PCI config space */
|
804 | 69b91039 | bellard | uint8_t config[256];
|
805 | 69b91039 | bellard | |
806 | 69b91039 | bellard | /* the following fields are read only */
|
807 | 46e50e9d | bellard | PCIBus *bus; |
808 | 69b91039 | bellard | int devfn;
|
809 | 69b91039 | bellard | char name[64]; |
810 | 8a8696a3 | bellard | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
811 | 3b46e624 | ths | |
812 | 69b91039 | bellard | /* do not access the following fields */
|
813 | 69b91039 | bellard | PCIConfigReadFunc *config_read; |
814 | 69b91039 | bellard | PCIConfigWriteFunc *config_write; |
815 | 502a5395 | pbrook | /* ??? This is a PC-specific hack, and should be removed. */
|
816 | 5768f5ac | bellard | int irq_index;
|
817 | d2b59317 | pbrook | |
818 | d537cf6c | pbrook | /* IRQ objects for the INTA-INTD pins. */
|
819 | d537cf6c | pbrook | qemu_irq *irq; |
820 | d537cf6c | pbrook | |
821 | d2b59317 | pbrook | /* Current IRQ levels. Used internally by the generic PCI code. */
|
822 | d2b59317 | pbrook | int irq_state[4]; |
823 | 69b91039 | bellard | }; |
824 | 69b91039 | bellard | |
825 | 46e50e9d | bellard | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
826 | 46e50e9d | bellard | int instance_size, int devfn, |
827 | 5fafdf24 | ths | PCIConfigReadFunc *config_read, |
828 | 69b91039 | bellard | PCIConfigWriteFunc *config_write); |
829 | 69b91039 | bellard | |
830 | 5fafdf24 | ths | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
831 | 5fafdf24 | ths | uint32_t size, int type,
|
832 | 69b91039 | bellard | PCIMapIORegionFunc *map_func); |
833 | 69b91039 | bellard | |
834 | 5fafdf24 | ths | uint32_t pci_default_read_config(PCIDevice *d, |
835 | 5768f5ac | bellard | uint32_t address, int len);
|
836 | 5fafdf24 | ths | void pci_default_write_config(PCIDevice *d,
|
837 | 5768f5ac | bellard | uint32_t address, uint32_t val, int len);
|
838 | 89b6b508 | bellard | void pci_device_save(PCIDevice *s, QEMUFile *f);
|
839 | 89b6b508 | bellard | int pci_device_load(PCIDevice *s, QEMUFile *f);
|
840 | 5768f5ac | bellard | |
841 | d537cf6c | pbrook | typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); |
842 | d2b59317 | pbrook | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
843 | d2b59317 | pbrook | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
844 | d537cf6c | pbrook | qemu_irq *pic, int devfn_min, int nirq); |
845 | 502a5395 | pbrook | |
846 | abcebc7e | ths | void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn); |
847 | 502a5395 | pbrook | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
848 | 502a5395 | pbrook | uint32_t pci_data_read(void *opaque, uint32_t addr, int len); |
849 | 502a5395 | pbrook | int pci_bus_num(PCIBus *s);
|
850 | 80b3ada7 | pbrook | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); |
851 | 9995c51f | bellard | |
852 | 5768f5ac | bellard | void pci_info(void); |
853 | 80b3ada7 | pbrook | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
|
854 | 80b3ada7 | pbrook | pci_map_irq_fn map_irq, const char *name); |
855 | 26aa7d72 | bellard | |
856 | 502a5395 | pbrook | /* prep_pci.c */
|
857 | d537cf6c | pbrook | PCIBus *pci_prep_init(qemu_irq *pic); |
858 | 77d4bc34 | bellard | |
859 | 502a5395 | pbrook | /* grackle_pci.c */
|
860 | d537cf6c | pbrook | PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic); |
861 | 502a5395 | pbrook | |
862 | 502a5395 | pbrook | /* unin_pci.c */
|
863 | d537cf6c | pbrook | PCIBus *pci_pmac_init(qemu_irq *pic); |
864 | 502a5395 | pbrook | |
865 | 502a5395 | pbrook | /* apb_pci.c */
|
866 | 5b9693dc | blueswir1 | PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base, |
867 | d537cf6c | pbrook | qemu_irq *pic); |
868 | 502a5395 | pbrook | |
869 | d537cf6c | pbrook | PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview); |
870 | 502a5395 | pbrook | |
871 | 502a5395 | pbrook | /* piix_pci.c */
|
872 | d537cf6c | pbrook | PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic); |
873 | f00fc47c | bellard | void i440fx_set_smm(PCIDevice *d, int val); |
874 | 8f1c91d8 | ths | int piix3_init(PCIBus *bus, int devfn); |
875 | f00fc47c | bellard | void i440fx_init_memory_mappings(PCIDevice *d);
|
876 | a41b2ff2 | pbrook | |
877 | 5856de80 | ths | int piix4_init(PCIBus *bus, int devfn); |
878 | 5856de80 | ths | |
879 | 28b9b5af | bellard | /* openpic.c */
|
880 | e9df014c | j_mayer | /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
|
881 | 47103572 | j_mayer | enum {
|
882 | e9df014c | j_mayer | OPENPIC_OUTPUT_INT = 0, /* IRQ */ |
883 | e9df014c | j_mayer | OPENPIC_OUTPUT_CINT, /* critical IRQ */
|
884 | e9df014c | j_mayer | OPENPIC_OUTPUT_MCK, /* Machine check event */
|
885 | e9df014c | j_mayer | OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
|
886 | e9df014c | j_mayer | OPENPIC_OUTPUT_RESET, /* Core reset event */
|
887 | e9df014c | j_mayer | OPENPIC_OUTPUT_NB, |
888 | 47103572 | j_mayer | }; |
889 | e9df014c | j_mayer | qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
890 | e9df014c | j_mayer | qemu_irq **irqs, qemu_irq irq_out); |
891 | 28b9b5af | bellard | |
892 | 54fa5af5 | bellard | /* heathrow_pic.c */
|
893 | d537cf6c | pbrook | qemu_irq *heathrow_pic_init(int *pmem_index);
|
894 | 54fa5af5 | bellard | |
895 | fde7d5bd | ths | /* gt64xxx.c */
|
896 | d537cf6c | pbrook | PCIBus *pci_gt64120_init(qemu_irq *pic); |
897 | fde7d5bd | ths | |
898 | 6a36d84e | bellard | #ifdef HAS_AUDIO
|
899 | 6a36d84e | bellard | struct soundhw {
|
900 | 6a36d84e | bellard | const char *name; |
901 | 6a36d84e | bellard | const char *descr; |
902 | 6a36d84e | bellard | int enabled;
|
903 | 6a36d84e | bellard | int isa;
|
904 | 6a36d84e | bellard | union {
|
905 | d537cf6c | pbrook | int (*init_isa) (AudioState *s, qemu_irq *pic);
|
906 | 6a36d84e | bellard | int (*init_pci) (PCIBus *bus, AudioState *s);
|
907 | 6a36d84e | bellard | } init; |
908 | 6a36d84e | bellard | }; |
909 | 6a36d84e | bellard | |
910 | 6a36d84e | bellard | extern struct soundhw soundhw[]; |
911 | 6a36d84e | bellard | #endif
|
912 | 6a36d84e | bellard | |
913 | 313aa567 | bellard | /* vga.c */
|
914 | 313aa567 | bellard | |
915 | eee0b836 | blueswir1 | #ifndef TARGET_SPARC
|
916 | 74a14f22 | bellard | #define VGA_RAM_SIZE (8192 * 1024) |
917 | eee0b836 | blueswir1 | #else
|
918 | eee0b836 | blueswir1 | #define VGA_RAM_SIZE (9 * 1024 * 1024) |
919 | eee0b836 | blueswir1 | #endif
|
920 | 313aa567 | bellard | |
921 | 82c643ff | bellard | struct DisplayState {
|
922 | 313aa567 | bellard | uint8_t *data; |
923 | 313aa567 | bellard | int linesize;
|
924 | 313aa567 | bellard | int depth;
|
925 | d3079cd2 | bellard | int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */ |
926 | 82c643ff | bellard | int width;
|
927 | 82c643ff | bellard | int height;
|
928 | 24236869 | bellard | void *opaque;
|
929 | 740733bb | ths | QEMUTimer *gui_timer; |
930 | 24236869 | bellard | |
931 | 313aa567 | bellard | void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h); |
932 | 313aa567 | bellard | void (*dpy_resize)(struct DisplayState *s, int w, int h); |
933 | 313aa567 | bellard | void (*dpy_refresh)(struct DisplayState *s); |
934 | d34cab9f | ths | void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, |
935 | d34cab9f | ths | int dst_x, int dst_y, int w, int h); |
936 | d34cab9f | ths | void (*dpy_fill)(struct DisplayState *s, int x, int y, |
937 | d34cab9f | ths | int w, int h, uint32_t c); |
938 | d34cab9f | ths | void (*mouse_set)(int x, int y, int on); |
939 | d34cab9f | ths | void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y, |
940 | d34cab9f | ths | uint8_t *image, uint8_t *mask); |
941 | 82c643ff | bellard | }; |
942 | 313aa567 | bellard | |
943 | 313aa567 | bellard | static inline void dpy_update(DisplayState *s, int x, int y, int w, int h) |
944 | 313aa567 | bellard | { |
945 | 313aa567 | bellard | s->dpy_update(s, x, y, w, h); |
946 | 313aa567 | bellard | } |
947 | 313aa567 | bellard | |
948 | 313aa567 | bellard | static inline void dpy_resize(DisplayState *s, int w, int h) |
949 | 313aa567 | bellard | { |
950 | 313aa567 | bellard | s->dpy_resize(s, w, h); |
951 | 313aa567 | bellard | } |
952 | 313aa567 | bellard | |
953 | 5fafdf24 | ths | int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
954 | 89b6b508 | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
955 | 5fafdf24 | ths | int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
956 | 89b6b508 | bellard | unsigned long vga_ram_offset, int vga_ram_size, |
957 | 89b6b508 | bellard | unsigned long vga_bios_offset, int vga_bios_size); |
958 | 2abec30b | ths | int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
|
959 | 2abec30b | ths | unsigned long vga_ram_offset, int vga_ram_size, |
960 | 2abec30b | ths | target_phys_addr_t vram_base, target_phys_addr_t ctrl_base, |
961 | 2abec30b | ths | int it_shift);
|
962 | 313aa567 | bellard | |
963 | d6bfa22f | bellard | /* cirrus_vga.c */
|
964 | 5fafdf24 | ths | void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
965 | d6bfa22f | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
966 | 5fafdf24 | ths | void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
967 | d6bfa22f | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
968 | d6bfa22f | bellard | |
969 | d34cab9f | ths | /* vmware_vga.c */
|
970 | d34cab9f | ths | void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
971 | d34cab9f | ths | unsigned long vga_ram_offset, int vga_ram_size); |
972 | d34cab9f | ths | |
973 | 313aa567 | bellard | /* sdl.c */
|
974 | 43523e93 | ths | void sdl_display_init(DisplayState *ds, int full_screen, int no_frame); |
975 | 313aa567 | bellard | |
976 | da4dbf74 | bellard | /* cocoa.m */
|
977 | da4dbf74 | bellard | void cocoa_display_init(DisplayState *ds, int full_screen); |
978 | da4dbf74 | bellard | |
979 | 24236869 | bellard | /* vnc.c */
|
980 | 71cab5ca | ths | void vnc_display_init(DisplayState *ds);
|
981 | 71cab5ca | ths | void vnc_display_close(DisplayState *ds);
|
982 | 71cab5ca | ths | int vnc_display_open(DisplayState *ds, const char *display); |
983 | 70848515 | ths | int vnc_display_password(DisplayState *ds, const char *password); |
984 | a9ce8590 | bellard | void do_info_vnc(void); |
985 | 24236869 | bellard | |
986 | 6070dd07 | ths | /* x_keymap.c */
|
987 | 6070dd07 | ths | extern uint8_t _translate_keycode(const int key); |
988 | 6070dd07 | ths | |
989 | 5391d806 | bellard | /* ide.c */
|
990 | 5391d806 | bellard | #define MAX_DISKS 4 |
991 | 5391d806 | bellard | |
992 | faea38e7 | bellard | extern BlockDriverState *bs_table[MAX_DISKS + 1]; |
993 | a1bb27b1 | pbrook | extern BlockDriverState *sd_bdrv;
|
994 | 3e3d5815 | balrog | extern BlockDriverState *mtd_bdrv;
|
995 | 5391d806 | bellard | |
996 | d537cf6c | pbrook | void isa_ide_init(int iobase, int iobase2, qemu_irq irq, |
997 | 69b91039 | bellard | BlockDriverState *hd0, BlockDriverState *hd1); |
998 | 54fa5af5 | bellard | void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
|
999 | 54fa5af5 | bellard | int secondary_ide_enabled);
|
1000 | d537cf6c | pbrook | void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
1001 | d537cf6c | pbrook | qemu_irq *pic); |
1002 | afcc3cdf | ths | void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
1003 | afcc3cdf | ths | qemu_irq *pic); |
1004 | d537cf6c | pbrook | int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
|
1005 | 5391d806 | bellard | |
1006 | 2e5d83bb | pbrook | /* cdrom.c */
|
1007 | 2e5d83bb | pbrook | int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track); |
1008 | 2e5d83bb | pbrook | int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num); |
1009 | 2e5d83bb | pbrook | |
1010 | 9542611a | ths | /* ds1225y.c */
|
1011 | 9542611a | ths | typedef struct ds1225y_t ds1225y_t; |
1012 | 71db710f | blueswir1 | ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename); |
1013 | 9542611a | ths | |
1014 | 1d14ffa9 | bellard | /* es1370.c */
|
1015 | c0fe3827 | bellard | int es1370_init (PCIBus *bus, AudioState *s);
|
1016 | 1d14ffa9 | bellard | |
1017 | fb065187 | bellard | /* sb16.c */
|
1018 | d537cf6c | pbrook | int SB16_init (AudioState *s, qemu_irq *pic);
|
1019 | fb065187 | bellard | |
1020 | fb065187 | bellard | /* adlib.c */
|
1021 | d537cf6c | pbrook | int Adlib_init (AudioState *s, qemu_irq *pic);
|
1022 | fb065187 | bellard | |
1023 | fb065187 | bellard | /* gus.c */
|
1024 | d537cf6c | pbrook | int GUS_init (AudioState *s, qemu_irq *pic);
|
1025 | 27503323 | bellard | |
1026 | 27503323 | bellard | /* dma.c */
|
1027 | 85571bc7 | bellard | typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size); |
1028 | 27503323 | bellard | int DMA_get_channel_mode (int nchan); |
1029 | 85571bc7 | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size); |
1030 | 85571bc7 | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size); |
1031 | 27503323 | bellard | void DMA_hold_DREQ (int nchan); |
1032 | 27503323 | bellard | void DMA_release_DREQ (int nchan); |
1033 | 16f62432 | bellard | void DMA_schedule(int nchan); |
1034 | 27503323 | bellard | void DMA_run (void); |
1035 | 28b9b5af | bellard | void DMA_init (int high_page_enable); |
1036 | 27503323 | bellard | void DMA_register_channel (int nchan, |
1037 | 85571bc7 | bellard | DMA_transfer_handler transfer_handler, |
1038 | 85571bc7 | bellard | void *opaque);
|
1039 | 7138fcfb | bellard | /* fdc.c */
|
1040 | 7138fcfb | bellard | #define MAX_FD 2 |
1041 | 7138fcfb | bellard | extern BlockDriverState *fd_table[MAX_FD];
|
1042 | 7138fcfb | bellard | |
1043 | baca51fa | bellard | typedef struct fdctrl_t fdctrl_t; |
1044 | baca51fa | bellard | |
1045 | 5fafdf24 | ths | fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, |
1046 | 5dcb6b91 | blueswir1 | target_phys_addr_t io_base, |
1047 | baca51fa | bellard | BlockDriverState **fds); |
1048 | baca51fa | bellard | int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num); |
1049 | 7138fcfb | bellard | |
1050 | 663e8e51 | ths | /* eepro100.c */
|
1051 | 663e8e51 | ths | |
1052 | 663e8e51 | ths | void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn); |
1053 | 663e8e51 | ths | void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn); |
1054 | 663e8e51 | ths | void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn); |
1055 | 663e8e51 | ths | |
1056 | 80cabfad | bellard | /* ne2000.c */
|
1057 | 80cabfad | bellard | |
1058 | d537cf6c | pbrook | void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd); |
1059 | abcebc7e | ths | void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); |
1060 | 80cabfad | bellard | |
1061 | a41b2ff2 | pbrook | /* rtl8139.c */
|
1062 | a41b2ff2 | pbrook | |
1063 | abcebc7e | ths | void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); |
1064 | a41b2ff2 | pbrook | |
1065 | e3c2613f | bellard | /* pcnet.c */
|
1066 | e3c2613f | bellard | |
1067 | abcebc7e | ths | void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); |
1068 | 70c0de96 | blueswir1 | void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque, |
1069 | 2d069bab | blueswir1 | qemu_irq irq, qemu_irq *reset); |
1070 | 67e999be | bellard | |
1071 | 548df2ac | ths | /* vmmouse.c */
|
1072 | 548df2ac | ths | void *vmmouse_init(void *m); |
1073 | e3c2613f | bellard | |
1074 | 591a6d62 | ths | /* vmport.c */
|
1075 | 591a6d62 | ths | #ifdef TARGET_I386
|
1076 | 591a6d62 | ths | void vmport_init(CPUState *env);
|
1077 | 591a6d62 | ths | void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque); |
1078 | 591a6d62 | ths | #endif
|
1079 | 591a6d62 | ths | |
1080 | 80cabfad | bellard | /* pckbd.c */
|
1081 | 80cabfad | bellard | |
1082 | b92bb99b | ths | void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
|
1083 | 71db710f | blueswir1 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
|
1084 | 71db710f | blueswir1 | target_phys_addr_t base, int it_shift);
|
1085 | 80cabfad | bellard | |
1086 | 80cabfad | bellard | /* mc146818rtc.c */
|
1087 | 80cabfad | bellard | |
1088 | 8a7ddc38 | bellard | typedef struct RTCState RTCState; |
1089 | 80cabfad | bellard | |
1090 | d537cf6c | pbrook | RTCState *rtc_init(int base, qemu_irq irq);
|
1091 | 18c6e2ff | ths | RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
|
1092 | 8a7ddc38 | bellard | void rtc_set_memory(RTCState *s, int addr, int val); |
1093 | 8a7ddc38 | bellard | void rtc_set_date(RTCState *s, const struct tm *tm); |
1094 | 80cabfad | bellard | |
1095 | 80cabfad | bellard | /* serial.c */
|
1096 | 80cabfad | bellard | |
1097 | c4b1fcc0 | bellard | typedef struct SerialState SerialState; |
1098 | d537cf6c | pbrook | SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
|
1099 | 71db710f | blueswir1 | SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
|
1100 | d537cf6c | pbrook | qemu_irq irq, CharDriverState *chr, |
1101 | a4bc3afc | ths | int ioregister);
|
1102 | a4bc3afc | ths | uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
|
1103 | a4bc3afc | ths | void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value); |
1104 | a4bc3afc | ths | uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
|
1105 | a4bc3afc | ths | void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value); |
1106 | a4bc3afc | ths | uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
|
1107 | a4bc3afc | ths | void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value); |
1108 | 80cabfad | bellard | |
1109 | 6508fe59 | bellard | /* parallel.c */
|
1110 | 6508fe59 | bellard | |
1111 | 6508fe59 | bellard | typedef struct ParallelState ParallelState; |
1112 | d537cf6c | pbrook | ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
|
1113 | d60532ca | ths | ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
|
1114 | 6508fe59 | bellard | |
1115 | 80cabfad | bellard | /* i8259.c */
|
1116 | 80cabfad | bellard | |
1117 | 3de388f6 | bellard | typedef struct PicState2 PicState2; |
1118 | 3de388f6 | bellard | extern PicState2 *isa_pic;
|
1119 | 80cabfad | bellard | void pic_set_irq(int irq, int level); |
1120 | 54fa5af5 | bellard | void pic_set_irq_new(void *opaque, int irq, int level); |
1121 | d537cf6c | pbrook | qemu_irq *i8259_init(qemu_irq parent_irq); |
1122 | d592d303 | bellard | void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
|
1123 | d592d303 | bellard | void *alt_irq_opaque);
|
1124 | 3de388f6 | bellard | int pic_read_irq(PicState2 *s);
|
1125 | 3de388f6 | bellard | void pic_update_irq(PicState2 *s);
|
1126 | 3de388f6 | bellard | uint32_t pic_intack_read(PicState2 *s); |
1127 | c20709aa | bellard | void pic_info(void); |
1128 | 4a0fb71e | bellard | void irq_info(void); |
1129 | 80cabfad | bellard | |
1130 | c27004ec | bellard | /* APIC */
|
1131 | d592d303 | bellard | typedef struct IOAPICState IOAPICState; |
1132 | d592d303 | bellard | |
1133 | c27004ec | bellard | int apic_init(CPUState *env);
|
1134 | 0e21e12b | ths | int apic_accept_pic_intr(CPUState *env);
|
1135 | c27004ec | bellard | int apic_get_interrupt(CPUState *env);
|
1136 | d592d303 | bellard | IOAPICState *ioapic_init(void);
|
1137 | d592d303 | bellard | void ioapic_set_irq(void *opaque, int vector, int level); |
1138 | c27004ec | bellard | |
1139 | 80cabfad | bellard | /* i8254.c */
|
1140 | 80cabfad | bellard | |
1141 | 80cabfad | bellard | #define PIT_FREQ 1193182 |
1142 | 80cabfad | bellard | |
1143 | ec844b96 | bellard | typedef struct PITState PITState; |
1144 | ec844b96 | bellard | |
1145 | d537cf6c | pbrook | PITState *pit_init(int base, qemu_irq irq);
|
1146 | ec844b96 | bellard | void pit_set_gate(PITState *pit, int channel, int val); |
1147 | ec844b96 | bellard | int pit_get_gate(PITState *pit, int channel); |
1148 | fd06c375 | bellard | int pit_get_initial_count(PITState *pit, int channel); |
1149 | fd06c375 | bellard | int pit_get_mode(PITState *pit, int channel); |
1150 | ec844b96 | bellard | int pit_get_out(PITState *pit, int channel, int64_t current_time); |
1151 | 80cabfad | bellard | |
1152 | 31211df1 | ths | /* jazz_led.c */
|
1153 | 31211df1 | ths | extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base); |
1154 | 31211df1 | ths | |
1155 | fd06c375 | bellard | /* pcspk.c */
|
1156 | fd06c375 | bellard | void pcspk_init(PITState *);
|
1157 | d537cf6c | pbrook | int pcspk_audio_init(AudioState *, qemu_irq *pic);
|
1158 | fd06c375 | bellard | |
1159 | 0ff596d0 | pbrook | #include "hw/i2c.h" |
1160 | 0ff596d0 | pbrook | |
1161 | 3fffc223 | ths | #include "hw/smbus.h" |
1162 | 3fffc223 | ths | |
1163 | 6515b203 | bellard | /* acpi.c */
|
1164 | 6515b203 | bellard | extern int acpi_enabled; |
1165 | 7b717336 | ths | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
|
1166 | 3fffc223 | ths | void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
|
1167 | 6515b203 | bellard | void acpi_bios_init(void); |
1168 | 6515b203 | bellard | |
1169 | f1ccf904 | ths | /* Axis ETRAX. */
|
1170 | f1ccf904 | ths | extern QEMUMachine bareetraxfs_machine;
|
1171 | f1ccf904 | ths | |
1172 | 80cabfad | bellard | /* pc.c */
|
1173 | 54fa5af5 | bellard | extern QEMUMachine pc_machine;
|
1174 | 3dbbdc25 | bellard | extern QEMUMachine isapc_machine;
|
1175 | 52ca8d6a | bellard | extern int fd_bootchk; |
1176 | 80cabfad | bellard | |
1177 | 6a00d601 | bellard | void ioport_set_a20(int enable); |
1178 | 6a00d601 | bellard | int ioport_get_a20(void); |
1179 | 6a00d601 | bellard | |
1180 | 26aa7d72 | bellard | /* ppc.c */
|
1181 | 54fa5af5 | bellard | extern QEMUMachine prep_machine;
|
1182 | 54fa5af5 | bellard | extern QEMUMachine core99_machine;
|
1183 | 54fa5af5 | bellard | extern QEMUMachine heathrow_machine;
|
1184 | 1a6c0886 | j_mayer | extern QEMUMachine ref405ep_machine;
|
1185 | 1a6c0886 | j_mayer | extern QEMUMachine taihu_machine;
|
1186 | 54fa5af5 | bellard | |
1187 | 6af0bf9c | bellard | /* mips_r4k.c */
|
1188 | 6af0bf9c | bellard | extern QEMUMachine mips_machine;
|
1189 | 6af0bf9c | bellard | |
1190 | 5856de80 | ths | /* mips_malta.c */
|
1191 | 5856de80 | ths | extern QEMUMachine mips_malta_machine;
|
1192 | 5856de80 | ths | |
1193 | ad6fe1d2 | ths | /* mips_int.c */
|
1194 | d537cf6c | pbrook | extern void cpu_mips_irq_init_cpu(CPUState *env); |
1195 | 4de9b249 | ths | |
1196 | ad6fe1d2 | ths | /* mips_pica61.c */
|
1197 | ad6fe1d2 | ths | extern QEMUMachine mips_pica61_machine;
|
1198 | ad6fe1d2 | ths | |
1199 | e16fe40c | ths | /* mips_timer.c */
|
1200 | e16fe40c | ths | extern void cpu_mips_clock_init(CPUState *); |
1201 | e16fe40c | ths | extern void cpu_mips_irqctrl_init (void); |
1202 | e16fe40c | ths | |
1203 | 27c7ca7e | bellard | /* shix.c */
|
1204 | 27c7ca7e | bellard | extern QEMUMachine shix_machine;
|
1205 | 27c7ca7e | bellard | |
1206 | 0d78f544 | ths | /* r2d.c */
|
1207 | 0d78f544 | ths | extern QEMUMachine r2d_machine;
|
1208 | 0d78f544 | ths | |
1209 | 8cc43fef | bellard | #ifdef TARGET_PPC
|
1210 | 47103572 | j_mayer | /* PowerPC hardware exceptions management helpers */
|
1211 | 8ecc7913 | j_mayer | typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); |
1212 | 8ecc7913 | j_mayer | typedef struct clk_setup_t clk_setup_t; |
1213 | 8ecc7913 | j_mayer | struct clk_setup_t {
|
1214 | 8ecc7913 | j_mayer | clk_setup_cb cb; |
1215 | 8ecc7913 | j_mayer | void *opaque;
|
1216 | 8ecc7913 | j_mayer | }; |
1217 | 8ecc7913 | j_mayer | static inline void clk_setup (clk_setup_t *clk, uint32_t freq) |
1218 | 8ecc7913 | j_mayer | { |
1219 | 8ecc7913 | j_mayer | if (clk->cb != NULL) |
1220 | 8ecc7913 | j_mayer | (*clk->cb)(clk->opaque, freq); |
1221 | 8ecc7913 | j_mayer | } |
1222 | 8ecc7913 | j_mayer | |
1223 | 8ecc7913 | j_mayer | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
1224 | 2e719ba3 | j_mayer | /* Embedded PowerPC DCR management */
|
1225 | 2e719ba3 | j_mayer | typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn); |
1226 | 2e719ba3 | j_mayer | typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val); |
1227 | 2e719ba3 | j_mayer | int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), |
1228 | 2e719ba3 | j_mayer | int (*dcr_write_error)(int dcrn)); |
1229 | 2e719ba3 | j_mayer | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
1230 | 2e719ba3 | j_mayer | dcr_read_cb drc_read, dcr_write_cb dcr_write); |
1231 | 8ecc7913 | j_mayer | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); |
1232 | 4a057712 | j_mayer | /* Embedded PowerPC reset */
|
1233 | 4a057712 | j_mayer | void ppc40x_core_reset (CPUState *env);
|
1234 | 4a057712 | j_mayer | void ppc40x_chip_reset (CPUState *env);
|
1235 | 4a057712 | j_mayer | void ppc40x_system_reset (CPUState *env);
|
1236 | 8cc43fef | bellard | #endif
|
1237 | 64201201 | bellard | void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1238 | 77d4bc34 | bellard | |
1239 | 77d4bc34 | bellard | extern CPUWriteMemoryFunc *PPC_io_write[];
|
1240 | 77d4bc34 | bellard | extern CPUReadMemoryFunc *PPC_io_read[];
|
1241 | 54fa5af5 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1242 | 26aa7d72 | bellard | |
1243 | e95c8d51 | bellard | /* sun4m.c */
|
1244 | e0353fe2 | blueswir1 | extern QEMUMachine ss5_machine, ss10_machine;
|
1245 | e95c8d51 | bellard | |
1246 | e95c8d51 | bellard | /* iommu.c */
|
1247 | 5dcb6b91 | blueswir1 | void *iommu_init(target_phys_addr_t addr);
|
1248 | 67e999be | bellard | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
1249 | a917d384 | pbrook | uint8_t *buf, int len, int is_write); |
1250 | 67e999be | bellard | static inline void sparc_iommu_memory_read(void *opaque, |
1251 | 67e999be | bellard | target_phys_addr_t addr, |
1252 | 67e999be | bellard | uint8_t *buf, int len)
|
1253 | 67e999be | bellard | { |
1254 | 67e999be | bellard | sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
|
1255 | 67e999be | bellard | } |
1256 | e95c8d51 | bellard | |
1257 | 67e999be | bellard | static inline void sparc_iommu_memory_write(void *opaque, |
1258 | 67e999be | bellard | target_phys_addr_t addr, |
1259 | 67e999be | bellard | uint8_t *buf, int len)
|
1260 | 67e999be | bellard | { |
1261 | 67e999be | bellard | sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
|
1262 | 67e999be | bellard | } |
1263 | e95c8d51 | bellard | |
1264 | e95c8d51 | bellard | /* tcx.c */
|
1265 | 5dcb6b91 | blueswir1 | void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
|
1266 | 5dcb6b91 | blueswir1 | unsigned long vram_offset, int vram_size, int width, int height, |
1267 | eee0b836 | blueswir1 | int depth);
|
1268 | e80cfcfc | bellard | |
1269 | e80cfcfc | bellard | /* slavio_intctl.c */
|
1270 | 5dcb6b91 | blueswir1 | void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
|
1271 | d537cf6c | pbrook | const uint32_t *intbit_to_level,
|
1272 | d7edfd27 | blueswir1 | qemu_irq **irq, qemu_irq **cpu_irq, |
1273 | b3a23197 | blueswir1 | qemu_irq **parent_irq, unsigned int cputimer); |
1274 | e80cfcfc | bellard | void slavio_pic_info(void *opaque); |
1275 | e80cfcfc | bellard | void slavio_irq_info(void *opaque); |
1276 | e95c8d51 | bellard | |
1277 | 5fe141fd | bellard | /* loader.c */
|
1278 | 5fe141fd | bellard | int get_image_size(const char *filename); |
1279 | 5fe141fd | bellard | int load_image(const char *filename, uint8_t *addr); |
1280 | 74287114 | ths | int load_elf(const char *filename, int64_t virt_to_phys_addend, |
1281 | 74287114 | ths | uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr); |
1282 | e80cfcfc | bellard | int load_aout(const char *filename, uint8_t *addr); |
1283 | 1c7b3754 | pbrook | int load_uboot(const char *filename, target_ulong *ep, int *is_linux); |
1284 | e80cfcfc | bellard | |
1285 | e80cfcfc | bellard | /* slavio_timer.c */
|
1286 | 81732d19 | blueswir1 | void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
|
1287 | 81732d19 | blueswir1 | qemu_irq *cpu_irqs); |
1288 | 8d5f07fa | bellard | |
1289 | e80cfcfc | bellard | /* slavio_serial.c */
|
1290 | 5dcb6b91 | blueswir1 | SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq, |
1291 | 5dcb6b91 | blueswir1 | CharDriverState *chr1, CharDriverState *chr2); |
1292 | 5dcb6b91 | blueswir1 | void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
|
1293 | e95c8d51 | bellard | |
1294 | 3475187d | bellard | /* slavio_misc.c */
|
1295 | 5dcb6b91 | blueswir1 | void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
|
1296 | 5dcb6b91 | blueswir1 | qemu_irq irq); |
1297 | 3475187d | bellard | void slavio_set_power_fail(void *opaque, int power_failing); |
1298 | 3475187d | bellard | |
1299 | 6f7e9aec | bellard | /* esp.c */
|
1300 | fa1fb14c | ths | void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
1301 | 5dcb6b91 | blueswir1 | void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
|
1302 | 2d069bab | blueswir1 | void *dma_opaque, qemu_irq irq, qemu_irq *reset);
|
1303 | 67e999be | bellard | |
1304 | 67e999be | bellard | /* sparc32_dma.c */
|
1305 | 70c0de96 | blueswir1 | void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
|
1306 | 2d069bab | blueswir1 | void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
|
1307 | 5fafdf24 | ths | void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
1308 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap); |
1309 | 5fafdf24 | ths | void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
1310 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap); |
1311 | 67e999be | bellard | void espdma_memory_read(void *opaque, uint8_t *buf, int len); |
1312 | 67e999be | bellard | void espdma_memory_write(void *opaque, uint8_t *buf, int len); |
1313 | 6f7e9aec | bellard | |
1314 | b8174937 | bellard | /* cs4231.c */
|
1315 | b8174937 | bellard | void cs_init(target_phys_addr_t base, int irq, void *intctl); |
1316 | b8174937 | bellard | |
1317 | 3475187d | bellard | /* sun4u.c */
|
1318 | 3475187d | bellard | extern QEMUMachine sun4u_machine;
|
1319 | 3475187d | bellard | |
1320 | 64201201 | bellard | /* NVRAM helpers */
|
1321 | 64201201 | bellard | #include "hw/m48t59.h" |
1322 | 64201201 | bellard | |
1323 | 64201201 | bellard | void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
|
1324 | 64201201 | bellard | uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr); |
1325 | 64201201 | bellard | void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
|
1326 | 64201201 | bellard | uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr); |
1327 | 64201201 | bellard | void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
|
1328 | 64201201 | bellard | uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr); |
1329 | 64201201 | bellard | void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
|
1330 | 64201201 | bellard | const unsigned char *str, uint32_t max); |
1331 | 64201201 | bellard | int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max); |
1332 | 64201201 | bellard | void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
|
1333 | 64201201 | bellard | uint32_t start, uint32_t count); |
1334 | 64201201 | bellard | int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
|
1335 | 64201201 | bellard | const unsigned char *arch, |
1336 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
1337 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
1338 | 28b9b5af | bellard | const char *cmdline, |
1339 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
1340 | 28b9b5af | bellard | uint32_t NVRAM_image, |
1341 | 28b9b5af | bellard | int width, int height, int depth); |
1342 | 64201201 | bellard | |
1343 | 63066f4f | bellard | /* adb.c */
|
1344 | 63066f4f | bellard | |
1345 | 63066f4f | bellard | #define MAX_ADB_DEVICES 16 |
1346 | 63066f4f | bellard | |
1347 | e2733d20 | bellard | #define ADB_MAX_OUT_LEN 16 |
1348 | 63066f4f | bellard | |
1349 | e2733d20 | bellard | typedef struct ADBDevice ADBDevice; |
1350 | 63066f4f | bellard | |
1351 | e2733d20 | bellard | /* buf = NULL means polling */
|
1352 | e2733d20 | bellard | typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out, |
1353 | e2733d20 | bellard | const uint8_t *buf, int len); |
1354 | 12c28fed | bellard | typedef int ADBDeviceReset(ADBDevice *d); |
1355 | 12c28fed | bellard | |
1356 | 63066f4f | bellard | struct ADBDevice {
|
1357 | 63066f4f | bellard | struct ADBBusState *bus;
|
1358 | 63066f4f | bellard | int devaddr;
|
1359 | 63066f4f | bellard | int handler;
|
1360 | e2733d20 | bellard | ADBDeviceRequest *devreq; |
1361 | 12c28fed | bellard | ADBDeviceReset *devreset; |
1362 | 63066f4f | bellard | void *opaque;
|
1363 | 63066f4f | bellard | }; |
1364 | 63066f4f | bellard | |
1365 | 63066f4f | bellard | typedef struct ADBBusState { |
1366 | 63066f4f | bellard | ADBDevice devices[MAX_ADB_DEVICES]; |
1367 | 63066f4f | bellard | int nb_devices;
|
1368 | e2733d20 | bellard | int poll_index;
|
1369 | 63066f4f | bellard | } ADBBusState; |
1370 | 63066f4f | bellard | |
1371 | e2733d20 | bellard | int adb_request(ADBBusState *s, uint8_t *buf_out,
|
1372 | e2733d20 | bellard | const uint8_t *buf, int len); |
1373 | e2733d20 | bellard | int adb_poll(ADBBusState *s, uint8_t *buf_out);
|
1374 | 63066f4f | bellard | |
1375 | 5fafdf24 | ths | ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
|
1376 | 5fafdf24 | ths | ADBDeviceRequest *devreq, |
1377 | 5fafdf24 | ths | ADBDeviceReset *devreset, |
1378 | 63066f4f | bellard | void *opaque);
|
1379 | 63066f4f | bellard | void adb_kbd_init(ADBBusState *bus);
|
1380 | 63066f4f | bellard | void adb_mouse_init(ADBBusState *bus);
|
1381 | 63066f4f | bellard | |
1382 | 63066f4f | bellard | /* cuda.c */
|
1383 | 63066f4f | bellard | |
1384 | 63066f4f | bellard | extern ADBBusState adb_bus;
|
1385 | d537cf6c | pbrook | int cuda_init(qemu_irq irq);
|
1386 | 63066f4f | bellard | |
1387 | bb36d470 | bellard | #include "hw/usb.h" |
1388 | bb36d470 | bellard | |
1389 | a594cfbf | bellard | /* usb ports of the VM */
|
1390 | a594cfbf | bellard | |
1391 | 0d92ed30 | pbrook | void qemu_register_usb_port(USBPort *port, void *opaque, int index, |
1392 | 0d92ed30 | pbrook | usb_attachfn attach); |
1393 | a594cfbf | bellard | |
1394 | 0d92ed30 | pbrook | #define VM_USB_HUB_SIZE 8 |
1395 | a594cfbf | bellard | |
1396 | a594cfbf | bellard | void do_usb_add(const char *devname); |
1397 | a594cfbf | bellard | void do_usb_del(const char *devname); |
1398 | a594cfbf | bellard | void usb_info(void); |
1399 | a594cfbf | bellard | |
1400 | 2e5d83bb | pbrook | /* scsi-disk.c */
|
1401 | 4d611c9a | pbrook | enum scsi_reason {
|
1402 | 4d611c9a | pbrook | SCSI_REASON_DONE, /* Command complete. */
|
1403 | 4d611c9a | pbrook | SCSI_REASON_DATA /* Transfer complete, more data required. */
|
1404 | 4d611c9a | pbrook | }; |
1405 | 4d611c9a | pbrook | |
1406 | 2e5d83bb | pbrook | typedef struct SCSIDevice SCSIDevice; |
1407 | a917d384 | pbrook | typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag, |
1408 | a917d384 | pbrook | uint32_t arg); |
1409 | 2e5d83bb | pbrook | |
1410 | 2e5d83bb | pbrook | SCSIDevice *scsi_disk_init(BlockDriverState *bdrv, |
1411 | a917d384 | pbrook | int tcq,
|
1412 | 2e5d83bb | pbrook | scsi_completionfn completion, |
1413 | 2e5d83bb | pbrook | void *opaque);
|
1414 | 2e5d83bb | pbrook | void scsi_disk_destroy(SCSIDevice *s);
|
1415 | 2e5d83bb | pbrook | |
1416 | 0fc5c15a | pbrook | int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
|
1417 | 4d611c9a | pbrook | /* SCSI data transfers are asynchrnonous. However, unlike the block IO
|
1418 | 4d611c9a | pbrook | layer the completion routine may be called directly by
|
1419 | 4d611c9a | pbrook | scsi_{read,write}_data. */
|
1420 | a917d384 | pbrook | void scsi_read_data(SCSIDevice *s, uint32_t tag);
|
1421 | a917d384 | pbrook | int scsi_write_data(SCSIDevice *s, uint32_t tag);
|
1422 | a917d384 | pbrook | void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
|
1423 | a917d384 | pbrook | uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag); |
1424 | 2e5d83bb | pbrook | |
1425 | 7d8406be | pbrook | /* lsi53c895a.c */
|
1426 | 7d8406be | pbrook | void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
1427 | 7d8406be | pbrook | void *lsi_scsi_init(PCIBus *bus, int devfn); |
1428 | 7d8406be | pbrook | |
1429 | b5ff1b31 | bellard | /* integratorcp.c */
|
1430 | 3371d272 | pbrook | extern QEMUMachine integratorcp_machine;
|
1431 | b5ff1b31 | bellard | |
1432 | cdbdb648 | pbrook | /* versatilepb.c */
|
1433 | cdbdb648 | pbrook | extern QEMUMachine versatilepb_machine;
|
1434 | 16406950 | pbrook | extern QEMUMachine versatileab_machine;
|
1435 | cdbdb648 | pbrook | |
1436 | e69954b9 | pbrook | /* realview.c */
|
1437 | e69954b9 | pbrook | extern QEMUMachine realview_machine;
|
1438 | e69954b9 | pbrook | |
1439 | b00052e4 | balrog | /* spitz.c */
|
1440 | b00052e4 | balrog | extern QEMUMachine akitapda_machine;
|
1441 | b00052e4 | balrog | extern QEMUMachine spitzpda_machine;
|
1442 | b00052e4 | balrog | extern QEMUMachine borzoipda_machine;
|
1443 | b00052e4 | balrog | extern QEMUMachine terrierpda_machine;
|
1444 | b00052e4 | balrog | |
1445 | c3d2689d | balrog | /* palm.c */
|
1446 | c3d2689d | balrog | extern QEMUMachine palmte_machine;
|
1447 | c3d2689d | balrog | |
1448 | daa57963 | bellard | /* ps2.c */
|
1449 | daa57963 | bellard | void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg); |
1450 | daa57963 | bellard | void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg); |
1451 | daa57963 | bellard | void ps2_write_mouse(void *, int val); |
1452 | daa57963 | bellard | void ps2_write_keyboard(void *, int val); |
1453 | daa57963 | bellard | uint32_t ps2_read_data(void *);
|
1454 | daa57963 | bellard | void ps2_queue(void *, int b); |
1455 | f94f5d71 | pbrook | void ps2_keyboard_set_translation(void *opaque, int mode); |
1456 | 548df2ac | ths | void ps2_mouse_fake_event(void *opaque); |
1457 | daa57963 | bellard | |
1458 | 80337b66 | bellard | /* smc91c111.c */
|
1459 | d537cf6c | pbrook | void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
|
1460 | 80337b66 | bellard | |
1461 | 7e1543c2 | pbrook | /* pl031.c */
|
1462 | 7e1543c2 | pbrook | void pl031_init(uint32_t base, qemu_irq irq);
|
1463 | 7e1543c2 | pbrook | |
1464 | bdd5003a | pbrook | /* pl110.c */
|
1465 | d537cf6c | pbrook | void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int); |
1466 | bdd5003a | pbrook | |
1467 | cdbdb648 | pbrook | /* pl011.c */
|
1468 | d537cf6c | pbrook | void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
|
1469 | cdbdb648 | pbrook | |
1470 | cdbdb648 | pbrook | /* pl050.c */
|
1471 | d537cf6c | pbrook | void pl050_init(uint32_t base, qemu_irq irq, int is_mouse); |
1472 | cdbdb648 | pbrook | |
1473 | cdbdb648 | pbrook | /* pl080.c */
|
1474 | d537cf6c | pbrook | void *pl080_init(uint32_t base, qemu_irq irq, int nchannels); |
1475 | cdbdb648 | pbrook | |
1476 | a1bb27b1 | pbrook | /* pl181.c */
|
1477 | a1bb27b1 | pbrook | void pl181_init(uint32_t base, BlockDriverState *bd,
|
1478 | d537cf6c | pbrook | qemu_irq irq0, qemu_irq irq1); |
1479 | a1bb27b1 | pbrook | |
1480 | cdbdb648 | pbrook | /* pl190.c */
|
1481 | d537cf6c | pbrook | qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq); |
1482 | cdbdb648 | pbrook | |
1483 | cdbdb648 | pbrook | /* arm-timer.c */
|
1484 | d537cf6c | pbrook | void sp804_init(uint32_t base, qemu_irq irq);
|
1485 | d537cf6c | pbrook | void icp_pit_init(uint32_t base, qemu_irq *pic, int irq); |
1486 | cdbdb648 | pbrook | |
1487 | e69954b9 | pbrook | /* arm_sysctl.c */
|
1488 | e69954b9 | pbrook | void arm_sysctl_init(uint32_t base, uint32_t sys_id);
|
1489 | e69954b9 | pbrook | |
1490 | e69954b9 | pbrook | /* arm_gic.c */
|
1491 | d537cf6c | pbrook | qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq); |
1492 | e69954b9 | pbrook | |
1493 | 16406950 | pbrook | /* arm_boot.c */
|
1494 | 16406950 | pbrook | |
1495 | daf90626 | pbrook | void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename, |
1496 | 16406950 | pbrook | const char *kernel_cmdline, const char *initrd_filename, |
1497 | 9d551997 | balrog | int board_id, target_phys_addr_t loader_start);
|
1498 | 16406950 | pbrook | |
1499 | 27c7ca7e | bellard | /* sh7750.c */
|
1500 | 27c7ca7e | bellard | struct SH7750State;
|
1501 | 27c7ca7e | bellard | |
1502 | 008a8818 | pbrook | struct SH7750State *sh7750_init(CPUState * cpu);
|
1503 | 27c7ca7e | bellard | |
1504 | 27c7ca7e | bellard | typedef struct { |
1505 | 27c7ca7e | bellard | /* The callback will be triggered if any of the designated lines change */
|
1506 | 27c7ca7e | bellard | uint16_t portamask_trigger; |
1507 | 27c7ca7e | bellard | uint16_t portbmask_trigger; |
1508 | 27c7ca7e | bellard | /* Return 0 if no action was taken */
|
1509 | 27c7ca7e | bellard | int (*port_change_cb) (uint16_t porta, uint16_t portb,
|
1510 | 27c7ca7e | bellard | uint16_t * periph_pdtra, |
1511 | 27c7ca7e | bellard | uint16_t * periph_portdira, |
1512 | 27c7ca7e | bellard | uint16_t * periph_pdtrb, |
1513 | 27c7ca7e | bellard | uint16_t * periph_portdirb); |
1514 | 27c7ca7e | bellard | } sh7750_io_device; |
1515 | 27c7ca7e | bellard | |
1516 | 27c7ca7e | bellard | int sh7750_register_io_device(struct SH7750State *s, |
1517 | 27c7ca7e | bellard | sh7750_io_device * device); |
1518 | cd1a3f68 | ths | /* sh_timer.c */
|
1519 | cd1a3f68 | ths | #define TMU012_FEAT_TOCR (1 << 0) |
1520 | cd1a3f68 | ths | #define TMU012_FEAT_3CHAN (1 << 1) |
1521 | cd1a3f68 | ths | #define TMU012_FEAT_EXTCLK (1 << 2) |
1522 | cd1a3f68 | ths | void tmu012_init(uint32_t base, int feat, uint32_t freq); |
1523 | cd1a3f68 | ths | |
1524 | 2f062c72 | ths | /* sh_serial.c */
|
1525 | 2f062c72 | ths | #define SH_SERIAL_FEAT_SCIF (1 << 0) |
1526 | 2f062c72 | ths | void sh_serial_init (target_phys_addr_t base, int feat, |
1527 | 2f062c72 | ths | uint32_t freq, CharDriverState *chr); |
1528 | 2f062c72 | ths | |
1529 | 27c7ca7e | bellard | /* tc58128.c */
|
1530 | 27c7ca7e | bellard | int tc58128_init(struct SH7750State *s, char *zone1, char *zone2); |
1531 | 27c7ca7e | bellard | |
1532 | 29133e9a | bellard | /* NOR flash devices */
|
1533 | 86f55663 | j_mayer | #define MAX_PFLASH 4 |
1534 | 86f55663 | j_mayer | extern BlockDriverState *pflash_table[MAX_PFLASH];
|
1535 | 29133e9a | bellard | typedef struct pflash_t pflash_t; |
1536 | 29133e9a | bellard | |
1537 | 71db710f | blueswir1 | pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, |
1538 | 29133e9a | bellard | BlockDriverState *bs, |
1539 | 71db710f | blueswir1 | uint32_t sector_len, int nb_blocs, int width, |
1540 | 5fafdf24 | ths | uint16_t id0, uint16_t id1, |
1541 | 29133e9a | bellard | uint16_t id2, uint16_t id3); |
1542 | 29133e9a | bellard | |
1543 | 3e3d5815 | balrog | /* nand.c */
|
1544 | 3e3d5815 | balrog | struct nand_flash_s;
|
1545 | 3e3d5815 | balrog | struct nand_flash_s *nand_init(int manf_id, int chip_id); |
1546 | 3e3d5815 | balrog | void nand_done(struct nand_flash_s *s); |
1547 | 5fafdf24 | ths | void nand_setpins(struct nand_flash_s *s, |
1548 | 3e3d5815 | balrog | int cle, int ale, int ce, int wp, int gnd); |
1549 | 3e3d5815 | balrog | void nand_getpins(struct nand_flash_s *s, int *rb); |
1550 | 3e3d5815 | balrog | void nand_setio(struct nand_flash_s *s, uint8_t value); |
1551 | 3e3d5815 | balrog | uint8_t nand_getio(struct nand_flash_s *s);
|
1552 | 3e3d5815 | balrog | |
1553 | 3e3d5815 | balrog | #define NAND_MFR_TOSHIBA 0x98 |
1554 | 3e3d5815 | balrog | #define NAND_MFR_SAMSUNG 0xec |
1555 | 3e3d5815 | balrog | #define NAND_MFR_FUJITSU 0x04 |
1556 | 3e3d5815 | balrog | #define NAND_MFR_NATIONAL 0x8f |
1557 | 3e3d5815 | balrog | #define NAND_MFR_RENESAS 0x07 |
1558 | 3e3d5815 | balrog | #define NAND_MFR_STMICRO 0x20 |
1559 | 3e3d5815 | balrog | #define NAND_MFR_HYNIX 0xad |
1560 | 3e3d5815 | balrog | #define NAND_MFR_MICRON 0x2c |
1561 | 3e3d5815 | balrog | |
1562 | 9ff6755b | balrog | /* ecc.c */
|
1563 | 9ff6755b | balrog | struct ecc_state_s {
|
1564 | 9ff6755b | balrog | uint8_t cp; /* Column parity */
|
1565 | 9ff6755b | balrog | uint16_t lp[2]; /* Line parity */ |
1566 | 9ff6755b | balrog | uint16_t count; |
1567 | 9ff6755b | balrog | }; |
1568 | 9ff6755b | balrog | |
1569 | 9ff6755b | balrog | uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
|
1570 | 9ff6755b | balrog | void ecc_reset(struct ecc_state_s *s); |
1571 | 9ff6755b | balrog | void ecc_put(QEMUFile *f, struct ecc_state_s *s); |
1572 | 9ff6755b | balrog | void ecc_get(QEMUFile *f, struct ecc_state_s *s); |
1573 | 3e3d5815 | balrog | |
1574 | 2a1d1880 | balrog | /* GPIO */
|
1575 | 2a1d1880 | balrog | typedef void (*gpio_handler_t)(int line, int level, void *opaque); |
1576 | 2a1d1880 | balrog | |
1577 | fd5a3b33 | balrog | /* ads7846.c */
|
1578 | fd5a3b33 | balrog | struct ads7846_state_s;
|
1579 | fd5a3b33 | balrog | uint32_t ads7846_read(void *opaque);
|
1580 | fd5a3b33 | balrog | void ads7846_write(void *opaque, uint32_t value); |
1581 | fd5a3b33 | balrog | struct ads7846_state_s *ads7846_init(qemu_irq penirq);
|
1582 | fd5a3b33 | balrog | |
1583 | c824cacd | balrog | /* max111x.c */
|
1584 | c824cacd | balrog | struct max111x_s;
|
1585 | c824cacd | balrog | uint32_t max111x_read(void *opaque);
|
1586 | c824cacd | balrog | void max111x_write(void *opaque, uint32_t value); |
1587 | c824cacd | balrog | struct max111x_s *max1110_init(qemu_irq cb);
|
1588 | c824cacd | balrog | struct max111x_s *max1111_init(qemu_irq cb);
|
1589 | c824cacd | balrog | void max111x_set_input(struct max111x_s *s, int line, uint8_t value); |
1590 | c824cacd | balrog | |
1591 | 201a51fc | balrog | /* PCMCIA/Cardbus */
|
1592 | 201a51fc | balrog | |
1593 | 201a51fc | balrog | struct pcmcia_socket_s {
|
1594 | 201a51fc | balrog | qemu_irq irq; |
1595 | 201a51fc | balrog | int attached;
|
1596 | 201a51fc | balrog | const char *slot_string; |
1597 | 201a51fc | balrog | const char *card_string; |
1598 | 201a51fc | balrog | }; |
1599 | 201a51fc | balrog | |
1600 | 201a51fc | balrog | void pcmcia_socket_register(struct pcmcia_socket_s *socket); |
1601 | 201a51fc | balrog | void pcmcia_socket_unregister(struct pcmcia_socket_s *socket); |
1602 | 201a51fc | balrog | void pcmcia_info(void); |
1603 | 201a51fc | balrog | |
1604 | 201a51fc | balrog | struct pcmcia_card_s {
|
1605 | 201a51fc | balrog | void *state;
|
1606 | 201a51fc | balrog | struct pcmcia_socket_s *slot;
|
1607 | 201a51fc | balrog | int (*attach)(void *state); |
1608 | 201a51fc | balrog | int (*detach)(void *state); |
1609 | 201a51fc | balrog | const uint8_t *cis;
|
1610 | 201a51fc | balrog | int cis_len;
|
1611 | 201a51fc | balrog | |
1612 | 201a51fc | balrog | /* Only valid if attached */
|
1613 | 9e315fa9 | balrog | uint8_t (*attr_read)(void *state, uint32_t address);
|
1614 | 9e315fa9 | balrog | void (*attr_write)(void *state, uint32_t address, uint8_t value); |
1615 | 9e315fa9 | balrog | uint16_t (*common_read)(void *state, uint32_t address);
|
1616 | 9e315fa9 | balrog | void (*common_write)(void *state, uint32_t address, uint16_t value); |
1617 | 9e315fa9 | balrog | uint16_t (*io_read)(void *state, uint32_t address);
|
1618 | 9e315fa9 | balrog | void (*io_write)(void *state, uint32_t address, uint16_t value); |
1619 | 201a51fc | balrog | }; |
1620 | 201a51fc | balrog | |
1621 | 201a51fc | balrog | #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */ |
1622 | 201a51fc | balrog | #define CISTPL_NO_LINK 0x14 /* No Link Tuple */ |
1623 | 201a51fc | balrog | #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */ |
1624 | 201a51fc | balrog | #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */ |
1625 | 201a51fc | balrog | #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */ |
1626 | 201a51fc | balrog | #define CISTPL_CONFIG 0x1a /* Configuration Tuple */ |
1627 | 201a51fc | balrog | #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */ |
1628 | 201a51fc | balrog | #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */ |
1629 | 201a51fc | balrog | #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */ |
1630 | 201a51fc | balrog | #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */ |
1631 | 201a51fc | balrog | #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */ |
1632 | 201a51fc | balrog | #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */ |
1633 | 201a51fc | balrog | #define CISTPL_FUNCID 0x21 /* Function ID Tuple */ |
1634 | 201a51fc | balrog | #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */ |
1635 | 201a51fc | balrog | #define CISTPL_END 0xff /* Tuple End */ |
1636 | 201a51fc | balrog | #define CISTPL_ENDMARK 0xff |
1637 | 201a51fc | balrog | |
1638 | 201a51fc | balrog | /* dscm1xxxx.c */
|
1639 | 201a51fc | balrog | struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
|
1640 | 201a51fc | balrog | |
1641 | 6963d7af | pbrook | /* ptimer.c */
|
1642 | 6963d7af | pbrook | typedef struct ptimer_state ptimer_state; |
1643 | 6963d7af | pbrook | typedef void (*ptimer_cb)(void *opaque); |
1644 | 6963d7af | pbrook | |
1645 | 6963d7af | pbrook | ptimer_state *ptimer_init(QEMUBH *bh); |
1646 | 6963d7af | pbrook | void ptimer_set_period(ptimer_state *s, int64_t period);
|
1647 | 6963d7af | pbrook | void ptimer_set_freq(ptimer_state *s, uint32_t freq);
|
1648 | 8d05ea8a | blueswir1 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); |
1649 | 8d05ea8a | blueswir1 | uint64_t ptimer_get_count(ptimer_state *s); |
1650 | 8d05ea8a | blueswir1 | void ptimer_set_count(ptimer_state *s, uint64_t count);
|
1651 | 6963d7af | pbrook | void ptimer_run(ptimer_state *s, int oneshot); |
1652 | 6963d7af | pbrook | void ptimer_stop(ptimer_state *s);
|
1653 | 8d05ea8a | blueswir1 | void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
|
1654 | 8d05ea8a | blueswir1 | void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
|
1655 | 6963d7af | pbrook | |
1656 | c1713132 | balrog | #include "hw/pxa.h" |
1657 | c1713132 | balrog | |
1658 | c3d2689d | balrog | #include "hw/omap.h" |
1659 | c3d2689d | balrog | |
1660 | 20dcee94 | pbrook | /* mcf_uart.c */
|
1661 | 20dcee94 | pbrook | uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
|
1662 | 20dcee94 | pbrook | void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val); |
1663 | 20dcee94 | pbrook | void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
|
1664 | 20dcee94 | pbrook | void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
|
1665 | 20dcee94 | pbrook | CharDriverState *chr); |
1666 | 20dcee94 | pbrook | |
1667 | 20dcee94 | pbrook | /* mcf_intc.c */
|
1668 | 20dcee94 | pbrook | qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env); |
1669 | 20dcee94 | pbrook | |
1670 | 7e049b8a | pbrook | /* mcf_fec.c */
|
1671 | 7e049b8a | pbrook | void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
|
1672 | 7e049b8a | pbrook | |
1673 | 0633879f | pbrook | /* mcf5206.c */
|
1674 | 0633879f | pbrook | qemu_irq *mcf5206_init(uint32_t base, CPUState *env); |
1675 | 0633879f | pbrook | |
1676 | 0633879f | pbrook | /* an5206.c */
|
1677 | 0633879f | pbrook | extern QEMUMachine an5206_machine;
|
1678 | 0633879f | pbrook | |
1679 | 20dcee94 | pbrook | /* mcf5208.c */
|
1680 | 20dcee94 | pbrook | extern QEMUMachine mcf5208evb_machine;
|
1681 | 20dcee94 | pbrook | |
1682 | 4046d913 | pbrook | #include "gdbstub.h" |
1683 | 4046d913 | pbrook | |
1684 | ea2384d3 | bellard | #endif /* defined(QEMU_TOOL) */ |
1685 | ea2384d3 | bellard | |
1686 | c4b1fcc0 | bellard | /* monitor.c */
|
1687 | 82c643ff | bellard | void monitor_init(CharDriverState *hd, int show_banner); |
1688 | ea2384d3 | bellard | void term_puts(const char *str); |
1689 | ea2384d3 | bellard | void term_vprintf(const char *fmt, va_list ap); |
1690 | 40c3bac3 | bellard | void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2))); |
1691 | fef30743 | ths | void term_print_filename(const char *filename); |
1692 | c4b1fcc0 | bellard | void term_flush(void); |
1693 | c4b1fcc0 | bellard | void term_print_help(void); |
1694 | ea2384d3 | bellard | void monitor_readline(const char *prompt, int is_password, |
1695 | ea2384d3 | bellard | char *buf, int buf_size); |
1696 | ea2384d3 | bellard | |
1697 | ea2384d3 | bellard | /* readline.c */
|
1698 | ea2384d3 | bellard | typedef void ReadLineFunc(void *opaque, const char *str); |
1699 | ea2384d3 | bellard | |
1700 | ea2384d3 | bellard | extern int completion_index; |
1701 | ea2384d3 | bellard | void add_completion(const char *str); |
1702 | ea2384d3 | bellard | void readline_handle_byte(int ch); |
1703 | ea2384d3 | bellard | void readline_find_completion(const char *cmdline); |
1704 | ea2384d3 | bellard | const char *readline_get_history(unsigned int index); |
1705 | ea2384d3 | bellard | void readline_start(const char *prompt, int is_password, |
1706 | ea2384d3 | bellard | ReadLineFunc *readline_func, void *opaque);
|
1707 | c4b1fcc0 | bellard | |
1708 | 5e6ad6f9 | bellard | void kqemu_record_dump(void); |
1709 | 5e6ad6f9 | bellard | |
1710 | fc01f7e7 | bellard | #endif /* VL_H */ |