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1 | 3475187d | bellard | /*
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2 | c7ba218d | blueswir1 | * QEMU Sun4u/Sun4v System Emulator
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3 | 5fafdf24 | ths | *
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4 | 3475187d | bellard | * Copyright (c) 2005 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | 3475187d | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 3475187d | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 3475187d | bellard | * in the Software without restriction, including without limitation the rights
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9 | 3475187d | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 3475187d | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 3475187d | bellard | * furnished to do so, subject to the following conditions:
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12 | 3475187d | bellard | *
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13 | 3475187d | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 3475187d | bellard | * all copies or substantial portions of the Software.
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15 | 3475187d | bellard | *
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16 | 3475187d | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 3475187d | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 3475187d | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 3475187d | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 3475187d | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 3475187d | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 3475187d | bellard | * THE SOFTWARE.
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23 | 3475187d | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "pci.h" |
26 | 87ecb68b | pbrook | #include "pc.h" |
27 | 87ecb68b | pbrook | #include "nvram.h" |
28 | 87ecb68b | pbrook | #include "fdc.h" |
29 | 87ecb68b | pbrook | #include "net.h" |
30 | 87ecb68b | pbrook | #include "qemu-timer.h" |
31 | 87ecb68b | pbrook | #include "sysemu.h" |
32 | 87ecb68b | pbrook | #include "boards.h" |
33 | d2c63fc1 | blueswir1 | #include "firmware_abi.h" |
34 | 3cce6243 | blueswir1 | #include "fw_cfg.h" |
35 | 3475187d | bellard | |
36 | 9d926598 | blueswir1 | //#define DEBUG_IRQ
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37 | 9d926598 | blueswir1 | |
38 | 9d926598 | blueswir1 | #ifdef DEBUG_IRQ
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39 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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40 | 001faf32 | Blue Swirl | do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) |
41 | 9d926598 | blueswir1 | #else
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42 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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43 | 9d926598 | blueswir1 | #endif
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44 | 9d926598 | blueswir1 | |
45 | 83469015 | bellard | #define KERNEL_LOAD_ADDR 0x00404000 |
46 | 83469015 | bellard | #define CMDLINE_ADDR 0x003ff000 |
47 | 83469015 | bellard | #define INITRD_LOAD_ADDR 0x00300000 |
48 | ac2e9d66 | blueswir1 | #define PROM_SIZE_MAX (4 * 1024 * 1024) |
49 | f930d07e | blueswir1 | #define PROM_VADDR 0x000ffd00000ULL |
50 | 83469015 | bellard | #define APB_SPECIAL_BASE 0x1fe00000000ULL |
51 | f930d07e | blueswir1 | #define APB_MEM_BASE 0x1ff00000000ULL |
52 | f930d07e | blueswir1 | #define VGA_BASE (APB_MEM_BASE + 0x400000ULL) |
53 | f930d07e | blueswir1 | #define PROM_FILENAME "openbios-sparc64" |
54 | 83469015 | bellard | #define NVRAM_SIZE 0x2000 |
55 | e4bcb14c | ths | #define MAX_IDE_BUS 2 |
56 | 3cce6243 | blueswir1 | #define BIOS_CFG_IOPORT 0x510 |
57 | 3475187d | bellard | |
58 | 9d926598 | blueswir1 | #define MAX_PILS 16 |
59 | 9d926598 | blueswir1 | |
60 | 8fa211e8 | blueswir1 | #define TICK_INT_DIS 0x8000000000000000ULL |
61 | 8fa211e8 | blueswir1 | #define TICK_MAX 0x7fffffffffffffffULL |
62 | 8fa211e8 | blueswir1 | |
63 | c7ba218d | blueswir1 | struct hwdef {
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64 | c7ba218d | blueswir1 | const char * const default_cpu_model; |
65 | 905fdcb5 | blueswir1 | uint16_t machine_id; |
66 | e87231d4 | blueswir1 | uint64_t prom_addr; |
67 | e87231d4 | blueswir1 | uint64_t console_serial_base; |
68 | c7ba218d | blueswir1 | }; |
69 | c7ba218d | blueswir1 | |
70 | 3475187d | bellard | int DMA_get_channel_mode (int nchan) |
71 | 3475187d | bellard | { |
72 | 3475187d | bellard | return 0; |
73 | 3475187d | bellard | } |
74 | 3475187d | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size) |
75 | 3475187d | bellard | { |
76 | 3475187d | bellard | return 0; |
77 | 3475187d | bellard | } |
78 | 3475187d | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size) |
79 | 3475187d | bellard | { |
80 | 3475187d | bellard | return 0; |
81 | 3475187d | bellard | } |
82 | 3475187d | bellard | void DMA_hold_DREQ (int nchan) {} |
83 | 3475187d | bellard | void DMA_release_DREQ (int nchan) {} |
84 | 3475187d | bellard | void DMA_schedule(int nchan) {} |
85 | 3475187d | bellard | void DMA_init (int high_page_enable) {} |
86 | 3475187d | bellard | void DMA_register_channel (int nchan, |
87 | 3475187d | bellard | DMA_transfer_handler transfer_handler, |
88 | 3475187d | bellard | void *opaque)
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89 | 3475187d | bellard | { |
90 | 3475187d | bellard | } |
91 | 3475187d | bellard | |
92 | 513f789f | blueswir1 | static int fw_cfg_boot_set(void *opaque, const char *boot_device) |
93 | 81864572 | blueswir1 | { |
94 | 513f789f | blueswir1 | fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
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95 | 81864572 | blueswir1 | return 0; |
96 | 81864572 | blueswir1 | } |
97 | 81864572 | blueswir1 | |
98 | d2c63fc1 | blueswir1 | static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size, |
99 | e7fb1406 | blueswir1 | const char *arch, |
100 | 77f193da | blueswir1 | ram_addr_t RAM_size, |
101 | 77f193da | blueswir1 | const char *boot_devices, |
102 | d2c63fc1 | blueswir1 | uint32_t kernel_image, uint32_t kernel_size, |
103 | d2c63fc1 | blueswir1 | const char *cmdline, |
104 | d2c63fc1 | blueswir1 | uint32_t initrd_image, uint32_t initrd_size, |
105 | d2c63fc1 | blueswir1 | uint32_t NVRAM_image, |
106 | 0d31cb99 | blueswir1 | int width, int height, int depth, |
107 | 0d31cb99 | blueswir1 | const uint8_t *macaddr)
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108 | 83469015 | bellard | { |
109 | 66508601 | blueswir1 | unsigned int i; |
110 | 66508601 | blueswir1 | uint32_t start, end; |
111 | d2c63fc1 | blueswir1 | uint8_t image[0x1ff0];
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112 | d2c63fc1 | blueswir1 | struct OpenBIOS_nvpart_v1 *part_header;
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113 | d2c63fc1 | blueswir1 | |
114 | d2c63fc1 | blueswir1 | memset(image, '\0', sizeof(image)); |
115 | d2c63fc1 | blueswir1 | |
116 | 513f789f | blueswir1 | start = 0;
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117 | 83469015 | bellard | |
118 | 66508601 | blueswir1 | // OpenBIOS nvram variables
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119 | 66508601 | blueswir1 | // Variable partition
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120 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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121 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_SYSTEM; |
122 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "system"); |
123 | 66508601 | blueswir1 | |
124 | d2c63fc1 | blueswir1 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
125 | 66508601 | blueswir1 | for (i = 0; i < nb_prom_envs; i++) |
126 | d2c63fc1 | blueswir1 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
127 | d2c63fc1 | blueswir1 | |
128 | d2c63fc1 | blueswir1 | // End marker
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129 | d2c63fc1 | blueswir1 | image[end++] = '\0';
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130 | 66508601 | blueswir1 | |
131 | 66508601 | blueswir1 | end = start + ((end - start + 15) & ~15); |
132 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
133 | 66508601 | blueswir1 | |
134 | 66508601 | blueswir1 | // free partition
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135 | 66508601 | blueswir1 | start = end; |
136 | d2c63fc1 | blueswir1 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
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137 | d2c63fc1 | blueswir1 | part_header->signature = OPENBIOS_PART_FREE; |
138 | 363a37d5 | blueswir1 | pstrcpy(part_header->name, sizeof(part_header->name), "free"); |
139 | 66508601 | blueswir1 | |
140 | 66508601 | blueswir1 | end = 0x1fd0;
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141 | d2c63fc1 | blueswir1 | OpenBIOS_finish_partition(part_header, end - start); |
142 | d2c63fc1 | blueswir1 | |
143 | 0d31cb99 | blueswir1 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80); |
144 | 0d31cb99 | blueswir1 | |
145 | d2c63fc1 | blueswir1 | for (i = 0; i < sizeof(image); i++) |
146 | d2c63fc1 | blueswir1 | m48t59_write(nvram, i, image[i]); |
147 | 66508601 | blueswir1 | |
148 | 83469015 | bellard | return 0; |
149 | 3475187d | bellard | } |
150 | 3475187d | bellard | |
151 | b4950060 | blueswir1 | void pic_info(Monitor *mon)
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152 | 3475187d | bellard | { |
153 | 3475187d | bellard | } |
154 | 3475187d | bellard | |
155 | b4950060 | blueswir1 | void irq_info(Monitor *mon)
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156 | 3475187d | bellard | { |
157 | 3475187d | bellard | } |
158 | 3475187d | bellard | |
159 | 9d926598 | blueswir1 | void cpu_check_irqs(CPUState *env)
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160 | 9d926598 | blueswir1 | { |
161 | 9d926598 | blueswir1 | uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) | |
162 | 9d926598 | blueswir1 | ((env->softint & SOFTINT_TIMER) << 14);
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163 | 9d926598 | blueswir1 | |
164 | 9d926598 | blueswir1 | if (pil && (env->interrupt_index == 0 || |
165 | 9d926598 | blueswir1 | (env->interrupt_index & ~15) == TT_EXTINT)) {
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166 | 9d926598 | blueswir1 | unsigned int i; |
167 | 9d926598 | blueswir1 | |
168 | 9d926598 | blueswir1 | for (i = 15; i > 0; i--) { |
169 | 9d926598 | blueswir1 | if (pil & (1 << i)) { |
170 | 9d926598 | blueswir1 | int old_interrupt = env->interrupt_index;
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171 | 9d926598 | blueswir1 | |
172 | 9d926598 | blueswir1 | env->interrupt_index = TT_EXTINT | i; |
173 | 9d926598 | blueswir1 | if (old_interrupt != env->interrupt_index) {
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174 | 9d926598 | blueswir1 | DPRINTF("Set CPU IRQ %d\n", i);
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175 | 9d926598 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
176 | 9d926598 | blueswir1 | } |
177 | 9d926598 | blueswir1 | break;
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178 | 9d926598 | blueswir1 | } |
179 | 9d926598 | blueswir1 | } |
180 | 9d926598 | blueswir1 | } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) { |
181 | 9d926598 | blueswir1 | DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15); |
182 | 9d926598 | blueswir1 | env->interrupt_index = 0;
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183 | 9d926598 | blueswir1 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
184 | 9d926598 | blueswir1 | } |
185 | 9d926598 | blueswir1 | } |
186 | 9d926598 | blueswir1 | |
187 | 9d926598 | blueswir1 | static void cpu_set_irq(void *opaque, int irq, int level) |
188 | 9d926598 | blueswir1 | { |
189 | 9d926598 | blueswir1 | CPUState *env = opaque; |
190 | 9d926598 | blueswir1 | |
191 | 9d926598 | blueswir1 | if (level) {
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192 | 9d926598 | blueswir1 | DPRINTF("Raise CPU IRQ %d\n", irq);
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193 | 9d926598 | blueswir1 | env->halted = 0;
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194 | 9d926598 | blueswir1 | env->pil_in |= 1 << irq;
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195 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
196 | 9d926598 | blueswir1 | } else {
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197 | 9d926598 | blueswir1 | DPRINTF("Lower CPU IRQ %d\n", irq);
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198 | 9d926598 | blueswir1 | env->pil_in &= ~(1 << irq);
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199 | 9d926598 | blueswir1 | cpu_check_irqs(env); |
200 | 9d926598 | blueswir1 | } |
201 | 9d926598 | blueswir1 | } |
202 | 9d926598 | blueswir1 | |
203 | 83469015 | bellard | void qemu_system_powerdown(void) |
204 | 3475187d | bellard | { |
205 | 3475187d | bellard | } |
206 | 3475187d | bellard | |
207 | e87231d4 | blueswir1 | typedef struct ResetData { |
208 | e87231d4 | blueswir1 | CPUState *env; |
209 | e87231d4 | blueswir1 | uint64_t reset_addr; |
210 | e87231d4 | blueswir1 | } ResetData; |
211 | e87231d4 | blueswir1 | |
212 | c68ea704 | bellard | static void main_cpu_reset(void *opaque) |
213 | c68ea704 | bellard | { |
214 | e87231d4 | blueswir1 | ResetData *s = (ResetData *)opaque; |
215 | e87231d4 | blueswir1 | CPUState *env = s->env; |
216 | 20c9f095 | blueswir1 | |
217 | c68ea704 | bellard | cpu_reset(env); |
218 | 8fa211e8 | blueswir1 | env->tick_cmpr = TICK_INT_DIS | 0;
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219 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->tick, TICK_MAX, 1);
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220 | 2f43e00e | blueswir1 | ptimer_run(env->tick, 1);
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221 | 8fa211e8 | blueswir1 | env->stick_cmpr = TICK_INT_DIS | 0;
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222 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->stick, TICK_MAX, 1);
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223 | 2f43e00e | blueswir1 | ptimer_run(env->stick, 1);
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224 | 8fa211e8 | blueswir1 | env->hstick_cmpr = TICK_INT_DIS | 0;
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225 | 8fa211e8 | blueswir1 | ptimer_set_limit(env->hstick, TICK_MAX, 1);
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226 | 2f43e00e | blueswir1 | ptimer_run(env->hstick, 1);
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227 | e87231d4 | blueswir1 | env->gregs[1] = 0; // Memory start |
228 | e87231d4 | blueswir1 | env->gregs[2] = ram_size; // Memory size |
229 | e87231d4 | blueswir1 | env->gregs[3] = 0; // Machine description XXX |
230 | e87231d4 | blueswir1 | env->pc = s->reset_addr; |
231 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
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232 | 20c9f095 | blueswir1 | } |
233 | 20c9f095 | blueswir1 | |
234 | 22548760 | blueswir1 | static void tick_irq(void *opaque) |
235 | 20c9f095 | blueswir1 | { |
236 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
237 | 20c9f095 | blueswir1 | |
238 | 8fa211e8 | blueswir1 | if (!(env->tick_cmpr & TICK_INT_DIS)) {
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239 | 8fa211e8 | blueswir1 | env->softint |= SOFTINT_TIMER; |
240 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
241 | 8fa211e8 | blueswir1 | } |
242 | 20c9f095 | blueswir1 | } |
243 | 20c9f095 | blueswir1 | |
244 | 22548760 | blueswir1 | static void stick_irq(void *opaque) |
245 | 20c9f095 | blueswir1 | { |
246 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
247 | 20c9f095 | blueswir1 | |
248 | 8fa211e8 | blueswir1 | if (!(env->stick_cmpr & TICK_INT_DIS)) {
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249 | 8fa211e8 | blueswir1 | env->softint |= SOFTINT_STIMER; |
250 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
251 | 8fa211e8 | blueswir1 | } |
252 | 20c9f095 | blueswir1 | } |
253 | 20c9f095 | blueswir1 | |
254 | 22548760 | blueswir1 | static void hstick_irq(void *opaque) |
255 | 20c9f095 | blueswir1 | { |
256 | 20c9f095 | blueswir1 | CPUState *env = opaque; |
257 | 20c9f095 | blueswir1 | |
258 | 8fa211e8 | blueswir1 | if (!(env->hstick_cmpr & TICK_INT_DIS)) {
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259 | 8fa211e8 | blueswir1 | cpu_interrupt(env, CPU_INTERRUPT_TIMER); |
260 | 8fa211e8 | blueswir1 | } |
261 | c68ea704 | bellard | } |
262 | c68ea704 | bellard | |
263 | f4b1a842 | blueswir1 | void cpu_tick_set_count(void *opaque, uint64_t count) |
264 | f4b1a842 | blueswir1 | { |
265 | f4b1a842 | blueswir1 | ptimer_set_count(opaque, -count); |
266 | f4b1a842 | blueswir1 | } |
267 | f4b1a842 | blueswir1 | |
268 | f4b1a842 | blueswir1 | uint64_t cpu_tick_get_count(void *opaque)
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269 | f4b1a842 | blueswir1 | { |
270 | f4b1a842 | blueswir1 | return -ptimer_get_count(opaque);
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271 | f4b1a842 | blueswir1 | } |
272 | f4b1a842 | blueswir1 | |
273 | f4b1a842 | blueswir1 | void cpu_tick_set_limit(void *opaque, uint64_t limit) |
274 | f4b1a842 | blueswir1 | { |
275 | f4b1a842 | blueswir1 | ptimer_set_limit(opaque, -limit, 0);
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276 | f4b1a842 | blueswir1 | } |
277 | f4b1a842 | blueswir1 | |
278 | 83469015 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
279 | 83469015 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
280 | 83469015 | bellard | static const int ide_irq[2] = { 14, 15 }; |
281 | 3475187d | bellard | |
282 | 83469015 | bellard | static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 }; |
283 | 83469015 | bellard | static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 }; |
284 | 83469015 | bellard | |
285 | 83469015 | bellard | static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc }; |
286 | 83469015 | bellard | static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 }; |
287 | 83469015 | bellard | |
288 | 83469015 | bellard | static fdctrl_t *floppy_controller;
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289 | 3475187d | bellard | |
290 | c190ea07 | blueswir1 | static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num, |
291 | c190ea07 | blueswir1 | uint32_t addr, uint32_t size, int type)
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292 | c190ea07 | blueswir1 | { |
293 | c190ea07 | blueswir1 | DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
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294 | c190ea07 | blueswir1 | switch (region_num) {
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295 | c190ea07 | blueswir1 | case 0: |
296 | c190ea07 | blueswir1 | isa_mmio_init(addr, 0x1000000);
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297 | c190ea07 | blueswir1 | break;
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298 | c190ea07 | blueswir1 | case 1: |
299 | c190ea07 | blueswir1 | isa_mmio_init(addr, 0x800000);
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300 | c190ea07 | blueswir1 | break;
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301 | c190ea07 | blueswir1 | } |
302 | c190ea07 | blueswir1 | } |
303 | c190ea07 | blueswir1 | |
304 | c190ea07 | blueswir1 | /* EBUS (Eight bit bus) bridge */
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305 | c190ea07 | blueswir1 | static void |
306 | c190ea07 | blueswir1 | pci_ebus_init(PCIBus *bus, int devfn)
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307 | c190ea07 | blueswir1 | { |
308 | c190ea07 | blueswir1 | PCIDevice *s; |
309 | c190ea07 | blueswir1 | |
310 | c190ea07 | blueswir1 | s = pci_register_device(bus, "EBUS", sizeof(*s), devfn, NULL, NULL); |
311 | deb54399 | aliguori | pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN); |
312 | deb54399 | aliguori | pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS); |
313 | c190ea07 | blueswir1 | s->config[0x04] = 0x06; // command = bus master, pci mem |
314 | c190ea07 | blueswir1 | s->config[0x05] = 0x00; |
315 | c190ea07 | blueswir1 | s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
316 | c190ea07 | blueswir1 | s->config[0x07] = 0x03; // status = medium devsel |
317 | c190ea07 | blueswir1 | s->config[0x08] = 0x01; // revision |
318 | c190ea07 | blueswir1 | s->config[0x09] = 0x00; // programming i/f |
319 | 173a543b | blueswir1 | pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER); |
320 | c190ea07 | blueswir1 | s->config[0x0D] = 0x0a; // latency_timer |
321 | 6407f373 | Isaku Yamahata | s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
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322 | c190ea07 | blueswir1 | |
323 | c190ea07 | blueswir1 | pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM, |
324 | c190ea07 | blueswir1 | ebus_mmio_mapfunc); |
325 | c190ea07 | blueswir1 | pci_register_io_region(s, 1, 0x800000, PCI_ADDRESS_SPACE_MEM, |
326 | c190ea07 | blueswir1 | ebus_mmio_mapfunc); |
327 | c190ea07 | blueswir1 | } |
328 | c190ea07 | blueswir1 | |
329 | fbe1b595 | Paul Brook | static void sun4uv_init(ram_addr_t RAM_size, |
330 | 3023f332 | aliguori | const char *boot_devices, |
331 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
332 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model, |
333 | c7ba218d | blueswir1 | const struct hwdef *hwdef) |
334 | 3475187d | bellard | { |
335 | c68ea704 | bellard | CPUState *env; |
336 | 3475187d | bellard | char buf[1024]; |
337 | 83469015 | bellard | m48t59_t *nvram; |
338 | 3475187d | bellard | int ret, linux_boot;
|
339 | 3475187d | bellard | unsigned int i; |
340 | b584726d | pbrook | ram_addr_t ram_offset, prom_offset; |
341 | 5c6602c5 | blueswir1 | long initrd_size, kernel_size;
|
342 | c190ea07 | blueswir1 | PCIBus *pci_bus, *pci_bus2, *pci_bus3; |
343 | 20c9f095 | blueswir1 | QEMUBH *bh; |
344 | f19e918d | blueswir1 | qemu_irq *irq; |
345 | 22548760 | blueswir1 | int drive_index;
|
346 | e4bcb14c | ths | BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; |
347 | e4bcb14c | ths | BlockDriverState *fd[MAX_FD]; |
348 | 3cce6243 | blueswir1 | void *fw_cfg;
|
349 | e87231d4 | blueswir1 | ResetData *reset_info; |
350 | 3475187d | bellard | |
351 | 3475187d | bellard | linux_boot = (kernel_filename != NULL);
|
352 | 3475187d | bellard | |
353 | 62724a37 | blueswir1 | /* init CPUs */
|
354 | c7ba218d | blueswir1 | if (!cpu_model)
|
355 | c7ba218d | blueswir1 | cpu_model = hwdef->default_cpu_model; |
356 | c7ba218d | blueswir1 | |
357 | aaed909a | bellard | env = cpu_init(cpu_model); |
358 | aaed909a | bellard | if (!env) {
|
359 | 62724a37 | blueswir1 | fprintf(stderr, "Unable to find Sparc CPU definition\n");
|
360 | 62724a37 | blueswir1 | exit(1);
|
361 | 62724a37 | blueswir1 | } |
362 | 20c9f095 | blueswir1 | bh = qemu_bh_new(tick_irq, env); |
363 | 20c9f095 | blueswir1 | env->tick = ptimer_init(bh); |
364 | 20c9f095 | blueswir1 | ptimer_set_period(env->tick, 1ULL);
|
365 | 20c9f095 | blueswir1 | |
366 | 20c9f095 | blueswir1 | bh = qemu_bh_new(stick_irq, env); |
367 | 20c9f095 | blueswir1 | env->stick = ptimer_init(bh); |
368 | 20c9f095 | blueswir1 | ptimer_set_period(env->stick, 1ULL);
|
369 | 20c9f095 | blueswir1 | |
370 | 20c9f095 | blueswir1 | bh = qemu_bh_new(hstick_irq, env); |
371 | 20c9f095 | blueswir1 | env->hstick = ptimer_init(bh); |
372 | 20c9f095 | blueswir1 | ptimer_set_period(env->hstick, 1ULL);
|
373 | e87231d4 | blueswir1 | |
374 | e87231d4 | blueswir1 | reset_info = qemu_mallocz(sizeof(ResetData));
|
375 | e87231d4 | blueswir1 | reset_info->env = env; |
376 | e87231d4 | blueswir1 | reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
|
377 | e87231d4 | blueswir1 | qemu_register_reset(main_cpu_reset, reset_info); |
378 | e87231d4 | blueswir1 | main_cpu_reset(reset_info); |
379 | e87231d4 | blueswir1 | // Override warm reset address with cold start address
|
380 | e87231d4 | blueswir1 | env->pc = hwdef->prom_addr + 0x20ULL;
|
381 | e87231d4 | blueswir1 | env->npc = env->pc + 4;
|
382 | c68ea704 | bellard | |
383 | 3475187d | bellard | /* allocate RAM */
|
384 | 5c6602c5 | blueswir1 | ram_offset = qemu_ram_alloc(RAM_size); |
385 | 5c6602c5 | blueswir1 | cpu_register_physical_memory(0, RAM_size, ram_offset);
|
386 | 3475187d | bellard | |
387 | 5c6602c5 | blueswir1 | prom_offset = qemu_ram_alloc(PROM_SIZE_MAX); |
388 | e87231d4 | blueswir1 | cpu_register_physical_memory(hwdef->prom_addr, |
389 | 77f193da | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & |
390 | 77f193da | blueswir1 | TARGET_PAGE_MASK, |
391 | b3783731 | bellard | prom_offset | IO_MEM_ROM); |
392 | 3475187d | bellard | |
393 | 1192dad8 | j_mayer | if (bios_name == NULL) |
394 | 1192dad8 | j_mayer | bios_name = PROM_FILENAME; |
395 | 1192dad8 | j_mayer | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); |
396 | e87231d4 | blueswir1 | ret = load_elf(buf, hwdef->prom_addr - PROM_VADDR, NULL, NULL, NULL); |
397 | 3475187d | bellard | if (ret < 0) { |
398 | e87231d4 | blueswir1 | ret = load_image_targphys(buf, hwdef->prom_addr, |
399 | e87231d4 | blueswir1 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE) & |
400 | e87231d4 | blueswir1 | TARGET_PAGE_MASK); |
401 | e87231d4 | blueswir1 | if (ret < 0) { |
402 | e87231d4 | blueswir1 | fprintf(stderr, "qemu: could not load prom '%s'\n",
|
403 | e87231d4 | blueswir1 | buf); |
404 | e87231d4 | blueswir1 | exit(1);
|
405 | e87231d4 | blueswir1 | } |
406 | 3475187d | bellard | } |
407 | 3475187d | bellard | |
408 | 3475187d | bellard | kernel_size = 0;
|
409 | 83469015 | bellard | initrd_size = 0;
|
410 | 3475187d | bellard | if (linux_boot) {
|
411 | b3783731 | bellard | /* XXX: put correct offset */
|
412 | 74287114 | ths | kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL); |
413 | 3475187d | bellard | if (kernel_size < 0) |
414 | 293f78bc | blueswir1 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
415 | 293f78bc | blueswir1 | ram_size - KERNEL_LOAD_ADDR); |
416 | f930d07e | blueswir1 | if (kernel_size < 0) |
417 | 293f78bc | blueswir1 | kernel_size = load_image_targphys(kernel_filename, |
418 | 293f78bc | blueswir1 | KERNEL_LOAD_ADDR, |
419 | 293f78bc | blueswir1 | ram_size - KERNEL_LOAD_ADDR); |
420 | 3475187d | bellard | if (kernel_size < 0) { |
421 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
422 | 3475187d | bellard | kernel_filename); |
423 | f930d07e | blueswir1 | exit(1);
|
424 | 3475187d | bellard | } |
425 | 3475187d | bellard | |
426 | 3475187d | bellard | /* load initrd */
|
427 | 3475187d | bellard | if (initrd_filename) {
|
428 | 293f78bc | blueswir1 | initrd_size = load_image_targphys(initrd_filename, |
429 | 293f78bc | blueswir1 | INITRD_LOAD_ADDR, |
430 | 293f78bc | blueswir1 | ram_size - INITRD_LOAD_ADDR); |
431 | 3475187d | bellard | if (initrd_size < 0) { |
432 | 5fafdf24 | ths | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
433 | 3475187d | bellard | initrd_filename); |
434 | 3475187d | bellard | exit(1);
|
435 | 3475187d | bellard | } |
436 | 3475187d | bellard | } |
437 | 3475187d | bellard | if (initrd_size > 0) { |
438 | f930d07e | blueswir1 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
439 | 293f78bc | blueswir1 | if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS |
440 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
|
441 | 293f78bc | blueswir1 | stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
|
442 | f930d07e | blueswir1 | break;
|
443 | f930d07e | blueswir1 | } |
444 | f930d07e | blueswir1 | } |
445 | 3475187d | bellard | } |
446 | 3475187d | bellard | } |
447 | c190ea07 | blueswir1 | pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,
|
448 | c190ea07 | blueswir1 | &pci_bus3); |
449 | 83469015 | bellard | isa_mem_base = VGA_BASE; |
450 | fbe1b595 | Paul Brook | pci_vga_init(pci_bus, 0, 0); |
451 | 83469015 | bellard | |
452 | c190ea07 | blueswir1 | // XXX Should be pci_bus3
|
453 | c190ea07 | blueswir1 | pci_ebus_init(pci_bus, -1);
|
454 | c190ea07 | blueswir1 | |
455 | e87231d4 | blueswir1 | i = 0;
|
456 | e87231d4 | blueswir1 | if (hwdef->console_serial_base) {
|
457 | e87231d4 | blueswir1 | serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200, |
458 | e87231d4 | blueswir1 | serial_hds[i], 1);
|
459 | e87231d4 | blueswir1 | i++; |
460 | e87231d4 | blueswir1 | } |
461 | e87231d4 | blueswir1 | for(; i < MAX_SERIAL_PORTS; i++) {
|
462 | 83469015 | bellard | if (serial_hds[i]) {
|
463 | cbf5c748 | blueswir1 | serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200, |
464 | cbf5c748 | blueswir1 | serial_hds[i]); |
465 | 83469015 | bellard | } |
466 | 83469015 | bellard | } |
467 | 83469015 | bellard | |
468 | 83469015 | bellard | for(i = 0; i < MAX_PARALLEL_PORTS; i++) { |
469 | 83469015 | bellard | if (parallel_hds[i]) {
|
470 | 77f193da | blueswir1 | parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/, |
471 | 77f193da | blueswir1 | parallel_hds[i]); |
472 | 83469015 | bellard | } |
473 | 83469015 | bellard | } |
474 | 83469015 | bellard | |
475 | cb457d76 | aliguori | for(i = 0; i < nb_nics; i++) |
476 | cb457d76 | aliguori | pci_nic_init(pci_bus, &nd_table[i], -1, "ne2k_pci"); |
477 | 83469015 | bellard | |
478 | 9d926598 | blueswir1 | irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); |
479 | e4bcb14c | ths | if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
|
480 | e4bcb14c | ths | fprintf(stderr, "qemu: too many IDE bus\n");
|
481 | e4bcb14c | ths | exit(1);
|
482 | e4bcb14c | ths | } |
483 | e4bcb14c | ths | for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) { |
484 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS, |
485 | 22548760 | blueswir1 | i % MAX_IDE_DEVS); |
486 | 22548760 | blueswir1 | if (drive_index != -1) |
487 | 22548760 | blueswir1 | hd[i] = drives_table[drive_index].bdrv; |
488 | e4bcb14c | ths | else
|
489 | e4bcb14c | ths | hd[i] = NULL;
|
490 | e4bcb14c | ths | } |
491 | e4bcb14c | ths | |
492 | 3b898dda | blueswir1 | pci_cmd646_ide_init(pci_bus, hd, 1);
|
493 | 3b898dda | blueswir1 | |
494 | d537cf6c | pbrook | /* FIXME: wire up interrupts. */
|
495 | d537cf6c | pbrook | i8042_init(NULL/*1*/, NULL/*12*/, 0x60); |
496 | e4bcb14c | ths | for(i = 0; i < MAX_FD; i++) { |
497 | 22548760 | blueswir1 | drive_index = drive_get_index(IF_FLOPPY, 0, i);
|
498 | 22548760 | blueswir1 | if (drive_index != -1) |
499 | 22548760 | blueswir1 | fd[i] = drives_table[drive_index].bdrv; |
500 | e4bcb14c | ths | else
|
501 | e4bcb14c | ths | fd[i] = NULL;
|
502 | e4bcb14c | ths | } |
503 | e4bcb14c | ths | floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd); |
504 | d537cf6c | pbrook | nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59); |
505 | 22548760 | blueswir1 | sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
|
506 | 0d31cb99 | blueswir1 | KERNEL_LOAD_ADDR, kernel_size, |
507 | 0d31cb99 | blueswir1 | kernel_cmdline, |
508 | 0d31cb99 | blueswir1 | INITRD_LOAD_ADDR, initrd_size, |
509 | 0d31cb99 | blueswir1 | /* XXX: need an option to load a NVRAM image */
|
510 | 0d31cb99 | blueswir1 | 0,
|
511 | 0d31cb99 | blueswir1 | graphic_width, graphic_height, graphic_depth, |
512 | 0d31cb99 | blueswir1 | (uint8_t *)&nd_table[0].macaddr);
|
513 | 83469015 | bellard | |
514 | 3cce6243 | blueswir1 | fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); |
515 | 3cce6243 | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
|
516 | 905fdcb5 | blueswir1 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
517 | 905fdcb5 | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
518 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
519 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); |
520 | 513f789f | blueswir1 | if (kernel_cmdline) {
|
521 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
522 | 513f789f | blueswir1 | pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline); |
523 | 513f789f | blueswir1 | } else {
|
524 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
|
525 | 513f789f | blueswir1 | } |
526 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); |
527 | 513f789f | blueswir1 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
528 | 513f789f | blueswir1 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
|
529 | 513f789f | blueswir1 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
530 | 3475187d | bellard | } |
531 | 3475187d | bellard | |
532 | 905fdcb5 | blueswir1 | enum {
|
533 | 905fdcb5 | blueswir1 | sun4u_id = 0,
|
534 | 905fdcb5 | blueswir1 | sun4v_id = 64,
|
535 | e87231d4 | blueswir1 | niagara_id, |
536 | 905fdcb5 | blueswir1 | }; |
537 | 905fdcb5 | blueswir1 | |
538 | c7ba218d | blueswir1 | static const struct hwdef hwdefs[] = { |
539 | c7ba218d | blueswir1 | /* Sun4u generic PC-like machine */
|
540 | c7ba218d | blueswir1 | { |
541 | c7ba218d | blueswir1 | .default_cpu_model = "TI UltraSparc II",
|
542 | 905fdcb5 | blueswir1 | .machine_id = sun4u_id, |
543 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
544 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
545 | c7ba218d | blueswir1 | }, |
546 | c7ba218d | blueswir1 | /* Sun4v generic PC-like machine */
|
547 | c7ba218d | blueswir1 | { |
548 | c7ba218d | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
549 | 905fdcb5 | blueswir1 | .machine_id = sun4v_id, |
550 | e87231d4 | blueswir1 | .prom_addr = 0x1fff0000000ULL,
|
551 | e87231d4 | blueswir1 | .console_serial_base = 0,
|
552 | e87231d4 | blueswir1 | }, |
553 | e87231d4 | blueswir1 | /* Sun4v generic Niagara machine */
|
554 | e87231d4 | blueswir1 | { |
555 | e87231d4 | blueswir1 | .default_cpu_model = "Sun UltraSparc T1",
|
556 | e87231d4 | blueswir1 | .machine_id = niagara_id, |
557 | e87231d4 | blueswir1 | .prom_addr = 0xfff0000000ULL,
|
558 | e87231d4 | blueswir1 | .console_serial_base = 0xfff0c2c000ULL,
|
559 | c7ba218d | blueswir1 | }, |
560 | c7ba218d | blueswir1 | }; |
561 | c7ba218d | blueswir1 | |
562 | c7ba218d | blueswir1 | /* Sun4u hardware initialisation */
|
563 | fbe1b595 | Paul Brook | static void sun4u_init(ram_addr_t RAM_size, |
564 | 3023f332 | aliguori | const char *boot_devices, |
565 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
566 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
567 | c7ba218d | blueswir1 | { |
568 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
569 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
|
570 | c7ba218d | blueswir1 | } |
571 | c7ba218d | blueswir1 | |
572 | c7ba218d | blueswir1 | /* Sun4v hardware initialisation */
|
573 | fbe1b595 | Paul Brook | static void sun4v_init(ram_addr_t RAM_size, |
574 | 3023f332 | aliguori | const char *boot_devices, |
575 | c7ba218d | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
576 | c7ba218d | blueswir1 | const char *initrd_filename, const char *cpu_model) |
577 | c7ba218d | blueswir1 | { |
578 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
579 | c7ba218d | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
|
580 | c7ba218d | blueswir1 | } |
581 | c7ba218d | blueswir1 | |
582 | e87231d4 | blueswir1 | /* Niagara hardware initialisation */
|
583 | fbe1b595 | Paul Brook | static void niagara_init(ram_addr_t RAM_size, |
584 | 3023f332 | aliguori | const char *boot_devices, |
585 | e87231d4 | blueswir1 | const char *kernel_filename, const char *kernel_cmdline, |
586 | e87231d4 | blueswir1 | const char *initrd_filename, const char *cpu_model) |
587 | e87231d4 | blueswir1 | { |
588 | fbe1b595 | Paul Brook | sun4uv_init(RAM_size, boot_devices, kernel_filename, |
589 | e87231d4 | blueswir1 | kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
|
590 | e87231d4 | blueswir1 | } |
591 | e87231d4 | blueswir1 | |
592 | 3475187d | bellard | QEMUMachine sun4u_machine = { |
593 | 66de733b | blueswir1 | .name = "sun4u",
|
594 | 66de733b | blueswir1 | .desc = "Sun4u platform",
|
595 | 66de733b | blueswir1 | .init = sun4u_init, |
596 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
597 | 3475187d | bellard | }; |
598 | c7ba218d | blueswir1 | |
599 | c7ba218d | blueswir1 | QEMUMachine sun4v_machine = { |
600 | 66de733b | blueswir1 | .name = "sun4v",
|
601 | 66de733b | blueswir1 | .desc = "Sun4v platform",
|
602 | 66de733b | blueswir1 | .init = sun4v_init, |
603 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
604 | c7ba218d | blueswir1 | }; |
605 | e87231d4 | blueswir1 | |
606 | e87231d4 | blueswir1 | QEMUMachine niagara_machine = { |
607 | e87231d4 | blueswir1 | .name = "Niagara",
|
608 | e87231d4 | blueswir1 | .desc = "Sun4v platform, Niagara",
|
609 | e87231d4 | blueswir1 | .init = niagara_init, |
610 | 1bcee014 | blueswir1 | .max_cpus = 1, // XXX for now |
611 | e87231d4 | blueswir1 | }; |