Revision 8bb6e981 target-alpha/op_helper.c
| b/target-alpha/op_helper.c | ||
|---|---|---|
| 22 | 22 |
#include "host-utils.h" |
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#include "softfloat.h" |
| 24 | 24 |
|
| 25 |
#include "op_helper.h" |
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| 26 |
|
|
| 27 | 25 |
void helper_tb_flush (void) |
| 28 | 26 |
{
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| 29 | 27 |
tlb_flush(env, 1); |
| 30 | 28 |
} |
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|
| 32 |
void cpu_dump_EA (target_ulong EA); |
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void helper_print_mem_EA (target_ulong EA) |
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{
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cpu_dump_EA(EA); |
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} |
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|
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/*****************************************************************************/ |
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/* Exceptions processing helpers */ |
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void helper_excp (int excp, int error) |
| ... | ... | |
| 990 | 982 |
return __helper_cvtql(a, 1, 1); |
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} |
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/* PALcode support special instructions */ |
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#if !defined (CONFIG_USER_ONLY) |
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void helper_mfpr (int iprn) |
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void helper_hw_rei (void) |
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{
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env->pc = env->ipr[IPR_EXC_ADDR] & ~3; |
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env->ipr[IPR_EXC_ADDR] = env->ipr[IPR_EXC_ADDR] & 1; |
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/* XXX: re-enable interrupts and memory mapping */ |
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} |
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|
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void helper_hw_ret (uint64_t a) |
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{
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env->pc = a & ~3; |
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env->ipr[IPR_EXC_ADDR] = a & 1; |
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/* XXX: re-enable interrupts and memory mapping */ |
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} |
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uint64_t helper_mfpr (int iprn, uint64_t val) |
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{
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uint64_t tmp; |
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|
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if (cpu_alpha_mfpr(env, iprn, &tmp) == 0) |
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val = tmp; |
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|
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return val; |
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} |
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void helper_mtpr (int iprn, uint64_t val) |
|
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{
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uint64_t val; |
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cpu_alpha_mtpr(env, iprn, val, NULL); |
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} |
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if (cpu_alpha_mfpr(env, iprn, &val) == 0) |
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T0 = val; |
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void helper_set_alt_mode (void) |
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{
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env->saved_mode = env->ps & 0xC; |
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env->ps = (env->ps & ~0xC) | (env->ipr[IPR_ALT_MODE] & 0xC); |
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| 1000 | 1020 |
} |
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void helper_mtpr (int iprn)
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void helper_restore_mode (void)
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{
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cpu_alpha_mtpr(env, iprn, T0, NULL);
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env->ps = (env->ps & ~0xC) | env->saved_mode;
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} |
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#endif |
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/*****************************************************************************/ |
| ... | ... | |
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* Hopefully, we emulate the PALcode, then we should never see |
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* HW_LD / HW_ST instructions. |
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*/ |
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void helper_ld_phys_to_virt (void)
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uint64_t helper_ld_virt_to_phys (uint64_t virtaddr)
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{
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uint64_t tlb_addr, physaddr; |
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int index, mmu_idx; |
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void *retaddr; |
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|
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mmu_idx = cpu_mmu_index(env); |
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index = (T0 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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index = (virtaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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|
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redo: |
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tlb_addr = env->tlb_table[mmu_idx][index].addr_read; |
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if ((T0 & TARGET_PAGE_MASK) ==
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if ((virtaddr & TARGET_PAGE_MASK) ==
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(tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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physaddr = T0 + env->tlb_table[mmu_idx][index].addend;
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physaddr = virtaddr + env->tlb_table[mmu_idx][index].addend;
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} else {
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/* the page is not in the TLB : fill it */ |
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retaddr = GETPC(); |
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tlb_fill(T0, 0, mmu_idx, retaddr);
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tlb_fill(virtaddr, 0, mmu_idx, retaddr);
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goto redo; |
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} |
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T0 = physaddr;
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return physaddr;
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} |
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void helper_st_phys_to_virt (void)
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uint64_t helper_st_virt_to_phys (uint64_t virtaddr)
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{
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uint64_t tlb_addr, physaddr; |
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int index, mmu_idx; |
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void *retaddr; |
| 1043 | 1064 |
|
| 1044 | 1065 |
mmu_idx = cpu_mmu_index(env); |
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index = (T0 >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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index = (virtaddr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
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redo: |
| 1047 | 1068 |
tlb_addr = env->tlb_table[mmu_idx][index].addr_write; |
| 1048 |
if ((T0 & TARGET_PAGE_MASK) ==
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if ((virtaddr & TARGET_PAGE_MASK) ==
|
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| 1049 | 1070 |
(tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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physaddr = T0 + env->tlb_table[mmu_idx][index].addend;
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physaddr = virtaddr + env->tlb_table[mmu_idx][index].addend;
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} else {
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| 1052 | 1073 |
/* the page is not in the TLB : fill it */ |
| 1053 | 1074 |
retaddr = GETPC(); |
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tlb_fill(T0, 1, mmu_idx, retaddr);
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tlb_fill(virtaddr, 1, mmu_idx, retaddr);
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goto redo; |
| 1056 | 1077 |
} |
| 1057 |
T0 = physaddr; |
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return physaddr; |
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} |
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| 1080 |
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| 1081 |
void helper_ldl_raw(uint64_t t0, uint64_t t1) |
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{
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ldl_raw(t1, t0); |
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} |
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| 1086 |
void helper_ldq_raw(uint64_t t0, uint64_t t1) |
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{
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| 1088 |
ldq_raw(t1, t0); |
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} |
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| 1090 |
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void helper_ldl_l_raw(uint64_t t0, uint64_t t1) |
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{
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env->lock = t1; |
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ldl_raw(t1, t0); |
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} |
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void helper_ldq_l_raw(uint64_t t0, uint64_t t1) |
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{
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| 1099 |
env->lock = t1; |
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ldl_raw(t1, t0); |
|
| 1101 |
} |
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| 1102 |
|
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| 1103 |
void helper_ldl_kernel(uint64_t t0, uint64_t t1) |
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{
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ldl_kernel(t1, t0); |
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} |
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| 1107 |
|
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| 1108 |
void helper_ldq_kernel(uint64_t t0, uint64_t t1) |
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{
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ldq_kernel(t1, t0); |
|
| 1111 |
} |
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| 1113 |
void helper_ldl_data(uint64_t t0, uint64_t t1) |
|
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{
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| 1115 |
ldl_data(t1, t0); |
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| 1116 |
} |
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| 1117 |
|
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| 1118 |
void helper_ldq_data(uint64_t t0, uint64_t t1) |
|
| 1119 |
{
|
|
| 1120 |
ldq_data(t1, t0); |
|
| 1121 |
} |
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| 1122 |
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| 1123 |
void helper_stl_raw(uint64_t t0, uint64_t t1) |
|
| 1124 |
{
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| 1125 |
stl_raw(t1, t0); |
|
| 1126 |
} |
|
| 1127 |
|
|
| 1128 |
void helper_stq_raw(uint64_t t0, uint64_t t1) |
|
| 1129 |
{
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|
| 1130 |
stq_raw(t1, t0); |
|
| 1131 |
} |
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| 1132 |
|
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| 1133 |
uint64_t helper_stl_c_raw(uint64_t t0, uint64_t t1) |
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{
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|
| 1135 |
uint64_t ret; |
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| 1136 |
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| 1137 |
if (t1 == env->lock) {
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|
| 1138 |
stl_raw(t1, t0); |
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| 1139 |
ret = 0; |
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| 1140 |
} else |
|
| 1141 |
ret = 1; |
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| 1142 |
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| 1143 |
env->lock = 1; |
|
| 1144 |
|
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| 1145 |
return ret; |
|
| 1146 |
} |
|
| 1147 |
|
|
| 1148 |
uint64_t helper_stq_c_raw(uint64_t t0, uint64_t t1) |
|
| 1149 |
{
|
|
| 1150 |
uint64_t ret; |
|
| 1151 |
|
|
| 1152 |
if (t1 == env->lock) {
|
|
| 1153 |
stq_raw(t1, t0); |
|
| 1154 |
ret = 0; |
|
| 1155 |
} else |
|
| 1156 |
ret = 1; |
|
| 1157 |
|
|
| 1158 |
env->lock = 1; |
|
| 1159 |
|
|
| 1160 |
return ret; |
|
| 1058 | 1161 |
} |
| 1059 | 1162 |
|
| 1060 | 1163 |
#define MMUSUFFIX _mmu |
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