Revision 8c0ab41f
| b/target-mips/translate.c | ||
|---|---|---|
| 6378 | 6378 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 6379 | 6379 |
TCGv_i32 fp1 = tcg_temp_new_i32(); |
| 6380 | 6380 |
|
| 6381 |
if (ctx->opcode & (1 << 6)) {
|
|
| 6382 |
check_cop1x(ctx); |
|
| 6383 |
} |
|
| 6384 |
|
|
| 6385 | 6381 |
gen_load_fpr32(fp0, fs); |
| 6386 | 6382 |
gen_load_fpr32(fp1, ft); |
| 6387 | 6383 |
if (ctx->opcode & (1 << 6)) {
|
| 6384 |
check_cop1x(ctx); |
|
| 6388 | 6385 |
gen_cmpabs_s(func-48, fp0, fp1, cc); |
| 6389 | 6386 |
opn = condnames_abs[func-48]; |
| 6390 | 6387 |
} else {
|
| ... | ... | |
| 6743 | 6740 |
{
|
| 6744 | 6741 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| 6745 | 6742 |
TCGv_i64 fp1 = tcg_temp_new_i64(); |
| 6746 |
if (ctx->opcode & (1 << 6)) {
|
|
| 6747 |
check_cop1x(ctx); |
|
| 6748 |
} |
|
| 6749 |
check_cp1_registers(ctx, fs | ft); |
|
| 6750 | 6743 |
|
| 6751 | 6744 |
gen_load_fpr64(ctx, fp0, fs); |
| 6752 | 6745 |
gen_load_fpr64(ctx, fp1, ft); |
| 6753 | 6746 |
if (ctx->opcode & (1 << 6)) {
|
| 6747 |
check_cop1x(ctx); |
|
| 6748 |
check_cp1_registers(ctx, fs | ft); |
|
| 6754 | 6749 |
gen_cmpabs_d(func-48, fp0, fp1, cc); |
| 6755 | 6750 |
opn = condnames_abs[func-48]; |
| 6756 | 6751 |
} else {
|
| 6752 |
check_cp1_registers(ctx, fs | ft); |
|
| 6757 | 6753 |
gen_cmp_d(func-48, fp0, fp1, cc); |
| 6758 | 6754 |
opn = condnames[func-48]; |
| 6759 | 6755 |
} |
| ... | ... | |
| 7222 | 7218 |
int store = 0; |
| 7223 | 7219 |
TCGv t0 = tcg_temp_new(); |
| 7224 | 7220 |
|
| 7225 |
switch (opc) {
|
|
| 7226 |
case OPC_LWXC1: |
|
| 7227 |
case OPC_SWXC1: |
|
| 7228 |
check_cop1x(ctx); |
|
| 7229 |
break; |
|
| 7230 |
case OPC_LDXC1: |
|
| 7231 |
case OPC_SDXC1: |
|
| 7232 |
check_cop1x(ctx); |
|
| 7233 |
check_cp1_registers(ctx, fd); |
|
| 7234 |
break; |
|
| 7235 |
case OPC_LUXC1: |
|
| 7236 |
case OPC_SUXC1: |
|
| 7237 |
check_cp1_64bitmode(ctx); |
|
| 7238 |
break; |
|
| 7239 |
} |
|
| 7240 |
|
|
| 7241 | 7221 |
if (base == 0) {
|
| 7242 | 7222 |
gen_load_gpr(t0, index); |
| 7243 | 7223 |
} else if (index == 0) {
|
| ... | ... | |
| 7251 | 7231 |
save_cpu_state(ctx, 0); |
| 7252 | 7232 |
switch (opc) {
|
| 7253 | 7233 |
case OPC_LWXC1: |
| 7234 |
check_cop1x(ctx); |
|
| 7254 | 7235 |
{
|
| 7255 | 7236 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 7256 | 7237 |
|
| ... | ... | |
| 7262 | 7243 |
opn = "lwxc1"; |
| 7263 | 7244 |
break; |
| 7264 | 7245 |
case OPC_LDXC1: |
| 7246 |
check_cop1x(ctx); |
|
| 7247 |
check_cp1_registers(ctx, fd); |
|
| 7265 | 7248 |
{
|
| 7266 | 7249 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| 7267 | 7250 |
|
| ... | ... | |
| 7272 | 7255 |
opn = "ldxc1"; |
| 7273 | 7256 |
break; |
| 7274 | 7257 |
case OPC_LUXC1: |
| 7258 |
check_cp1_64bitmode(ctx); |
|
| 7275 | 7259 |
tcg_gen_andi_tl(t0, t0, ~0x7); |
| 7276 | 7260 |
{
|
| 7277 | 7261 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| ... | ... | |
| 7283 | 7267 |
opn = "luxc1"; |
| 7284 | 7268 |
break; |
| 7285 | 7269 |
case OPC_SWXC1: |
| 7270 |
check_cop1x(ctx); |
|
| 7286 | 7271 |
{
|
| 7287 | 7272 |
TCGv_i32 fp0 = tcg_temp_new_i32(); |
| 7288 | 7273 |
TCGv t1 = tcg_temp_new(); |
| ... | ... | |
| 7297 | 7282 |
store = 1; |
| 7298 | 7283 |
break; |
| 7299 | 7284 |
case OPC_SDXC1: |
| 7285 |
check_cop1x(ctx); |
|
| 7286 |
check_cp1_registers(ctx, fs); |
|
| 7300 | 7287 |
{
|
| 7301 | 7288 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
| 7302 | 7289 |
|
| ... | ... | |
| 7308 | 7295 |
store = 1; |
| 7309 | 7296 |
break; |
| 7310 | 7297 |
case OPC_SUXC1: |
| 7298 |
check_cp1_64bitmode(ctx); |
|
| 7311 | 7299 |
tcg_gen_andi_tl(t0, t0, ~0x7); |
| 7312 | 7300 |
{
|
| 7313 | 7301 |
TCGv_i64 fp0 = tcg_temp_new_i64(); |
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