root / hw / pci.c @ 8c5e95d8
History | View | Annotate | Download (20.2 kB)
| 1 |
/*
|
|---|---|
| 2 |
* QEMU PCI bus manager
|
| 3 |
*
|
| 4 |
* Copyright (c) 2004 Fabrice Bellard
|
| 5 |
*
|
| 6 |
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
| 7 |
* of this software and associated documentation files (the "Software"), to deal
|
| 8 |
* in the Software without restriction, including without limitation the rights
|
| 9 |
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
| 10 |
* copies of the Software, and to permit persons to whom the Software is
|
| 11 |
* furnished to do so, subject to the following conditions:
|
| 12 |
*
|
| 13 |
* The above copyright notice and this permission notice shall be included in
|
| 14 |
* all copies or substantial portions of the Software.
|
| 15 |
*
|
| 16 |
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
| 17 |
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
| 18 |
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
| 19 |
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
| 20 |
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
| 21 |
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
| 22 |
* THE SOFTWARE.
|
| 23 |
*/
|
| 24 |
#include "hw.h" |
| 25 |
#include "pci.h" |
| 26 |
#include "console.h" |
| 27 |
#include "net.h" |
| 28 |
|
| 29 |
//#define DEBUG_PCI
|
| 30 |
|
| 31 |
struct PCIBus {
|
| 32 |
int bus_num;
|
| 33 |
int devfn_min;
|
| 34 |
pci_set_irq_fn set_irq; |
| 35 |
pci_map_irq_fn map_irq; |
| 36 |
uint32_t config_reg; /* XXX: suppress */
|
| 37 |
/* low level pic */
|
| 38 |
SetIRQFunc *low_set_irq; |
| 39 |
qemu_irq *irq_opaque; |
| 40 |
PCIDevice *devices[256];
|
| 41 |
PCIDevice *parent_dev; |
| 42 |
PCIBus *next; |
| 43 |
/* The bus IRQ state is the logical OR of the connected devices.
|
| 44 |
Keep a count of the number of devices with raised IRQs. */
|
| 45 |
int nirq;
|
| 46 |
int irq_count[];
|
| 47 |
}; |
| 48 |
|
| 49 |
static void pci_update_mappings(PCIDevice *d); |
| 50 |
static void pci_set_irq(void *opaque, int irq_num, int level); |
| 51 |
|
| 52 |
target_phys_addr_t pci_mem_base; |
| 53 |
static int pci_irq_index; |
| 54 |
static PCIBus *first_bus;
|
| 55 |
|
| 56 |
static void pcibus_save(QEMUFile *f, void *opaque) |
| 57 |
{
|
| 58 |
PCIBus *bus = (PCIBus *)opaque; |
| 59 |
int i;
|
| 60 |
|
| 61 |
qemu_put_be32(f, bus->nirq); |
| 62 |
for (i = 0; i < bus->nirq; i++) |
| 63 |
qemu_put_be32(f, bus->irq_count[i]); |
| 64 |
} |
| 65 |
|
| 66 |
static int pcibus_load(QEMUFile *f, void *opaque, int version_id) |
| 67 |
{
|
| 68 |
PCIBus *bus = (PCIBus *)opaque; |
| 69 |
int i, nirq;
|
| 70 |
|
| 71 |
if (version_id != 1) |
| 72 |
return -EINVAL;
|
| 73 |
|
| 74 |
nirq = qemu_get_be32(f); |
| 75 |
if (bus->nirq != nirq) {
|
| 76 |
fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
|
| 77 |
nirq, bus->nirq); |
| 78 |
return -EINVAL;
|
| 79 |
} |
| 80 |
|
| 81 |
for (i = 0; i < nirq; i++) |
| 82 |
bus->irq_count[i] = qemu_get_be32(f); |
| 83 |
|
| 84 |
return 0; |
| 85 |
} |
| 86 |
|
| 87 |
PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
| 88 |
qemu_irq *pic, int devfn_min, int nirq) |
| 89 |
{
|
| 90 |
PCIBus *bus; |
| 91 |
static int nbus = 0; |
| 92 |
|
| 93 |
bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int))); |
| 94 |
bus->set_irq = set_irq; |
| 95 |
bus->map_irq = map_irq; |
| 96 |
bus->irq_opaque = pic; |
| 97 |
bus->devfn_min = devfn_min; |
| 98 |
bus->nirq = nirq; |
| 99 |
first_bus = bus; |
| 100 |
register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus); |
| 101 |
return bus;
|
| 102 |
} |
| 103 |
|
| 104 |
static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
|
| 105 |
{
|
| 106 |
PCIBus *bus; |
| 107 |
bus = qemu_mallocz(sizeof(PCIBus));
|
| 108 |
bus->map_irq = map_irq; |
| 109 |
bus->parent_dev = dev; |
| 110 |
bus->next = dev->bus->next; |
| 111 |
dev->bus->next = bus; |
| 112 |
return bus;
|
| 113 |
} |
| 114 |
|
| 115 |
int pci_bus_num(PCIBus *s)
|
| 116 |
{
|
| 117 |
return s->bus_num;
|
| 118 |
} |
| 119 |
|
| 120 |
void pci_device_save(PCIDevice *s, QEMUFile *f)
|
| 121 |
{
|
| 122 |
int i;
|
| 123 |
|
| 124 |
qemu_put_be32(f, 2); /* PCI device version */ |
| 125 |
qemu_put_buffer(f, s->config, 256);
|
| 126 |
for (i = 0; i < 4; i++) |
| 127 |
qemu_put_be32(f, s->irq_state[i]); |
| 128 |
} |
| 129 |
|
| 130 |
int pci_device_load(PCIDevice *s, QEMUFile *f)
|
| 131 |
{
|
| 132 |
uint32_t version_id; |
| 133 |
int i;
|
| 134 |
|
| 135 |
version_id = qemu_get_be32(f); |
| 136 |
if (version_id > 2) |
| 137 |
return -EINVAL;
|
| 138 |
qemu_get_buffer(f, s->config, 256);
|
| 139 |
pci_update_mappings(s); |
| 140 |
|
| 141 |
if (version_id >= 2) |
| 142 |
for (i = 0; i < 4; i ++) |
| 143 |
s->irq_state[i] = qemu_get_be32(f); |
| 144 |
|
| 145 |
return 0; |
| 146 |
} |
| 147 |
|
| 148 |
/* -1 for devfn means auto assign */
|
| 149 |
PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
| 150 |
int instance_size, int devfn, |
| 151 |
PCIConfigReadFunc *config_read, |
| 152 |
PCIConfigWriteFunc *config_write) |
| 153 |
{
|
| 154 |
PCIDevice *pci_dev; |
| 155 |
|
| 156 |
if (pci_irq_index >= PCI_DEVICES_MAX)
|
| 157 |
return NULL; |
| 158 |
|
| 159 |
if (devfn < 0) { |
| 160 |
for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) { |
| 161 |
if (!bus->devices[devfn])
|
| 162 |
goto found;
|
| 163 |
} |
| 164 |
return NULL; |
| 165 |
found: ;
|
| 166 |
} |
| 167 |
pci_dev = qemu_mallocz(instance_size); |
| 168 |
if (!pci_dev)
|
| 169 |
return NULL; |
| 170 |
pci_dev->bus = bus; |
| 171 |
pci_dev->devfn = devfn; |
| 172 |
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
| 173 |
memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state)); |
| 174 |
|
| 175 |
if (!config_read)
|
| 176 |
config_read = pci_default_read_config; |
| 177 |
if (!config_write)
|
| 178 |
config_write = pci_default_write_config; |
| 179 |
pci_dev->config_read = config_read; |
| 180 |
pci_dev->config_write = config_write; |
| 181 |
pci_dev->irq_index = pci_irq_index++; |
| 182 |
bus->devices[devfn] = pci_dev; |
| 183 |
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
|
| 184 |
return pci_dev;
|
| 185 |
} |
| 186 |
|
| 187 |
void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
| 188 |
uint32_t size, int type,
|
| 189 |
PCIMapIORegionFunc *map_func) |
| 190 |
{
|
| 191 |
PCIIORegion *r; |
| 192 |
uint32_t addr; |
| 193 |
|
| 194 |
if ((unsigned int)region_num >= PCI_NUM_REGIONS) |
| 195 |
return;
|
| 196 |
r = &pci_dev->io_regions[region_num]; |
| 197 |
r->addr = -1;
|
| 198 |
r->size = size; |
| 199 |
r->type = type; |
| 200 |
r->map_func = map_func; |
| 201 |
if (region_num == PCI_ROM_SLOT) {
|
| 202 |
addr = 0x30;
|
| 203 |
} else {
|
| 204 |
addr = 0x10 + region_num * 4; |
| 205 |
} |
| 206 |
*(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type); |
| 207 |
} |
| 208 |
|
| 209 |
static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
|
| 210 |
{
|
| 211 |
return addr + pci_mem_base;
|
| 212 |
} |
| 213 |
|
| 214 |
static void pci_update_mappings(PCIDevice *d) |
| 215 |
{
|
| 216 |
PCIIORegion *r; |
| 217 |
int cmd, i;
|
| 218 |
uint32_t last_addr, new_addr, config_ofs; |
| 219 |
|
| 220 |
cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND)); |
| 221 |
for(i = 0; i < PCI_NUM_REGIONS; i++) { |
| 222 |
r = &d->io_regions[i]; |
| 223 |
if (i == PCI_ROM_SLOT) {
|
| 224 |
config_ofs = 0x30;
|
| 225 |
} else {
|
| 226 |
config_ofs = 0x10 + i * 4; |
| 227 |
} |
| 228 |
if (r->size != 0) { |
| 229 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
| 230 |
if (cmd & PCI_COMMAND_IO) {
|
| 231 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
| 232 |
config_ofs)); |
| 233 |
new_addr = new_addr & ~(r->size - 1);
|
| 234 |
last_addr = new_addr + r->size - 1;
|
| 235 |
/* NOTE: we have only 64K ioports on PC */
|
| 236 |
if (last_addr <= new_addr || new_addr == 0 || |
| 237 |
last_addr >= 0x10000) {
|
| 238 |
new_addr = -1;
|
| 239 |
} |
| 240 |
} else {
|
| 241 |
new_addr = -1;
|
| 242 |
} |
| 243 |
} else {
|
| 244 |
if (cmd & PCI_COMMAND_MEMORY) {
|
| 245 |
new_addr = le32_to_cpu(*(uint32_t *)(d->config + |
| 246 |
config_ofs)); |
| 247 |
/* the ROM slot has a specific enable bit */
|
| 248 |
if (i == PCI_ROM_SLOT && !(new_addr & 1)) |
| 249 |
goto no_mem_map;
|
| 250 |
new_addr = new_addr & ~(r->size - 1);
|
| 251 |
last_addr = new_addr + r->size - 1;
|
| 252 |
/* NOTE: we do not support wrapping */
|
| 253 |
/* XXX: as we cannot support really dynamic
|
| 254 |
mappings, we handle specific values as invalid
|
| 255 |
mappings. */
|
| 256 |
if (last_addr <= new_addr || new_addr == 0 || |
| 257 |
last_addr == -1) {
|
| 258 |
new_addr = -1;
|
| 259 |
} |
| 260 |
} else {
|
| 261 |
no_mem_map:
|
| 262 |
new_addr = -1;
|
| 263 |
} |
| 264 |
} |
| 265 |
/* now do the real mapping */
|
| 266 |
if (new_addr != r->addr) {
|
| 267 |
if (r->addr != -1) { |
| 268 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
| 269 |
int class;
|
| 270 |
/* NOTE: specific hack for IDE in PC case:
|
| 271 |
only one byte must be mapped. */
|
| 272 |
class = d->config[0x0a] | (d->config[0x0b] << 8); |
| 273 |
if (class == 0x0101 && r->size == 4) { |
| 274 |
isa_unassign_ioport(r->addr + 2, 1); |
| 275 |
} else {
|
| 276 |
isa_unassign_ioport(r->addr, r->size); |
| 277 |
} |
| 278 |
} else {
|
| 279 |
cpu_register_physical_memory(pci_to_cpu_addr(r->addr), |
| 280 |
r->size, |
| 281 |
IO_MEM_UNASSIGNED); |
| 282 |
} |
| 283 |
} |
| 284 |
r->addr = new_addr; |
| 285 |
if (r->addr != -1) { |
| 286 |
r->map_func(d, i, r->addr, r->size, r->type); |
| 287 |
} |
| 288 |
} |
| 289 |
} |
| 290 |
} |
| 291 |
} |
| 292 |
|
| 293 |
uint32_t pci_default_read_config(PCIDevice *d, |
| 294 |
uint32_t address, int len)
|
| 295 |
{
|
| 296 |
uint32_t val; |
| 297 |
|
| 298 |
switch(len) {
|
| 299 |
default:
|
| 300 |
case 4: |
| 301 |
if (address <= 0xfc) { |
| 302 |
val = le32_to_cpu(*(uint32_t *)(d->config + address)); |
| 303 |
break;
|
| 304 |
} |
| 305 |
/* fall through */
|
| 306 |
case 2: |
| 307 |
if (address <= 0xfe) { |
| 308 |
val = le16_to_cpu(*(uint16_t *)(d->config + address)); |
| 309 |
break;
|
| 310 |
} |
| 311 |
/* fall through */
|
| 312 |
case 1: |
| 313 |
val = d->config[address]; |
| 314 |
break;
|
| 315 |
} |
| 316 |
return val;
|
| 317 |
} |
| 318 |
|
| 319 |
void pci_default_write_config(PCIDevice *d,
|
| 320 |
uint32_t address, uint32_t val, int len)
|
| 321 |
{
|
| 322 |
int can_write, i;
|
| 323 |
uint32_t end, addr; |
| 324 |
|
| 325 |
if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) || |
| 326 |
(address >= 0x30 && address < 0x34))) { |
| 327 |
PCIIORegion *r; |
| 328 |
int reg;
|
| 329 |
|
| 330 |
if ( address >= 0x30 ) { |
| 331 |
reg = PCI_ROM_SLOT; |
| 332 |
}else{
|
| 333 |
reg = (address - 0x10) >> 2; |
| 334 |
} |
| 335 |
r = &d->io_regions[reg]; |
| 336 |
if (r->size == 0) |
| 337 |
goto default_config;
|
| 338 |
/* compute the stored value */
|
| 339 |
if (reg == PCI_ROM_SLOT) {
|
| 340 |
/* keep ROM enable bit */
|
| 341 |
val &= (~(r->size - 1)) | 1; |
| 342 |
} else {
|
| 343 |
val &= ~(r->size - 1);
|
| 344 |
val |= r->type; |
| 345 |
} |
| 346 |
*(uint32_t *)(d->config + address) = cpu_to_le32(val); |
| 347 |
pci_update_mappings(d); |
| 348 |
return;
|
| 349 |
} |
| 350 |
default_config:
|
| 351 |
/* not efficient, but simple */
|
| 352 |
addr = address; |
| 353 |
for(i = 0; i < len; i++) { |
| 354 |
/* default read/write accesses */
|
| 355 |
switch(d->config[0x0e]) { |
| 356 |
case 0x00: |
| 357 |
case 0x80: |
| 358 |
switch(addr) {
|
| 359 |
case 0x00: |
| 360 |
case 0x01: |
| 361 |
case 0x02: |
| 362 |
case 0x03: |
| 363 |
case 0x08: |
| 364 |
case 0x09: |
| 365 |
case 0x0a: |
| 366 |
case 0x0b: |
| 367 |
case 0x0e: |
| 368 |
case 0x10 ... 0x27: /* base */ |
| 369 |
case 0x30 ... 0x33: /* rom */ |
| 370 |
case 0x3d: |
| 371 |
can_write = 0;
|
| 372 |
break;
|
| 373 |
default:
|
| 374 |
can_write = 1;
|
| 375 |
break;
|
| 376 |
} |
| 377 |
break;
|
| 378 |
default:
|
| 379 |
case 0x01: |
| 380 |
switch(addr) {
|
| 381 |
case 0x00: |
| 382 |
case 0x01: |
| 383 |
case 0x02: |
| 384 |
case 0x03: |
| 385 |
case 0x08: |
| 386 |
case 0x09: |
| 387 |
case 0x0a: |
| 388 |
case 0x0b: |
| 389 |
case 0x0e: |
| 390 |
case 0x38 ... 0x3b: /* rom */ |
| 391 |
case 0x3d: |
| 392 |
can_write = 0;
|
| 393 |
break;
|
| 394 |
default:
|
| 395 |
can_write = 1;
|
| 396 |
break;
|
| 397 |
} |
| 398 |
break;
|
| 399 |
} |
| 400 |
if (can_write) {
|
| 401 |
d->config[addr] = val; |
| 402 |
} |
| 403 |
if (++addr > 0xff) |
| 404 |
break;
|
| 405 |
val >>= 8;
|
| 406 |
} |
| 407 |
|
| 408 |
end = address + len; |
| 409 |
if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) { |
| 410 |
/* if the command register is modified, we must modify the mappings */
|
| 411 |
pci_update_mappings(d); |
| 412 |
} |
| 413 |
} |
| 414 |
|
| 415 |
void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len) |
| 416 |
{
|
| 417 |
PCIBus *s = opaque; |
| 418 |
PCIDevice *pci_dev; |
| 419 |
int config_addr, bus_num;
|
| 420 |
|
| 421 |
#if defined(DEBUG_PCI) && 0 |
| 422 |
printf("pci_data_write: addr=%08x val=%08x len=%d\n",
|
| 423 |
addr, val, len); |
| 424 |
#endif
|
| 425 |
bus_num = (addr >> 16) & 0xff; |
| 426 |
while (s && s->bus_num != bus_num)
|
| 427 |
s = s->next; |
| 428 |
if (!s)
|
| 429 |
return;
|
| 430 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
| 431 |
if (!pci_dev)
|
| 432 |
return;
|
| 433 |
config_addr = addr & 0xff;
|
| 434 |
#if defined(DEBUG_PCI)
|
| 435 |
printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
|
| 436 |
pci_dev->name, config_addr, val, len); |
| 437 |
#endif
|
| 438 |
pci_dev->config_write(pci_dev, config_addr, val, len); |
| 439 |
} |
| 440 |
|
| 441 |
uint32_t pci_data_read(void *opaque, uint32_t addr, int len) |
| 442 |
{
|
| 443 |
PCIBus *s = opaque; |
| 444 |
PCIDevice *pci_dev; |
| 445 |
int config_addr, bus_num;
|
| 446 |
uint32_t val; |
| 447 |
|
| 448 |
bus_num = (addr >> 16) & 0xff; |
| 449 |
while (s && s->bus_num != bus_num)
|
| 450 |
s= s->next; |
| 451 |
if (!s)
|
| 452 |
goto fail;
|
| 453 |
pci_dev = s->devices[(addr >> 8) & 0xff]; |
| 454 |
if (!pci_dev) {
|
| 455 |
fail:
|
| 456 |
switch(len) {
|
| 457 |
case 1: |
| 458 |
val = 0xff;
|
| 459 |
break;
|
| 460 |
case 2: |
| 461 |
val = 0xffff;
|
| 462 |
break;
|
| 463 |
default:
|
| 464 |
case 4: |
| 465 |
val = 0xffffffff;
|
| 466 |
break;
|
| 467 |
} |
| 468 |
goto the_end;
|
| 469 |
} |
| 470 |
config_addr = addr & 0xff;
|
| 471 |
val = pci_dev->config_read(pci_dev, config_addr, len); |
| 472 |
#if defined(DEBUG_PCI)
|
| 473 |
printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
|
| 474 |
pci_dev->name, config_addr, val, len); |
| 475 |
#endif
|
| 476 |
the_end:
|
| 477 |
#if defined(DEBUG_PCI) && 0 |
| 478 |
printf("pci_data_read: addr=%08x val=%08x len=%d\n",
|
| 479 |
addr, val, len); |
| 480 |
#endif
|
| 481 |
return val;
|
| 482 |
} |
| 483 |
|
| 484 |
/***********************************************************/
|
| 485 |
/* generic PCI irq support */
|
| 486 |
|
| 487 |
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
| 488 |
static void pci_set_irq(void *opaque, int irq_num, int level) |
| 489 |
{
|
| 490 |
PCIDevice *pci_dev = (PCIDevice *)opaque; |
| 491 |
PCIBus *bus; |
| 492 |
int change;
|
| 493 |
|
| 494 |
change = level - pci_dev->irq_state[irq_num]; |
| 495 |
if (!change)
|
| 496 |
return;
|
| 497 |
|
| 498 |
pci_dev->irq_state[irq_num] = level; |
| 499 |
for (;;) {
|
| 500 |
bus = pci_dev->bus; |
| 501 |
irq_num = bus->map_irq(pci_dev, irq_num); |
| 502 |
if (bus->set_irq)
|
| 503 |
break;
|
| 504 |
pci_dev = bus->parent_dev; |
| 505 |
} |
| 506 |
bus->irq_count[irq_num] += change; |
| 507 |
bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
|
| 508 |
} |
| 509 |
|
| 510 |
/***********************************************************/
|
| 511 |
/* monitor info on PCI */
|
| 512 |
|
| 513 |
typedef struct { |
| 514 |
uint16_t class; |
| 515 |
const char *desc; |
| 516 |
} pci_class_desc; |
| 517 |
|
| 518 |
static pci_class_desc pci_class_descriptions[] =
|
| 519 |
{
|
| 520 |
{ 0x0100, "SCSI controller"},
|
| 521 |
{ 0x0101, "IDE controller"},
|
| 522 |
{ 0x0102, "Floppy controller"},
|
| 523 |
{ 0x0103, "IPI controller"},
|
| 524 |
{ 0x0104, "RAID controller"},
|
| 525 |
{ 0x0106, "SATA controller"},
|
| 526 |
{ 0x0107, "SAS controller"},
|
| 527 |
{ 0x0180, "Storage controller"},
|
| 528 |
{ 0x0200, "Ethernet controller"},
|
| 529 |
{ 0x0201, "Token Ring controller"},
|
| 530 |
{ 0x0202, "FDDI controller"},
|
| 531 |
{ 0x0203, "ATM controller"},
|
| 532 |
{ 0x0280, "Network controller"},
|
| 533 |
{ 0x0300, "VGA controller"},
|
| 534 |
{ 0x0301, "XGA controller"},
|
| 535 |
{ 0x0302, "3D controller"},
|
| 536 |
{ 0x0380, "Display controller"},
|
| 537 |
{ 0x0400, "Video controller"},
|
| 538 |
{ 0x0401, "Audio controller"},
|
| 539 |
{ 0x0402, "Phone"},
|
| 540 |
{ 0x0480, "Multimedia controller"},
|
| 541 |
{ 0x0500, "RAM controller"},
|
| 542 |
{ 0x0501, "Flash controller"},
|
| 543 |
{ 0x0580, "Memory controller"},
|
| 544 |
{ 0x0600, "Host bridge"},
|
| 545 |
{ 0x0601, "ISA bridge"},
|
| 546 |
{ 0x0602, "EISA bridge"},
|
| 547 |
{ 0x0603, "MC bridge"},
|
| 548 |
{ 0x0604, "PCI bridge"},
|
| 549 |
{ 0x0605, "PCMCIA bridge"},
|
| 550 |
{ 0x0606, "NUBUS bridge"},
|
| 551 |
{ 0x0607, "CARDBUS bridge"},
|
| 552 |
{ 0x0608, "RACEWAY bridge"},
|
| 553 |
{ 0x0680, "Bridge"},
|
| 554 |
{ 0x0c03, "USB controller"},
|
| 555 |
{ 0, NULL}
|
| 556 |
}; |
| 557 |
|
| 558 |
static void pci_info_device(PCIDevice *d) |
| 559 |
{
|
| 560 |
int i, class;
|
| 561 |
PCIIORegion *r; |
| 562 |
pci_class_desc *desc; |
| 563 |
|
| 564 |
term_printf(" Bus %2d, device %3d, function %d:\n",
|
| 565 |
d->bus->bus_num, d->devfn >> 3, d->devfn & 7); |
| 566 |
class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE))); |
| 567 |
term_printf(" ");
|
| 568 |
desc = pci_class_descriptions; |
| 569 |
while (desc->desc && class != desc->class)
|
| 570 |
desc++; |
| 571 |
if (desc->desc) {
|
| 572 |
term_printf("%s", desc->desc);
|
| 573 |
} else {
|
| 574 |
term_printf("Class %04x", class);
|
| 575 |
} |
| 576 |
term_printf(": PCI device %04x:%04x\n",
|
| 577 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))), |
| 578 |
le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID)))); |
| 579 |
|
| 580 |
if (d->config[PCI_INTERRUPT_PIN] != 0) { |
| 581 |
term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
|
| 582 |
} |
| 583 |
if (class == 0x0604) { |
| 584 |
term_printf(" BUS %d.\n", d->config[0x19]); |
| 585 |
} |
| 586 |
for(i = 0;i < PCI_NUM_REGIONS; i++) { |
| 587 |
r = &d->io_regions[i]; |
| 588 |
if (r->size != 0) { |
| 589 |
term_printf(" BAR%d: ", i);
|
| 590 |
if (r->type & PCI_ADDRESS_SPACE_IO) {
|
| 591 |
term_printf("I/O at 0x%04x [0x%04x].\n",
|
| 592 |
r->addr, r->addr + r->size - 1);
|
| 593 |
} else {
|
| 594 |
term_printf("32 bit memory at 0x%08x [0x%08x].\n",
|
| 595 |
r->addr, r->addr + r->size - 1);
|
| 596 |
} |
| 597 |
} |
| 598 |
} |
| 599 |
if (class == 0x0604 && d->config[0x19] != 0) { |
| 600 |
pci_for_each_device(d->config[0x19], pci_info_device);
|
| 601 |
} |
| 602 |
} |
| 603 |
|
| 604 |
void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)) |
| 605 |
{
|
| 606 |
PCIBus *bus = first_bus; |
| 607 |
PCIDevice *d; |
| 608 |
int devfn;
|
| 609 |
|
| 610 |
while (bus && bus->bus_num != bus_num)
|
| 611 |
bus = bus->next; |
| 612 |
if (bus) {
|
| 613 |
for(devfn = 0; devfn < 256; devfn++) { |
| 614 |
d = bus->devices[devfn]; |
| 615 |
if (d)
|
| 616 |
fn(d); |
| 617 |
} |
| 618 |
} |
| 619 |
} |
| 620 |
|
| 621 |
void pci_info(void) |
| 622 |
{
|
| 623 |
pci_for_each_device(0, pci_info_device);
|
| 624 |
} |
| 625 |
|
| 626 |
/* Initialize a PCI NIC. */
|
| 627 |
void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn) |
| 628 |
{
|
| 629 |
if (strcmp(nd->model, "ne2k_pci") == 0) { |
| 630 |
pci_ne2000_init(bus, nd, devfn); |
| 631 |
} else if (strcmp(nd->model, "i82551") == 0) { |
| 632 |
pci_i82551_init(bus, nd, devfn); |
| 633 |
} else if (strcmp(nd->model, "i82557b") == 0) { |
| 634 |
pci_i82557b_init(bus, nd, devfn); |
| 635 |
} else if (strcmp(nd->model, "i82559er") == 0) { |
| 636 |
pci_i82559er_init(bus, nd, devfn); |
| 637 |
} else if (strcmp(nd->model, "rtl8139") == 0) { |
| 638 |
pci_rtl8139_init(bus, nd, devfn); |
| 639 |
} else if (strcmp(nd->model, "e1000") == 0) { |
| 640 |
pci_e1000_init(bus, nd, devfn); |
| 641 |
} else if (strcmp(nd->model, "pcnet") == 0) { |
| 642 |
pci_pcnet_init(bus, nd, devfn); |
| 643 |
} else if (strcmp(nd->model, "?") == 0) { |
| 644 |
fprintf(stderr, "qemu: Supported PCI NICs: i82551 i82557b i82559er"
|
| 645 |
" ne2k_pci pcnet rtl8139 e1000\n");
|
| 646 |
exit (1);
|
| 647 |
} else {
|
| 648 |
fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
|
| 649 |
exit (1);
|
| 650 |
} |
| 651 |
} |
| 652 |
|
| 653 |
typedef struct { |
| 654 |
PCIDevice dev; |
| 655 |
PCIBus *bus; |
| 656 |
} PCIBridge; |
| 657 |
|
| 658 |
static void pci_bridge_write_config(PCIDevice *d, |
| 659 |
uint32_t address, uint32_t val, int len)
|
| 660 |
{
|
| 661 |
PCIBridge *s = (PCIBridge *)d; |
| 662 |
|
| 663 |
if (address == 0x19 || (address == 0x18 && len > 1)) { |
| 664 |
if (address == 0x19) |
| 665 |
s->bus->bus_num = val & 0xff;
|
| 666 |
else
|
| 667 |
s->bus->bus_num = (val >> 8) & 0xff; |
| 668 |
#if defined(DEBUG_PCI)
|
| 669 |
printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
|
| 670 |
#endif
|
| 671 |
} |
| 672 |
pci_default_write_config(d, address, val, len); |
| 673 |
} |
| 674 |
|
| 675 |
PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
|
| 676 |
pci_map_irq_fn map_irq, const char *name) |
| 677 |
{
|
| 678 |
PCIBridge *s; |
| 679 |
s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
|
| 680 |
devfn, NULL, pci_bridge_write_config);
|
| 681 |
s->dev.config[0x00] = id >> 16; |
| 682 |
s->dev.config[0x01] = id >> 24; |
| 683 |
s->dev.config[0x02] = id; // device_id |
| 684 |
s->dev.config[0x03] = id >> 8; |
| 685 |
s->dev.config[0x04] = 0x06; // command = bus master, pci mem |
| 686 |
s->dev.config[0x05] = 0x00; |
| 687 |
s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error |
| 688 |
s->dev.config[0x07] = 0x00; // status = fast devsel |
| 689 |
s->dev.config[0x08] = 0x00; // revision |
| 690 |
s->dev.config[0x09] = 0x00; // programming i/f |
| 691 |
s->dev.config[0x0A] = 0x04; // class_sub = PCI to PCI bridge |
| 692 |
s->dev.config[0x0B] = 0x06; // class_base = PCI_bridge |
| 693 |
s->dev.config[0x0D] = 0x10; // latency_timer |
| 694 |
s->dev.config[0x0E] = 0x81; // header_type |
| 695 |
s->dev.config[0x1E] = 0xa0; // secondary status |
| 696 |
|
| 697 |
s->bus = pci_register_secondary_bus(&s->dev, map_irq); |
| 698 |
return s->bus;
|
| 699 |
} |