root / target-i386 / seg_helper.c @ 8c723b79
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/*
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* x86 segmentation related helpers:
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* TSS, interrupts, system calls, jumps and call/task gates, descriptors
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h" |
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#include "qemu-log.h" |
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#include "helper.h" |
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//#define DEBUG_PCALL
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#if !defined(CONFIG_USER_ONLY)
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#include "softmmu_exec.h" |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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#ifdef DEBUG_PCALL
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# define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__) |
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# define LOG_PCALL_STATE(env) \
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log_cpu_state_mask(CPU_LOG_PCALL, (env), CPU_DUMP_CCOP) |
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#else
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# define LOG_PCALL(...) do { } while (0) |
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# define LOG_PCALL_STATE(env) do { } while (0) |
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#endif
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/* return non zero if error */
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static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr, |
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uint32_t *e2_ptr, int selector)
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{ |
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SegmentCache *dt; |
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int index;
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target_ulong ptr; |
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if (selector & 0x4) { |
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dt = &env->ldt; |
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} else {
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dt = &env->gdt; |
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} |
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index = selector & ~7;
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if ((index + 7) > dt->limit) { |
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return -1; |
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} |
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ptr = dt->base + index; |
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*e1_ptr = cpu_ldl_kernel(env, ptr); |
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*e2_ptr = cpu_ldl_kernel(env, ptr + 4);
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return 0; |
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} |
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static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2) |
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{ |
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unsigned int limit; |
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limit = (e1 & 0xffff) | (e2 & 0x000f0000); |
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if (e2 & DESC_G_MASK) {
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limit = (limit << 12) | 0xfff; |
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} |
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return limit;
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} |
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static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2) |
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{ |
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return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000); |
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} |
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static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, |
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uint32_t e2) |
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{ |
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sc->base = get_seg_base(e1, e2); |
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sc->limit = get_seg_limit(e1, e2); |
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sc->flags = e2; |
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} |
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/* init the segment cache in vm86 mode. */
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static inline void load_seg_vm(CPUX86State *env, int seg, int selector) |
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{ |
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selector &= 0xffff;
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cpu_x86_load_seg_cache(env, seg, selector, |
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(selector << 4), 0xffff, 0); |
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} |
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static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, |
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uint32_t *esp_ptr, int dpl)
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{ |
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int type, index, shift;
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#if 0
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{
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int i;
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printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
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for (i = 0; i < env->tr.limit; i++) {
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printf("%02x ", env->tr.base[i]);
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if ((i & 7) == 7) {
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printf("\n");
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}
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}
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printf("\n");
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}
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#endif
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if (!(env->tr.flags & DESC_P_MASK)) {
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cpu_abort(env, "invalid tss");
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} |
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type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
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if ((type & 7) != 1) { |
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cpu_abort(env, "invalid tss type");
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} |
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shift = type >> 3;
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index = (dpl * 4 + 2) << shift; |
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if (index + (4 << shift) - 1 > env->tr.limit) { |
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raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
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} |
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if (shift == 0) { |
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*esp_ptr = cpu_lduw_kernel(env, env->tr.base + index); |
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*ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 2);
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} else {
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*esp_ptr = cpu_ldl_kernel(env, env->tr.base + index); |
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*ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 4);
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} |
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} |
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/* XXX: merge with load_seg() */
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static void tss_load_seg(CPUX86State *env, int seg_reg, int selector) |
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{ |
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uint32_t e1, e2; |
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int rpl, dpl, cpl;
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if ((selector & 0xfffc) != 0) { |
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if (load_segment(env, &e1, &e2, selector) != 0) { |
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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if (!(e2 & DESC_S_MASK)) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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rpl = selector & 3;
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dpl = (e2 >> DESC_DPL_SHIFT) & 3;
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cpl = env->hflags & HF_CPL_MASK; |
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if (seg_reg == R_CS) {
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if (!(e2 & DESC_CS_MASK)) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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/* XXX: is it correct? */
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if (dpl != rpl) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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if ((e2 & DESC_C_MASK) && dpl > rpl) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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} else if (seg_reg == R_SS) { |
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/* SS must be writable data */
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if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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if (dpl != cpl || dpl != rpl) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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} else {
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/* not readable code */
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if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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/* if data or non conforming code, checks the rights */
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if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) { |
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if (dpl < cpl || dpl < rpl) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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} |
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} |
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if (!(e2 & DESC_P_MASK)) {
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raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
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} |
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cpu_x86_load_seg_cache(env, seg_reg, selector, |
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get_seg_base(e1, e2), |
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get_seg_limit(e1, e2), |
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e2); |
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} else {
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if (seg_reg == R_SS || seg_reg == R_CS) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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} |
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} |
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#define SWITCH_TSS_JMP 0 |
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#define SWITCH_TSS_IRET 1 |
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#define SWITCH_TSS_CALL 2 |
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/* XXX: restore CPU state in registers (PowerPC case) */
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static void switch_tss(CPUX86State *env, int tss_selector, |
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uint32_t e1, uint32_t e2, int source,
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uint32_t next_eip) |
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{ |
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int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
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target_ulong tss_base; |
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uint32_t new_regs[8], new_segs[6]; |
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uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap; |
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uint32_t old_eflags, eflags_mask; |
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SegmentCache *dt; |
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int index;
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target_ulong ptr; |
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type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
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LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
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source); |
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/* if task gate, we read the TSS segment and we load it */
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if (type == 5) { |
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if (!(e2 & DESC_P_MASK)) {
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raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
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} |
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tss_selector = e1 >> 16;
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if (tss_selector & 4) { |
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raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
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} |
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if (load_segment(env, &e1, &e2, tss_selector) != 0) { |
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raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
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} |
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if (e2 & DESC_S_MASK) {
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raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
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} |
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type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
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if ((type & 7) != 1) { |
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raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
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} |
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} |
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if (!(e2 & DESC_P_MASK)) {
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raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
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} |
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if (type & 8) { |
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tss_limit_max = 103;
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} else {
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tss_limit_max = 43;
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} |
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tss_limit = get_seg_limit(e1, e2); |
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tss_base = get_seg_base(e1, e2); |
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if ((tss_selector & 4) != 0 || |
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tss_limit < tss_limit_max) { |
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raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
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} |
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old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
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if (old_type & 8) { |
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old_tss_limit_max = 103;
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} else {
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old_tss_limit_max = 43;
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} |
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/* read all the registers from the new TSS */
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if (type & 8) { |
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/* 32 bit */
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new_cr3 = cpu_ldl_kernel(env, tss_base + 0x1c);
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new_eip = cpu_ldl_kernel(env, tss_base + 0x20);
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new_eflags = cpu_ldl_kernel(env, tss_base + 0x24);
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for (i = 0; i < 8; i++) { |
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new_regs[i] = cpu_ldl_kernel(env, tss_base + (0x28 + i * 4)); |
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} |
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for (i = 0; i < 6; i++) { |
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new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x48 + i * 4)); |
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} |
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new_ldt = cpu_lduw_kernel(env, tss_base + 0x60);
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new_trap = cpu_ldl_kernel(env, tss_base + 0x64);
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} else {
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/* 16 bit */
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new_cr3 = 0;
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new_eip = cpu_lduw_kernel(env, tss_base + 0x0e);
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new_eflags = cpu_lduw_kernel(env, tss_base + 0x10);
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for (i = 0; i < 8; i++) { |
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new_regs[i] = cpu_lduw_kernel(env, tss_base + (0x12 + i * 2)) | |
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0xffff0000;
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} |
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for (i = 0; i < 4; i++) { |
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new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x22 + i * 4)); |
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} |
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new_ldt = cpu_lduw_kernel(env, tss_base + 0x2a);
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new_segs[R_FS] = 0;
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new_segs[R_GS] = 0;
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new_trap = 0;
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} |
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/* XXX: avoid a compiler warning, see
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http://support.amd.com/us/Processor_TechDocs/24593.pdf
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chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
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(void)new_trap;
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/* NOTE: we must avoid memory exceptions during the task switch,
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so we make dummy accesses before */
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/* XXX: it can still fail in some cases, so a bigger hack is
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necessary to valid the TLB after having done the accesses */
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v1 = cpu_ldub_kernel(env, env->tr.base); |
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v2 = cpu_ldub_kernel(env, env->tr.base + old_tss_limit_max); |
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cpu_stb_kernel(env, env->tr.base, v1); |
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cpu_stb_kernel(env, env->tr.base + old_tss_limit_max, v2); |
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/* clear busy bit (it is restartable) */
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if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
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target_ulong ptr; |
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uint32_t e2; |
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ptr = env->gdt.base + (env->tr.selector & ~7);
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e2 = cpu_ldl_kernel(env, ptr + 4);
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e2 &= ~DESC_TSS_BUSY_MASK; |
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cpu_stl_kernel(env, ptr + 4, e2);
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} |
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old_eflags = cpu_compute_eflags(env); |
318 |
if (source == SWITCH_TSS_IRET) {
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old_eflags &= ~NT_MASK; |
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} |
321 |
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/* save the current state in the old TSS */
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if (type & 8) { |
324 |
/* 32 bit */
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cpu_stl_kernel(env, env->tr.base + 0x20, next_eip);
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cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
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cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), EAX); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), ECX); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), EDX); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), EBX); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), ESP); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), EBP); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), ESI); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), EDI); |
335 |
for (i = 0; i < 6; i++) { |
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cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4), |
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env->segs[i].selector); |
338 |
} |
339 |
} else {
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/* 16 bit */
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cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip);
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cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
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cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), EAX); |
344 |
cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), ECX); |
345 |
cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), EDX); |
346 |
cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), EBX); |
347 |
cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), ESP); |
348 |
cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), EBP); |
349 |
cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), ESI); |
350 |
cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), EDI); |
351 |
for (i = 0; i < 4; i++) { |
352 |
cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4), |
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env->segs[i].selector); |
354 |
} |
355 |
} |
356 |
|
357 |
/* now if an exception occurs, it will occurs in the next task
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context */
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359 |
|
360 |
if (source == SWITCH_TSS_CALL) {
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cpu_stw_kernel(env, tss_base, env->tr.selector); |
362 |
new_eflags |= NT_MASK; |
363 |
} |
364 |
|
365 |
/* set busy bit */
|
366 |
if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
|
367 |
target_ulong ptr; |
368 |
uint32_t e2; |
369 |
|
370 |
ptr = env->gdt.base + (tss_selector & ~7);
|
371 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
372 |
e2 |= DESC_TSS_BUSY_MASK; |
373 |
cpu_stl_kernel(env, ptr + 4, e2);
|
374 |
} |
375 |
|
376 |
/* set the new CPU state */
|
377 |
/* from this point, any exception which occurs can give problems */
|
378 |
env->cr[0] |= CR0_TS_MASK;
|
379 |
env->hflags |= HF_TS_MASK; |
380 |
env->tr.selector = tss_selector; |
381 |
env->tr.base = tss_base; |
382 |
env->tr.limit = tss_limit; |
383 |
env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK; |
384 |
|
385 |
if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) { |
386 |
cpu_x86_update_cr3(env, new_cr3); |
387 |
} |
388 |
|
389 |
/* load all registers without an exception, then reload them with
|
390 |
possible exception */
|
391 |
env->eip = new_eip; |
392 |
eflags_mask = TF_MASK | AC_MASK | ID_MASK | |
393 |
IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK; |
394 |
if (!(type & 8)) { |
395 |
eflags_mask &= 0xffff;
|
396 |
} |
397 |
cpu_load_eflags(env, new_eflags, eflags_mask); |
398 |
/* XXX: what to do in 16 bit case? */
|
399 |
EAX = new_regs[0];
|
400 |
ECX = new_regs[1];
|
401 |
EDX = new_regs[2];
|
402 |
EBX = new_regs[3];
|
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ESP = new_regs[4];
|
404 |
EBP = new_regs[5];
|
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ESI = new_regs[6];
|
406 |
EDI = new_regs[7];
|
407 |
if (new_eflags & VM_MASK) {
|
408 |
for (i = 0; i < 6; i++) { |
409 |
load_seg_vm(env, i, new_segs[i]); |
410 |
} |
411 |
/* in vm86, CPL is always 3 */
|
412 |
cpu_x86_set_cpl(env, 3);
|
413 |
} else {
|
414 |
/* CPL is set the RPL of CS */
|
415 |
cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
|
416 |
/* first just selectors as the rest may trigger exceptions */
|
417 |
for (i = 0; i < 6; i++) { |
418 |
cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0); |
419 |
} |
420 |
} |
421 |
|
422 |
env->ldt.selector = new_ldt & ~4;
|
423 |
env->ldt.base = 0;
|
424 |
env->ldt.limit = 0;
|
425 |
env->ldt.flags = 0;
|
426 |
|
427 |
/* load the LDT */
|
428 |
if (new_ldt & 4) { |
429 |
raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
430 |
} |
431 |
|
432 |
if ((new_ldt & 0xfffc) != 0) { |
433 |
dt = &env->gdt; |
434 |
index = new_ldt & ~7;
|
435 |
if ((index + 7) > dt->limit) { |
436 |
raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
437 |
} |
438 |
ptr = dt->base + index; |
439 |
e1 = cpu_ldl_kernel(env, ptr); |
440 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
441 |
if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) { |
442 |
raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
443 |
} |
444 |
if (!(e2 & DESC_P_MASK)) {
|
445 |
raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
446 |
} |
447 |
load_seg_cache_raw_dt(&env->ldt, e1, e2); |
448 |
} |
449 |
|
450 |
/* load the segments */
|
451 |
if (!(new_eflags & VM_MASK)) {
|
452 |
tss_load_seg(env, R_CS, new_segs[R_CS]); |
453 |
tss_load_seg(env, R_SS, new_segs[R_SS]); |
454 |
tss_load_seg(env, R_ES, new_segs[R_ES]); |
455 |
tss_load_seg(env, R_DS, new_segs[R_DS]); |
456 |
tss_load_seg(env, R_FS, new_segs[R_FS]); |
457 |
tss_load_seg(env, R_GS, new_segs[R_GS]); |
458 |
} |
459 |
|
460 |
/* check that EIP is in the CS segment limits */
|
461 |
if (new_eip > env->segs[R_CS].limit) {
|
462 |
/* XXX: different exception if CALL? */
|
463 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
464 |
} |
465 |
|
466 |
#ifndef CONFIG_USER_ONLY
|
467 |
/* reset local breakpoints */
|
468 |
if (env->dr[7] & 0x55) { |
469 |
for (i = 0; i < 4; i++) { |
470 |
if (hw_breakpoint_enabled(env->dr[7], i) == 0x1) { |
471 |
hw_breakpoint_remove(env, i); |
472 |
} |
473 |
} |
474 |
env->dr[7] &= ~0x55; |
475 |
} |
476 |
#endif
|
477 |
} |
478 |
|
479 |
static inline unsigned int get_sp_mask(unsigned int e2) |
480 |
{ |
481 |
if (e2 & DESC_B_MASK) {
|
482 |
return 0xffffffff; |
483 |
} else {
|
484 |
return 0xffff; |
485 |
} |
486 |
} |
487 |
|
488 |
static int exception_has_error_code(int intno) |
489 |
{ |
490 |
switch (intno) {
|
491 |
case 8: |
492 |
case 10: |
493 |
case 11: |
494 |
case 12: |
495 |
case 13: |
496 |
case 14: |
497 |
case 17: |
498 |
return 1; |
499 |
} |
500 |
return 0; |
501 |
} |
502 |
|
503 |
#ifdef TARGET_X86_64
|
504 |
#define SET_ESP(val, sp_mask) \
|
505 |
do { \
|
506 |
if ((sp_mask) == 0xffff) { \ |
507 |
ESP = (ESP & ~0xffff) | ((val) & 0xffff); \ |
508 |
} else if ((sp_mask) == 0xffffffffLL) { \ |
509 |
ESP = (uint32_t)(val); \ |
510 |
} else { \
|
511 |
ESP = (val); \ |
512 |
} \ |
513 |
} while (0) |
514 |
#else
|
515 |
#define SET_ESP(val, sp_mask) \
|
516 |
do { \
|
517 |
ESP = (ESP & ~(sp_mask)) | ((val) & (sp_mask)); \ |
518 |
} while (0) |
519 |
#endif
|
520 |
|
521 |
/* in 64-bit machines, this can overflow. So this segment addition macro
|
522 |
* can be used to trim the value to 32-bit whenever needed */
|
523 |
#define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
|
524 |
|
525 |
/* XXX: add a is_user flag to have proper security support */
|
526 |
#define PUSHW(ssp, sp, sp_mask, val) \
|
527 |
{ \ |
528 |
sp -= 2; \
|
529 |
cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \ |
530 |
} |
531 |
|
532 |
#define PUSHL(ssp, sp, sp_mask, val) \
|
533 |
{ \ |
534 |
sp -= 4; \
|
535 |
cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \ |
536 |
} |
537 |
|
538 |
#define POPW(ssp, sp, sp_mask, val) \
|
539 |
{ \ |
540 |
val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \ |
541 |
sp += 2; \
|
542 |
} |
543 |
|
544 |
#define POPL(ssp, sp, sp_mask, val) \
|
545 |
{ \ |
546 |
val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \ |
547 |
sp += 4; \
|
548 |
} |
549 |
|
550 |
/* protected mode interrupt */
|
551 |
static void do_interrupt_protected(CPUX86State *env, int intno, int is_int, |
552 |
int error_code, unsigned int next_eip, |
553 |
int is_hw)
|
554 |
{ |
555 |
SegmentCache *dt; |
556 |
target_ulong ptr, ssp; |
557 |
int type, dpl, selector, ss_dpl, cpl;
|
558 |
int has_error_code, new_stack, shift;
|
559 |
uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0; |
560 |
uint32_t old_eip, sp_mask; |
561 |
|
562 |
has_error_code = 0;
|
563 |
if (!is_int && !is_hw) {
|
564 |
has_error_code = exception_has_error_code(intno); |
565 |
} |
566 |
if (is_int) {
|
567 |
old_eip = next_eip; |
568 |
} else {
|
569 |
old_eip = env->eip; |
570 |
} |
571 |
|
572 |
dt = &env->idt; |
573 |
if (intno * 8 + 7 > dt->limit) { |
574 |
raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
575 |
} |
576 |
ptr = dt->base + intno * 8;
|
577 |
e1 = cpu_ldl_kernel(env, ptr); |
578 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
579 |
/* check gate type */
|
580 |
type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
|
581 |
switch (type) {
|
582 |
case 5: /* task gate */ |
583 |
/* must do that check here to return the correct error code */
|
584 |
if (!(e2 & DESC_P_MASK)) {
|
585 |
raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2); |
586 |
} |
587 |
switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
|
588 |
if (has_error_code) {
|
589 |
int type;
|
590 |
uint32_t mask; |
591 |
|
592 |
/* push the error code */
|
593 |
type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
|
594 |
shift = type >> 3;
|
595 |
if (env->segs[R_SS].flags & DESC_B_MASK) {
|
596 |
mask = 0xffffffff;
|
597 |
} else {
|
598 |
mask = 0xffff;
|
599 |
} |
600 |
esp = (ESP - (2 << shift)) & mask;
|
601 |
ssp = env->segs[R_SS].base + esp; |
602 |
if (shift) {
|
603 |
cpu_stl_kernel(env, ssp, error_code); |
604 |
} else {
|
605 |
cpu_stw_kernel(env, ssp, error_code); |
606 |
} |
607 |
SET_ESP(esp, mask); |
608 |
} |
609 |
return;
|
610 |
case 6: /* 286 interrupt gate */ |
611 |
case 7: /* 286 trap gate */ |
612 |
case 14: /* 386 interrupt gate */ |
613 |
case 15: /* 386 trap gate */ |
614 |
break;
|
615 |
default:
|
616 |
raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
617 |
break;
|
618 |
} |
619 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
620 |
cpl = env->hflags & HF_CPL_MASK; |
621 |
/* check privilege if software int */
|
622 |
if (is_int && dpl < cpl) {
|
623 |
raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
624 |
} |
625 |
/* check valid bit */
|
626 |
if (!(e2 & DESC_P_MASK)) {
|
627 |
raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2); |
628 |
} |
629 |
selector = e1 >> 16;
|
630 |
offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); |
631 |
if ((selector & 0xfffc) == 0) { |
632 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
633 |
} |
634 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
635 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
636 |
} |
637 |
if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
|
638 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
639 |
} |
640 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
641 |
if (dpl > cpl) {
|
642 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
643 |
} |
644 |
if (!(e2 & DESC_P_MASK)) {
|
645 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
646 |
} |
647 |
if (!(e2 & DESC_C_MASK) && dpl < cpl) {
|
648 |
/* to inner privilege */
|
649 |
get_ss_esp_from_tss(env, &ss, &esp, dpl); |
650 |
if ((ss & 0xfffc) == 0) { |
651 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
652 |
} |
653 |
if ((ss & 3) != dpl) { |
654 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
655 |
} |
656 |
if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) { |
657 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
658 |
} |
659 |
ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
|
660 |
if (ss_dpl != dpl) {
|
661 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
662 |
} |
663 |
if (!(ss_e2 & DESC_S_MASK) ||
|
664 |
(ss_e2 & DESC_CS_MASK) || |
665 |
!(ss_e2 & DESC_W_MASK)) { |
666 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
667 |
} |
668 |
if (!(ss_e2 & DESC_P_MASK)) {
|
669 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
670 |
} |
671 |
new_stack = 1;
|
672 |
sp_mask = get_sp_mask(ss_e2); |
673 |
ssp = get_seg_base(ss_e1, ss_e2); |
674 |
} else if ((e2 & DESC_C_MASK) || dpl == cpl) { |
675 |
/* to same privilege */
|
676 |
if (env->eflags & VM_MASK) {
|
677 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
678 |
} |
679 |
new_stack = 0;
|
680 |
sp_mask = get_sp_mask(env->segs[R_SS].flags); |
681 |
ssp = env->segs[R_SS].base; |
682 |
esp = ESP; |
683 |
dpl = cpl; |
684 |
} else {
|
685 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
686 |
new_stack = 0; /* avoid warning */ |
687 |
sp_mask = 0; /* avoid warning */ |
688 |
ssp = 0; /* avoid warning */ |
689 |
esp = 0; /* avoid warning */ |
690 |
} |
691 |
|
692 |
shift = type >> 3;
|
693 |
|
694 |
#if 0
|
695 |
/* XXX: check that enough room is available */
|
696 |
push_size = 6 + (new_stack << 2) + (has_error_code << 1);
|
697 |
if (env->eflags & VM_MASK) {
|
698 |
push_size += 8;
|
699 |
}
|
700 |
push_size <<= shift;
|
701 |
#endif
|
702 |
if (shift == 1) { |
703 |
if (new_stack) {
|
704 |
if (env->eflags & VM_MASK) {
|
705 |
PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector); |
706 |
PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector); |
707 |
PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector); |
708 |
PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector); |
709 |
} |
710 |
PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector); |
711 |
PUSHL(ssp, esp, sp_mask, ESP); |
712 |
} |
713 |
PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env)); |
714 |
PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector); |
715 |
PUSHL(ssp, esp, sp_mask, old_eip); |
716 |
if (has_error_code) {
|
717 |
PUSHL(ssp, esp, sp_mask, error_code); |
718 |
} |
719 |
} else {
|
720 |
if (new_stack) {
|
721 |
if (env->eflags & VM_MASK) {
|
722 |
PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector); |
723 |
PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector); |
724 |
PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector); |
725 |
PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector); |
726 |
} |
727 |
PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector); |
728 |
PUSHW(ssp, esp, sp_mask, ESP); |
729 |
} |
730 |
PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env)); |
731 |
PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector); |
732 |
PUSHW(ssp, esp, sp_mask, old_eip); |
733 |
if (has_error_code) {
|
734 |
PUSHW(ssp, esp, sp_mask, error_code); |
735 |
} |
736 |
} |
737 |
|
738 |
if (new_stack) {
|
739 |
if (env->eflags & VM_MASK) {
|
740 |
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0); |
741 |
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0); |
742 |
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0); |
743 |
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0); |
744 |
} |
745 |
ss = (ss & ~3) | dpl;
|
746 |
cpu_x86_load_seg_cache(env, R_SS, ss, |
747 |
ssp, get_seg_limit(ss_e1, ss_e2), ss_e2); |
748 |
} |
749 |
SET_ESP(esp, sp_mask); |
750 |
|
751 |
selector = (selector & ~3) | dpl;
|
752 |
cpu_x86_load_seg_cache(env, R_CS, selector, |
753 |
get_seg_base(e1, e2), |
754 |
get_seg_limit(e1, e2), |
755 |
e2); |
756 |
cpu_x86_set_cpl(env, dpl); |
757 |
env->eip = offset; |
758 |
|
759 |
/* interrupt gate clear IF mask */
|
760 |
if ((type & 1) == 0) { |
761 |
env->eflags &= ~IF_MASK; |
762 |
} |
763 |
env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); |
764 |
} |
765 |
|
766 |
#ifdef TARGET_X86_64
|
767 |
|
768 |
#define PUSHQ(sp, val) \
|
769 |
{ \ |
770 |
sp -= 8; \
|
771 |
cpu_stq_kernel(env, sp, (val)); \ |
772 |
} |
773 |
|
774 |
#define POPQ(sp, val) \
|
775 |
{ \ |
776 |
val = cpu_ldq_kernel(env, sp); \ |
777 |
sp += 8; \
|
778 |
} |
779 |
|
780 |
static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) |
781 |
{ |
782 |
int index;
|
783 |
|
784 |
#if 0
|
785 |
printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
|
786 |
env->tr.base, env->tr.limit);
|
787 |
#endif
|
788 |
|
789 |
if (!(env->tr.flags & DESC_P_MASK)) {
|
790 |
cpu_abort(env, "invalid tss");
|
791 |
} |
792 |
index = 8 * level + 4; |
793 |
if ((index + 7) > env->tr.limit) { |
794 |
raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
|
795 |
} |
796 |
return cpu_ldq_kernel(env, env->tr.base + index);
|
797 |
} |
798 |
|
799 |
/* 64 bit interrupt */
|
800 |
static void do_interrupt64(CPUX86State *env, int intno, int is_int, |
801 |
int error_code, target_ulong next_eip, int is_hw) |
802 |
{ |
803 |
SegmentCache *dt; |
804 |
target_ulong ptr; |
805 |
int type, dpl, selector, cpl, ist;
|
806 |
int has_error_code, new_stack;
|
807 |
uint32_t e1, e2, e3, ss; |
808 |
target_ulong old_eip, esp, offset; |
809 |
|
810 |
has_error_code = 0;
|
811 |
if (!is_int && !is_hw) {
|
812 |
has_error_code = exception_has_error_code(intno); |
813 |
} |
814 |
if (is_int) {
|
815 |
old_eip = next_eip; |
816 |
} else {
|
817 |
old_eip = env->eip; |
818 |
} |
819 |
|
820 |
dt = &env->idt; |
821 |
if (intno * 16 + 15 > dt->limit) { |
822 |
raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
823 |
} |
824 |
ptr = dt->base + intno * 16;
|
825 |
e1 = cpu_ldl_kernel(env, ptr); |
826 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
827 |
e3 = cpu_ldl_kernel(env, ptr + 8);
|
828 |
/* check gate type */
|
829 |
type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
|
830 |
switch (type) {
|
831 |
case 14: /* 386 interrupt gate */ |
832 |
case 15: /* 386 trap gate */ |
833 |
break;
|
834 |
default:
|
835 |
raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
836 |
break;
|
837 |
} |
838 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
839 |
cpl = env->hflags & HF_CPL_MASK; |
840 |
/* check privilege if software int */
|
841 |
if (is_int && dpl < cpl) {
|
842 |
raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
843 |
} |
844 |
/* check valid bit */
|
845 |
if (!(e2 & DESC_P_MASK)) {
|
846 |
raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2); |
847 |
} |
848 |
selector = e1 >> 16;
|
849 |
offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff); |
850 |
ist = e2 & 7;
|
851 |
if ((selector & 0xfffc) == 0) { |
852 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
853 |
} |
854 |
|
855 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
856 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
857 |
} |
858 |
if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
|
859 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
860 |
} |
861 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
862 |
if (dpl > cpl) {
|
863 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
864 |
} |
865 |
if (!(e2 & DESC_P_MASK)) {
|
866 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
867 |
} |
868 |
if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
|
869 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
870 |
} |
871 |
if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) { |
872 |
/* to inner privilege */
|
873 |
if (ist != 0) { |
874 |
esp = get_rsp_from_tss(env, ist + 3);
|
875 |
} else {
|
876 |
esp = get_rsp_from_tss(env, dpl); |
877 |
} |
878 |
esp &= ~0xfLL; /* align stack */ |
879 |
ss = 0;
|
880 |
new_stack = 1;
|
881 |
} else if ((e2 & DESC_C_MASK) || dpl == cpl) { |
882 |
/* to same privilege */
|
883 |
if (env->eflags & VM_MASK) {
|
884 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
885 |
} |
886 |
new_stack = 0;
|
887 |
if (ist != 0) { |
888 |
esp = get_rsp_from_tss(env, ist + 3);
|
889 |
} else {
|
890 |
esp = ESP; |
891 |
} |
892 |
esp &= ~0xfLL; /* align stack */ |
893 |
dpl = cpl; |
894 |
} else {
|
895 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
896 |
new_stack = 0; /* avoid warning */ |
897 |
esp = 0; /* avoid warning */ |
898 |
} |
899 |
|
900 |
PUSHQ(esp, env->segs[R_SS].selector); |
901 |
PUSHQ(esp, ESP); |
902 |
PUSHQ(esp, cpu_compute_eflags(env)); |
903 |
PUSHQ(esp, env->segs[R_CS].selector); |
904 |
PUSHQ(esp, old_eip); |
905 |
if (has_error_code) {
|
906 |
PUSHQ(esp, error_code); |
907 |
} |
908 |
|
909 |
if (new_stack) {
|
910 |
ss = 0 | dpl;
|
911 |
cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0); |
912 |
} |
913 |
ESP = esp; |
914 |
|
915 |
selector = (selector & ~3) | dpl;
|
916 |
cpu_x86_load_seg_cache(env, R_CS, selector, |
917 |
get_seg_base(e1, e2), |
918 |
get_seg_limit(e1, e2), |
919 |
e2); |
920 |
cpu_x86_set_cpl(env, dpl); |
921 |
env->eip = offset; |
922 |
|
923 |
/* interrupt gate clear IF mask */
|
924 |
if ((type & 1) == 0) { |
925 |
env->eflags &= ~IF_MASK; |
926 |
} |
927 |
env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); |
928 |
} |
929 |
#endif
|
930 |
|
931 |
#ifdef TARGET_X86_64
|
932 |
#if defined(CONFIG_USER_ONLY)
|
933 |
void helper_syscall(CPUX86State *env, int next_eip_addend) |
934 |
{ |
935 |
env->exception_index = EXCP_SYSCALL; |
936 |
env->exception_next_eip = env->eip + next_eip_addend; |
937 |
cpu_loop_exit(env); |
938 |
} |
939 |
#else
|
940 |
void helper_syscall(CPUX86State *env, int next_eip_addend) |
941 |
{ |
942 |
int selector;
|
943 |
|
944 |
if (!(env->efer & MSR_EFER_SCE)) {
|
945 |
raise_exception_err(env, EXCP06_ILLOP, 0);
|
946 |
} |
947 |
selector = (env->star >> 32) & 0xffff; |
948 |
if (env->hflags & HF_LMA_MASK) {
|
949 |
int code64;
|
950 |
|
951 |
ECX = env->eip + next_eip_addend; |
952 |
env->regs[11] = cpu_compute_eflags(env);
|
953 |
|
954 |
code64 = env->hflags & HF_CS64_MASK; |
955 |
|
956 |
cpu_x86_set_cpl(env, 0);
|
957 |
cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
|
958 |
0, 0xffffffff, |
959 |
DESC_G_MASK | DESC_P_MASK | |
960 |
DESC_S_MASK | |
961 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
962 |
DESC_L_MASK); |
963 |
cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
964 |
0, 0xffffffff, |
965 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
966 |
DESC_S_MASK | |
967 |
DESC_W_MASK | DESC_A_MASK); |
968 |
env->eflags &= ~env->fmask; |
969 |
cpu_load_eflags(env, env->eflags, 0);
|
970 |
if (code64) {
|
971 |
env->eip = env->lstar; |
972 |
} else {
|
973 |
env->eip = env->cstar; |
974 |
} |
975 |
} else {
|
976 |
ECX = (uint32_t)(env->eip + next_eip_addend); |
977 |
|
978 |
cpu_x86_set_cpl(env, 0);
|
979 |
cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
|
980 |
0, 0xffffffff, |
981 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
982 |
DESC_S_MASK | |
983 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
984 |
cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
985 |
0, 0xffffffff, |
986 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
987 |
DESC_S_MASK | |
988 |
DESC_W_MASK | DESC_A_MASK); |
989 |
env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK); |
990 |
env->eip = (uint32_t)env->star; |
991 |
} |
992 |
} |
993 |
#endif
|
994 |
#endif
|
995 |
|
996 |
#ifdef TARGET_X86_64
|
997 |
void helper_sysret(CPUX86State *env, int dflag) |
998 |
{ |
999 |
int cpl, selector;
|
1000 |
|
1001 |
if (!(env->efer & MSR_EFER_SCE)) {
|
1002 |
raise_exception_err(env, EXCP06_ILLOP, 0);
|
1003 |
} |
1004 |
cpl = env->hflags & HF_CPL_MASK; |
1005 |
if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) { |
1006 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1007 |
} |
1008 |
selector = (env->star >> 48) & 0xffff; |
1009 |
if (env->hflags & HF_LMA_MASK) {
|
1010 |
if (dflag == 2) { |
1011 |
cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3, |
1012 |
0, 0xffffffff, |
1013 |
DESC_G_MASK | DESC_P_MASK | |
1014 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
1015 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
1016 |
DESC_L_MASK); |
1017 |
env->eip = ECX; |
1018 |
} else {
|
1019 |
cpu_x86_load_seg_cache(env, R_CS, selector | 3,
|
1020 |
0, 0xffffffff, |
1021 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
1022 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
1023 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
1024 |
env->eip = (uint32_t)ECX; |
1025 |
} |
1026 |
cpu_x86_load_seg_cache(env, R_SS, selector + 8,
|
1027 |
0, 0xffffffff, |
1028 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
1029 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
1030 |
DESC_W_MASK | DESC_A_MASK); |
1031 |
cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
|
1032 |
| ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | |
1033 |
NT_MASK); |
1034 |
cpu_x86_set_cpl(env, 3);
|
1035 |
} else {
|
1036 |
cpu_x86_load_seg_cache(env, R_CS, selector | 3,
|
1037 |
0, 0xffffffff, |
1038 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
1039 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
1040 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
1041 |
env->eip = (uint32_t)ECX; |
1042 |
cpu_x86_load_seg_cache(env, R_SS, selector + 8,
|
1043 |
0, 0xffffffff, |
1044 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
1045 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
1046 |
DESC_W_MASK | DESC_A_MASK); |
1047 |
env->eflags |= IF_MASK; |
1048 |
cpu_x86_set_cpl(env, 3);
|
1049 |
} |
1050 |
} |
1051 |
#endif
|
1052 |
|
1053 |
/* real mode interrupt */
|
1054 |
static void do_interrupt_real(CPUX86State *env, int intno, int is_int, |
1055 |
int error_code, unsigned int next_eip) |
1056 |
{ |
1057 |
SegmentCache *dt; |
1058 |
target_ulong ptr, ssp; |
1059 |
int selector;
|
1060 |
uint32_t offset, esp; |
1061 |
uint32_t old_cs, old_eip; |
1062 |
|
1063 |
/* real mode (simpler!) */
|
1064 |
dt = &env->idt; |
1065 |
if (intno * 4 + 3 > dt->limit) { |
1066 |
raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
1067 |
} |
1068 |
ptr = dt->base + intno * 4;
|
1069 |
offset = cpu_lduw_kernel(env, ptr); |
1070 |
selector = cpu_lduw_kernel(env, ptr + 2);
|
1071 |
esp = ESP; |
1072 |
ssp = env->segs[R_SS].base; |
1073 |
if (is_int) {
|
1074 |
old_eip = next_eip; |
1075 |
} else {
|
1076 |
old_eip = env->eip; |
1077 |
} |
1078 |
old_cs = env->segs[R_CS].selector; |
1079 |
/* XXX: use SS segment size? */
|
1080 |
PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
|
1081 |
PUSHW(ssp, esp, 0xffff, old_cs);
|
1082 |
PUSHW(ssp, esp, 0xffff, old_eip);
|
1083 |
|
1084 |
/* update processor state */
|
1085 |
ESP = (ESP & ~0xffff) | (esp & 0xffff); |
1086 |
env->eip = offset; |
1087 |
env->segs[R_CS].selector = selector; |
1088 |
env->segs[R_CS].base = (selector << 4);
|
1089 |
env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK); |
1090 |
} |
1091 |
|
1092 |
#if defined(CONFIG_USER_ONLY)
|
1093 |
/* fake user mode interrupt */
|
1094 |
static void do_interrupt_user(CPUX86State *env, int intno, int is_int, |
1095 |
int error_code, target_ulong next_eip)
|
1096 |
{ |
1097 |
SegmentCache *dt; |
1098 |
target_ulong ptr; |
1099 |
int dpl, cpl, shift;
|
1100 |
uint32_t e2; |
1101 |
|
1102 |
dt = &env->idt; |
1103 |
if (env->hflags & HF_LMA_MASK) {
|
1104 |
shift = 4;
|
1105 |
} else {
|
1106 |
shift = 3;
|
1107 |
} |
1108 |
ptr = dt->base + (intno << shift); |
1109 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
1110 |
|
1111 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1112 |
cpl = env->hflags & HF_CPL_MASK; |
1113 |
/* check privilege if software int */
|
1114 |
if (is_int && dpl < cpl) {
|
1115 |
raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2);
|
1116 |
} |
1117 |
|
1118 |
/* Since we emulate only user space, we cannot do more than
|
1119 |
exiting the emulation with the suitable exception and error
|
1120 |
code */
|
1121 |
if (is_int) {
|
1122 |
EIP = next_eip; |
1123 |
} |
1124 |
} |
1125 |
|
1126 |
#else
|
1127 |
|
1128 |
static void handle_even_inj(CPUX86State *env, int intno, int is_int, |
1129 |
int error_code, int is_hw, int rm) |
1130 |
{ |
1131 |
uint32_t event_inj = ldl_phys(env->vm_vmcb + offsetof(struct vmcb,
|
1132 |
control.event_inj)); |
1133 |
|
1134 |
if (!(event_inj & SVM_EVTINJ_VALID)) {
|
1135 |
int type;
|
1136 |
|
1137 |
if (is_int) {
|
1138 |
type = SVM_EVTINJ_TYPE_SOFT; |
1139 |
} else {
|
1140 |
type = SVM_EVTINJ_TYPE_EXEPT; |
1141 |
} |
1142 |
event_inj = intno | type | SVM_EVTINJ_VALID; |
1143 |
if (!rm && exception_has_error_code(intno)) {
|
1144 |
event_inj |= SVM_EVTINJ_VALID_ERR; |
1145 |
stl_phys(env->vm_vmcb + offsetof(struct vmcb,
|
1146 |
control.event_inj_err), |
1147 |
error_code); |
1148 |
} |
1149 |
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
|
1150 |
event_inj); |
1151 |
} |
1152 |
} |
1153 |
#endif
|
1154 |
|
1155 |
/*
|
1156 |
* Begin execution of an interruption. is_int is TRUE if coming from
|
1157 |
* the int instruction. next_eip is the EIP value AFTER the interrupt
|
1158 |
* instruction. It is only relevant if is_int is TRUE.
|
1159 |
*/
|
1160 |
static void do_interrupt_all(CPUX86State *env, int intno, int is_int, |
1161 |
int error_code, target_ulong next_eip, int is_hw) |
1162 |
{ |
1163 |
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
1164 |
if ((env->cr[0] & CR0_PE_MASK)) { |
1165 |
static int count; |
1166 |
|
1167 |
qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
|
1168 |
" pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx, |
1169 |
count, intno, error_code, is_int, |
1170 |
env->hflags & HF_CPL_MASK, |
1171 |
env->segs[R_CS].selector, EIP, |
1172 |
(int)env->segs[R_CS].base + EIP,
|
1173 |
env->segs[R_SS].selector, ESP); |
1174 |
if (intno == 0x0e) { |
1175 |
qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]); |
1176 |
} else {
|
1177 |
qemu_log(" EAX=" TARGET_FMT_lx, EAX);
|
1178 |
} |
1179 |
qemu_log("\n");
|
1180 |
log_cpu_state(env, CPU_DUMP_CCOP); |
1181 |
#if 0
|
1182 |
{
|
1183 |
int i;
|
1184 |
target_ulong ptr;
|
1185 |
|
1186 |
qemu_log(" code=");
|
1187 |
ptr = env->segs[R_CS].base + env->eip;
|
1188 |
for (i = 0; i < 16; i++) {
|
1189 |
qemu_log(" %02x", ldub(ptr + i));
|
1190 |
}
|
1191 |
qemu_log("\n");
|
1192 |
}
|
1193 |
#endif
|
1194 |
count++; |
1195 |
} |
1196 |
} |
1197 |
if (env->cr[0] & CR0_PE_MASK) { |
1198 |
#if !defined(CONFIG_USER_ONLY)
|
1199 |
if (env->hflags & HF_SVMI_MASK) {
|
1200 |
handle_even_inj(env, intno, is_int, error_code, is_hw, 0);
|
1201 |
} |
1202 |
#endif
|
1203 |
#ifdef TARGET_X86_64
|
1204 |
if (env->hflags & HF_LMA_MASK) {
|
1205 |
do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw); |
1206 |
} else
|
1207 |
#endif
|
1208 |
{ |
1209 |
do_interrupt_protected(env, intno, is_int, error_code, next_eip, |
1210 |
is_hw); |
1211 |
} |
1212 |
} else {
|
1213 |
#if !defined(CONFIG_USER_ONLY)
|
1214 |
if (env->hflags & HF_SVMI_MASK) {
|
1215 |
handle_even_inj(env, intno, is_int, error_code, is_hw, 1);
|
1216 |
} |
1217 |
#endif
|
1218 |
do_interrupt_real(env, intno, is_int, error_code, next_eip); |
1219 |
} |
1220 |
|
1221 |
#if !defined(CONFIG_USER_ONLY)
|
1222 |
if (env->hflags & HF_SVMI_MASK) {
|
1223 |
uint32_t event_inj = ldl_phys(env->vm_vmcb + |
1224 |
offsetof(struct vmcb,
|
1225 |
control.event_inj)); |
1226 |
|
1227 |
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
|
1228 |
event_inj & ~SVM_EVTINJ_VALID); |
1229 |
} |
1230 |
#endif
|
1231 |
} |
1232 |
|
1233 |
void do_interrupt(CPUX86State *env)
|
1234 |
{ |
1235 |
#if defined(CONFIG_USER_ONLY)
|
1236 |
/* if user mode only, we simulate a fake exception
|
1237 |
which will be handled outside the cpu execution
|
1238 |
loop */
|
1239 |
do_interrupt_user(env, env->exception_index, |
1240 |
env->exception_is_int, |
1241 |
env->error_code, |
1242 |
env->exception_next_eip); |
1243 |
/* successfully delivered */
|
1244 |
env->old_exception = -1;
|
1245 |
#else
|
1246 |
/* simulate a real cpu exception. On i386, it can
|
1247 |
trigger new exceptions, but we do not handle
|
1248 |
double or triple faults yet. */
|
1249 |
do_interrupt_all(env, env->exception_index, |
1250 |
env->exception_is_int, |
1251 |
env->error_code, |
1252 |
env->exception_next_eip, 0);
|
1253 |
/* successfully delivered */
|
1254 |
env->old_exception = -1;
|
1255 |
#endif
|
1256 |
} |
1257 |
|
1258 |
void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) |
1259 |
{ |
1260 |
do_interrupt_all(env, intno, 0, 0, 0, is_hw); |
1261 |
} |
1262 |
|
1263 |
void helper_enter_level(CPUX86State *env, int level, int data32, |
1264 |
target_ulong t1) |
1265 |
{ |
1266 |
target_ulong ssp; |
1267 |
uint32_t esp_mask, esp, ebp; |
1268 |
|
1269 |
esp_mask = get_sp_mask(env->segs[R_SS].flags); |
1270 |
ssp = env->segs[R_SS].base; |
1271 |
ebp = EBP; |
1272 |
esp = ESP; |
1273 |
if (data32) {
|
1274 |
/* 32 bit */
|
1275 |
esp -= 4;
|
1276 |
while (--level) {
|
1277 |
esp -= 4;
|
1278 |
ebp -= 4;
|
1279 |
cpu_stl_data(env, ssp + (esp & esp_mask), |
1280 |
cpu_ldl_data(env, ssp + (ebp & esp_mask))); |
1281 |
} |
1282 |
esp -= 4;
|
1283 |
cpu_stl_data(env, ssp + (esp & esp_mask), t1); |
1284 |
} else {
|
1285 |
/* 16 bit */
|
1286 |
esp -= 2;
|
1287 |
while (--level) {
|
1288 |
esp -= 2;
|
1289 |
ebp -= 2;
|
1290 |
cpu_stw_data(env, ssp + (esp & esp_mask), |
1291 |
cpu_lduw_data(env, ssp + (ebp & esp_mask))); |
1292 |
} |
1293 |
esp -= 2;
|
1294 |
cpu_stw_data(env, ssp + (esp & esp_mask), t1); |
1295 |
} |
1296 |
} |
1297 |
|
1298 |
#ifdef TARGET_X86_64
|
1299 |
void helper_enter64_level(CPUX86State *env, int level, int data64, |
1300 |
target_ulong t1) |
1301 |
{ |
1302 |
target_ulong esp, ebp; |
1303 |
|
1304 |
ebp = EBP; |
1305 |
esp = ESP; |
1306 |
|
1307 |
if (data64) {
|
1308 |
/* 64 bit */
|
1309 |
esp -= 8;
|
1310 |
while (--level) {
|
1311 |
esp -= 8;
|
1312 |
ebp -= 8;
|
1313 |
cpu_stq_data(env, esp, cpu_ldq_data(env, ebp)); |
1314 |
} |
1315 |
esp -= 8;
|
1316 |
cpu_stq_data(env, esp, t1); |
1317 |
} else {
|
1318 |
/* 16 bit */
|
1319 |
esp -= 2;
|
1320 |
while (--level) {
|
1321 |
esp -= 2;
|
1322 |
ebp -= 2;
|
1323 |
cpu_stw_data(env, esp, cpu_lduw_data(env, ebp)); |
1324 |
} |
1325 |
esp -= 2;
|
1326 |
cpu_stw_data(env, esp, t1); |
1327 |
} |
1328 |
} |
1329 |
#endif
|
1330 |
|
1331 |
void helper_lldt(CPUX86State *env, int selector) |
1332 |
{ |
1333 |
SegmentCache *dt; |
1334 |
uint32_t e1, e2; |
1335 |
int index, entry_limit;
|
1336 |
target_ulong ptr; |
1337 |
|
1338 |
selector &= 0xffff;
|
1339 |
if ((selector & 0xfffc) == 0) { |
1340 |
/* XXX: NULL selector case: invalid LDT */
|
1341 |
env->ldt.base = 0;
|
1342 |
env->ldt.limit = 0;
|
1343 |
} else {
|
1344 |
if (selector & 0x4) { |
1345 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1346 |
} |
1347 |
dt = &env->gdt; |
1348 |
index = selector & ~7;
|
1349 |
#ifdef TARGET_X86_64
|
1350 |
if (env->hflags & HF_LMA_MASK) {
|
1351 |
entry_limit = 15;
|
1352 |
} else
|
1353 |
#endif
|
1354 |
{ |
1355 |
entry_limit = 7;
|
1356 |
} |
1357 |
if ((index + entry_limit) > dt->limit) {
|
1358 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1359 |
} |
1360 |
ptr = dt->base + index; |
1361 |
e1 = cpu_ldl_kernel(env, ptr); |
1362 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
1363 |
if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) { |
1364 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1365 |
} |
1366 |
if (!(e2 & DESC_P_MASK)) {
|
1367 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
1368 |
} |
1369 |
#ifdef TARGET_X86_64
|
1370 |
if (env->hflags & HF_LMA_MASK) {
|
1371 |
uint32_t e3; |
1372 |
|
1373 |
e3 = cpu_ldl_kernel(env, ptr + 8);
|
1374 |
load_seg_cache_raw_dt(&env->ldt, e1, e2); |
1375 |
env->ldt.base |= (target_ulong)e3 << 32;
|
1376 |
} else
|
1377 |
#endif
|
1378 |
{ |
1379 |
load_seg_cache_raw_dt(&env->ldt, e1, e2); |
1380 |
} |
1381 |
} |
1382 |
env->ldt.selector = selector; |
1383 |
} |
1384 |
|
1385 |
void helper_ltr(CPUX86State *env, int selector) |
1386 |
{ |
1387 |
SegmentCache *dt; |
1388 |
uint32_t e1, e2; |
1389 |
int index, type, entry_limit;
|
1390 |
target_ulong ptr; |
1391 |
|
1392 |
selector &= 0xffff;
|
1393 |
if ((selector & 0xfffc) == 0) { |
1394 |
/* NULL selector case: invalid TR */
|
1395 |
env->tr.base = 0;
|
1396 |
env->tr.limit = 0;
|
1397 |
env->tr.flags = 0;
|
1398 |
} else {
|
1399 |
if (selector & 0x4) { |
1400 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1401 |
} |
1402 |
dt = &env->gdt; |
1403 |
index = selector & ~7;
|
1404 |
#ifdef TARGET_X86_64
|
1405 |
if (env->hflags & HF_LMA_MASK) {
|
1406 |
entry_limit = 15;
|
1407 |
} else
|
1408 |
#endif
|
1409 |
{ |
1410 |
entry_limit = 7;
|
1411 |
} |
1412 |
if ((index + entry_limit) > dt->limit) {
|
1413 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1414 |
} |
1415 |
ptr = dt->base + index; |
1416 |
e1 = cpu_ldl_kernel(env, ptr); |
1417 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
1418 |
type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
1419 |
if ((e2 & DESC_S_MASK) ||
|
1420 |
(type != 1 && type != 9)) { |
1421 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1422 |
} |
1423 |
if (!(e2 & DESC_P_MASK)) {
|
1424 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
1425 |
} |
1426 |
#ifdef TARGET_X86_64
|
1427 |
if (env->hflags & HF_LMA_MASK) {
|
1428 |
uint32_t e3, e4; |
1429 |
|
1430 |
e3 = cpu_ldl_kernel(env, ptr + 8);
|
1431 |
e4 = cpu_ldl_kernel(env, ptr + 12);
|
1432 |
if ((e4 >> DESC_TYPE_SHIFT) & 0xf) { |
1433 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1434 |
} |
1435 |
load_seg_cache_raw_dt(&env->tr, e1, e2); |
1436 |
env->tr.base |= (target_ulong)e3 << 32;
|
1437 |
} else
|
1438 |
#endif
|
1439 |
{ |
1440 |
load_seg_cache_raw_dt(&env->tr, e1, e2); |
1441 |
} |
1442 |
e2 |= DESC_TSS_BUSY_MASK; |
1443 |
cpu_stl_kernel(env, ptr + 4, e2);
|
1444 |
} |
1445 |
env->tr.selector = selector; |
1446 |
} |
1447 |
|
1448 |
/* only works if protected mode and not VM86. seg_reg must be != R_CS */
|
1449 |
void helper_load_seg(CPUX86State *env, int seg_reg, int selector) |
1450 |
{ |
1451 |
uint32_t e1, e2; |
1452 |
int cpl, dpl, rpl;
|
1453 |
SegmentCache *dt; |
1454 |
int index;
|
1455 |
target_ulong ptr; |
1456 |
|
1457 |
selector &= 0xffff;
|
1458 |
cpl = env->hflags & HF_CPL_MASK; |
1459 |
if ((selector & 0xfffc) == 0) { |
1460 |
/* null selector case */
|
1461 |
if (seg_reg == R_SS
|
1462 |
#ifdef TARGET_X86_64
|
1463 |
&& (!(env->hflags & HF_CS64_MASK) || cpl == 3)
|
1464 |
#endif
|
1465 |
) { |
1466 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1467 |
} |
1468 |
cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0); |
1469 |
} else {
|
1470 |
|
1471 |
if (selector & 0x4) { |
1472 |
dt = &env->ldt; |
1473 |
} else {
|
1474 |
dt = &env->gdt; |
1475 |
} |
1476 |
index = selector & ~7;
|
1477 |
if ((index + 7) > dt->limit) { |
1478 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1479 |
} |
1480 |
ptr = dt->base + index; |
1481 |
e1 = cpu_ldl_kernel(env, ptr); |
1482 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
1483 |
|
1484 |
if (!(e2 & DESC_S_MASK)) {
|
1485 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1486 |
} |
1487 |
rpl = selector & 3;
|
1488 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1489 |
if (seg_reg == R_SS) {
|
1490 |
/* must be writable segment */
|
1491 |
if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
|
1492 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1493 |
} |
1494 |
if (rpl != cpl || dpl != cpl) {
|
1495 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1496 |
} |
1497 |
} else {
|
1498 |
/* must be readable segment */
|
1499 |
if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
|
1500 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1501 |
} |
1502 |
|
1503 |
if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
|
1504 |
/* if not conforming code, test rights */
|
1505 |
if (dpl < cpl || dpl < rpl) {
|
1506 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1507 |
} |
1508 |
} |
1509 |
} |
1510 |
|
1511 |
if (!(e2 & DESC_P_MASK)) {
|
1512 |
if (seg_reg == R_SS) {
|
1513 |
raise_exception_err(env, EXCP0C_STACK, selector & 0xfffc);
|
1514 |
} else {
|
1515 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
1516 |
} |
1517 |
} |
1518 |
|
1519 |
/* set the access bit if not already set */
|
1520 |
if (!(e2 & DESC_A_MASK)) {
|
1521 |
e2 |= DESC_A_MASK; |
1522 |
cpu_stl_kernel(env, ptr + 4, e2);
|
1523 |
} |
1524 |
|
1525 |
cpu_x86_load_seg_cache(env, seg_reg, selector, |
1526 |
get_seg_base(e1, e2), |
1527 |
get_seg_limit(e1, e2), |
1528 |
e2); |
1529 |
#if 0
|
1530 |
qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
|
1531 |
selector, (unsigned long)sc->base, sc->limit, sc->flags);
|
1532 |
#endif
|
1533 |
} |
1534 |
} |
1535 |
|
1536 |
/* protected mode jump */
|
1537 |
void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip, |
1538 |
int next_eip_addend)
|
1539 |
{ |
1540 |
int gate_cs, type;
|
1541 |
uint32_t e1, e2, cpl, dpl, rpl, limit; |
1542 |
target_ulong next_eip; |
1543 |
|
1544 |
if ((new_cs & 0xfffc) == 0) { |
1545 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1546 |
} |
1547 |
if (load_segment(env, &e1, &e2, new_cs) != 0) { |
1548 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1549 |
} |
1550 |
cpl = env->hflags & HF_CPL_MASK; |
1551 |
if (e2 & DESC_S_MASK) {
|
1552 |
if (!(e2 & DESC_CS_MASK)) {
|
1553 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1554 |
} |
1555 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1556 |
if (e2 & DESC_C_MASK) {
|
1557 |
/* conforming code segment */
|
1558 |
if (dpl > cpl) {
|
1559 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1560 |
} |
1561 |
} else {
|
1562 |
/* non conforming code segment */
|
1563 |
rpl = new_cs & 3;
|
1564 |
if (rpl > cpl) {
|
1565 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1566 |
} |
1567 |
if (dpl != cpl) {
|
1568 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1569 |
} |
1570 |
} |
1571 |
if (!(e2 & DESC_P_MASK)) {
|
1572 |
raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
1573 |
} |
1574 |
limit = get_seg_limit(e1, e2); |
1575 |
if (new_eip > limit &&
|
1576 |
!(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) { |
1577 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1578 |
} |
1579 |
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
|
1580 |
get_seg_base(e1, e2), limit, e2); |
1581 |
EIP = new_eip; |
1582 |
} else {
|
1583 |
/* jump to call or task gate */
|
1584 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1585 |
rpl = new_cs & 3;
|
1586 |
cpl = env->hflags & HF_CPL_MASK; |
1587 |
type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
1588 |
switch (type) {
|
1589 |
case 1: /* 286 TSS */ |
1590 |
case 9: /* 386 TSS */ |
1591 |
case 5: /* task gate */ |
1592 |
if (dpl < cpl || dpl < rpl) {
|
1593 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1594 |
} |
1595 |
next_eip = env->eip + next_eip_addend; |
1596 |
switch_tss(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip); |
1597 |
CC_OP = CC_OP_EFLAGS; |
1598 |
break;
|
1599 |
case 4: /* 286 call gate */ |
1600 |
case 12: /* 386 call gate */ |
1601 |
if ((dpl < cpl) || (dpl < rpl)) {
|
1602 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1603 |
} |
1604 |
if (!(e2 & DESC_P_MASK)) {
|
1605 |
raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
1606 |
} |
1607 |
gate_cs = e1 >> 16;
|
1608 |
new_eip = (e1 & 0xffff);
|
1609 |
if (type == 12) { |
1610 |
new_eip |= (e2 & 0xffff0000);
|
1611 |
} |
1612 |
if (load_segment(env, &e1, &e2, gate_cs) != 0) { |
1613 |
raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
1614 |
} |
1615 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1616 |
/* must be code segment */
|
1617 |
if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
|
1618 |
(DESC_S_MASK | DESC_CS_MASK))) { |
1619 |
raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
1620 |
} |
1621 |
if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
|
1622 |
(!(e2 & DESC_C_MASK) && (dpl != cpl))) { |
1623 |
raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
1624 |
} |
1625 |
if (!(e2 & DESC_P_MASK)) {
|
1626 |
raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
1627 |
} |
1628 |
limit = get_seg_limit(e1, e2); |
1629 |
if (new_eip > limit) {
|
1630 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1631 |
} |
1632 |
cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
|
1633 |
get_seg_base(e1, e2), limit, e2); |
1634 |
EIP = new_eip; |
1635 |
break;
|
1636 |
default:
|
1637 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1638 |
break;
|
1639 |
} |
1640 |
} |
1641 |
} |
1642 |
|
1643 |
/* real mode call */
|
1644 |
void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1, |
1645 |
int shift, int next_eip) |
1646 |
{ |
1647 |
int new_eip;
|
1648 |
uint32_t esp, esp_mask; |
1649 |
target_ulong ssp; |
1650 |
|
1651 |
new_eip = new_eip1; |
1652 |
esp = ESP; |
1653 |
esp_mask = get_sp_mask(env->segs[R_SS].flags); |
1654 |
ssp = env->segs[R_SS].base; |
1655 |
if (shift) {
|
1656 |
PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector); |
1657 |
PUSHL(ssp, esp, esp_mask, next_eip); |
1658 |
} else {
|
1659 |
PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector); |
1660 |
PUSHW(ssp, esp, esp_mask, next_eip); |
1661 |
} |
1662 |
|
1663 |
SET_ESP(esp, esp_mask); |
1664 |
env->eip = new_eip; |
1665 |
env->segs[R_CS].selector = new_cs; |
1666 |
env->segs[R_CS].base = (new_cs << 4);
|
1667 |
} |
1668 |
|
1669 |
/* protected mode call */
|
1670 |
void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, |
1671 |
int shift, int next_eip_addend) |
1672 |
{ |
1673 |
int new_stack, i;
|
1674 |
uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count; |
1675 |
uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask; |
1676 |
uint32_t val, limit, old_sp_mask; |
1677 |
target_ulong ssp, old_ssp, next_eip; |
1678 |
|
1679 |
next_eip = env->eip + next_eip_addend; |
1680 |
LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
|
1681 |
LOG_PCALL_STATE(env); |
1682 |
if ((new_cs & 0xfffc) == 0) { |
1683 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1684 |
} |
1685 |
if (load_segment(env, &e1, &e2, new_cs) != 0) { |
1686 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1687 |
} |
1688 |
cpl = env->hflags & HF_CPL_MASK; |
1689 |
LOG_PCALL("desc=%08x:%08x\n", e1, e2);
|
1690 |
if (e2 & DESC_S_MASK) {
|
1691 |
if (!(e2 & DESC_CS_MASK)) {
|
1692 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1693 |
} |
1694 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1695 |
if (e2 & DESC_C_MASK) {
|
1696 |
/* conforming code segment */
|
1697 |
if (dpl > cpl) {
|
1698 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1699 |
} |
1700 |
} else {
|
1701 |
/* non conforming code segment */
|
1702 |
rpl = new_cs & 3;
|
1703 |
if (rpl > cpl) {
|
1704 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1705 |
} |
1706 |
if (dpl != cpl) {
|
1707 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1708 |
} |
1709 |
} |
1710 |
if (!(e2 & DESC_P_MASK)) {
|
1711 |
raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
1712 |
} |
1713 |
|
1714 |
#ifdef TARGET_X86_64
|
1715 |
/* XXX: check 16/32 bit cases in long mode */
|
1716 |
if (shift == 2) { |
1717 |
target_ulong rsp; |
1718 |
|
1719 |
/* 64 bit case */
|
1720 |
rsp = ESP; |
1721 |
PUSHQ(rsp, env->segs[R_CS].selector); |
1722 |
PUSHQ(rsp, next_eip); |
1723 |
/* from this point, not restartable */
|
1724 |
ESP = rsp; |
1725 |
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
|
1726 |
get_seg_base(e1, e2), |
1727 |
get_seg_limit(e1, e2), e2); |
1728 |
EIP = new_eip; |
1729 |
} else
|
1730 |
#endif
|
1731 |
{ |
1732 |
sp = ESP; |
1733 |
sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1734 |
ssp = env->segs[R_SS].base; |
1735 |
if (shift) {
|
1736 |
PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector); |
1737 |
PUSHL(ssp, sp, sp_mask, next_eip); |
1738 |
} else {
|
1739 |
PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector); |
1740 |
PUSHW(ssp, sp, sp_mask, next_eip); |
1741 |
} |
1742 |
|
1743 |
limit = get_seg_limit(e1, e2); |
1744 |
if (new_eip > limit) {
|
1745 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1746 |
} |
1747 |
/* from this point, not restartable */
|
1748 |
SET_ESP(sp, sp_mask); |
1749 |
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
|
1750 |
get_seg_base(e1, e2), limit, e2); |
1751 |
EIP = new_eip; |
1752 |
} |
1753 |
} else {
|
1754 |
/* check gate type */
|
1755 |
type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
|
1756 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1757 |
rpl = new_cs & 3;
|
1758 |
switch (type) {
|
1759 |
case 1: /* available 286 TSS */ |
1760 |
case 9: /* available 386 TSS */ |
1761 |
case 5: /* task gate */ |
1762 |
if (dpl < cpl || dpl < rpl) {
|
1763 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1764 |
} |
1765 |
switch_tss(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip); |
1766 |
CC_OP = CC_OP_EFLAGS; |
1767 |
return;
|
1768 |
case 4: /* 286 call gate */ |
1769 |
case 12: /* 386 call gate */ |
1770 |
break;
|
1771 |
default:
|
1772 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1773 |
break;
|
1774 |
} |
1775 |
shift = type >> 3;
|
1776 |
|
1777 |
if (dpl < cpl || dpl < rpl) {
|
1778 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1779 |
} |
1780 |
/* check valid bit */
|
1781 |
if (!(e2 & DESC_P_MASK)) {
|
1782 |
raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
1783 |
} |
1784 |
selector = e1 >> 16;
|
1785 |
offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); |
1786 |
param_count = e2 & 0x1f;
|
1787 |
if ((selector & 0xfffc) == 0) { |
1788 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1789 |
} |
1790 |
|
1791 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
1792 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1793 |
} |
1794 |
if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
|
1795 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1796 |
} |
1797 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1798 |
if (dpl > cpl) {
|
1799 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1800 |
} |
1801 |
if (!(e2 & DESC_P_MASK)) {
|
1802 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
1803 |
} |
1804 |
|
1805 |
if (!(e2 & DESC_C_MASK) && dpl < cpl) {
|
1806 |
/* to inner privilege */
|
1807 |
get_ss_esp_from_tss(env, &ss, &sp, dpl); |
1808 |
LOG_PCALL("new ss:esp=%04x:%08x param_count=%d ESP=" TARGET_FMT_lx
|
1809 |
"\n",
|
1810 |
ss, sp, param_count, ESP); |
1811 |
if ((ss & 0xfffc) == 0) { |
1812 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1813 |
} |
1814 |
if ((ss & 3) != dpl) { |
1815 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1816 |
} |
1817 |
if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) { |
1818 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1819 |
} |
1820 |
ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
|
1821 |
if (ss_dpl != dpl) {
|
1822 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1823 |
} |
1824 |
if (!(ss_e2 & DESC_S_MASK) ||
|
1825 |
(ss_e2 & DESC_CS_MASK) || |
1826 |
!(ss_e2 & DESC_W_MASK)) { |
1827 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1828 |
} |
1829 |
if (!(ss_e2 & DESC_P_MASK)) {
|
1830 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1831 |
} |
1832 |
|
1833 |
/* push_size = ((param_count * 2) + 8) << shift; */
|
1834 |
|
1835 |
old_sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1836 |
old_ssp = env->segs[R_SS].base; |
1837 |
|
1838 |
sp_mask = get_sp_mask(ss_e2); |
1839 |
ssp = get_seg_base(ss_e1, ss_e2); |
1840 |
if (shift) {
|
1841 |
PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector); |
1842 |
PUSHL(ssp, sp, sp_mask, ESP); |
1843 |
for (i = param_count - 1; i >= 0; i--) { |
1844 |
val = cpu_ldl_kernel(env, old_ssp + ((ESP + i * 4) &
|
1845 |
old_sp_mask)); |
1846 |
PUSHL(ssp, sp, sp_mask, val); |
1847 |
} |
1848 |
} else {
|
1849 |
PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector); |
1850 |
PUSHW(ssp, sp, sp_mask, ESP); |
1851 |
for (i = param_count - 1; i >= 0; i--) { |
1852 |
val = cpu_lduw_kernel(env, old_ssp + ((ESP + i * 2) &
|
1853 |
old_sp_mask)); |
1854 |
PUSHW(ssp, sp, sp_mask, val); |
1855 |
} |
1856 |
} |
1857 |
new_stack = 1;
|
1858 |
} else {
|
1859 |
/* to same privilege */
|
1860 |
sp = ESP; |
1861 |
sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1862 |
ssp = env->segs[R_SS].base; |
1863 |
/* push_size = (4 << shift); */
|
1864 |
new_stack = 0;
|
1865 |
} |
1866 |
|
1867 |
if (shift) {
|
1868 |
PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector); |
1869 |
PUSHL(ssp, sp, sp_mask, next_eip); |
1870 |
} else {
|
1871 |
PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector); |
1872 |
PUSHW(ssp, sp, sp_mask, next_eip); |
1873 |
} |
1874 |
|
1875 |
/* from this point, not restartable */
|
1876 |
|
1877 |
if (new_stack) {
|
1878 |
ss = (ss & ~3) | dpl;
|
1879 |
cpu_x86_load_seg_cache(env, R_SS, ss, |
1880 |
ssp, |
1881 |
get_seg_limit(ss_e1, ss_e2), |
1882 |
ss_e2); |
1883 |
} |
1884 |
|
1885 |
selector = (selector & ~3) | dpl;
|
1886 |
cpu_x86_load_seg_cache(env, R_CS, selector, |
1887 |
get_seg_base(e1, e2), |
1888 |
get_seg_limit(e1, e2), |
1889 |
e2); |
1890 |
cpu_x86_set_cpl(env, dpl); |
1891 |
SET_ESP(sp, sp_mask); |
1892 |
EIP = offset; |
1893 |
} |
1894 |
} |
1895 |
|
1896 |
/* real and vm86 mode iret */
|
1897 |
void helper_iret_real(CPUX86State *env, int shift) |
1898 |
{ |
1899 |
uint32_t sp, new_cs, new_eip, new_eflags, sp_mask; |
1900 |
target_ulong ssp; |
1901 |
int eflags_mask;
|
1902 |
|
1903 |
sp_mask = 0xffff; /* XXXX: use SS segment size? */ |
1904 |
sp = ESP; |
1905 |
ssp = env->segs[R_SS].base; |
1906 |
if (shift == 1) { |
1907 |
/* 32 bits */
|
1908 |
POPL(ssp, sp, sp_mask, new_eip); |
1909 |
POPL(ssp, sp, sp_mask, new_cs); |
1910 |
new_cs &= 0xffff;
|
1911 |
POPL(ssp, sp, sp_mask, new_eflags); |
1912 |
} else {
|
1913 |
/* 16 bits */
|
1914 |
POPW(ssp, sp, sp_mask, new_eip); |
1915 |
POPW(ssp, sp, sp_mask, new_cs); |
1916 |
POPW(ssp, sp, sp_mask, new_eflags); |
1917 |
} |
1918 |
ESP = (ESP & ~sp_mask) | (sp & sp_mask); |
1919 |
env->segs[R_CS].selector = new_cs; |
1920 |
env->segs[R_CS].base = (new_cs << 4);
|
1921 |
env->eip = new_eip; |
1922 |
if (env->eflags & VM_MASK) {
|
1923 |
eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | |
1924 |
NT_MASK; |
1925 |
} else {
|
1926 |
eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | |
1927 |
RF_MASK | NT_MASK; |
1928 |
} |
1929 |
if (shift == 0) { |
1930 |
eflags_mask &= 0xffff;
|
1931 |
} |
1932 |
cpu_load_eflags(env, new_eflags, eflags_mask); |
1933 |
env->hflags2 &= ~HF2_NMI_MASK; |
1934 |
} |
1935 |
|
1936 |
static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl) |
1937 |
{ |
1938 |
int dpl;
|
1939 |
uint32_t e2; |
1940 |
|
1941 |
/* XXX: on x86_64, we do not want to nullify FS and GS because
|
1942 |
they may still contain a valid base. I would be interested to
|
1943 |
know how a real x86_64 CPU behaves */
|
1944 |
if ((seg_reg == R_FS || seg_reg == R_GS) &&
|
1945 |
(env->segs[seg_reg].selector & 0xfffc) == 0) { |
1946 |
return;
|
1947 |
} |
1948 |
|
1949 |
e2 = env->segs[seg_reg].flags; |
1950 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1951 |
if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
|
1952 |
/* data or non conforming code segment */
|
1953 |
if (dpl < cpl) {
|
1954 |
cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0); |
1955 |
} |
1956 |
} |
1957 |
} |
1958 |
|
1959 |
/* protected mode iret */
|
1960 |
static inline void helper_ret_protected(CPUX86State *env, int shift, |
1961 |
int is_iret, int addend) |
1962 |
{ |
1963 |
uint32_t new_cs, new_eflags, new_ss; |
1964 |
uint32_t new_es, new_ds, new_fs, new_gs; |
1965 |
uint32_t e1, e2, ss_e1, ss_e2; |
1966 |
int cpl, dpl, rpl, eflags_mask, iopl;
|
1967 |
target_ulong ssp, sp, new_eip, new_esp, sp_mask; |
1968 |
|
1969 |
#ifdef TARGET_X86_64
|
1970 |
if (shift == 2) { |
1971 |
sp_mask = -1;
|
1972 |
} else
|
1973 |
#endif
|
1974 |
{ |
1975 |
sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1976 |
} |
1977 |
sp = ESP; |
1978 |
ssp = env->segs[R_SS].base; |
1979 |
new_eflags = 0; /* avoid warning */ |
1980 |
#ifdef TARGET_X86_64
|
1981 |
if (shift == 2) { |
1982 |
POPQ(sp, new_eip); |
1983 |
POPQ(sp, new_cs); |
1984 |
new_cs &= 0xffff;
|
1985 |
if (is_iret) {
|
1986 |
POPQ(sp, new_eflags); |
1987 |
} |
1988 |
} else
|
1989 |
#endif
|
1990 |
{ |
1991 |
if (shift == 1) { |
1992 |
/* 32 bits */
|
1993 |
POPL(ssp, sp, sp_mask, new_eip); |
1994 |
POPL(ssp, sp, sp_mask, new_cs); |
1995 |
new_cs &= 0xffff;
|
1996 |
if (is_iret) {
|
1997 |
POPL(ssp, sp, sp_mask, new_eflags); |
1998 |
if (new_eflags & VM_MASK) {
|
1999 |
goto return_to_vm86;
|
2000 |
} |
2001 |
} |
2002 |
} else {
|
2003 |
/* 16 bits */
|
2004 |
POPW(ssp, sp, sp_mask, new_eip); |
2005 |
POPW(ssp, sp, sp_mask, new_cs); |
2006 |
if (is_iret) {
|
2007 |
POPW(ssp, sp, sp_mask, new_eflags); |
2008 |
} |
2009 |
} |
2010 |
} |
2011 |
LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n", |
2012 |
new_cs, new_eip, shift, addend); |
2013 |
LOG_PCALL_STATE(env); |
2014 |
if ((new_cs & 0xfffc) == 0) { |
2015 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2016 |
} |
2017 |
if (load_segment(env, &e1, &e2, new_cs) != 0) { |
2018 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2019 |
} |
2020 |
if (!(e2 & DESC_S_MASK) ||
|
2021 |
!(e2 & DESC_CS_MASK)) { |
2022 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2023 |
} |
2024 |
cpl = env->hflags & HF_CPL_MASK; |
2025 |
rpl = new_cs & 3;
|
2026 |
if (rpl < cpl) {
|
2027 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2028 |
} |
2029 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
2030 |
if (e2 & DESC_C_MASK) {
|
2031 |
if (dpl > rpl) {
|
2032 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2033 |
} |
2034 |
} else {
|
2035 |
if (dpl != rpl) {
|
2036 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2037 |
} |
2038 |
} |
2039 |
if (!(e2 & DESC_P_MASK)) {
|
2040 |
raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
2041 |
} |
2042 |
|
2043 |
sp += addend; |
2044 |
if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
|
2045 |
((env->hflags & HF_CS64_MASK) && !is_iret))) { |
2046 |
/* return to same privilege level */
|
2047 |
cpu_x86_load_seg_cache(env, R_CS, new_cs, |
2048 |
get_seg_base(e1, e2), |
2049 |
get_seg_limit(e1, e2), |
2050 |
e2); |
2051 |
} else {
|
2052 |
/* return to different privilege level */
|
2053 |
#ifdef TARGET_X86_64
|
2054 |
if (shift == 2) { |
2055 |
POPQ(sp, new_esp); |
2056 |
POPQ(sp, new_ss); |
2057 |
new_ss &= 0xffff;
|
2058 |
} else
|
2059 |
#endif
|
2060 |
{ |
2061 |
if (shift == 1) { |
2062 |
/* 32 bits */
|
2063 |
POPL(ssp, sp, sp_mask, new_esp); |
2064 |
POPL(ssp, sp, sp_mask, new_ss); |
2065 |
new_ss &= 0xffff;
|
2066 |
} else {
|
2067 |
/* 16 bits */
|
2068 |
POPW(ssp, sp, sp_mask, new_esp); |
2069 |
POPW(ssp, sp, sp_mask, new_ss); |
2070 |
} |
2071 |
} |
2072 |
LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n", |
2073 |
new_ss, new_esp); |
2074 |
if ((new_ss & 0xfffc) == 0) { |
2075 |
#ifdef TARGET_X86_64
|
2076 |
/* NULL ss is allowed in long mode if cpl != 3 */
|
2077 |
/* XXX: test CS64? */
|
2078 |
if ((env->hflags & HF_LMA_MASK) && rpl != 3) { |
2079 |
cpu_x86_load_seg_cache(env, R_SS, new_ss, |
2080 |
0, 0xffffffff, |
2081 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2082 |
DESC_S_MASK | (rpl << DESC_DPL_SHIFT) | |
2083 |
DESC_W_MASK | DESC_A_MASK); |
2084 |
ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
|
2085 |
} else
|
2086 |
#endif
|
2087 |
{ |
2088 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
2089 |
} |
2090 |
} else {
|
2091 |
if ((new_ss & 3) != rpl) { |
2092 |
raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
2093 |
} |
2094 |
if (load_segment(env, &ss_e1, &ss_e2, new_ss) != 0) { |
2095 |
raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
2096 |
} |
2097 |
if (!(ss_e2 & DESC_S_MASK) ||
|
2098 |
(ss_e2 & DESC_CS_MASK) || |
2099 |
!(ss_e2 & DESC_W_MASK)) { |
2100 |
raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
2101 |
} |
2102 |
dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
|
2103 |
if (dpl != rpl) {
|
2104 |
raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
2105 |
} |
2106 |
if (!(ss_e2 & DESC_P_MASK)) {
|
2107 |
raise_exception_err(env, EXCP0B_NOSEG, new_ss & 0xfffc);
|
2108 |
} |
2109 |
cpu_x86_load_seg_cache(env, R_SS, new_ss, |
2110 |
get_seg_base(ss_e1, ss_e2), |
2111 |
get_seg_limit(ss_e1, ss_e2), |
2112 |
ss_e2); |
2113 |
} |
2114 |
|
2115 |
cpu_x86_load_seg_cache(env, R_CS, new_cs, |
2116 |
get_seg_base(e1, e2), |
2117 |
get_seg_limit(e1, e2), |
2118 |
e2); |
2119 |
cpu_x86_set_cpl(env, rpl); |
2120 |
sp = new_esp; |
2121 |
#ifdef TARGET_X86_64
|
2122 |
if (env->hflags & HF_CS64_MASK) {
|
2123 |
sp_mask = -1;
|
2124 |
} else
|
2125 |
#endif
|
2126 |
{ |
2127 |
sp_mask = get_sp_mask(ss_e2); |
2128 |
} |
2129 |
|
2130 |
/* validate data segments */
|
2131 |
validate_seg(env, R_ES, rpl); |
2132 |
validate_seg(env, R_DS, rpl); |
2133 |
validate_seg(env, R_FS, rpl); |
2134 |
validate_seg(env, R_GS, rpl); |
2135 |
|
2136 |
sp += addend; |
2137 |
} |
2138 |
SET_ESP(sp, sp_mask); |
2139 |
env->eip = new_eip; |
2140 |
if (is_iret) {
|
2141 |
/* NOTE: 'cpl' is the _old_ CPL */
|
2142 |
eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK; |
2143 |
if (cpl == 0) { |
2144 |
eflags_mask |= IOPL_MASK; |
2145 |
} |
2146 |
iopl = (env->eflags >> IOPL_SHIFT) & 3;
|
2147 |
if (cpl <= iopl) {
|
2148 |
eflags_mask |= IF_MASK; |
2149 |
} |
2150 |
if (shift == 0) { |
2151 |
eflags_mask &= 0xffff;
|
2152 |
} |
2153 |
cpu_load_eflags(env, new_eflags, eflags_mask); |
2154 |
} |
2155 |
return;
|
2156 |
|
2157 |
return_to_vm86:
|
2158 |
POPL(ssp, sp, sp_mask, new_esp); |
2159 |
POPL(ssp, sp, sp_mask, new_ss); |
2160 |
POPL(ssp, sp, sp_mask, new_es); |
2161 |
POPL(ssp, sp, sp_mask, new_ds); |
2162 |
POPL(ssp, sp, sp_mask, new_fs); |
2163 |
POPL(ssp, sp, sp_mask, new_gs); |
2164 |
|
2165 |
/* modify processor state */
|
2166 |
cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK | |
2167 |
IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | |
2168 |
VIP_MASK); |
2169 |
load_seg_vm(env, R_CS, new_cs & 0xffff);
|
2170 |
cpu_x86_set_cpl(env, 3);
|
2171 |
load_seg_vm(env, R_SS, new_ss & 0xffff);
|
2172 |
load_seg_vm(env, R_ES, new_es & 0xffff);
|
2173 |
load_seg_vm(env, R_DS, new_ds & 0xffff);
|
2174 |
load_seg_vm(env, R_FS, new_fs & 0xffff);
|
2175 |
load_seg_vm(env, R_GS, new_gs & 0xffff);
|
2176 |
|
2177 |
env->eip = new_eip & 0xffff;
|
2178 |
ESP = new_esp; |
2179 |
} |
2180 |
|
2181 |
void helper_iret_protected(CPUX86State *env, int shift, int next_eip) |
2182 |
{ |
2183 |
int tss_selector, type;
|
2184 |
uint32_t e1, e2; |
2185 |
|
2186 |
/* specific case for TSS */
|
2187 |
if (env->eflags & NT_MASK) {
|
2188 |
#ifdef TARGET_X86_64
|
2189 |
if (env->hflags & HF_LMA_MASK) {
|
2190 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
2191 |
} |
2192 |
#endif
|
2193 |
tss_selector = cpu_lduw_kernel(env, env->tr.base + 0);
|
2194 |
if (tss_selector & 4) { |
2195 |
raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
|
2196 |
} |
2197 |
if (load_segment(env, &e1, &e2, tss_selector) != 0) { |
2198 |
raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
|
2199 |
} |
2200 |
type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
|
2201 |
/* NOTE: we check both segment and busy TSS */
|
2202 |
if (type != 3) { |
2203 |
raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
|
2204 |
} |
2205 |
switch_tss(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip); |
2206 |
} else {
|
2207 |
helper_ret_protected(env, shift, 1, 0); |
2208 |
} |
2209 |
env->hflags2 &= ~HF2_NMI_MASK; |
2210 |
} |
2211 |
|
2212 |
void helper_lret_protected(CPUX86State *env, int shift, int addend) |
2213 |
{ |
2214 |
helper_ret_protected(env, shift, 0, addend);
|
2215 |
} |
2216 |
|
2217 |
void helper_sysenter(CPUX86State *env)
|
2218 |
{ |
2219 |
if (env->sysenter_cs == 0) { |
2220 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
2221 |
} |
2222 |
env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK); |
2223 |
cpu_x86_set_cpl(env, 0);
|
2224 |
|
2225 |
#ifdef TARGET_X86_64
|
2226 |
if (env->hflags & HF_LMA_MASK) {
|
2227 |
cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
|
2228 |
0, 0xffffffff, |
2229 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2230 |
DESC_S_MASK | |
2231 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
2232 |
DESC_L_MASK); |
2233 |
} else
|
2234 |
#endif
|
2235 |
{ |
2236 |
cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
|
2237 |
0, 0xffffffff, |
2238 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2239 |
DESC_S_MASK | |
2240 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
2241 |
} |
2242 |
cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc, |
2243 |
0, 0xffffffff, |
2244 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2245 |
DESC_S_MASK | |
2246 |
DESC_W_MASK | DESC_A_MASK); |
2247 |
ESP = env->sysenter_esp; |
2248 |
EIP = env->sysenter_eip; |
2249 |
} |
2250 |
|
2251 |
void helper_sysexit(CPUX86State *env, int dflag) |
2252 |
{ |
2253 |
int cpl;
|
2254 |
|
2255 |
cpl = env->hflags & HF_CPL_MASK; |
2256 |
if (env->sysenter_cs == 0 || cpl != 0) { |
2257 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
2258 |
} |
2259 |
cpu_x86_set_cpl(env, 3);
|
2260 |
#ifdef TARGET_X86_64
|
2261 |
if (dflag == 2) { |
2262 |
cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) | |
2263 |
3, 0, 0xffffffff, |
2264 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2265 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
2266 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
2267 |
DESC_L_MASK); |
2268 |
cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) | |
2269 |
3, 0, 0xffffffff, |
2270 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2271 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
2272 |
DESC_W_MASK | DESC_A_MASK); |
2273 |
} else
|
2274 |
#endif
|
2275 |
{ |
2276 |
cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | |
2277 |
3, 0, 0xffffffff, |
2278 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2279 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
2280 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
2281 |
cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | |
2282 |
3, 0, 0xffffffff, |
2283 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2284 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
2285 |
DESC_W_MASK | DESC_A_MASK); |
2286 |
} |
2287 |
ESP = ECX; |
2288 |
EIP = EDX; |
2289 |
} |
2290 |
|
2291 |
target_ulong helper_lsl(CPUX86State *env, target_ulong selector1) |
2292 |
{ |
2293 |
unsigned int limit; |
2294 |
uint32_t e1, e2, eflags, selector; |
2295 |
int rpl, dpl, cpl, type;
|
2296 |
|
2297 |
selector = selector1 & 0xffff;
|
2298 |
eflags = cpu_cc_compute_all(env, CC_OP); |
2299 |
if ((selector & 0xfffc) == 0) { |
2300 |
goto fail;
|
2301 |
} |
2302 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
2303 |
goto fail;
|
2304 |
} |
2305 |
rpl = selector & 3;
|
2306 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
2307 |
cpl = env->hflags & HF_CPL_MASK; |
2308 |
if (e2 & DESC_S_MASK) {
|
2309 |
if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
|
2310 |
/* conforming */
|
2311 |
} else {
|
2312 |
if (dpl < cpl || dpl < rpl) {
|
2313 |
goto fail;
|
2314 |
} |
2315 |
} |
2316 |
} else {
|
2317 |
type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
2318 |
switch (type) {
|
2319 |
case 1: |
2320 |
case 2: |
2321 |
case 3: |
2322 |
case 9: |
2323 |
case 11: |
2324 |
break;
|
2325 |
default:
|
2326 |
goto fail;
|
2327 |
} |
2328 |
if (dpl < cpl || dpl < rpl) {
|
2329 |
fail:
|
2330 |
CC_SRC = eflags & ~CC_Z; |
2331 |
return 0; |
2332 |
} |
2333 |
} |
2334 |
limit = get_seg_limit(e1, e2); |
2335 |
CC_SRC = eflags | CC_Z; |
2336 |
return limit;
|
2337 |
} |
2338 |
|
2339 |
target_ulong helper_lar(CPUX86State *env, target_ulong selector1) |
2340 |
{ |
2341 |
uint32_t e1, e2, eflags, selector; |
2342 |
int rpl, dpl, cpl, type;
|
2343 |
|
2344 |
selector = selector1 & 0xffff;
|
2345 |
eflags = cpu_cc_compute_all(env, CC_OP); |
2346 |
if ((selector & 0xfffc) == 0) { |
2347 |
goto fail;
|
2348 |
} |
2349 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
2350 |
goto fail;
|
2351 |
} |
2352 |
rpl = selector & 3;
|
2353 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
2354 |
cpl = env->hflags & HF_CPL_MASK; |
2355 |
if (e2 & DESC_S_MASK) {
|
2356 |
if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
|
2357 |
/* conforming */
|
2358 |
} else {
|
2359 |
if (dpl < cpl || dpl < rpl) {
|
2360 |
goto fail;
|
2361 |
} |
2362 |
} |
2363 |
} else {
|
2364 |
type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
2365 |
switch (type) {
|
2366 |
case 1: |
2367 |
case 2: |
2368 |
case 3: |
2369 |
case 4: |
2370 |
case 5: |
2371 |
case 9: |
2372 |
case 11: |
2373 |
case 12: |
2374 |
break;
|
2375 |
default:
|
2376 |
goto fail;
|
2377 |
} |
2378 |
if (dpl < cpl || dpl < rpl) {
|
2379 |
fail:
|
2380 |
CC_SRC = eflags & ~CC_Z; |
2381 |
return 0; |
2382 |
} |
2383 |
} |
2384 |
CC_SRC = eflags | CC_Z; |
2385 |
return e2 & 0x00f0ff00; |
2386 |
} |
2387 |
|
2388 |
void helper_verr(CPUX86State *env, target_ulong selector1)
|
2389 |
{ |
2390 |
uint32_t e1, e2, eflags, selector; |
2391 |
int rpl, dpl, cpl;
|
2392 |
|
2393 |
selector = selector1 & 0xffff;
|
2394 |
eflags = cpu_cc_compute_all(env, CC_OP); |
2395 |
if ((selector & 0xfffc) == 0) { |
2396 |
goto fail;
|
2397 |
} |
2398 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
2399 |
goto fail;
|
2400 |
} |
2401 |
if (!(e2 & DESC_S_MASK)) {
|
2402 |
goto fail;
|
2403 |
} |
2404 |
rpl = selector & 3;
|
2405 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
2406 |
cpl = env->hflags & HF_CPL_MASK; |
2407 |
if (e2 & DESC_CS_MASK) {
|
2408 |
if (!(e2 & DESC_R_MASK)) {
|
2409 |
goto fail;
|
2410 |
} |
2411 |
if (!(e2 & DESC_C_MASK)) {
|
2412 |
if (dpl < cpl || dpl < rpl) {
|
2413 |
goto fail;
|
2414 |
} |
2415 |
} |
2416 |
} else {
|
2417 |
if (dpl < cpl || dpl < rpl) {
|
2418 |
fail:
|
2419 |
CC_SRC = eflags & ~CC_Z; |
2420 |
return;
|
2421 |
} |
2422 |
} |
2423 |
CC_SRC = eflags | CC_Z; |
2424 |
} |
2425 |
|
2426 |
void helper_verw(CPUX86State *env, target_ulong selector1)
|
2427 |
{ |
2428 |
uint32_t e1, e2, eflags, selector; |
2429 |
int rpl, dpl, cpl;
|
2430 |
|
2431 |
selector = selector1 & 0xffff;
|
2432 |
eflags = cpu_cc_compute_all(env, CC_OP); |
2433 |
if ((selector & 0xfffc) == 0) { |
2434 |
goto fail;
|
2435 |
} |
2436 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
2437 |
goto fail;
|
2438 |
} |
2439 |
if (!(e2 & DESC_S_MASK)) {
|
2440 |
goto fail;
|
2441 |
} |
2442 |
rpl = selector & 3;
|
2443 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
2444 |
cpl = env->hflags & HF_CPL_MASK; |
2445 |
if (e2 & DESC_CS_MASK) {
|
2446 |
goto fail;
|
2447 |
} else {
|
2448 |
if (dpl < cpl || dpl < rpl) {
|
2449 |
goto fail;
|
2450 |
} |
2451 |
if (!(e2 & DESC_W_MASK)) {
|
2452 |
fail:
|
2453 |
CC_SRC = eflags & ~CC_Z; |
2454 |
return;
|
2455 |
} |
2456 |
} |
2457 |
CC_SRC = eflags | CC_Z; |
2458 |
} |
2459 |
|
2460 |
#if defined(CONFIG_USER_ONLY)
|
2461 |
void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector) |
2462 |
{ |
2463 |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
2464 |
selector &= 0xffff;
|
2465 |
cpu_x86_load_seg_cache(env, seg_reg, selector, |
2466 |
(selector << 4), 0xffff, 0); |
2467 |
} else {
|
2468 |
helper_load_seg(env, seg_reg, selector); |
2469 |
} |
2470 |
} |
2471 |
#endif
|