root / cpu-all.h @ 8c99506c
History | View | Annotate | Download (26.1 kB)
1 | 5a9fdfec | bellard | /*
|
---|---|---|---|
2 | 5a9fdfec | bellard | * defines common to all virtual CPUs
|
3 | 5fafdf24 | ths | *
|
4 | 5a9fdfec | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | 5a9fdfec | bellard | *
|
6 | 5a9fdfec | bellard | * This library is free software; you can redistribute it and/or
|
7 | 5a9fdfec | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 5a9fdfec | bellard | * License as published by the Free Software Foundation; either
|
9 | 5a9fdfec | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 5a9fdfec | bellard | *
|
11 | 5a9fdfec | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 5a9fdfec | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 5a9fdfec | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 5a9fdfec | bellard | * Lesser General Public License for more details.
|
15 | 5a9fdfec | bellard | *
|
16 | 5a9fdfec | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 5a9fdfec | bellard | * License along with this library; if not, write to the Free Software
|
18 | 5a9fdfec | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | 5a9fdfec | bellard | */
|
20 | 5a9fdfec | bellard | #ifndef CPU_ALL_H
|
21 | 5a9fdfec | bellard | #define CPU_ALL_H
|
22 | 5a9fdfec | bellard | |
23 | f54b3f92 | aurel32 | #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
|
24 | 0ac4bd56 | bellard | #define WORDS_ALIGNED
|
25 | 0ac4bd56 | bellard | #endif
|
26 | 0ac4bd56 | bellard | |
27 | 5fafdf24 | ths | /* some important defines:
|
28 | 5fafdf24 | ths | *
|
29 | 0ac4bd56 | bellard | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
|
30 | 0ac4bd56 | bellard | * memory accesses.
|
31 | 5fafdf24 | ths | *
|
32 | 0ac4bd56 | bellard | * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
|
33 | 0ac4bd56 | bellard | * otherwise little endian.
|
34 | 5fafdf24 | ths | *
|
35 | 0ac4bd56 | bellard | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
|
36 | 5fafdf24 | ths | *
|
37 | 0ac4bd56 | bellard | * TARGET_WORDS_BIGENDIAN : same for target cpu
|
38 | 0ac4bd56 | bellard | */
|
39 | 0ac4bd56 | bellard | |
40 | f193c797 | bellard | #include "bswap.h" |
41 | 939ef593 | aurel32 | #include "softfloat.h" |
42 | f193c797 | bellard | |
43 | f193c797 | bellard | #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
|
44 | f193c797 | bellard | #define BSWAP_NEEDED
|
45 | f193c797 | bellard | #endif
|
46 | f193c797 | bellard | |
47 | f193c797 | bellard | #ifdef BSWAP_NEEDED
|
48 | f193c797 | bellard | |
49 | f193c797 | bellard | static inline uint16_t tswap16(uint16_t s) |
50 | f193c797 | bellard | { |
51 | f193c797 | bellard | return bswap16(s);
|
52 | f193c797 | bellard | } |
53 | f193c797 | bellard | |
54 | f193c797 | bellard | static inline uint32_t tswap32(uint32_t s) |
55 | f193c797 | bellard | { |
56 | f193c797 | bellard | return bswap32(s);
|
57 | f193c797 | bellard | } |
58 | f193c797 | bellard | |
59 | f193c797 | bellard | static inline uint64_t tswap64(uint64_t s) |
60 | f193c797 | bellard | { |
61 | f193c797 | bellard | return bswap64(s);
|
62 | f193c797 | bellard | } |
63 | f193c797 | bellard | |
64 | f193c797 | bellard | static inline void tswap16s(uint16_t *s) |
65 | f193c797 | bellard | { |
66 | f193c797 | bellard | *s = bswap16(*s); |
67 | f193c797 | bellard | } |
68 | f193c797 | bellard | |
69 | f193c797 | bellard | static inline void tswap32s(uint32_t *s) |
70 | f193c797 | bellard | { |
71 | f193c797 | bellard | *s = bswap32(*s); |
72 | f193c797 | bellard | } |
73 | f193c797 | bellard | |
74 | f193c797 | bellard | static inline void tswap64s(uint64_t *s) |
75 | f193c797 | bellard | { |
76 | f193c797 | bellard | *s = bswap64(*s); |
77 | f193c797 | bellard | } |
78 | f193c797 | bellard | |
79 | f193c797 | bellard | #else
|
80 | f193c797 | bellard | |
81 | f193c797 | bellard | static inline uint16_t tswap16(uint16_t s) |
82 | f193c797 | bellard | { |
83 | f193c797 | bellard | return s;
|
84 | f193c797 | bellard | } |
85 | f193c797 | bellard | |
86 | f193c797 | bellard | static inline uint32_t tswap32(uint32_t s) |
87 | f193c797 | bellard | { |
88 | f193c797 | bellard | return s;
|
89 | f193c797 | bellard | } |
90 | f193c797 | bellard | |
91 | f193c797 | bellard | static inline uint64_t tswap64(uint64_t s) |
92 | f193c797 | bellard | { |
93 | f193c797 | bellard | return s;
|
94 | f193c797 | bellard | } |
95 | f193c797 | bellard | |
96 | f193c797 | bellard | static inline void tswap16s(uint16_t *s) |
97 | f193c797 | bellard | { |
98 | f193c797 | bellard | } |
99 | f193c797 | bellard | |
100 | f193c797 | bellard | static inline void tswap32s(uint32_t *s) |
101 | f193c797 | bellard | { |
102 | f193c797 | bellard | } |
103 | f193c797 | bellard | |
104 | f193c797 | bellard | static inline void tswap64s(uint64_t *s) |
105 | f193c797 | bellard | { |
106 | f193c797 | bellard | } |
107 | f193c797 | bellard | |
108 | f193c797 | bellard | #endif
|
109 | f193c797 | bellard | |
110 | f193c797 | bellard | #if TARGET_LONG_SIZE == 4 |
111 | f193c797 | bellard | #define tswapl(s) tswap32(s)
|
112 | f193c797 | bellard | #define tswapls(s) tswap32s((uint32_t *)(s))
|
113 | 0a962c02 | bellard | #define bswaptls(s) bswap32s(s)
|
114 | f193c797 | bellard | #else
|
115 | f193c797 | bellard | #define tswapl(s) tswap64(s)
|
116 | f193c797 | bellard | #define tswapls(s) tswap64s((uint64_t *)(s))
|
117 | 0a962c02 | bellard | #define bswaptls(s) bswap64s(s)
|
118 | f193c797 | bellard | #endif
|
119 | f193c797 | bellard | |
120 | 0ca9d380 | aurel32 | typedef union { |
121 | 0ca9d380 | aurel32 | float32 f; |
122 | 0ca9d380 | aurel32 | uint32_t l; |
123 | 0ca9d380 | aurel32 | } CPU_FloatU; |
124 | 0ca9d380 | aurel32 | |
125 | 832ed0fa | bellard | /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
|
126 | 832ed0fa | bellard | endian ! */
|
127 | 0ac4bd56 | bellard | typedef union { |
128 | 53cd6637 | bellard | float64 d; |
129 | 9d60cac0 | bellard | #if defined(WORDS_BIGENDIAN) \
|
130 | 9d60cac0 | bellard | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) |
131 | 0ac4bd56 | bellard | struct {
|
132 | 0ac4bd56 | bellard | uint32_t upper; |
133 | 832ed0fa | bellard | uint32_t lower; |
134 | 0ac4bd56 | bellard | } l; |
135 | 0ac4bd56 | bellard | #else
|
136 | 0ac4bd56 | bellard | struct {
|
137 | 0ac4bd56 | bellard | uint32_t lower; |
138 | 832ed0fa | bellard | uint32_t upper; |
139 | 0ac4bd56 | bellard | } l; |
140 | 0ac4bd56 | bellard | #endif
|
141 | 0ac4bd56 | bellard | uint64_t ll; |
142 | 0ac4bd56 | bellard | } CPU_DoubleU; |
143 | 0ac4bd56 | bellard | |
144 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC
|
145 | 1f587329 | blueswir1 | typedef union { |
146 | 1f587329 | blueswir1 | float128 q; |
147 | 1f587329 | blueswir1 | #if defined(WORDS_BIGENDIAN) \
|
148 | 1f587329 | blueswir1 | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) |
149 | 1f587329 | blueswir1 | struct {
|
150 | 1f587329 | blueswir1 | uint32_t upmost; |
151 | 1f587329 | blueswir1 | uint32_t upper; |
152 | 1f587329 | blueswir1 | uint32_t lower; |
153 | 1f587329 | blueswir1 | uint32_t lowest; |
154 | 1f587329 | blueswir1 | } l; |
155 | 1f587329 | blueswir1 | struct {
|
156 | 1f587329 | blueswir1 | uint64_t upper; |
157 | 1f587329 | blueswir1 | uint64_t lower; |
158 | 1f587329 | blueswir1 | } ll; |
159 | 1f587329 | blueswir1 | #else
|
160 | 1f587329 | blueswir1 | struct {
|
161 | 1f587329 | blueswir1 | uint32_t lowest; |
162 | 1f587329 | blueswir1 | uint32_t lower; |
163 | 1f587329 | blueswir1 | uint32_t upper; |
164 | 1f587329 | blueswir1 | uint32_t upmost; |
165 | 1f587329 | blueswir1 | } l; |
166 | 1f587329 | blueswir1 | struct {
|
167 | 1f587329 | blueswir1 | uint64_t lower; |
168 | 1f587329 | blueswir1 | uint64_t upper; |
169 | 1f587329 | blueswir1 | } ll; |
170 | 1f587329 | blueswir1 | #endif
|
171 | 1f587329 | blueswir1 | } CPU_QuadU; |
172 | 1f587329 | blueswir1 | #endif
|
173 | 1f587329 | blueswir1 | |
174 | 61382a50 | bellard | /* CPU memory access without any memory or io remapping */
|
175 | 61382a50 | bellard | |
176 | 83d73968 | bellard | /*
|
177 | 83d73968 | bellard | * the generic syntax for the memory accesses is:
|
178 | 83d73968 | bellard | *
|
179 | 83d73968 | bellard | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
|
180 | 83d73968 | bellard | *
|
181 | 83d73968 | bellard | * store: st{type}{size}{endian}_{access_type}(ptr, val)
|
182 | 83d73968 | bellard | *
|
183 | 83d73968 | bellard | * type is:
|
184 | 83d73968 | bellard | * (empty): integer access
|
185 | 83d73968 | bellard | * f : float access
|
186 | 5fafdf24 | ths | *
|
187 | 83d73968 | bellard | * sign is:
|
188 | 83d73968 | bellard | * (empty): for floats or 32 bit size
|
189 | 83d73968 | bellard | * u : unsigned
|
190 | 83d73968 | bellard | * s : signed
|
191 | 83d73968 | bellard | *
|
192 | 83d73968 | bellard | * size is:
|
193 | 83d73968 | bellard | * b: 8 bits
|
194 | 83d73968 | bellard | * w: 16 bits
|
195 | 83d73968 | bellard | * l: 32 bits
|
196 | 83d73968 | bellard | * q: 64 bits
|
197 | 5fafdf24 | ths | *
|
198 | 83d73968 | bellard | * endian is:
|
199 | 83d73968 | bellard | * (empty): target cpu endianness or 8 bit access
|
200 | 83d73968 | bellard | * r : reversed target cpu endianness (not implemented yet)
|
201 | 83d73968 | bellard | * be : big endian (not implemented yet)
|
202 | 83d73968 | bellard | * le : little endian (not implemented yet)
|
203 | 83d73968 | bellard | *
|
204 | 83d73968 | bellard | * access_type is:
|
205 | 83d73968 | bellard | * raw : host memory access
|
206 | 83d73968 | bellard | * user : user mode access using soft MMU
|
207 | 83d73968 | bellard | * kernel : kernel mode access using soft MMU
|
208 | 83d73968 | bellard | */
|
209 | c27004ec | bellard | static inline int ldub_p(void *ptr) |
210 | 5a9fdfec | bellard | { |
211 | 5a9fdfec | bellard | return *(uint8_t *)ptr;
|
212 | 5a9fdfec | bellard | } |
213 | 5a9fdfec | bellard | |
214 | c27004ec | bellard | static inline int ldsb_p(void *ptr) |
215 | 5a9fdfec | bellard | { |
216 | 5a9fdfec | bellard | return *(int8_t *)ptr;
|
217 | 5a9fdfec | bellard | } |
218 | 5a9fdfec | bellard | |
219 | c27004ec | bellard | static inline void stb_p(void *ptr, int v) |
220 | 5a9fdfec | bellard | { |
221 | 5a9fdfec | bellard | *(uint8_t *)ptr = v; |
222 | 5a9fdfec | bellard | } |
223 | 5a9fdfec | bellard | |
224 | 5a9fdfec | bellard | /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
|
225 | 5a9fdfec | bellard | kernel handles unaligned load/stores may give better results, but
|
226 | 5a9fdfec | bellard | it is a system wide setting : bad */
|
227 | 2df3b95d | bellard | #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
|
228 | 5a9fdfec | bellard | |
229 | 5a9fdfec | bellard | /* conservative code for little endian unaligned accesses */
|
230 | 2df3b95d | bellard | static inline int lduw_le_p(void *ptr) |
231 | 5a9fdfec | bellard | { |
232 | 5a9fdfec | bellard | #ifdef __powerpc__
|
233 | 5a9fdfec | bellard | int val;
|
234 | 5a9fdfec | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
235 | 5a9fdfec | bellard | return val;
|
236 | 5a9fdfec | bellard | #else
|
237 | 5a9fdfec | bellard | uint8_t *p = ptr; |
238 | 5a9fdfec | bellard | return p[0] | (p[1] << 8); |
239 | 5a9fdfec | bellard | #endif
|
240 | 5a9fdfec | bellard | } |
241 | 5a9fdfec | bellard | |
242 | 2df3b95d | bellard | static inline int ldsw_le_p(void *ptr) |
243 | 5a9fdfec | bellard | { |
244 | 5a9fdfec | bellard | #ifdef __powerpc__
|
245 | 5a9fdfec | bellard | int val;
|
246 | 5a9fdfec | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
247 | 5a9fdfec | bellard | return (int16_t)val;
|
248 | 5a9fdfec | bellard | #else
|
249 | 5a9fdfec | bellard | uint8_t *p = ptr; |
250 | 5a9fdfec | bellard | return (int16_t)(p[0] | (p[1] << 8)); |
251 | 5a9fdfec | bellard | #endif
|
252 | 5a9fdfec | bellard | } |
253 | 5a9fdfec | bellard | |
254 | 2df3b95d | bellard | static inline int ldl_le_p(void *ptr) |
255 | 5a9fdfec | bellard | { |
256 | 5a9fdfec | bellard | #ifdef __powerpc__
|
257 | 5a9fdfec | bellard | int val;
|
258 | 5a9fdfec | bellard | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
259 | 5a9fdfec | bellard | return val;
|
260 | 5a9fdfec | bellard | #else
|
261 | 5a9fdfec | bellard | uint8_t *p = ptr; |
262 | 5a9fdfec | bellard | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); |
263 | 5a9fdfec | bellard | #endif
|
264 | 5a9fdfec | bellard | } |
265 | 5a9fdfec | bellard | |
266 | 2df3b95d | bellard | static inline uint64_t ldq_le_p(void *ptr) |
267 | 5a9fdfec | bellard | { |
268 | 5a9fdfec | bellard | uint8_t *p = ptr; |
269 | 5a9fdfec | bellard | uint32_t v1, v2; |
270 | f0aca822 | bellard | v1 = ldl_le_p(p); |
271 | f0aca822 | bellard | v2 = ldl_le_p(p + 4);
|
272 | 5a9fdfec | bellard | return v1 | ((uint64_t)v2 << 32); |
273 | 5a9fdfec | bellard | } |
274 | 5a9fdfec | bellard | |
275 | 2df3b95d | bellard | static inline void stw_le_p(void *ptr, int v) |
276 | 5a9fdfec | bellard | { |
277 | 5a9fdfec | bellard | #ifdef __powerpc__
|
278 | 5a9fdfec | bellard | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); |
279 | 5a9fdfec | bellard | #else
|
280 | 5a9fdfec | bellard | uint8_t *p = ptr; |
281 | 5a9fdfec | bellard | p[0] = v;
|
282 | 5a9fdfec | bellard | p[1] = v >> 8; |
283 | 5a9fdfec | bellard | #endif
|
284 | 5a9fdfec | bellard | } |
285 | 5a9fdfec | bellard | |
286 | 2df3b95d | bellard | static inline void stl_le_p(void *ptr, int v) |
287 | 5a9fdfec | bellard | { |
288 | 5a9fdfec | bellard | #ifdef __powerpc__
|
289 | 5a9fdfec | bellard | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); |
290 | 5a9fdfec | bellard | #else
|
291 | 5a9fdfec | bellard | uint8_t *p = ptr; |
292 | 5a9fdfec | bellard | p[0] = v;
|
293 | 5a9fdfec | bellard | p[1] = v >> 8; |
294 | 5a9fdfec | bellard | p[2] = v >> 16; |
295 | 5a9fdfec | bellard | p[3] = v >> 24; |
296 | 5a9fdfec | bellard | #endif
|
297 | 5a9fdfec | bellard | } |
298 | 5a9fdfec | bellard | |
299 | 2df3b95d | bellard | static inline void stq_le_p(void *ptr, uint64_t v) |
300 | 5a9fdfec | bellard | { |
301 | 5a9fdfec | bellard | uint8_t *p = ptr; |
302 | f0aca822 | bellard | stl_le_p(p, (uint32_t)v); |
303 | f0aca822 | bellard | stl_le_p(p + 4, v >> 32); |
304 | 5a9fdfec | bellard | } |
305 | 5a9fdfec | bellard | |
306 | 5a9fdfec | bellard | /* float access */
|
307 | 5a9fdfec | bellard | |
308 | 2df3b95d | bellard | static inline float32 ldfl_le_p(void *ptr) |
309 | 5a9fdfec | bellard | { |
310 | 5a9fdfec | bellard | union {
|
311 | 53cd6637 | bellard | float32 f; |
312 | 5a9fdfec | bellard | uint32_t i; |
313 | 5a9fdfec | bellard | } u; |
314 | 2df3b95d | bellard | u.i = ldl_le_p(ptr); |
315 | 5a9fdfec | bellard | return u.f;
|
316 | 5a9fdfec | bellard | } |
317 | 5a9fdfec | bellard | |
318 | 2df3b95d | bellard | static inline void stfl_le_p(void *ptr, float32 v) |
319 | 5a9fdfec | bellard | { |
320 | 5a9fdfec | bellard | union {
|
321 | 53cd6637 | bellard | float32 f; |
322 | 5a9fdfec | bellard | uint32_t i; |
323 | 5a9fdfec | bellard | } u; |
324 | 5a9fdfec | bellard | u.f = v; |
325 | 2df3b95d | bellard | stl_le_p(ptr, u.i); |
326 | 5a9fdfec | bellard | } |
327 | 5a9fdfec | bellard | |
328 | 2df3b95d | bellard | static inline float64 ldfq_le_p(void *ptr) |
329 | 5a9fdfec | bellard | { |
330 | 0ac4bd56 | bellard | CPU_DoubleU u; |
331 | 2df3b95d | bellard | u.l.lower = ldl_le_p(ptr); |
332 | 2df3b95d | bellard | u.l.upper = ldl_le_p(ptr + 4);
|
333 | 5a9fdfec | bellard | return u.d;
|
334 | 5a9fdfec | bellard | } |
335 | 5a9fdfec | bellard | |
336 | 2df3b95d | bellard | static inline void stfq_le_p(void *ptr, float64 v) |
337 | 5a9fdfec | bellard | { |
338 | 0ac4bd56 | bellard | CPU_DoubleU u; |
339 | 5a9fdfec | bellard | u.d = v; |
340 | 2df3b95d | bellard | stl_le_p(ptr, u.l.lower); |
341 | 2df3b95d | bellard | stl_le_p(ptr + 4, u.l.upper);
|
342 | 5a9fdfec | bellard | } |
343 | 5a9fdfec | bellard | |
344 | 2df3b95d | bellard | #else
|
345 | 2df3b95d | bellard | |
346 | 2df3b95d | bellard | static inline int lduw_le_p(void *ptr) |
347 | 2df3b95d | bellard | { |
348 | 2df3b95d | bellard | return *(uint16_t *)ptr;
|
349 | 2df3b95d | bellard | } |
350 | 2df3b95d | bellard | |
351 | 2df3b95d | bellard | static inline int ldsw_le_p(void *ptr) |
352 | 2df3b95d | bellard | { |
353 | 2df3b95d | bellard | return *(int16_t *)ptr;
|
354 | 2df3b95d | bellard | } |
355 | 93ac68bc | bellard | |
356 | 2df3b95d | bellard | static inline int ldl_le_p(void *ptr) |
357 | 2df3b95d | bellard | { |
358 | 2df3b95d | bellard | return *(uint32_t *)ptr;
|
359 | 2df3b95d | bellard | } |
360 | 2df3b95d | bellard | |
361 | 2df3b95d | bellard | static inline uint64_t ldq_le_p(void *ptr) |
362 | 2df3b95d | bellard | { |
363 | 2df3b95d | bellard | return *(uint64_t *)ptr;
|
364 | 2df3b95d | bellard | } |
365 | 2df3b95d | bellard | |
366 | 2df3b95d | bellard | static inline void stw_le_p(void *ptr, int v) |
367 | 2df3b95d | bellard | { |
368 | 2df3b95d | bellard | *(uint16_t *)ptr = v; |
369 | 2df3b95d | bellard | } |
370 | 2df3b95d | bellard | |
371 | 2df3b95d | bellard | static inline void stl_le_p(void *ptr, int v) |
372 | 2df3b95d | bellard | { |
373 | 2df3b95d | bellard | *(uint32_t *)ptr = v; |
374 | 2df3b95d | bellard | } |
375 | 2df3b95d | bellard | |
376 | 2df3b95d | bellard | static inline void stq_le_p(void *ptr, uint64_t v) |
377 | 2df3b95d | bellard | { |
378 | 2df3b95d | bellard | *(uint64_t *)ptr = v; |
379 | 2df3b95d | bellard | } |
380 | 2df3b95d | bellard | |
381 | 2df3b95d | bellard | /* float access */
|
382 | 2df3b95d | bellard | |
383 | 2df3b95d | bellard | static inline float32 ldfl_le_p(void *ptr) |
384 | 2df3b95d | bellard | { |
385 | 2df3b95d | bellard | return *(float32 *)ptr;
|
386 | 2df3b95d | bellard | } |
387 | 2df3b95d | bellard | |
388 | 2df3b95d | bellard | static inline float64 ldfq_le_p(void *ptr) |
389 | 2df3b95d | bellard | { |
390 | 2df3b95d | bellard | return *(float64 *)ptr;
|
391 | 2df3b95d | bellard | } |
392 | 2df3b95d | bellard | |
393 | 2df3b95d | bellard | static inline void stfl_le_p(void *ptr, float32 v) |
394 | 2df3b95d | bellard | { |
395 | 2df3b95d | bellard | *(float32 *)ptr = v; |
396 | 2df3b95d | bellard | } |
397 | 2df3b95d | bellard | |
398 | 2df3b95d | bellard | static inline void stfq_le_p(void *ptr, float64 v) |
399 | 2df3b95d | bellard | { |
400 | 2df3b95d | bellard | *(float64 *)ptr = v; |
401 | 2df3b95d | bellard | } |
402 | 2df3b95d | bellard | #endif
|
403 | 2df3b95d | bellard | |
404 | 2df3b95d | bellard | #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
|
405 | 2df3b95d | bellard | |
406 | 2df3b95d | bellard | static inline int lduw_be_p(void *ptr) |
407 | 93ac68bc | bellard | { |
408 | 83d73968 | bellard | #if defined(__i386__)
|
409 | 83d73968 | bellard | int val;
|
410 | 83d73968 | bellard | asm volatile ("movzwl %1, %0\n" |
411 | 83d73968 | bellard | "xchgb %b0, %h0\n"
|
412 | 83d73968 | bellard | : "=q" (val)
|
413 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr));
|
414 | 83d73968 | bellard | return val;
|
415 | 83d73968 | bellard | #else
|
416 | 93ac68bc | bellard | uint8_t *b = (uint8_t *) ptr; |
417 | 83d73968 | bellard | return ((b[0] << 8) | b[1]); |
418 | 83d73968 | bellard | #endif
|
419 | 93ac68bc | bellard | } |
420 | 93ac68bc | bellard | |
421 | 2df3b95d | bellard | static inline int ldsw_be_p(void *ptr) |
422 | 93ac68bc | bellard | { |
423 | 83d73968 | bellard | #if defined(__i386__)
|
424 | 83d73968 | bellard | int val;
|
425 | 83d73968 | bellard | asm volatile ("movzwl %1, %0\n" |
426 | 83d73968 | bellard | "xchgb %b0, %h0\n"
|
427 | 83d73968 | bellard | : "=q" (val)
|
428 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr));
|
429 | 83d73968 | bellard | return (int16_t)val;
|
430 | 83d73968 | bellard | #else
|
431 | 83d73968 | bellard | uint8_t *b = (uint8_t *) ptr; |
432 | 83d73968 | bellard | return (int16_t)((b[0] << 8) | b[1]); |
433 | 83d73968 | bellard | #endif
|
434 | 93ac68bc | bellard | } |
435 | 93ac68bc | bellard | |
436 | 2df3b95d | bellard | static inline int ldl_be_p(void *ptr) |
437 | 93ac68bc | bellard | { |
438 | 4f2ac237 | bellard | #if defined(__i386__) || defined(__x86_64__)
|
439 | 83d73968 | bellard | int val;
|
440 | 83d73968 | bellard | asm volatile ("movl %1, %0\n" |
441 | 83d73968 | bellard | "bswap %0\n"
|
442 | 83d73968 | bellard | : "=r" (val)
|
443 | 83d73968 | bellard | : "m" (*(uint32_t *)ptr));
|
444 | 83d73968 | bellard | return val;
|
445 | 83d73968 | bellard | #else
|
446 | 93ac68bc | bellard | uint8_t *b = (uint8_t *) ptr; |
447 | 83d73968 | bellard | return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; |
448 | 83d73968 | bellard | #endif
|
449 | 93ac68bc | bellard | } |
450 | 93ac68bc | bellard | |
451 | 2df3b95d | bellard | static inline uint64_t ldq_be_p(void *ptr) |
452 | 93ac68bc | bellard | { |
453 | 93ac68bc | bellard | uint32_t a,b; |
454 | 2df3b95d | bellard | a = ldl_be_p(ptr); |
455 | 4d7a0880 | blueswir1 | b = ldl_be_p((uint8_t *)ptr + 4);
|
456 | 93ac68bc | bellard | return (((uint64_t)a<<32)|b); |
457 | 93ac68bc | bellard | } |
458 | 93ac68bc | bellard | |
459 | 2df3b95d | bellard | static inline void stw_be_p(void *ptr, int v) |
460 | 93ac68bc | bellard | { |
461 | 83d73968 | bellard | #if defined(__i386__)
|
462 | 83d73968 | bellard | asm volatile ("xchgb %b0, %h0\n" |
463 | 83d73968 | bellard | "movw %w0, %1\n"
|
464 | 83d73968 | bellard | : "=q" (v)
|
465 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr), "0" (v)); |
466 | 83d73968 | bellard | #else
|
467 | 93ac68bc | bellard | uint8_t *d = (uint8_t *) ptr; |
468 | 93ac68bc | bellard | d[0] = v >> 8; |
469 | 93ac68bc | bellard | d[1] = v;
|
470 | 83d73968 | bellard | #endif
|
471 | 93ac68bc | bellard | } |
472 | 93ac68bc | bellard | |
473 | 2df3b95d | bellard | static inline void stl_be_p(void *ptr, int v) |
474 | 93ac68bc | bellard | { |
475 | 4f2ac237 | bellard | #if defined(__i386__) || defined(__x86_64__)
|
476 | 83d73968 | bellard | asm volatile ("bswap %0\n" |
477 | 83d73968 | bellard | "movl %0, %1\n"
|
478 | 83d73968 | bellard | : "=r" (v)
|
479 | 83d73968 | bellard | : "m" (*(uint32_t *)ptr), "0" (v)); |
480 | 83d73968 | bellard | #else
|
481 | 93ac68bc | bellard | uint8_t *d = (uint8_t *) ptr; |
482 | 93ac68bc | bellard | d[0] = v >> 24; |
483 | 93ac68bc | bellard | d[1] = v >> 16; |
484 | 93ac68bc | bellard | d[2] = v >> 8; |
485 | 93ac68bc | bellard | d[3] = v;
|
486 | 83d73968 | bellard | #endif
|
487 | 93ac68bc | bellard | } |
488 | 93ac68bc | bellard | |
489 | 2df3b95d | bellard | static inline void stq_be_p(void *ptr, uint64_t v) |
490 | 93ac68bc | bellard | { |
491 | 2df3b95d | bellard | stl_be_p(ptr, v >> 32);
|
492 | 4d7a0880 | blueswir1 | stl_be_p((uint8_t *)ptr + 4, v);
|
493 | 0ac4bd56 | bellard | } |
494 | 0ac4bd56 | bellard | |
495 | 0ac4bd56 | bellard | /* float access */
|
496 | 0ac4bd56 | bellard | |
497 | 2df3b95d | bellard | static inline float32 ldfl_be_p(void *ptr) |
498 | 0ac4bd56 | bellard | { |
499 | 0ac4bd56 | bellard | union {
|
500 | 53cd6637 | bellard | float32 f; |
501 | 0ac4bd56 | bellard | uint32_t i; |
502 | 0ac4bd56 | bellard | } u; |
503 | 2df3b95d | bellard | u.i = ldl_be_p(ptr); |
504 | 0ac4bd56 | bellard | return u.f;
|
505 | 0ac4bd56 | bellard | } |
506 | 0ac4bd56 | bellard | |
507 | 2df3b95d | bellard | static inline void stfl_be_p(void *ptr, float32 v) |
508 | 0ac4bd56 | bellard | { |
509 | 0ac4bd56 | bellard | union {
|
510 | 53cd6637 | bellard | float32 f; |
511 | 0ac4bd56 | bellard | uint32_t i; |
512 | 0ac4bd56 | bellard | } u; |
513 | 0ac4bd56 | bellard | u.f = v; |
514 | 2df3b95d | bellard | stl_be_p(ptr, u.i); |
515 | 0ac4bd56 | bellard | } |
516 | 0ac4bd56 | bellard | |
517 | 2df3b95d | bellard | static inline float64 ldfq_be_p(void *ptr) |
518 | 0ac4bd56 | bellard | { |
519 | 0ac4bd56 | bellard | CPU_DoubleU u; |
520 | 2df3b95d | bellard | u.l.upper = ldl_be_p(ptr); |
521 | 4d7a0880 | blueswir1 | u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
|
522 | 0ac4bd56 | bellard | return u.d;
|
523 | 0ac4bd56 | bellard | } |
524 | 0ac4bd56 | bellard | |
525 | 2df3b95d | bellard | static inline void stfq_be_p(void *ptr, float64 v) |
526 | 0ac4bd56 | bellard | { |
527 | 0ac4bd56 | bellard | CPU_DoubleU u; |
528 | 0ac4bd56 | bellard | u.d = v; |
529 | 2df3b95d | bellard | stl_be_p(ptr, u.l.upper); |
530 | 4d7a0880 | blueswir1 | stl_be_p((uint8_t *)ptr + 4, u.l.lower);
|
531 | 93ac68bc | bellard | } |
532 | 93ac68bc | bellard | |
533 | 5a9fdfec | bellard | #else
|
534 | 5a9fdfec | bellard | |
535 | 2df3b95d | bellard | static inline int lduw_be_p(void *ptr) |
536 | 5a9fdfec | bellard | { |
537 | 5a9fdfec | bellard | return *(uint16_t *)ptr;
|
538 | 5a9fdfec | bellard | } |
539 | 5a9fdfec | bellard | |
540 | 2df3b95d | bellard | static inline int ldsw_be_p(void *ptr) |
541 | 5a9fdfec | bellard | { |
542 | 5a9fdfec | bellard | return *(int16_t *)ptr;
|
543 | 5a9fdfec | bellard | } |
544 | 5a9fdfec | bellard | |
545 | 2df3b95d | bellard | static inline int ldl_be_p(void *ptr) |
546 | 5a9fdfec | bellard | { |
547 | 5a9fdfec | bellard | return *(uint32_t *)ptr;
|
548 | 5a9fdfec | bellard | } |
549 | 5a9fdfec | bellard | |
550 | 2df3b95d | bellard | static inline uint64_t ldq_be_p(void *ptr) |
551 | 5a9fdfec | bellard | { |
552 | 5a9fdfec | bellard | return *(uint64_t *)ptr;
|
553 | 5a9fdfec | bellard | } |
554 | 5a9fdfec | bellard | |
555 | 2df3b95d | bellard | static inline void stw_be_p(void *ptr, int v) |
556 | 5a9fdfec | bellard | { |
557 | 5a9fdfec | bellard | *(uint16_t *)ptr = v; |
558 | 5a9fdfec | bellard | } |
559 | 5a9fdfec | bellard | |
560 | 2df3b95d | bellard | static inline void stl_be_p(void *ptr, int v) |
561 | 5a9fdfec | bellard | { |
562 | 5a9fdfec | bellard | *(uint32_t *)ptr = v; |
563 | 5a9fdfec | bellard | } |
564 | 5a9fdfec | bellard | |
565 | 2df3b95d | bellard | static inline void stq_be_p(void *ptr, uint64_t v) |
566 | 5a9fdfec | bellard | { |
567 | 5a9fdfec | bellard | *(uint64_t *)ptr = v; |
568 | 5a9fdfec | bellard | } |
569 | 5a9fdfec | bellard | |
570 | 5a9fdfec | bellard | /* float access */
|
571 | 5a9fdfec | bellard | |
572 | 2df3b95d | bellard | static inline float32 ldfl_be_p(void *ptr) |
573 | 5a9fdfec | bellard | { |
574 | 53cd6637 | bellard | return *(float32 *)ptr;
|
575 | 5a9fdfec | bellard | } |
576 | 5a9fdfec | bellard | |
577 | 2df3b95d | bellard | static inline float64 ldfq_be_p(void *ptr) |
578 | 5a9fdfec | bellard | { |
579 | 53cd6637 | bellard | return *(float64 *)ptr;
|
580 | 5a9fdfec | bellard | } |
581 | 5a9fdfec | bellard | |
582 | 2df3b95d | bellard | static inline void stfl_be_p(void *ptr, float32 v) |
583 | 5a9fdfec | bellard | { |
584 | 53cd6637 | bellard | *(float32 *)ptr = v; |
585 | 5a9fdfec | bellard | } |
586 | 5a9fdfec | bellard | |
587 | 2df3b95d | bellard | static inline void stfq_be_p(void *ptr, float64 v) |
588 | 5a9fdfec | bellard | { |
589 | 53cd6637 | bellard | *(float64 *)ptr = v; |
590 | 5a9fdfec | bellard | } |
591 | 2df3b95d | bellard | |
592 | 2df3b95d | bellard | #endif
|
593 | 2df3b95d | bellard | |
594 | 2df3b95d | bellard | /* target CPU memory access functions */
|
595 | 2df3b95d | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
|
596 | 2df3b95d | bellard | #define lduw_p(p) lduw_be_p(p)
|
597 | 2df3b95d | bellard | #define ldsw_p(p) ldsw_be_p(p)
|
598 | 2df3b95d | bellard | #define ldl_p(p) ldl_be_p(p)
|
599 | 2df3b95d | bellard | #define ldq_p(p) ldq_be_p(p)
|
600 | 2df3b95d | bellard | #define ldfl_p(p) ldfl_be_p(p)
|
601 | 2df3b95d | bellard | #define ldfq_p(p) ldfq_be_p(p)
|
602 | 2df3b95d | bellard | #define stw_p(p, v) stw_be_p(p, v)
|
603 | 2df3b95d | bellard | #define stl_p(p, v) stl_be_p(p, v)
|
604 | 2df3b95d | bellard | #define stq_p(p, v) stq_be_p(p, v)
|
605 | 2df3b95d | bellard | #define stfl_p(p, v) stfl_be_p(p, v)
|
606 | 2df3b95d | bellard | #define stfq_p(p, v) stfq_be_p(p, v)
|
607 | 2df3b95d | bellard | #else
|
608 | 2df3b95d | bellard | #define lduw_p(p) lduw_le_p(p)
|
609 | 2df3b95d | bellard | #define ldsw_p(p) ldsw_le_p(p)
|
610 | 2df3b95d | bellard | #define ldl_p(p) ldl_le_p(p)
|
611 | 2df3b95d | bellard | #define ldq_p(p) ldq_le_p(p)
|
612 | 2df3b95d | bellard | #define ldfl_p(p) ldfl_le_p(p)
|
613 | 2df3b95d | bellard | #define ldfq_p(p) ldfq_le_p(p)
|
614 | 2df3b95d | bellard | #define stw_p(p, v) stw_le_p(p, v)
|
615 | 2df3b95d | bellard | #define stl_p(p, v) stl_le_p(p, v)
|
616 | 2df3b95d | bellard | #define stq_p(p, v) stq_le_p(p, v)
|
617 | 2df3b95d | bellard | #define stfl_p(p, v) stfl_le_p(p, v)
|
618 | 2df3b95d | bellard | #define stfq_p(p, v) stfq_le_p(p, v)
|
619 | 5a9fdfec | bellard | #endif
|
620 | 5a9fdfec | bellard | |
621 | 61382a50 | bellard | /* MMU memory access macros */
|
622 | 61382a50 | bellard | |
623 | 53a5960a | pbrook | #if defined(CONFIG_USER_ONLY)
|
624 | 53a5960a | pbrook | /* On some host systems the guest address space is reserved on the host.
|
625 | 53a5960a | pbrook | * This allows the guest address space to be offset to a convenient location.
|
626 | 53a5960a | pbrook | */
|
627 | 53a5960a | pbrook | //#define GUEST_BASE 0x20000000
|
628 | 53a5960a | pbrook | #define GUEST_BASE 0 |
629 | 53a5960a | pbrook | |
630 | 53a5960a | pbrook | /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
|
631 | 53a5960a | pbrook | #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE)) |
632 | 53a5960a | pbrook | #define h2g(x) ((target_ulong)(x - GUEST_BASE))
|
633 | 53a5960a | pbrook | |
634 | 53a5960a | pbrook | #define saddr(x) g2h(x)
|
635 | 53a5960a | pbrook | #define laddr(x) g2h(x)
|
636 | 53a5960a | pbrook | |
637 | 53a5960a | pbrook | #else /* !CONFIG_USER_ONLY */ |
638 | c27004ec | bellard | /* NOTE: we use double casts if pointers and target_ulong have
|
639 | c27004ec | bellard | different sizes */
|
640 | 53a5960a | pbrook | #define saddr(x) (uint8_t *)(long)(x) |
641 | 53a5960a | pbrook | #define laddr(x) (uint8_t *)(long)(x) |
642 | 53a5960a | pbrook | #endif
|
643 | 53a5960a | pbrook | |
644 | 53a5960a | pbrook | #define ldub_raw(p) ldub_p(laddr((p)))
|
645 | 53a5960a | pbrook | #define ldsb_raw(p) ldsb_p(laddr((p)))
|
646 | 53a5960a | pbrook | #define lduw_raw(p) lduw_p(laddr((p)))
|
647 | 53a5960a | pbrook | #define ldsw_raw(p) ldsw_p(laddr((p)))
|
648 | 53a5960a | pbrook | #define ldl_raw(p) ldl_p(laddr((p)))
|
649 | 53a5960a | pbrook | #define ldq_raw(p) ldq_p(laddr((p)))
|
650 | 53a5960a | pbrook | #define ldfl_raw(p) ldfl_p(laddr((p)))
|
651 | 53a5960a | pbrook | #define ldfq_raw(p) ldfq_p(laddr((p)))
|
652 | 53a5960a | pbrook | #define stb_raw(p, v) stb_p(saddr((p)), v)
|
653 | 53a5960a | pbrook | #define stw_raw(p, v) stw_p(saddr((p)), v)
|
654 | 53a5960a | pbrook | #define stl_raw(p, v) stl_p(saddr((p)), v)
|
655 | 53a5960a | pbrook | #define stq_raw(p, v) stq_p(saddr((p)), v)
|
656 | 53a5960a | pbrook | #define stfl_raw(p, v) stfl_p(saddr((p)), v)
|
657 | 53a5960a | pbrook | #define stfq_raw(p, v) stfq_p(saddr((p)), v)
|
658 | c27004ec | bellard | |
659 | c27004ec | bellard | |
660 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
|
661 | 61382a50 | bellard | |
662 | 61382a50 | bellard | /* if user mode, no other memory access functions */
|
663 | 61382a50 | bellard | #define ldub(p) ldub_raw(p)
|
664 | 61382a50 | bellard | #define ldsb(p) ldsb_raw(p)
|
665 | 61382a50 | bellard | #define lduw(p) lduw_raw(p)
|
666 | 61382a50 | bellard | #define ldsw(p) ldsw_raw(p)
|
667 | 61382a50 | bellard | #define ldl(p) ldl_raw(p)
|
668 | 61382a50 | bellard | #define ldq(p) ldq_raw(p)
|
669 | 61382a50 | bellard | #define ldfl(p) ldfl_raw(p)
|
670 | 61382a50 | bellard | #define ldfq(p) ldfq_raw(p)
|
671 | 61382a50 | bellard | #define stb(p, v) stb_raw(p, v)
|
672 | 61382a50 | bellard | #define stw(p, v) stw_raw(p, v)
|
673 | 61382a50 | bellard | #define stl(p, v) stl_raw(p, v)
|
674 | 61382a50 | bellard | #define stq(p, v) stq_raw(p, v)
|
675 | 61382a50 | bellard | #define stfl(p, v) stfl_raw(p, v)
|
676 | 61382a50 | bellard | #define stfq(p, v) stfq_raw(p, v)
|
677 | 61382a50 | bellard | |
678 | 61382a50 | bellard | #define ldub_code(p) ldub_raw(p)
|
679 | 61382a50 | bellard | #define ldsb_code(p) ldsb_raw(p)
|
680 | 61382a50 | bellard | #define lduw_code(p) lduw_raw(p)
|
681 | 61382a50 | bellard | #define ldsw_code(p) ldsw_raw(p)
|
682 | 61382a50 | bellard | #define ldl_code(p) ldl_raw(p)
|
683 | bc98a7ef | j_mayer | #define ldq_code(p) ldq_raw(p)
|
684 | 61382a50 | bellard | |
685 | 61382a50 | bellard | #define ldub_kernel(p) ldub_raw(p)
|
686 | 61382a50 | bellard | #define ldsb_kernel(p) ldsb_raw(p)
|
687 | 61382a50 | bellard | #define lduw_kernel(p) lduw_raw(p)
|
688 | 61382a50 | bellard | #define ldsw_kernel(p) ldsw_raw(p)
|
689 | 61382a50 | bellard | #define ldl_kernel(p) ldl_raw(p)
|
690 | bc98a7ef | j_mayer | #define ldq_kernel(p) ldq_raw(p)
|
691 | 0ac4bd56 | bellard | #define ldfl_kernel(p) ldfl_raw(p)
|
692 | 0ac4bd56 | bellard | #define ldfq_kernel(p) ldfq_raw(p)
|
693 | 61382a50 | bellard | #define stb_kernel(p, v) stb_raw(p, v)
|
694 | 61382a50 | bellard | #define stw_kernel(p, v) stw_raw(p, v)
|
695 | 61382a50 | bellard | #define stl_kernel(p, v) stl_raw(p, v)
|
696 | 61382a50 | bellard | #define stq_kernel(p, v) stq_raw(p, v)
|
697 | 0ac4bd56 | bellard | #define stfl_kernel(p, v) stfl_raw(p, v)
|
698 | 0ac4bd56 | bellard | #define stfq_kernel(p, vt) stfq_raw(p, v)
|
699 | 61382a50 | bellard | |
700 | 61382a50 | bellard | #endif /* defined(CONFIG_USER_ONLY) */ |
701 | 61382a50 | bellard | |
702 | 5a9fdfec | bellard | /* page related stuff */
|
703 | 5a9fdfec | bellard | |
704 | 03875444 | aurel32 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
705 | 5a9fdfec | bellard | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
706 | 5a9fdfec | bellard | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) |
707 | 5a9fdfec | bellard | |
708 | 53a5960a | pbrook | /* ??? These should be the larger of unsigned long and target_ulong. */
|
709 | 83fb7adf | bellard | extern unsigned long qemu_real_host_page_size; |
710 | 83fb7adf | bellard | extern unsigned long qemu_host_page_bits; |
711 | 83fb7adf | bellard | extern unsigned long qemu_host_page_size; |
712 | 83fb7adf | bellard | extern unsigned long qemu_host_page_mask; |
713 | 5a9fdfec | bellard | |
714 | 83fb7adf | bellard | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
715 | 5a9fdfec | bellard | |
716 | 5a9fdfec | bellard | /* same as PROT_xxx */
|
717 | 5a9fdfec | bellard | #define PAGE_READ 0x0001 |
718 | 5a9fdfec | bellard | #define PAGE_WRITE 0x0002 |
719 | 5a9fdfec | bellard | #define PAGE_EXEC 0x0004 |
720 | 5a9fdfec | bellard | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
|
721 | 5a9fdfec | bellard | #define PAGE_VALID 0x0008 |
722 | 5a9fdfec | bellard | /* original state of the write flag (used when tracking self-modifying
|
723 | 5a9fdfec | bellard | code */
|
724 | 5fafdf24 | ths | #define PAGE_WRITE_ORG 0x0010 |
725 | 50a9569b | balrog | #define PAGE_RESERVED 0x0020 |
726 | 5a9fdfec | bellard | |
727 | 5a9fdfec | bellard | void page_dump(FILE *f);
|
728 | 53a5960a | pbrook | int page_get_flags(target_ulong address);
|
729 | 53a5960a | pbrook | void page_set_flags(target_ulong start, target_ulong end, int flags); |
730 | 3d97b40b | ths | int page_check_range(target_ulong start, target_ulong len, int flags); |
731 | 5a9fdfec | bellard | |
732 | c5be9f08 | ths | CPUState *cpu_copy(CPUState *env); |
733 | c5be9f08 | ths | |
734 | 5fafdf24 | ths | void cpu_dump_state(CPUState *env, FILE *f,
|
735 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
736 | 7fe48483 | bellard | int flags);
|
737 | 76a66253 | j_mayer | void cpu_dump_statistics (CPUState *env, FILE *f,
|
738 | 76a66253 | j_mayer | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
739 | 76a66253 | j_mayer | int flags);
|
740 | 7fe48483 | bellard | |
741 | a90b7318 | balrog | void cpu_abort(CPUState *env, const char *fmt, ...) |
742 | c3d2689d | balrog | __attribute__ ((__format__ (__printf__, 2, 3))) |
743 | c3d2689d | balrog | __attribute__ ((__noreturn__)); |
744 | f0aca822 | bellard | extern CPUState *first_cpu;
|
745 | e2f22898 | bellard | extern CPUState *cpu_single_env;
|
746 | 5a9fdfec | bellard | |
747 | 9acbed06 | bellard | #define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */ |
748 | 9acbed06 | bellard | #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */ |
749 | 9acbed06 | bellard | #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ |
750 | ef792f9d | bellard | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ |
751 | 98699967 | bellard | #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */ |
752 | ba3c64fb | bellard | #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */ |
753 | 3b21e03e | bellard | #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */ |
754 | 6658ffb8 | pbrook | #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */ |
755 | 0573fbfc | ths | #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */ |
756 | 474ea849 | aurel32 | #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */ |
757 | 98699967 | bellard | |
758 | 4690764b | bellard | void cpu_interrupt(CPUState *s, int mask); |
759 | b54ad049 | bellard | void cpu_reset_interrupt(CPUState *env, int mask); |
760 | 68a79315 | bellard | |
761 | 6658ffb8 | pbrook | int cpu_watchpoint_insert(CPUState *env, target_ulong addr);
|
762 | 6658ffb8 | pbrook | int cpu_watchpoint_remove(CPUState *env, target_ulong addr);
|
763 | 7d03f82f | edgar_igl | void cpu_watchpoint_remove_all(CPUState *env);
|
764 | 2e12669a | bellard | int cpu_breakpoint_insert(CPUState *env, target_ulong pc);
|
765 | 2e12669a | bellard | int cpu_breakpoint_remove(CPUState *env, target_ulong pc);
|
766 | 7d03f82f | edgar_igl | void cpu_breakpoint_remove_all(CPUState *env);
|
767 | 60897d36 | edgar_igl | |
768 | 60897d36 | edgar_igl | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
769 | 60897d36 | edgar_igl | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ |
770 | 60897d36 | edgar_igl | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ |
771 | 60897d36 | edgar_igl | |
772 | c33a346e | bellard | void cpu_single_step(CPUState *env, int enabled); |
773 | d95dc32d | bellard | void cpu_reset(CPUState *s);
|
774 | 4c3a88a2 | bellard | |
775 | 13eb76e0 | bellard | /* Return the physical page corresponding to a virtual one. Use it
|
776 | 13eb76e0 | bellard | only for debugging because no protection checks are done. Return -1
|
777 | 13eb76e0 | bellard | if no page found. */
|
778 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
779 | 13eb76e0 | bellard | |
780 | 5fafdf24 | ths | #define CPU_LOG_TB_OUT_ASM (1 << 0) |
781 | 9fddaa0c | bellard | #define CPU_LOG_TB_IN_ASM (1 << 1) |
782 | f193c797 | bellard | #define CPU_LOG_TB_OP (1 << 2) |
783 | f193c797 | bellard | #define CPU_LOG_TB_OP_OPT (1 << 3) |
784 | f193c797 | bellard | #define CPU_LOG_INT (1 << 4) |
785 | f193c797 | bellard | #define CPU_LOG_EXEC (1 << 5) |
786 | f193c797 | bellard | #define CPU_LOG_PCALL (1 << 6) |
787 | fd872598 | bellard | #define CPU_LOG_IOPORT (1 << 7) |
788 | 9fddaa0c | bellard | #define CPU_LOG_TB_CPU (1 << 8) |
789 | f193c797 | bellard | |
790 | f193c797 | bellard | /* define log items */
|
791 | f193c797 | bellard | typedef struct CPULogItem { |
792 | f193c797 | bellard | int mask;
|
793 | f193c797 | bellard | const char *name; |
794 | f193c797 | bellard | const char *help; |
795 | f193c797 | bellard | } CPULogItem; |
796 | f193c797 | bellard | |
797 | f193c797 | bellard | extern CPULogItem cpu_log_items[];
|
798 | f193c797 | bellard | |
799 | 34865134 | bellard | void cpu_set_log(int log_flags); |
800 | 34865134 | bellard | void cpu_set_log_filename(const char *filename); |
801 | f193c797 | bellard | int cpu_str_to_log_mask(const char *str); |
802 | 34865134 | bellard | |
803 | 09683d35 | bellard | /* IO ports API */
|
804 | 09683d35 | bellard | |
805 | 09683d35 | bellard | /* NOTE: as these functions may be even used when there is an isa
|
806 | 09683d35 | bellard | brige on non x86 targets, we always defined them */
|
807 | 09683d35 | bellard | #ifndef NO_CPU_IO_DEFS
|
808 | 09683d35 | bellard | void cpu_outb(CPUState *env, int addr, int val); |
809 | 09683d35 | bellard | void cpu_outw(CPUState *env, int addr, int val); |
810 | 09683d35 | bellard | void cpu_outl(CPUState *env, int addr, int val); |
811 | 09683d35 | bellard | int cpu_inb(CPUState *env, int addr); |
812 | 09683d35 | bellard | int cpu_inw(CPUState *env, int addr); |
813 | 09683d35 | bellard | int cpu_inl(CPUState *env, int addr); |
814 | 09683d35 | bellard | #endif
|
815 | 09683d35 | bellard | |
816 | 00f82b8a | aurel32 | /* address in the RAM (different from a physical address) */
|
817 | 00f82b8a | aurel32 | #ifdef USE_KQEMU
|
818 | 00f82b8a | aurel32 | typedef uint32_t ram_addr_t;
|
819 | 00f82b8a | aurel32 | #else
|
820 | 00f82b8a | aurel32 | typedef unsigned long ram_addr_t; |
821 | 00f82b8a | aurel32 | #endif
|
822 | 00f82b8a | aurel32 | |
823 | 33417e70 | bellard | /* memory API */
|
824 | 33417e70 | bellard | |
825 | 00f82b8a | aurel32 | extern ram_addr_t phys_ram_size;
|
826 | edf75d59 | bellard | extern int phys_ram_fd; |
827 | edf75d59 | bellard | extern uint8_t *phys_ram_base;
|
828 | 1ccde1cb | bellard | extern uint8_t *phys_ram_dirty;
|
829 | 00f82b8a | aurel32 | extern ram_addr_t ram_size;
|
830 | edf75d59 | bellard | |
831 | edf75d59 | bellard | /* physical memory access */
|
832 | edf75d59 | bellard | #define TLB_INVALID_MASK (1 << 3) |
833 | edf75d59 | bellard | #define IO_MEM_SHIFT 4 |
834 | 98699967 | bellard | #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT)) |
835 | edf75d59 | bellard | |
836 | edf75d59 | bellard | #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ |
837 | edf75d59 | bellard | #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ |
838 | edf75d59 | bellard | #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) |
839 | 1ccde1cb | bellard | #define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */ |
840 | 2a4188a3 | bellard | /* acts like a ROM when read and like a device when written. As an
|
841 | 2a4188a3 | bellard | exception, the write memory callback gets the ram offset instead of
|
842 | 2a4188a3 | bellard | the physical address */
|
843 | 2a4188a3 | bellard | #define IO_MEM_ROMD (1) |
844 | db7b5426 | blueswir1 | #define IO_MEM_SUBPAGE (2) |
845 | 4254fab8 | blueswir1 | #define IO_MEM_SUBWIDTH (4) |
846 | edf75d59 | bellard | |
847 | 7727994d | bellard | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); |
848 | 7727994d | bellard | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); |
849 | 33417e70 | bellard | |
850 | 5fafdf24 | ths | void cpu_register_physical_memory(target_phys_addr_t start_addr,
|
851 | 00f82b8a | aurel32 | ram_addr_t size, |
852 | 00f82b8a | aurel32 | ram_addr_t phys_offset); |
853 | 00f82b8a | aurel32 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr); |
854 | 00f82b8a | aurel32 | ram_addr_t qemu_ram_alloc(ram_addr_t); |
855 | e9a1ab19 | bellard | void qemu_ram_free(ram_addr_t addr);
|
856 | 33417e70 | bellard | int cpu_register_io_memory(int io_index, |
857 | 33417e70 | bellard | CPUReadMemoryFunc **mem_read, |
858 | 7727994d | bellard | CPUWriteMemoryFunc **mem_write, |
859 | 7727994d | bellard | void *opaque);
|
860 | 8926b517 | bellard | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
|
861 | 8926b517 | bellard | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
|
862 | 33417e70 | bellard | |
863 | 2e12669a | bellard | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
|
864 | 13eb76e0 | bellard | int len, int is_write); |
865 | 5fafdf24 | ths | static inline void cpu_physical_memory_read(target_phys_addr_t addr, |
866 | 2e12669a | bellard | uint8_t *buf, int len)
|
867 | 8b1f24b0 | bellard | { |
868 | 8b1f24b0 | bellard | cpu_physical_memory_rw(addr, buf, len, 0);
|
869 | 8b1f24b0 | bellard | } |
870 | 5fafdf24 | ths | static inline void cpu_physical_memory_write(target_phys_addr_t addr, |
871 | 2e12669a | bellard | const uint8_t *buf, int len) |
872 | 8b1f24b0 | bellard | { |
873 | 8b1f24b0 | bellard | cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
|
874 | 8b1f24b0 | bellard | } |
875 | aab33094 | bellard | uint32_t ldub_phys(target_phys_addr_t addr); |
876 | aab33094 | bellard | uint32_t lduw_phys(target_phys_addr_t addr); |
877 | 8df1cd07 | bellard | uint32_t ldl_phys(target_phys_addr_t addr); |
878 | aab33094 | bellard | uint64_t ldq_phys(target_phys_addr_t addr); |
879 | 8df1cd07 | bellard | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
|
880 | bc98a7ef | j_mayer | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
|
881 | aab33094 | bellard | void stb_phys(target_phys_addr_t addr, uint32_t val);
|
882 | aab33094 | bellard | void stw_phys(target_phys_addr_t addr, uint32_t val);
|
883 | 8df1cd07 | bellard | void stl_phys(target_phys_addr_t addr, uint32_t val);
|
884 | aab33094 | bellard | void stq_phys(target_phys_addr_t addr, uint64_t val);
|
885 | 8b1f24b0 | bellard | |
886 | 5fafdf24 | ths | void cpu_physical_memory_write_rom(target_phys_addr_t addr,
|
887 | d0ecd2aa | bellard | const uint8_t *buf, int len); |
888 | 5fafdf24 | ths | int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
889 | 8b1f24b0 | bellard | uint8_t *buf, int len, int is_write); |
890 | 13eb76e0 | bellard | |
891 | 04c504cc | bellard | #define VGA_DIRTY_FLAG 0x01 |
892 | 04c504cc | bellard | #define CODE_DIRTY_FLAG 0x02 |
893 | 0a962c02 | bellard | |
894 | 1ccde1cb | bellard | /* read dirty bit (return 0 or 1) */
|
895 | 04c504cc | bellard | static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) |
896 | 1ccde1cb | bellard | { |
897 | 0a962c02 | bellard | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; |
898 | 0a962c02 | bellard | } |
899 | 0a962c02 | bellard | |
900 | 5fafdf24 | ths | static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, |
901 | 0a962c02 | bellard | int dirty_flags)
|
902 | 0a962c02 | bellard | { |
903 | 0a962c02 | bellard | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
|
904 | 1ccde1cb | bellard | } |
905 | 1ccde1cb | bellard | |
906 | 04c504cc | bellard | static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) |
907 | 1ccde1cb | bellard | { |
908 | 0a962c02 | bellard | phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
|
909 | 1ccde1cb | bellard | } |
910 | 1ccde1cb | bellard | |
911 | 04c504cc | bellard | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
|
912 | 0a962c02 | bellard | int dirty_flags);
|
913 | 04c504cc | bellard | void cpu_tlb_update_dirty(CPUState *env);
|
914 | 1ccde1cb | bellard | |
915 | e3db7226 | bellard | void dump_exec_info(FILE *f,
|
916 | e3db7226 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
917 | e3db7226 | bellard | |
918 | effedbc9 | bellard | /*******************************************/
|
919 | effedbc9 | bellard | /* host CPU ticks (if available) */
|
920 | effedbc9 | bellard | |
921 | effedbc9 | bellard | #if defined(__powerpc__)
|
922 | effedbc9 | bellard | |
923 | 5fafdf24 | ths | static inline uint32_t get_tbl(void) |
924 | effedbc9 | bellard | { |
925 | effedbc9 | bellard | uint32_t tbl; |
926 | effedbc9 | bellard | asm volatile("mftb %0" : "=r" (tbl)); |
927 | effedbc9 | bellard | return tbl;
|
928 | effedbc9 | bellard | } |
929 | effedbc9 | bellard | |
930 | 5fafdf24 | ths | static inline uint32_t get_tbu(void) |
931 | effedbc9 | bellard | { |
932 | effedbc9 | bellard | uint32_t tbl; |
933 | effedbc9 | bellard | asm volatile("mftbu %0" : "=r" (tbl)); |
934 | effedbc9 | bellard | return tbl;
|
935 | effedbc9 | bellard | } |
936 | effedbc9 | bellard | |
937 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
938 | effedbc9 | bellard | { |
939 | effedbc9 | bellard | uint32_t l, h, h1; |
940 | effedbc9 | bellard | /* NOTE: we test if wrapping has occurred */
|
941 | effedbc9 | bellard | do {
|
942 | effedbc9 | bellard | h = get_tbu(); |
943 | effedbc9 | bellard | l = get_tbl(); |
944 | effedbc9 | bellard | h1 = get_tbu(); |
945 | effedbc9 | bellard | } while (h != h1);
|
946 | effedbc9 | bellard | return ((int64_t)h << 32) | l; |
947 | effedbc9 | bellard | } |
948 | effedbc9 | bellard | |
949 | effedbc9 | bellard | #elif defined(__i386__)
|
950 | effedbc9 | bellard | |
951 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
952 | 5f1ce948 | bellard | { |
953 | 5f1ce948 | bellard | int64_t val; |
954 | 5f1ce948 | bellard | asm volatile ("rdtsc" : "=A" (val)); |
955 | 5f1ce948 | bellard | return val;
|
956 | 5f1ce948 | bellard | } |
957 | 5f1ce948 | bellard | |
958 | effedbc9 | bellard | #elif defined(__x86_64__)
|
959 | effedbc9 | bellard | |
960 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
961 | effedbc9 | bellard | { |
962 | effedbc9 | bellard | uint32_t low,high; |
963 | effedbc9 | bellard | int64_t val; |
964 | effedbc9 | bellard | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
965 | effedbc9 | bellard | val = high; |
966 | effedbc9 | bellard | val <<= 32;
|
967 | effedbc9 | bellard | val |= low; |
968 | effedbc9 | bellard | return val;
|
969 | effedbc9 | bellard | } |
970 | effedbc9 | bellard | |
971 | f54b3f92 | aurel32 | #elif defined(__hppa__)
|
972 | f54b3f92 | aurel32 | |
973 | f54b3f92 | aurel32 | static inline int64_t cpu_get_real_ticks(void) |
974 | f54b3f92 | aurel32 | { |
975 | f54b3f92 | aurel32 | int val;
|
976 | f54b3f92 | aurel32 | asm volatile ("mfctl %%cr16, %0" : "=r"(val)); |
977 | f54b3f92 | aurel32 | return val;
|
978 | f54b3f92 | aurel32 | } |
979 | f54b3f92 | aurel32 | |
980 | effedbc9 | bellard | #elif defined(__ia64)
|
981 | effedbc9 | bellard | |
982 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
983 | effedbc9 | bellard | { |
984 | effedbc9 | bellard | int64_t val; |
985 | effedbc9 | bellard | asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory"); |
986 | effedbc9 | bellard | return val;
|
987 | effedbc9 | bellard | } |
988 | effedbc9 | bellard | |
989 | effedbc9 | bellard | #elif defined(__s390__)
|
990 | effedbc9 | bellard | |
991 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
992 | effedbc9 | bellard | { |
993 | effedbc9 | bellard | int64_t val; |
994 | effedbc9 | bellard | asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc"); |
995 | effedbc9 | bellard | return val;
|
996 | effedbc9 | bellard | } |
997 | effedbc9 | bellard | |
998 | 3142255c | blueswir1 | #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
|
999 | effedbc9 | bellard | |
1000 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks (void) |
1001 | effedbc9 | bellard | { |
1002 | effedbc9 | bellard | #if defined(_LP64)
|
1003 | effedbc9 | bellard | uint64_t rval; |
1004 | effedbc9 | bellard | asm volatile("rd %%tick,%0" : "=r"(rval)); |
1005 | effedbc9 | bellard | return rval;
|
1006 | effedbc9 | bellard | #else
|
1007 | effedbc9 | bellard | union {
|
1008 | effedbc9 | bellard | uint64_t i64; |
1009 | effedbc9 | bellard | struct {
|
1010 | effedbc9 | bellard | uint32_t high; |
1011 | effedbc9 | bellard | uint32_t low; |
1012 | effedbc9 | bellard | } i32; |
1013 | effedbc9 | bellard | } rval; |
1014 | effedbc9 | bellard | asm volatile("rd %%tick,%1; srlx %1,32,%0" |
1015 | effedbc9 | bellard | : "=r"(rval.i32.high), "=r"(rval.i32.low)); |
1016 | effedbc9 | bellard | return rval.i64;
|
1017 | effedbc9 | bellard | #endif
|
1018 | effedbc9 | bellard | } |
1019 | c4b89d18 | ths | |
1020 | c4b89d18 | ths | #elif defined(__mips__)
|
1021 | c4b89d18 | ths | |
1022 | c4b89d18 | ths | static inline int64_t cpu_get_real_ticks(void) |
1023 | c4b89d18 | ths | { |
1024 | c4b89d18 | ths | #if __mips_isa_rev >= 2 |
1025 | c4b89d18 | ths | uint32_t count; |
1026 | c4b89d18 | ths | static uint32_t cyc_per_count = 0; |
1027 | c4b89d18 | ths | |
1028 | c4b89d18 | ths | if (!cyc_per_count)
|
1029 | c4b89d18 | ths | __asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count)); |
1030 | c4b89d18 | ths | |
1031 | c4b89d18 | ths | __asm__ __volatile__("rdhwr %1, $2" : "=r" (count)); |
1032 | c4b89d18 | ths | return (int64_t)(count * cyc_per_count);
|
1033 | c4b89d18 | ths | #else
|
1034 | c4b89d18 | ths | /* FIXME */
|
1035 | c4b89d18 | ths | static int64_t ticks = 0; |
1036 | c4b89d18 | ths | return ticks++;
|
1037 | c4b89d18 | ths | #endif
|
1038 | c4b89d18 | ths | } |
1039 | c4b89d18 | ths | |
1040 | 46152182 | pbrook | #else
|
1041 | 46152182 | pbrook | /* The host CPU doesn't have an easily accessible cycle counter.
|
1042 | 85028e4d | ths | Just return a monotonically increasing value. This will be
|
1043 | 85028e4d | ths | totally wrong, but hopefully better than nothing. */
|
1044 | 46152182 | pbrook | static inline int64_t cpu_get_real_ticks (void) |
1045 | 46152182 | pbrook | { |
1046 | 46152182 | pbrook | static int64_t ticks = 0; |
1047 | 46152182 | pbrook | return ticks++;
|
1048 | 46152182 | pbrook | } |
1049 | effedbc9 | bellard | #endif
|
1050 | effedbc9 | bellard | |
1051 | effedbc9 | bellard | /* profiling */
|
1052 | effedbc9 | bellard | #ifdef CONFIG_PROFILER
|
1053 | effedbc9 | bellard | static inline int64_t profile_getclock(void) |
1054 | effedbc9 | bellard | { |
1055 | effedbc9 | bellard | return cpu_get_real_ticks();
|
1056 | effedbc9 | bellard | } |
1057 | effedbc9 | bellard | |
1058 | 5f1ce948 | bellard | extern int64_t kqemu_time, kqemu_time_start;
|
1059 | 5f1ce948 | bellard | extern int64_t qemu_time, qemu_time_start;
|
1060 | 5f1ce948 | bellard | extern int64_t tlb_flush_time;
|
1061 | 5f1ce948 | bellard | extern int64_t kqemu_exec_count;
|
1062 | 5f1ce948 | bellard | extern int64_t dev_time;
|
1063 | 5f1ce948 | bellard | extern int64_t kqemu_ret_int_count;
|
1064 | 5f1ce948 | bellard | extern int64_t kqemu_ret_excp_count;
|
1065 | 5f1ce948 | bellard | extern int64_t kqemu_ret_intr_count;
|
1066 | 5f1ce948 | bellard | |
1067 | 57fec1fe | bellard | extern int64_t dyngen_tb_count1;
|
1068 | 57fec1fe | bellard | extern int64_t dyngen_tb_count;
|
1069 | 57fec1fe | bellard | extern int64_t dyngen_op_count;
|
1070 | 57fec1fe | bellard | extern int64_t dyngen_old_op_count;
|
1071 | 57fec1fe | bellard | extern int64_t dyngen_tcg_del_op_count;
|
1072 | 57fec1fe | bellard | extern int dyngen_op_count_max; |
1073 | 57fec1fe | bellard | extern int64_t dyngen_code_in_len;
|
1074 | 57fec1fe | bellard | extern int64_t dyngen_code_out_len;
|
1075 | 57fec1fe | bellard | extern int64_t dyngen_interm_time;
|
1076 | 57fec1fe | bellard | extern int64_t dyngen_code_time;
|
1077 | 57fec1fe | bellard | extern int64_t dyngen_restore_count;
|
1078 | 57fec1fe | bellard | extern int64_t dyngen_restore_time;
|
1079 | 5f1ce948 | bellard | #endif
|
1080 | 5f1ce948 | bellard | |
1081 | 5a9fdfec | bellard | #endif /* CPU_ALL_H */ |