root / exec-all.h @ 8c99506c
History | View | Annotate | Download (17.6 kB)
1 | d4e8164f | bellard | /*
|
---|---|---|---|
2 | d4e8164f | bellard | * internal execution defines for qemu
|
3 | 5fafdf24 | ths | *
|
4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | d4e8164f | bellard | *
|
6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
|
7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
|
9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | d4e8164f | bellard | *
|
11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
|
12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | d4e8164f | bellard | * Lesser General Public License for more details.
|
15 | d4e8164f | bellard | *
|
16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
|
18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
19 | d4e8164f | bellard | */
|
20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
|
22 | cb7cca1a | aurel32 | #define DEBUG_DISAS
|
23 | b346ff46 | bellard | |
24 | b346ff46 | bellard | /* is_jmp field values */
|
25 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
26 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
27 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
28 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
29 | b346ff46 | bellard | |
30 | b346ff46 | bellard | struct TranslationBlock;
|
31 | b346ff46 | bellard | |
32 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
|
33 | e83a8673 | edgar_igl | #define MAX_OP_PER_INSTR 64 |
34 | 0115be31 | pbrook | /* A Call op needs up to 6 + 2N parameters (N = number of arguments). */
|
35 | 0115be31 | pbrook | #define MAX_OPC_PARAM 10 |
36 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
37 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
|
38 | b346ff46 | bellard | |
39 | a208e54a | pbrook | /* Maximum size a TCG op can expand to. This is complicated because a
|
40 | a208e54a | pbrook | single op may require several host instructions and regirster reloads.
|
41 | a208e54a | pbrook | For now take a wild guess at 128 bytes, which should allow at least
|
42 | a208e54a | pbrook | a couple of fixup instructions per argument. */
|
43 | a208e54a | pbrook | #define TCG_MAX_OP_SIZE 128 |
44 | a208e54a | pbrook | |
45 | 0115be31 | pbrook | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
|
46 | b346ff46 | bellard | |
47 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
|
48 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
|
49 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
|
50 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
|
51 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
52 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
|
53 | b346ff46 | bellard | |
54 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
55 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
56 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
57 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
58 | 3b46e624 | ths | |
59 | b346ff46 | bellard | #if defined(TARGET_I386)
|
60 | b346ff46 | bellard | |
61 | 33417e70 | bellard | void optimize_flags_init(void); |
62 | d4e8164f | bellard | |
63 | b346ff46 | bellard | #endif
|
64 | b346ff46 | bellard | |
65 | b346ff46 | bellard | extern FILE *logfile;
|
66 | b346ff46 | bellard | extern int loglevel; |
67 | b346ff46 | bellard | |
68 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
69 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
70 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, struct TranslationBlock *tb, |
71 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc); |
72 | d2856f1a | aurel32 | |
73 | d07bde88 | blueswir1 | unsigned long code_gen_max_block_size(void); |
74 | 57fec1fe | bellard | void cpu_gen_init(void); |
75 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
76 | d07bde88 | blueswir1 | int *gen_code_size_ptr);
|
77 | 5fafdf24 | ths | int cpu_restore_state(struct TranslationBlock *tb, |
78 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
79 | 58fe2f10 | bellard | void *puc);
|
80 | 5fafdf24 | ths | int cpu_restore_state_copy(struct TranslationBlock *tb, |
81 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
82 | 58fe2f10 | bellard | void *puc);
|
83 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
84 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
|
85 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
86 | 00f82b8a | aurel32 | void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
|
87 | 2e12669a | bellard | int is_cpu_write_access);
|
88 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
|
89 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
|
90 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
91 | 5fafdf24 | ths | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
|
92 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
|
93 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
94 | 4d7a0880 | blueswir1 | static inline int tlb_set_page(CPUState *env1, target_ulong vaddr, |
95 | 5fafdf24 | ths | target_phys_addr_t paddr, int prot,
|
96 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
97 | 84b7b8e7 | bellard | { |
98 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
|
99 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
100 | 4d7a0880 | blueswir1 | return tlb_set_page_exec(env1, vaddr, paddr, prot, mmu_idx, is_softmmu);
|
101 | 84b7b8e7 | bellard | } |
102 | d4e8164f | bellard | |
103 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
104 | d4e8164f | bellard | |
105 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
106 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
107 | 4390df51 | bellard | |
108 | d4e8164f | bellard | /* maximum total translate dcode allocated */
|
109 | 4390df51 | bellard | |
110 | 4390df51 | bellard | /* NOTE: the translated code area cannot be too big because on some
|
111 | c4c7e3e6 | bellard | archs the range of "fast" function calls is limited. Here is a
|
112 | 4390df51 | bellard | summary of the ranges:
|
113 | 4390df51 | bellard | |
114 | 4390df51 | bellard | i386 : signed 32 bits
|
115 | 4390df51 | bellard | arm : signed 26 bits
|
116 | 4390df51 | bellard | ppc : signed 24 bits
|
117 | 4390df51 | bellard | sparc : signed 32 bits
|
118 | 4390df51 | bellard | alpha : signed 23 bits
|
119 | 4390df51 | bellard | */
|
120 | 4390df51 | bellard | |
121 | 4390df51 | bellard | #if defined(__alpha__)
|
122 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
123 | b8076a74 | bellard | #elif defined(__ia64)
|
124 | b8076a74 | bellard | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ |
125 | 4390df51 | bellard | #elif defined(__powerpc__)
|
126 | c4c7e3e6 | bellard | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
127 | 4390df51 | bellard | #else
|
128 | 57fec1fe | bellard | /* XXX: make it dynamic on x86 */
|
129 | c98baaac | bellard | #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) |
130 | 4390df51 | bellard | #endif
|
131 | 4390df51 | bellard | |
132 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
|
133 | d4e8164f | bellard | |
134 | 4390df51 | bellard | /* estimated block size for TB allocation */
|
135 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
|
136 | 4390df51 | bellard | according to the host CPU */
|
137 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
|
138 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
139 | 4390df51 | bellard | #else
|
140 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
141 | 4390df51 | bellard | #endif
|
142 | 4390df51 | bellard | |
143 | 4390df51 | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
|
144 | 4390df51 | bellard | |
145 | 57fec1fe | bellard | #if defined(__powerpc__) || defined(__x86_64__)
|
146 | 4390df51 | bellard | #define USE_DIRECT_JUMP
|
147 | 4390df51 | bellard | #endif
|
148 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
|
149 | d4e8164f | bellard | #define USE_DIRECT_JUMP
|
150 | d4e8164f | bellard | #endif
|
151 | d4e8164f | bellard | |
152 | d4e8164f | bellard | typedef struct TranslationBlock { |
153 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
|
154 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
|
155 | c068688b | j_mayer | uint64_t flags; /* flags defining in which context the code was generated */
|
156 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
|
157 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
|
158 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
|
159 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
160 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
161 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
162 | 58fe2f10 | bellard | |
163 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
|
164 | 4390df51 | bellard | /* next matching tb for physical address. */
|
165 | 5fafdf24 | ths | struct TranslationBlock *phys_hash_next;
|
166 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
|
167 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
|
168 | 5fafdf24 | ths | struct TranslationBlock *page_next[2]; |
169 | 5fafdf24 | ths | target_ulong page_addr[2];
|
170 | 4390df51 | bellard | |
171 | d4e8164f | bellard | /* the following data are used to directly call another TB from
|
172 | d4e8164f | bellard | the code of this one. */
|
173 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
174 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
|
175 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
176 | d4e8164f | bellard | #else
|
177 | 57fec1fe | bellard | unsigned long tb_next[2]; /* address of jump generated code */ |
178 | d4e8164f | bellard | #endif
|
179 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
|
180 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
|
181 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
|
182 | d4e8164f | bellard | jmp_first */
|
183 | 5fafdf24 | ths | struct TranslationBlock *jmp_next[2]; |
184 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
|
185 | d4e8164f | bellard | } TranslationBlock; |
186 | d4e8164f | bellard | |
187 | b362e5e0 | pbrook | static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc) |
188 | b362e5e0 | pbrook | { |
189 | b362e5e0 | pbrook | target_ulong tmp; |
190 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
191 | b5e19d4c | edgar_igl | return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
|
192 | b362e5e0 | pbrook | } |
193 | b362e5e0 | pbrook | |
194 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
195 | d4e8164f | bellard | { |
196 | b362e5e0 | pbrook | target_ulong tmp; |
197 | b362e5e0 | pbrook | tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); |
198 | b5e19d4c | edgar_igl | return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
|
199 | b5e19d4c | edgar_igl | | (tmp & TB_JMP_ADDR_MASK)); |
200 | d4e8164f | bellard | } |
201 | d4e8164f | bellard | |
202 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
203 | 4390df51 | bellard | { |
204 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
205 | 4390df51 | bellard | } |
206 | 4390df51 | bellard | |
207 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
208 | 0124311e | bellard | void tb_flush(CPUState *env);
|
209 | 5fafdf24 | ths | void tb_link_phys(TranslationBlock *tb,
|
210 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
211 | d4e8164f | bellard | |
212 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
|
213 | d4e8164f | bellard | |
214 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
|
215 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
|
216 | d4e8164f | bellard | |
217 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
|
218 | 4390df51 | bellard | |
219 | 4390df51 | bellard | #if defined(__powerpc__)
|
220 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
221 | d4e8164f | bellard | { |
222 | d4e8164f | bellard | uint32_t val, *ptr; |
223 | d4e8164f | bellard | |
224 | d4e8164f | bellard | /* patch the branch destination */
|
225 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
226 | d4e8164f | bellard | val = *ptr; |
227 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
228 | d4e8164f | bellard | *ptr = val; |
229 | d4e8164f | bellard | /* flush icache */
|
230 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
231 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
232 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
233 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
234 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
235 | d4e8164f | bellard | } |
236 | 57fec1fe | bellard | #elif defined(__i386__) || defined(__x86_64__)
|
237 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
238 | 4390df51 | bellard | { |
239 | 4390df51 | bellard | /* patch the branch destination */
|
240 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
|
241 | 4390df51 | bellard | /* no need to flush icache explicitely */
|
242 | 4390df51 | bellard | } |
243 | 4390df51 | bellard | #endif
|
244 | d4e8164f | bellard | |
245 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
246 | 4cbb86e1 | bellard | int n, unsigned long addr) |
247 | 4cbb86e1 | bellard | { |
248 | 4cbb86e1 | bellard | unsigned long offset; |
249 | 4cbb86e1 | bellard | |
250 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
251 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
252 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
|
253 | 4cbb86e1 | bellard | if (offset != 0xffff) |
254 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
255 | 4cbb86e1 | bellard | } |
256 | 4cbb86e1 | bellard | |
257 | d4e8164f | bellard | #else
|
258 | d4e8164f | bellard | |
259 | d4e8164f | bellard | /* set the jump target */
|
260 | 5fafdf24 | ths | static inline void tb_set_jmp_target(TranslationBlock *tb, |
261 | d4e8164f | bellard | int n, unsigned long addr) |
262 | d4e8164f | bellard | { |
263 | 95f7652d | bellard | tb->tb_next[n] = addr; |
264 | d4e8164f | bellard | } |
265 | d4e8164f | bellard | |
266 | d4e8164f | bellard | #endif
|
267 | d4e8164f | bellard | |
268 | 5fafdf24 | ths | static inline void tb_add_jump(TranslationBlock *tb, int n, |
269 | d4e8164f | bellard | TranslationBlock *tb_next) |
270 | d4e8164f | bellard | { |
271 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
|
272 | cf25629d | bellard | if (!tb->jmp_next[n]) {
|
273 | cf25629d | bellard | /* patch the native jump address */
|
274 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
275 | 3b46e624 | ths | |
276 | cf25629d | bellard | /* add in TB jmp circular list */
|
277 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
278 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
|
279 | cf25629d | bellard | } |
280 | d4e8164f | bellard | } |
281 | d4e8164f | bellard | |
282 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
283 | a513fe19 | bellard | |
284 | d4e8164f | bellard | #ifndef offsetof
|
285 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
286 | d4e8164f | bellard | #endif
|
287 | d4e8164f | bellard | |
288 | d549f7d9 | bellard | #if defined(_WIN32)
|
289 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
290 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
291 | d549f7d9 | bellard | #elif defined(__APPLE__)
|
292 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
293 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
294 | d549f7d9 | bellard | #else
|
295 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
296 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
297 | d549f7d9 | bellard | #endif
|
298 | d549f7d9 | bellard | |
299 | 75913b72 | bellard | #define ASM_OP_LABEL_NAME(n, opname) \
|
300 | 75913b72 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
301 | 75913b72 | bellard | |
302 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
303 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
304 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
305 | 33417e70 | bellard | |
306 | 15a51156 | aurel32 | #if defined(__hppa__)
|
307 | 15a51156 | aurel32 | |
308 | 15a51156 | aurel32 | typedef int spinlock_t[4]; |
309 | 15a51156 | aurel32 | |
310 | 15a51156 | aurel32 | #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 } |
311 | 15a51156 | aurel32 | |
312 | 15a51156 | aurel32 | static inline void resetlock (spinlock_t *p) |
313 | 15a51156 | aurel32 | { |
314 | 15a51156 | aurel32 | (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1; |
315 | 15a51156 | aurel32 | } |
316 | 15a51156 | aurel32 | |
317 | 15a51156 | aurel32 | #else
|
318 | 15a51156 | aurel32 | |
319 | 15a51156 | aurel32 | typedef int spinlock_t; |
320 | 15a51156 | aurel32 | |
321 | 15a51156 | aurel32 | #define SPIN_LOCK_UNLOCKED 0 |
322 | 15a51156 | aurel32 | |
323 | 15a51156 | aurel32 | static inline void resetlock (spinlock_t *p) |
324 | 15a51156 | aurel32 | { |
325 | 15a51156 | aurel32 | *p = SPIN_LOCK_UNLOCKED; |
326 | 15a51156 | aurel32 | } |
327 | 15a51156 | aurel32 | |
328 | 15a51156 | aurel32 | #endif
|
329 | 15a51156 | aurel32 | |
330 | 204a1b8d | ths | #if defined(__powerpc__)
|
331 | d4e8164f | bellard | static inline int testandset (int *p) |
332 | d4e8164f | bellard | { |
333 | d4e8164f | bellard | int ret;
|
334 | d4e8164f | bellard | __asm__ __volatile__ ( |
335 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
|
336 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
|
337 | 02e1ec9b | bellard | " bne 1f\n"
|
338 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
|
339 | 02e1ec9b | bellard | " bne- 0b\n"
|
340 | d4e8164f | bellard | "1: "
|
341 | d4e8164f | bellard | : "=&r" (ret)
|
342 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
343 | d4e8164f | bellard | : "cr0", "memory"); |
344 | d4e8164f | bellard | return ret;
|
345 | d4e8164f | bellard | } |
346 | 204a1b8d | ths | #elif defined(__i386__)
|
347 | d4e8164f | bellard | static inline int testandset (int *p) |
348 | d4e8164f | bellard | { |
349 | 4955a2cd | bellard | long int readval = 0; |
350 | 3b46e624 | ths | |
351 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
|
352 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
353 | 4955a2cd | bellard | : "r" (1) |
354 | 4955a2cd | bellard | : "cc");
|
355 | 4955a2cd | bellard | return readval;
|
356 | d4e8164f | bellard | } |
357 | 204a1b8d | ths | #elif defined(__x86_64__)
|
358 | bc51c5c9 | bellard | static inline int testandset (int *p) |
359 | bc51c5c9 | bellard | { |
360 | 4955a2cd | bellard | long int readval = 0; |
361 | 3b46e624 | ths | |
362 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
|
363 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
364 | 4955a2cd | bellard | : "r" (1) |
365 | 4955a2cd | bellard | : "cc");
|
366 | 4955a2cd | bellard | return readval;
|
367 | bc51c5c9 | bellard | } |
368 | 204a1b8d | ths | #elif defined(__s390__)
|
369 | d4e8164f | bellard | static inline int testandset (int *p) |
370 | d4e8164f | bellard | { |
371 | d4e8164f | bellard | int ret;
|
372 | d4e8164f | bellard | |
373 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
|
374 | d4e8164f | bellard | " jl 0b"
|
375 | d4e8164f | bellard | : "=&d" (ret)
|
376 | 5fafdf24 | ths | : "r" (1), "a" (p), "0" (*p) |
377 | d4e8164f | bellard | : "cc", "memory" ); |
378 | d4e8164f | bellard | return ret;
|
379 | d4e8164f | bellard | } |
380 | 204a1b8d | ths | #elif defined(__alpha__)
|
381 | 2f87c607 | bellard | static inline int testandset (int *p) |
382 | d4e8164f | bellard | { |
383 | d4e8164f | bellard | int ret;
|
384 | d4e8164f | bellard | unsigned long one; |
385 | d4e8164f | bellard | |
386 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
|
387 | d4e8164f | bellard | " ldl_l %0,%1\n"
|
388 | d4e8164f | bellard | " stl_c %2,%1\n"
|
389 | d4e8164f | bellard | " beq %2,1f\n"
|
390 | d4e8164f | bellard | ".subsection 2\n"
|
391 | d4e8164f | bellard | "1: br 0b\n"
|
392 | d4e8164f | bellard | ".previous"
|
393 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
394 | d4e8164f | bellard | : "m" (*p));
|
395 | d4e8164f | bellard | return ret;
|
396 | d4e8164f | bellard | } |
397 | 204a1b8d | ths | #elif defined(__sparc__)
|
398 | d4e8164f | bellard | static inline int testandset (int *p) |
399 | d4e8164f | bellard | { |
400 | d4e8164f | bellard | int ret;
|
401 | d4e8164f | bellard | |
402 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
|
403 | d4e8164f | bellard | : "=r" (ret)
|
404 | d4e8164f | bellard | : "r" (p)
|
405 | d4e8164f | bellard | : "memory");
|
406 | d4e8164f | bellard | |
407 | d4e8164f | bellard | return (ret ? 1 : 0); |
408 | d4e8164f | bellard | } |
409 | 204a1b8d | ths | #elif defined(__arm__)
|
410 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
411 | a95c6790 | bellard | { |
412 | a95c6790 | bellard | register unsigned int ret; |
413 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
|
414 | a95c6790 | bellard | : "=r"(ret)
|
415 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
416 | 3b46e624 | ths | |
417 | a95c6790 | bellard | return ret;
|
418 | a95c6790 | bellard | } |
419 | 204a1b8d | ths | #elif defined(__mc68000)
|
420 | 38e584a0 | bellard | static inline int testandset (int *p) |
421 | 38e584a0 | bellard | { |
422 | 38e584a0 | bellard | char ret;
|
423 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
|
424 | 38e584a0 | bellard | : "=r" (ret)
|
425 | 38e584a0 | bellard | : "m" (p)
|
426 | 38e584a0 | bellard | : "cc","memory"); |
427 | 4955a2cd | bellard | return ret;
|
428 | 38e584a0 | bellard | } |
429 | 15a51156 | aurel32 | #elif defined(__hppa__)
|
430 | 15a51156 | aurel32 | |
431 | 15a51156 | aurel32 | /* Because malloc only guarantees 8-byte alignment for malloc'd data,
|
432 | 15a51156 | aurel32 | and GCC only guarantees 8-byte alignment for stack locals, we can't
|
433 | 15a51156 | aurel32 | be assured of 16-byte alignment for atomic lock data even if we
|
434 | 15a51156 | aurel32 | specify "__attribute ((aligned(16)))" in the type declaration. So,
|
435 | 15a51156 | aurel32 | we use a struct containing an array of four ints for the atomic lock
|
436 | 15a51156 | aurel32 | type and dynamically select the 16-byte aligned int from the array
|
437 | 15a51156 | aurel32 | for the semaphore. */
|
438 | 15a51156 | aurel32 | #define __PA_LDCW_ALIGNMENT 16 |
439 | 15a51156 | aurel32 | static inline void *ldcw_align (void *p) { |
440 | 15a51156 | aurel32 | unsigned long a = (unsigned long)p; |
441 | 15a51156 | aurel32 | a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1); |
442 | 15a51156 | aurel32 | return (void *)a; |
443 | 15a51156 | aurel32 | } |
444 | 15a51156 | aurel32 | |
445 | 15a51156 | aurel32 | static inline int testandset (spinlock_t *p) |
446 | 15a51156 | aurel32 | { |
447 | 15a51156 | aurel32 | unsigned int ret; |
448 | 15a51156 | aurel32 | p = ldcw_align(p); |
449 | 15a51156 | aurel32 | __asm__ __volatile__("ldcw 0(%1),%0"
|
450 | 15a51156 | aurel32 | : "=r" (ret)
|
451 | 15a51156 | aurel32 | : "r" (p)
|
452 | 15a51156 | aurel32 | : "memory" );
|
453 | 15a51156 | aurel32 | return !ret;
|
454 | 15a51156 | aurel32 | } |
455 | 15a51156 | aurel32 | |
456 | 204a1b8d | ths | #elif defined(__ia64)
|
457 | 38e584a0 | bellard | |
458 | b8076a74 | bellard | #include <ia64intrin.h> |
459 | b8076a74 | bellard | |
460 | b8076a74 | bellard | static inline int testandset (int *p) |
461 | b8076a74 | bellard | { |
462 | b8076a74 | bellard | return __sync_lock_test_and_set (p, 1); |
463 | b8076a74 | bellard | } |
464 | 204a1b8d | ths | #elif defined(__mips__)
|
465 | c4b89d18 | ths | static inline int testandset (int *p) |
466 | c4b89d18 | ths | { |
467 | c4b89d18 | ths | int ret;
|
468 | c4b89d18 | ths | |
469 | c4b89d18 | ths | __asm__ __volatile__ ( |
470 | c4b89d18 | ths | " .set push \n"
|
471 | c4b89d18 | ths | " .set noat \n"
|
472 | c4b89d18 | ths | " .set mips2 \n"
|
473 | c4b89d18 | ths | "1: li $1, 1 \n"
|
474 | c4b89d18 | ths | " ll %0, %1 \n"
|
475 | c4b89d18 | ths | " sc $1, %1 \n"
|
476 | 976a0d0d | ths | " beqz $1, 1b \n"
|
477 | c4b89d18 | ths | " .set pop "
|
478 | c4b89d18 | ths | : "=r" (ret), "+R" (*p) |
479 | c4b89d18 | ths | : |
480 | c4b89d18 | ths | : "memory");
|
481 | c4b89d18 | ths | |
482 | c4b89d18 | ths | return ret;
|
483 | c4b89d18 | ths | } |
484 | 204a1b8d | ths | #else
|
485 | 204a1b8d | ths | #error unimplemented CPU support
|
486 | c4b89d18 | ths | #endif
|
487 | c4b89d18 | ths | |
488 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
|
489 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
490 | d4e8164f | bellard | { |
491 | d4e8164f | bellard | while (testandset(lock));
|
492 | d4e8164f | bellard | } |
493 | d4e8164f | bellard | |
494 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
495 | d4e8164f | bellard | { |
496 | 15a51156 | aurel32 | resetlock(lock); |
497 | d4e8164f | bellard | } |
498 | d4e8164f | bellard | |
499 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
500 | d4e8164f | bellard | { |
501 | d4e8164f | bellard | return !testandset(lock);
|
502 | d4e8164f | bellard | } |
503 | 3c1cf9fa | bellard | #else
|
504 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
505 | 3c1cf9fa | bellard | { |
506 | 3c1cf9fa | bellard | } |
507 | 3c1cf9fa | bellard | |
508 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
509 | 3c1cf9fa | bellard | { |
510 | 3c1cf9fa | bellard | } |
511 | 3c1cf9fa | bellard | |
512 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
513 | 3c1cf9fa | bellard | { |
514 | 3c1cf9fa | bellard | return 1; |
515 | 3c1cf9fa | bellard | } |
516 | 3c1cf9fa | bellard | #endif
|
517 | d4e8164f | bellard | |
518 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
519 | d4e8164f | bellard | |
520 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
521 | 6e59c1db | bellard | |
522 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
523 | 6e59c1db | bellard | |
524 | 6ebbf390 | j_mayer | void tlb_fill(target_ulong addr, int is_write, int mmu_idx, |
525 | 6e59c1db | bellard | void *retaddr);
|
526 | 6e59c1db | bellard | |
527 | 6ebbf390 | j_mayer | #define ACCESS_TYPE (NB_MMU_MODES + 1) |
528 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
529 | 6e59c1db | bellard | #define env cpu_single_env
|
530 | 6e59c1db | bellard | |
531 | 6e59c1db | bellard | #define DATA_SIZE 1 |
532 | 6e59c1db | bellard | #include "softmmu_header.h" |
533 | 6e59c1db | bellard | |
534 | 6e59c1db | bellard | #define DATA_SIZE 2 |
535 | 6e59c1db | bellard | #include "softmmu_header.h" |
536 | 6e59c1db | bellard | |
537 | 6e59c1db | bellard | #define DATA_SIZE 4 |
538 | 6e59c1db | bellard | #include "softmmu_header.h" |
539 | 6e59c1db | bellard | |
540 | c27004ec | bellard | #define DATA_SIZE 8 |
541 | c27004ec | bellard | #include "softmmu_header.h" |
542 | c27004ec | bellard | |
543 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
544 | 6e59c1db | bellard | #undef MEMSUFFIX
|
545 | 6e59c1db | bellard | #undef env
|
546 | 6e59c1db | bellard | |
547 | 6e59c1db | bellard | #endif
|
548 | 4390df51 | bellard | |
549 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
550 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
551 | 4390df51 | bellard | { |
552 | 4390df51 | bellard | return addr;
|
553 | 4390df51 | bellard | } |
554 | 4390df51 | bellard | #else
|
555 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
556 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
557 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
558 | 4d7a0880 | blueswir1 | static inline target_ulong get_phys_addr_code(CPUState *env1, target_ulong addr) |
559 | 4390df51 | bellard | { |
560 | 4d7a0880 | blueswir1 | int mmu_idx, page_index, pd;
|
561 | 4390df51 | bellard | |
562 | 4d7a0880 | blueswir1 | page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
563 | 4d7a0880 | blueswir1 | mmu_idx = cpu_mmu_index(env1); |
564 | 4d7a0880 | blueswir1 | if (__builtin_expect(env1->tlb_table[mmu_idx][page_index].addr_code !=
|
565 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
566 | c27004ec | bellard | ldub_code(addr); |
567 | c27004ec | bellard | } |
568 | 4d7a0880 | blueswir1 | pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK; |
569 | 2a4188a3 | bellard | if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
|
570 | 647de6ca | ths | #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
|
571 | 6c36d3fa | blueswir1 | do_unassigned_access(addr, 0, 1, 0); |
572 | 6c36d3fa | blueswir1 | #else
|
573 | 4d7a0880 | blueswir1 | cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr); |
574 | 6c36d3fa | blueswir1 | #endif
|
575 | 4390df51 | bellard | } |
576 | 4d7a0880 | blueswir1 | return addr + env1->tlb_table[mmu_idx][page_index].addend - (unsigned long)phys_ram_base; |
577 | 4390df51 | bellard | } |
578 | 4390df51 | bellard | #endif
|
579 | 9df217a3 | bellard | |
580 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
581 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
582 | f32fc648 | bellard | |
583 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
|
584 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
|
585 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
586 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
587 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
588 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
589 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
|
590 | f32fc648 | bellard | void kqemu_record_dump(void); |
591 | 9df217a3 | bellard | |
592 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
593 | 9df217a3 | bellard | { |
594 | 9df217a3 | bellard | return(env->kqemu_enabled &&
|
595 | 5fafdf24 | ths | (env->cr[0] & CR0_PE_MASK) &&
|
596 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
597 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
598 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
599 | 5fafdf24 | ths | (env->kqemu_enabled == 2 ||
|
600 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
|
601 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
602 | 9df217a3 | bellard | } |
603 | 9df217a3 | bellard | |
604 | 9df217a3 | bellard | #endif |