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| 1 | 6af0bf9c | bellard | /*
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| 2 | 6af0bf9c | bellard | * MIPS emulation micro-operations for qemu.
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| 3 | 5fafdf24 | ths | *
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| 4 | 6af0bf9c | bellard | * Copyright (c) 2004-2005 Jocelyn Mayer
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| 5 | 6ea83fed | bellard | * Copyright (c) 2006 Marius Groeger (FPU operations)
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| 6 | 93b12ccc | ths | * Copyright (c) 2007 Thiemo Seufer (64-bit FPU support)
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| 7 | 6af0bf9c | bellard | *
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| 8 | 6af0bf9c | bellard | * This library is free software; you can redistribute it and/or
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| 9 | 6af0bf9c | bellard | * modify it under the terms of the GNU Lesser General Public
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| 10 | 6af0bf9c | bellard | * License as published by the Free Software Foundation; either
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| 11 | 6af0bf9c | bellard | * version 2 of the License, or (at your option) any later version.
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| 12 | 6af0bf9c | bellard | *
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| 13 | 6af0bf9c | bellard | * This library is distributed in the hope that it will be useful,
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| 14 | 6af0bf9c | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 15 | 6af0bf9c | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 16 | 6af0bf9c | bellard | * Lesser General Public License for more details.
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| 17 | 6af0bf9c | bellard | *
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| 18 | 6af0bf9c | bellard | * You should have received a copy of the GNU Lesser General Public
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| 19 | 6af0bf9c | bellard | * License along with this library; if not, write to the Free Software
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| 20 | 6af0bf9c | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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| 21 | 6af0bf9c | bellard | */
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| 22 | 6af0bf9c | bellard | |
| 23 | 6af0bf9c | bellard | #include "config.h" |
| 24 | 6af0bf9c | bellard | #include "exec.h" |
| 25 | 05f778c8 | ths | #include "host-utils.h" |
| 26 | 6af0bf9c | bellard | |
| 27 | 1b351e52 | bellard | #ifndef CALL_FROM_TB0
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| 28 | 5a5012ec | ths | #define CALL_FROM_TB0(func) func()
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| 29 | 1b351e52 | bellard | #endif
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| 30 | 1b351e52 | bellard | #ifndef CALL_FROM_TB1
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| 31 | 5a5012ec | ths | #define CALL_FROM_TB1(func, arg0) func(arg0)
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| 32 | 1b351e52 | bellard | #endif
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| 33 | 1b351e52 | bellard | #ifndef CALL_FROM_TB1_CONST16
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| 34 | 5a5012ec | ths | #define CALL_FROM_TB1_CONST16(func, arg0) CALL_FROM_TB1(func, arg0)
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| 35 | 1b351e52 | bellard | #endif
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| 36 | 1b351e52 | bellard | #ifndef CALL_FROM_TB2
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| 37 | 5a5012ec | ths | #define CALL_FROM_TB2(func, arg0, arg1) func(arg0, arg1)
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| 38 | 1b351e52 | bellard | #endif
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| 39 | 1b351e52 | bellard | #ifndef CALL_FROM_TB2_CONST16
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| 40 | 1b351e52 | bellard | #define CALL_FROM_TB2_CONST16(func, arg0, arg1) \
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| 41 | 5a5012ec | ths | CALL_FROM_TB2(func, arg0, arg1) |
| 42 | 1b351e52 | bellard | #endif
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| 43 | 1b351e52 | bellard | #ifndef CALL_FROM_TB3
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| 44 | 5a5012ec | ths | #define CALL_FROM_TB3(func, arg0, arg1, arg2) func(arg0, arg1, arg2)
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| 45 | 1b351e52 | bellard | #endif
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| 46 | 1b351e52 | bellard | #ifndef CALL_FROM_TB4
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| 47 | 1b351e52 | bellard | #define CALL_FROM_TB4(func, arg0, arg1, arg2, arg3) \
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| 48 | 5a5012ec | ths | func(arg0, arg1, arg2, arg3) |
| 49 | 1b351e52 | bellard | #endif
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| 50 | 1b351e52 | bellard | |
| 51 | 5a5012ec | ths | #define FREG 0 |
| 52 | 6ea83fed | bellard | #include "fop_template.c" |
| 53 | 5a5012ec | ths | #undef FREG
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| 54 | 5a5012ec | ths | #define FREG 1 |
| 55 | 6ea83fed | bellard | #include "fop_template.c" |
| 56 | 5a5012ec | ths | #undef FREG
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| 57 | 5a5012ec | ths | #define FREG 2 |
| 58 | 6ea83fed | bellard | #include "fop_template.c" |
| 59 | 5a5012ec | ths | #undef FREG
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| 60 | 5a5012ec | ths | #define FREG 3 |
| 61 | 6ea83fed | bellard | #include "fop_template.c" |
| 62 | 5a5012ec | ths | #undef FREG
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| 63 | 5a5012ec | ths | #define FREG 4 |
| 64 | 6ea83fed | bellard | #include "fop_template.c" |
| 65 | 5a5012ec | ths | #undef FREG
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| 66 | 5a5012ec | ths | #define FREG 5 |
| 67 | 6ea83fed | bellard | #include "fop_template.c" |
| 68 | 5a5012ec | ths | #undef FREG
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| 69 | 5a5012ec | ths | #define FREG 6 |
| 70 | 6ea83fed | bellard | #include "fop_template.c" |
| 71 | 5a5012ec | ths | #undef FREG
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| 72 | 5a5012ec | ths | #define FREG 7 |
| 73 | 6ea83fed | bellard | #include "fop_template.c" |
| 74 | 5a5012ec | ths | #undef FREG
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| 75 | 5a5012ec | ths | #define FREG 8 |
| 76 | 6ea83fed | bellard | #include "fop_template.c" |
| 77 | 5a5012ec | ths | #undef FREG
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| 78 | 5a5012ec | ths | #define FREG 9 |
| 79 | 6ea83fed | bellard | #include "fop_template.c" |
| 80 | 5a5012ec | ths | #undef FREG
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| 81 | 5a5012ec | ths | #define FREG 10 |
| 82 | 6ea83fed | bellard | #include "fop_template.c" |
| 83 | 5a5012ec | ths | #undef FREG
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| 84 | 5a5012ec | ths | #define FREG 11 |
| 85 | 6ea83fed | bellard | #include "fop_template.c" |
| 86 | 5a5012ec | ths | #undef FREG
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| 87 | 5a5012ec | ths | #define FREG 12 |
| 88 | 6ea83fed | bellard | #include "fop_template.c" |
| 89 | 5a5012ec | ths | #undef FREG
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| 90 | 5a5012ec | ths | #define FREG 13 |
| 91 | 6ea83fed | bellard | #include "fop_template.c" |
| 92 | 5a5012ec | ths | #undef FREG
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| 93 | 5a5012ec | ths | #define FREG 14 |
| 94 | 6ea83fed | bellard | #include "fop_template.c" |
| 95 | 5a5012ec | ths | #undef FREG
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| 96 | 5a5012ec | ths | #define FREG 15 |
| 97 | 6ea83fed | bellard | #include "fop_template.c" |
| 98 | 5a5012ec | ths | #undef FREG
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| 99 | 5a5012ec | ths | #define FREG 16 |
| 100 | 6ea83fed | bellard | #include "fop_template.c" |
| 101 | 5a5012ec | ths | #undef FREG
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| 102 | 5a5012ec | ths | #define FREG 17 |
| 103 | 6ea83fed | bellard | #include "fop_template.c" |
| 104 | 5a5012ec | ths | #undef FREG
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| 105 | 5a5012ec | ths | #define FREG 18 |
| 106 | 6ea83fed | bellard | #include "fop_template.c" |
| 107 | 5a5012ec | ths | #undef FREG
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| 108 | 5a5012ec | ths | #define FREG 19 |
| 109 | 6ea83fed | bellard | #include "fop_template.c" |
| 110 | 5a5012ec | ths | #undef FREG
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| 111 | 5a5012ec | ths | #define FREG 20 |
| 112 | 6ea83fed | bellard | #include "fop_template.c" |
| 113 | 5a5012ec | ths | #undef FREG
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| 114 | 5a5012ec | ths | #define FREG 21 |
| 115 | 6ea83fed | bellard | #include "fop_template.c" |
| 116 | 5a5012ec | ths | #undef FREG
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| 117 | 5a5012ec | ths | #define FREG 22 |
| 118 | 6ea83fed | bellard | #include "fop_template.c" |
| 119 | 5a5012ec | ths | #undef FREG
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| 120 | 5a5012ec | ths | #define FREG 23 |
| 121 | 6ea83fed | bellard | #include "fop_template.c" |
| 122 | 5a5012ec | ths | #undef FREG
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| 123 | 5a5012ec | ths | #define FREG 24 |
| 124 | 6ea83fed | bellard | #include "fop_template.c" |
| 125 | 5a5012ec | ths | #undef FREG
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| 126 | 5a5012ec | ths | #define FREG 25 |
| 127 | 6ea83fed | bellard | #include "fop_template.c" |
| 128 | 5a5012ec | ths | #undef FREG
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| 129 | 5a5012ec | ths | #define FREG 26 |
| 130 | 6ea83fed | bellard | #include "fop_template.c" |
| 131 | 5a5012ec | ths | #undef FREG
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| 132 | 5a5012ec | ths | #define FREG 27 |
| 133 | 6ea83fed | bellard | #include "fop_template.c" |
| 134 | 5a5012ec | ths | #undef FREG
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| 135 | 5a5012ec | ths | #define FREG 28 |
| 136 | 6ea83fed | bellard | #include "fop_template.c" |
| 137 | 5a5012ec | ths | #undef FREG
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| 138 | 5a5012ec | ths | #define FREG 29 |
| 139 | 6ea83fed | bellard | #include "fop_template.c" |
| 140 | 5a5012ec | ths | #undef FREG
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| 141 | 5a5012ec | ths | #define FREG 30 |
| 142 | 6ea83fed | bellard | #include "fop_template.c" |
| 143 | 5a5012ec | ths | #undef FREG
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| 144 | 5a5012ec | ths | #define FREG 31 |
| 145 | 6ea83fed | bellard | #include "fop_template.c" |
| 146 | 5a5012ec | ths | #undef FREG
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| 147 | 6ea83fed | bellard | |
| 148 | 6ea83fed | bellard | #define FTN
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| 149 | 6ea83fed | bellard | #include "fop_template.c" |
| 150 | 6ea83fed | bellard | #undef FTN
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| 151 | 6ea83fed | bellard | |
| 152 | 6af0bf9c | bellard | /* Load and store */
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| 153 | 6af0bf9c | bellard | #define MEMSUFFIX _raw
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| 154 | 6af0bf9c | bellard | #include "op_mem.c" |
| 155 | 6af0bf9c | bellard | #undef MEMSUFFIX
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| 156 | 6af0bf9c | bellard | #if !defined(CONFIG_USER_ONLY)
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| 157 | 6af0bf9c | bellard | #define MEMSUFFIX _user
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| 158 | 6af0bf9c | bellard | #include "op_mem.c" |
| 159 | 6af0bf9c | bellard | #undef MEMSUFFIX
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| 160 | 6af0bf9c | bellard | |
| 161 | 623a930e | ths | #define MEMSUFFIX _super
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| 162 | 623a930e | ths | #include "op_mem.c" |
| 163 | 623a930e | ths | #undef MEMSUFFIX
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| 164 | 623a930e | ths | |
| 165 | 6af0bf9c | bellard | #define MEMSUFFIX _kernel
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| 166 | 6af0bf9c | bellard | #include "op_mem.c" |
| 167 | 6af0bf9c | bellard | #undef MEMSUFFIX
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| 168 | 6af0bf9c | bellard | #endif
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| 169 | 6af0bf9c | bellard | |
| 170 | a6763a58 | ths | /* Addresses computation */
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| 171 | a6763a58 | ths | void op_addr_add (void) |
| 172 | a6763a58 | ths | {
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| 173 | a6763a58 | ths | /* For compatibility with 32-bit code, data reference in user mode
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| 174 | a6763a58 | ths | with Status_UX = 0 should be casted to 32-bit and sign extended.
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| 175 | a6763a58 | ths | See the MIPS64 PRA manual, section 4.10. */
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| 176 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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| 177 | 623a930e | ths | if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
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| 178 | a6763a58 | ths | !(env->CP0_Status & (1 << CP0St_UX)))
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| 179 | a6763a58 | ths | T0 = (int64_t)(int32_t)(T0 + T1); |
| 180 | a6763a58 | ths | else
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| 181 | a6763a58 | ths | #endif
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| 182 | a6763a58 | ths | T0 += T1; |
| 183 | 8f6f6026 | ths | FORCE_RET(); |
| 184 | a6763a58 | ths | } |
| 185 | a6763a58 | ths | |
| 186 | 6af0bf9c | bellard | /* Arithmetic */
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| 187 | 6af0bf9c | bellard | void op_add (void) |
| 188 | 6af0bf9c | bellard | {
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| 189 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 + (int32_t)T1); |
| 190 | 8f6f6026 | ths | FORCE_RET(); |
| 191 | 6af0bf9c | bellard | } |
| 192 | 6af0bf9c | bellard | |
| 193 | 6af0bf9c | bellard | void op_addo (void) |
| 194 | 6af0bf9c | bellard | {
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| 195 | 6af0bf9c | bellard | target_ulong tmp; |
| 196 | 6af0bf9c | bellard | |
| 197 | c570fd16 | ths | tmp = (int32_t)T0; |
| 198 | c570fd16 | ths | T0 = (int32_t)T0 + (int32_t)T1; |
| 199 | 76e050c2 | bellard | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 31) { |
| 200 | c570fd16 | ths | /* operands of same sign, result different sign */
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| 201 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
| 202 | 6af0bf9c | bellard | } |
| 203 | 5dc4b744 | ths | T0 = (int32_t)T0; |
| 204 | 8f6f6026 | ths | FORCE_RET(); |
| 205 | 6af0bf9c | bellard | } |
| 206 | 6af0bf9c | bellard | |
| 207 | 6af0bf9c | bellard | void op_sub (void) |
| 208 | 6af0bf9c | bellard | {
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| 209 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 - (int32_t)T1); |
| 210 | 8f6f6026 | ths | FORCE_RET(); |
| 211 | 6af0bf9c | bellard | } |
| 212 | 6af0bf9c | bellard | |
| 213 | 6af0bf9c | bellard | void op_subo (void) |
| 214 | 6af0bf9c | bellard | {
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| 215 | 6af0bf9c | bellard | target_ulong tmp; |
| 216 | 6af0bf9c | bellard | |
| 217 | c570fd16 | ths | tmp = (int32_t)T0; |
| 218 | 6af0bf9c | bellard | T0 = (int32_t)T0 - (int32_t)T1; |
| 219 | 76e050c2 | bellard | if (((tmp ^ T1) & (tmp ^ T0)) >> 31) { |
| 220 | c570fd16 | ths | /* operands of different sign, first operand and result different sign */
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| 221 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
| 222 | 6af0bf9c | bellard | } |
| 223 | 5dc4b744 | ths | T0 = (int32_t)T0; |
| 224 | 8f6f6026 | ths | FORCE_RET(); |
| 225 | 6af0bf9c | bellard | } |
| 226 | 6af0bf9c | bellard | |
| 227 | 6af0bf9c | bellard | void op_mul (void) |
| 228 | 6af0bf9c | bellard | {
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| 229 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T0 * (int32_t)T1); |
| 230 | 8f6f6026 | ths | FORCE_RET(); |
| 231 | 6af0bf9c | bellard | } |
| 232 | 6af0bf9c | bellard | |
| 233 | 80c27194 | ths | #if HOST_LONG_BITS < 64 |
| 234 | 80c27194 | ths | void op_div (void) |
| 235 | 80c27194 | ths | {
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| 236 | 80c27194 | ths | CALL_FROM_TB0(do_div); |
| 237 | 8f6f6026 | ths | FORCE_RET(); |
| 238 | 80c27194 | ths | } |
| 239 | 80c27194 | ths | #else
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| 240 | 6af0bf9c | bellard | void op_div (void) |
| 241 | 6af0bf9c | bellard | {
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| 242 | 6af0bf9c | bellard | if (T1 != 0) { |
| 243 | d0dc7dc3 | ths | env->LO[env->current_tc][0] = (int32_t)((int64_t)(int32_t)T0 / (int32_t)T1);
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| 244 | d0dc7dc3 | ths | env->HI[env->current_tc][0] = (int32_t)((int64_t)(int32_t)T0 % (int32_t)T1);
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| 245 | 6af0bf9c | bellard | } |
| 246 | 8f6f6026 | ths | FORCE_RET(); |
| 247 | 6af0bf9c | bellard | } |
| 248 | 80c27194 | ths | #endif
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| 249 | 6af0bf9c | bellard | |
| 250 | 6af0bf9c | bellard | void op_divu (void) |
| 251 | 6af0bf9c | bellard | {
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| 252 | 6af0bf9c | bellard | if (T1 != 0) { |
| 253 | d0dc7dc3 | ths | env->LO[env->current_tc][0] = (int32_t)((uint32_t)T0 / (uint32_t)T1);
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| 254 | d0dc7dc3 | ths | env->HI[env->current_tc][0] = (int32_t)((uint32_t)T0 % (uint32_t)T1);
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| 255 | c570fd16 | ths | } |
| 256 | 8f6f6026 | ths | FORCE_RET(); |
| 257 | c570fd16 | ths | } |
| 258 | c570fd16 | ths | |
| 259 | d26bc211 | ths | #if defined(TARGET_MIPS64)
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| 260 | c570fd16 | ths | /* Arithmetic */
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| 261 | c570fd16 | ths | void op_dadd (void) |
| 262 | c570fd16 | ths | {
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| 263 | c570fd16 | ths | T0 += T1; |
| 264 | 8f6f6026 | ths | FORCE_RET(); |
| 265 | c570fd16 | ths | } |
| 266 | c570fd16 | ths | |
| 267 | c570fd16 | ths | void op_daddo (void) |
| 268 | c570fd16 | ths | {
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| 269 | c570fd16 | ths | target_long tmp; |
| 270 | c570fd16 | ths | |
| 271 | c570fd16 | ths | tmp = T0; |
| 272 | c570fd16 | ths | T0 += T1; |
| 273 | c570fd16 | ths | if (((tmp ^ T1 ^ (-1)) & (T0 ^ T1)) >> 63) { |
| 274 | c570fd16 | ths | /* operands of same sign, result different sign */
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| 275 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
| 276 | c570fd16 | ths | } |
| 277 | 8f6f6026 | ths | FORCE_RET(); |
| 278 | c570fd16 | ths | } |
| 279 | c570fd16 | ths | |
| 280 | c570fd16 | ths | void op_dsub (void) |
| 281 | c570fd16 | ths | {
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| 282 | c570fd16 | ths | T0 -= T1; |
| 283 | 8f6f6026 | ths | FORCE_RET(); |
| 284 | c570fd16 | ths | } |
| 285 | c570fd16 | ths | |
| 286 | c570fd16 | ths | void op_dsubo (void) |
| 287 | c570fd16 | ths | {
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| 288 | c570fd16 | ths | target_long tmp; |
| 289 | c570fd16 | ths | |
| 290 | c570fd16 | ths | tmp = T0; |
| 291 | c570fd16 | ths | T0 = (int64_t)T0 - (int64_t)T1; |
| 292 | c570fd16 | ths | if (((tmp ^ T1) & (tmp ^ T0)) >> 63) { |
| 293 | c570fd16 | ths | /* operands of different sign, first operand and result different sign */
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| 294 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_OVERFLOW); |
| 295 | c570fd16 | ths | } |
| 296 | 8f6f6026 | ths | FORCE_RET(); |
| 297 | c570fd16 | ths | } |
| 298 | c570fd16 | ths | |
| 299 | c570fd16 | ths | void op_dmul (void) |
| 300 | c570fd16 | ths | {
|
| 301 | c570fd16 | ths | T0 = (int64_t)T0 * (int64_t)T1; |
| 302 | 8f6f6026 | ths | FORCE_RET(); |
| 303 | c570fd16 | ths | } |
| 304 | c570fd16 | ths | |
| 305 | c570fd16 | ths | /* Those might call libgcc functions. */
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| 306 | c570fd16 | ths | void op_ddiv (void) |
| 307 | c570fd16 | ths | {
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| 308 | c570fd16 | ths | do_ddiv(); |
| 309 | 8f6f6026 | ths | FORCE_RET(); |
| 310 | c570fd16 | ths | } |
| 311 | c570fd16 | ths | |
| 312 | 80c27194 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
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| 313 | c570fd16 | ths | void op_ddivu (void) |
| 314 | c570fd16 | ths | {
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| 315 | c570fd16 | ths | do_ddivu(); |
| 316 | 8f6f6026 | ths | FORCE_RET(); |
| 317 | c570fd16 | ths | } |
| 318 | c570fd16 | ths | #else
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| 319 | c570fd16 | ths | void op_ddivu (void) |
| 320 | c570fd16 | ths | {
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| 321 | c570fd16 | ths | if (T1 != 0) { |
| 322 | d0dc7dc3 | ths | env->LO[env->current_tc][0] = T0 / T1;
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| 323 | d0dc7dc3 | ths | env->HI[env->current_tc][0] = T0 % T1;
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| 324 | 6af0bf9c | bellard | } |
| 325 | 8f6f6026 | ths | FORCE_RET(); |
| 326 | 6af0bf9c | bellard | } |
| 327 | c570fd16 | ths | #endif
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| 328 | d26bc211 | ths | #endif /* TARGET_MIPS64 */ |
| 329 | 6af0bf9c | bellard | |
| 330 | 6af0bf9c | bellard | /* Logical */
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| 331 | 6af0bf9c | bellard | void op_and (void) |
| 332 | 6af0bf9c | bellard | {
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| 333 | 6af0bf9c | bellard | T0 &= T1; |
| 334 | 8f6f6026 | ths | FORCE_RET(); |
| 335 | 6af0bf9c | bellard | } |
| 336 | 6af0bf9c | bellard | |
| 337 | 6af0bf9c | bellard | void op_nor (void) |
| 338 | 6af0bf9c | bellard | {
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| 339 | 6af0bf9c | bellard | T0 = ~(T0 | T1); |
| 340 | 8f6f6026 | ths | FORCE_RET(); |
| 341 | 6af0bf9c | bellard | } |
| 342 | 6af0bf9c | bellard | |
| 343 | 6af0bf9c | bellard | void op_or (void) |
| 344 | 6af0bf9c | bellard | {
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| 345 | 6af0bf9c | bellard | T0 |= T1; |
| 346 | 8f6f6026 | ths | FORCE_RET(); |
| 347 | 6af0bf9c | bellard | } |
| 348 | 6af0bf9c | bellard | |
| 349 | 6af0bf9c | bellard | void op_xor (void) |
| 350 | 6af0bf9c | bellard | {
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| 351 | 6af0bf9c | bellard | T0 ^= T1; |
| 352 | 8f6f6026 | ths | FORCE_RET(); |
| 353 | 6af0bf9c | bellard | } |
| 354 | 6af0bf9c | bellard | |
| 355 | 6af0bf9c | bellard | void op_sll (void) |
| 356 | 6af0bf9c | bellard | {
|
| 357 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 << T1); |
| 358 | 8f6f6026 | ths | FORCE_RET(); |
| 359 | 6af0bf9c | bellard | } |
| 360 | 6af0bf9c | bellard | |
| 361 | 6af0bf9c | bellard | void op_sra (void) |
| 362 | 6af0bf9c | bellard | {
|
| 363 | 5a63bcb2 | ths | T0 = (int32_t)((int32_t)T0 >> T1); |
| 364 | 8f6f6026 | ths | FORCE_RET(); |
| 365 | 6af0bf9c | bellard | } |
| 366 | 6af0bf9c | bellard | |
| 367 | 6af0bf9c | bellard | void op_srl (void) |
| 368 | 6af0bf9c | bellard | {
|
| 369 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 >> T1); |
| 370 | 8f6f6026 | ths | FORCE_RET(); |
| 371 | 6af0bf9c | bellard | } |
| 372 | 6af0bf9c | bellard | |
| 373 | 7a387fff | ths | void op_rotr (void) |
| 374 | 7a387fff | ths | {
|
| 375 | 7a387fff | ths | target_ulong tmp; |
| 376 | 7a387fff | ths | |
| 377 | 7a387fff | ths | if (T1) {
|
| 378 | 5a63bcb2 | ths | tmp = (int32_t)((uint32_t)T0 << (0x20 - T1));
|
| 379 | 5a63bcb2 | ths | T0 = (int32_t)((uint32_t)T0 >> T1) | tmp; |
| 380 | 5a63bcb2 | ths | } |
| 381 | 8f6f6026 | ths | FORCE_RET(); |
| 382 | 7a387fff | ths | } |
| 383 | 7a387fff | ths | |
| 384 | 6af0bf9c | bellard | void op_sllv (void) |
| 385 | 6af0bf9c | bellard | {
|
| 386 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 << ((uint32_t)T0 & 0x1F));
|
| 387 | 8f6f6026 | ths | FORCE_RET(); |
| 388 | 6af0bf9c | bellard | } |
| 389 | 6af0bf9c | bellard | |
| 390 | 6af0bf9c | bellard | void op_srav (void) |
| 391 | 6af0bf9c | bellard | {
|
| 392 | 5dc4b744 | ths | T0 = (int32_t)((int32_t)T1 >> (T0 & 0x1F));
|
| 393 | 8f6f6026 | ths | FORCE_RET(); |
| 394 | 6af0bf9c | bellard | } |
| 395 | 6af0bf9c | bellard | |
| 396 | 6af0bf9c | bellard | void op_srlv (void) |
| 397 | 6af0bf9c | bellard | {
|
| 398 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 >> (T0 & 0x1F));
|
| 399 | 8f6f6026 | ths | FORCE_RET(); |
| 400 | 6af0bf9c | bellard | } |
| 401 | 6af0bf9c | bellard | |
| 402 | 7a387fff | ths | void op_rotrv (void) |
| 403 | 7a387fff | ths | {
|
| 404 | 7a387fff | ths | target_ulong tmp; |
| 405 | 7a387fff | ths | |
| 406 | 7a387fff | ths | T0 &= 0x1F;
|
| 407 | 7a387fff | ths | if (T0) {
|
| 408 | 5dc4b744 | ths | tmp = (int32_t)((uint32_t)T1 << (0x20 - T0));
|
| 409 | 5dc4b744 | ths | T0 = (int32_t)((uint32_t)T1 >> T0) | tmp; |
| 410 | 7a387fff | ths | } else
|
| 411 | 7a387fff | ths | T0 = T1; |
| 412 | 8f6f6026 | ths | FORCE_RET(); |
| 413 | 7a387fff | ths | } |
| 414 | 7a387fff | ths | |
| 415 | 6af0bf9c | bellard | void op_clo (void) |
| 416 | 6af0bf9c | bellard | {
|
| 417 | 05f778c8 | ths | T0 = clo32(T0); |
| 418 | 8f6f6026 | ths | FORCE_RET(); |
| 419 | 6af0bf9c | bellard | } |
| 420 | 6af0bf9c | bellard | |
| 421 | 6af0bf9c | bellard | void op_clz (void) |
| 422 | 6af0bf9c | bellard | {
|
| 423 | 05f778c8 | ths | T0 = clz32(T0); |
| 424 | 8f6f6026 | ths | FORCE_RET(); |
| 425 | 6af0bf9c | bellard | } |
| 426 | 6af0bf9c | bellard | |
| 427 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
| 428 | c570fd16 | ths | |
| 429 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
| 430 | c570fd16 | ths | /* Those might call libgcc functions. */
|
| 431 | c570fd16 | ths | void op_dsll (void) |
| 432 | 6af0bf9c | bellard | {
|
| 433 | c570fd16 | ths | CALL_FROM_TB0(do_dsll); |
| 434 | 8f6f6026 | ths | FORCE_RET(); |
| 435 | 6af0bf9c | bellard | } |
| 436 | 6af0bf9c | bellard | |
| 437 | c570fd16 | ths | void op_dsll32 (void) |
| 438 | 6af0bf9c | bellard | {
|
| 439 | c570fd16 | ths | CALL_FROM_TB0(do_dsll32); |
| 440 | 8f6f6026 | ths | FORCE_RET(); |
| 441 | 6af0bf9c | bellard | } |
| 442 | 6af0bf9c | bellard | |
| 443 | c570fd16 | ths | void op_dsra (void) |
| 444 | 6af0bf9c | bellard | {
|
| 445 | c570fd16 | ths | CALL_FROM_TB0(do_dsra); |
| 446 | 8f6f6026 | ths | FORCE_RET(); |
| 447 | 6af0bf9c | bellard | } |
| 448 | 6af0bf9c | bellard | |
| 449 | c570fd16 | ths | void op_dsra32 (void) |
| 450 | 6af0bf9c | bellard | {
|
| 451 | c570fd16 | ths | CALL_FROM_TB0(do_dsra32); |
| 452 | 8f6f6026 | ths | FORCE_RET(); |
| 453 | 6af0bf9c | bellard | } |
| 454 | 6af0bf9c | bellard | |
| 455 | c570fd16 | ths | void op_dsrl (void) |
| 456 | 6af0bf9c | bellard | {
|
| 457 | c570fd16 | ths | CALL_FROM_TB0(do_dsrl); |
| 458 | 8f6f6026 | ths | FORCE_RET(); |
| 459 | c570fd16 | ths | } |
| 460 | 6af0bf9c | bellard | |
| 461 | c570fd16 | ths | void op_dsrl32 (void) |
| 462 | c570fd16 | ths | {
|
| 463 | c570fd16 | ths | CALL_FROM_TB0(do_dsrl32); |
| 464 | 8f6f6026 | ths | FORCE_RET(); |
| 465 | 6af0bf9c | bellard | } |
| 466 | 6af0bf9c | bellard | |
| 467 | c570fd16 | ths | void op_drotr (void) |
| 468 | 6af0bf9c | bellard | {
|
| 469 | c570fd16 | ths | CALL_FROM_TB0(do_drotr); |
| 470 | 8f6f6026 | ths | FORCE_RET(); |
| 471 | c570fd16 | ths | } |
| 472 | 6af0bf9c | bellard | |
| 473 | c570fd16 | ths | void op_drotr32 (void) |
| 474 | c570fd16 | ths | {
|
| 475 | c570fd16 | ths | CALL_FROM_TB0(do_drotr32); |
| 476 | 8f6f6026 | ths | FORCE_RET(); |
| 477 | 6af0bf9c | bellard | } |
| 478 | 6af0bf9c | bellard | |
| 479 | c570fd16 | ths | void op_dsllv (void) |
| 480 | 6af0bf9c | bellard | {
|
| 481 | c570fd16 | ths | CALL_FROM_TB0(do_dsllv); |
| 482 | 8f6f6026 | ths | FORCE_RET(); |
| 483 | c570fd16 | ths | } |
| 484 | 6af0bf9c | bellard | |
| 485 | c570fd16 | ths | void op_dsrav (void) |
| 486 | c570fd16 | ths | {
|
| 487 | c570fd16 | ths | CALL_FROM_TB0(do_dsrav); |
| 488 | 8f6f6026 | ths | FORCE_RET(); |
| 489 | 6af0bf9c | bellard | } |
| 490 | 6af0bf9c | bellard | |
| 491 | c570fd16 | ths | void op_dsrlv (void) |
| 492 | 6af0bf9c | bellard | {
|
| 493 | c570fd16 | ths | CALL_FROM_TB0(do_dsrlv); |
| 494 | 8f6f6026 | ths | FORCE_RET(); |
| 495 | c570fd16 | ths | } |
| 496 | 6af0bf9c | bellard | |
| 497 | c570fd16 | ths | void op_drotrv (void) |
| 498 | c570fd16 | ths | {
|
| 499 | c570fd16 | ths | CALL_FROM_TB0(do_drotrv); |
| 500 | 8f6f6026 | ths | FORCE_RET(); |
| 501 | 6af0bf9c | bellard | } |
| 502 | c570fd16 | ths | |
| 503 | 05f778c8 | ths | void op_dclo (void) |
| 504 | 05f778c8 | ths | {
|
| 505 | 05f778c8 | ths | CALL_FROM_TB0(do_dclo); |
| 506 | 8f6f6026 | ths | FORCE_RET(); |
| 507 | 05f778c8 | ths | } |
| 508 | 05f778c8 | ths | |
| 509 | 05f778c8 | ths | void op_dclz (void) |
| 510 | 05f778c8 | ths | {
|
| 511 | 05f778c8 | ths | CALL_FROM_TB0(do_dclz); |
| 512 | 8f6f6026 | ths | FORCE_RET(); |
| 513 | 05f778c8 | ths | } |
| 514 | 05f778c8 | ths | |
| 515 | c570fd16 | ths | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
| 516 | c570fd16 | ths | |
| 517 | c570fd16 | ths | void op_dsll (void) |
| 518 | c570fd16 | ths | {
|
| 519 | c570fd16 | ths | T0 = T0 << T1; |
| 520 | 8f6f6026 | ths | FORCE_RET(); |
| 521 | c570fd16 | ths | } |
| 522 | c570fd16 | ths | |
| 523 | c570fd16 | ths | void op_dsll32 (void) |
| 524 | c570fd16 | ths | {
|
| 525 | c570fd16 | ths | T0 = T0 << (T1 + 32);
|
| 526 | 8f6f6026 | ths | FORCE_RET(); |
| 527 | c570fd16 | ths | } |
| 528 | c570fd16 | ths | |
| 529 | c570fd16 | ths | void op_dsra (void) |
| 530 | c570fd16 | ths | {
|
| 531 | c570fd16 | ths | T0 = (int64_t)T0 >> T1; |
| 532 | 8f6f6026 | ths | FORCE_RET(); |
| 533 | c570fd16 | ths | } |
| 534 | c570fd16 | ths | |
| 535 | c570fd16 | ths | void op_dsra32 (void) |
| 536 | c570fd16 | ths | {
|
| 537 | c570fd16 | ths | T0 = (int64_t)T0 >> (T1 + 32);
|
| 538 | 8f6f6026 | ths | FORCE_RET(); |
| 539 | c570fd16 | ths | } |
| 540 | c570fd16 | ths | |
| 541 | c570fd16 | ths | void op_dsrl (void) |
| 542 | c570fd16 | ths | {
|
| 543 | c570fd16 | ths | T0 = T0 >> T1; |
| 544 | 8f6f6026 | ths | FORCE_RET(); |
| 545 | c570fd16 | ths | } |
| 546 | c570fd16 | ths | |
| 547 | c570fd16 | ths | void op_dsrl32 (void) |
| 548 | c570fd16 | ths | {
|
| 549 | c570fd16 | ths | T0 = T0 >> (T1 + 32);
|
| 550 | 8f6f6026 | ths | FORCE_RET(); |
| 551 | c570fd16 | ths | } |
| 552 | c570fd16 | ths | |
| 553 | c570fd16 | ths | void op_drotr (void) |
| 554 | c570fd16 | ths | {
|
| 555 | c570fd16 | ths | target_ulong tmp; |
| 556 | c570fd16 | ths | |
| 557 | c570fd16 | ths | if (T1) {
|
| 558 | c6d6dd7c | ths | tmp = T0 << (0x40 - T1);
|
| 559 | c6d6dd7c | ths | T0 = (T0 >> T1) | tmp; |
| 560 | 5a63bcb2 | ths | } |
| 561 | 8f6f6026 | ths | FORCE_RET(); |
| 562 | c570fd16 | ths | } |
| 563 | c570fd16 | ths | |
| 564 | c570fd16 | ths | void op_drotr32 (void) |
| 565 | c570fd16 | ths | {
|
| 566 | c570fd16 | ths | target_ulong tmp; |
| 567 | c570fd16 | ths | |
| 568 | c6d6dd7c | ths | tmp = T0 << (0x40 - (32 + T1)); |
| 569 | c6d6dd7c | ths | T0 = (T0 >> (32 + T1)) | tmp;
|
| 570 | 8f6f6026 | ths | FORCE_RET(); |
| 571 | c570fd16 | ths | } |
| 572 | c570fd16 | ths | |
| 573 | c570fd16 | ths | void op_dsllv (void) |
| 574 | c570fd16 | ths | {
|
| 575 | c570fd16 | ths | T0 = T1 << (T0 & 0x3F);
|
| 576 | 8f6f6026 | ths | FORCE_RET(); |
| 577 | c570fd16 | ths | } |
| 578 | c570fd16 | ths | |
| 579 | c570fd16 | ths | void op_dsrav (void) |
| 580 | c570fd16 | ths | {
|
| 581 | c570fd16 | ths | T0 = (int64_t)T1 >> (T0 & 0x3F);
|
| 582 | 8f6f6026 | ths | FORCE_RET(); |
| 583 | c570fd16 | ths | } |
| 584 | c570fd16 | ths | |
| 585 | c570fd16 | ths | void op_dsrlv (void) |
| 586 | c570fd16 | ths | {
|
| 587 | c570fd16 | ths | T0 = T1 >> (T0 & 0x3F);
|
| 588 | 8f6f6026 | ths | FORCE_RET(); |
| 589 | c570fd16 | ths | } |
| 590 | c570fd16 | ths | |
| 591 | c570fd16 | ths | void op_drotrv (void) |
| 592 | c570fd16 | ths | {
|
| 593 | c570fd16 | ths | target_ulong tmp; |
| 594 | c570fd16 | ths | |
| 595 | c570fd16 | ths | T0 &= 0x3F;
|
| 596 | c570fd16 | ths | if (T0) {
|
| 597 | c6d6dd7c | ths | tmp = T1 << (0x40 - T0);
|
| 598 | c6d6dd7c | ths | T0 = (T1 >> T0) | tmp; |
| 599 | c570fd16 | ths | } else
|
| 600 | c6d6dd7c | ths | T0 = T1; |
| 601 | 8f6f6026 | ths | FORCE_RET(); |
| 602 | c570fd16 | ths | } |
| 603 | c570fd16 | ths | |
| 604 | c570fd16 | ths | void op_dclo (void) |
| 605 | c570fd16 | ths | {
|
| 606 | 05f778c8 | ths | T0 = clo64(T0); |
| 607 | 8f6f6026 | ths | FORCE_RET(); |
| 608 | c570fd16 | ths | } |
| 609 | c570fd16 | ths | |
| 610 | c570fd16 | ths | void op_dclz (void) |
| 611 | c570fd16 | ths | {
|
| 612 | 05f778c8 | ths | T0 = clz64(T0); |
| 613 | 8f6f6026 | ths | FORCE_RET(); |
| 614 | c570fd16 | ths | } |
| 615 | 05f778c8 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
| 616 | d26bc211 | ths | #endif /* TARGET_MIPS64 */ |
| 617 | c570fd16 | ths | |
| 618 | c570fd16 | ths | /* 64 bits arithmetic */
|
| 619 | c570fd16 | ths | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
| 620 | 6af0bf9c | bellard | void op_mult (void) |
| 621 | 6af0bf9c | bellard | {
|
| 622 | 6af0bf9c | bellard | CALL_FROM_TB0(do_mult); |
| 623 | 8f6f6026 | ths | FORCE_RET(); |
| 624 | 6af0bf9c | bellard | } |
| 625 | 6af0bf9c | bellard | |
| 626 | 6af0bf9c | bellard | void op_multu (void) |
| 627 | 6af0bf9c | bellard | {
|
| 628 | 6af0bf9c | bellard | CALL_FROM_TB0(do_multu); |
| 629 | 8f6f6026 | ths | FORCE_RET(); |
| 630 | 6af0bf9c | bellard | } |
| 631 | 6af0bf9c | bellard | |
| 632 | 6af0bf9c | bellard | void op_madd (void) |
| 633 | 6af0bf9c | bellard | {
|
| 634 | 6af0bf9c | bellard | CALL_FROM_TB0(do_madd); |
| 635 | 8f6f6026 | ths | FORCE_RET(); |
| 636 | 6af0bf9c | bellard | } |
| 637 | 6af0bf9c | bellard | |
| 638 | 6af0bf9c | bellard | void op_maddu (void) |
| 639 | 6af0bf9c | bellard | {
|
| 640 | 6af0bf9c | bellard | CALL_FROM_TB0(do_maddu); |
| 641 | 8f6f6026 | ths | FORCE_RET(); |
| 642 | 6af0bf9c | bellard | } |
| 643 | 6af0bf9c | bellard | |
| 644 | 6af0bf9c | bellard | void op_msub (void) |
| 645 | 6af0bf9c | bellard | {
|
| 646 | 6af0bf9c | bellard | CALL_FROM_TB0(do_msub); |
| 647 | 8f6f6026 | ths | FORCE_RET(); |
| 648 | 6af0bf9c | bellard | } |
| 649 | 6af0bf9c | bellard | |
| 650 | 6af0bf9c | bellard | void op_msubu (void) |
| 651 | 6af0bf9c | bellard | {
|
| 652 | 6af0bf9c | bellard | CALL_FROM_TB0(do_msubu); |
| 653 | 8f6f6026 | ths | FORCE_RET(); |
| 654 | 6af0bf9c | bellard | } |
| 655 | c570fd16 | ths | |
| 656 | e9c71dd1 | ths | /* Multiplication variants of the vr54xx. */
|
| 657 | e9c71dd1 | ths | void op_muls (void) |
| 658 | e9c71dd1 | ths | {
|
| 659 | e9c71dd1 | ths | CALL_FROM_TB0(do_muls); |
| 660 | e9c71dd1 | ths | FORCE_RET(); |
| 661 | e9c71dd1 | ths | } |
| 662 | e9c71dd1 | ths | |
| 663 | e9c71dd1 | ths | void op_mulsu (void) |
| 664 | e9c71dd1 | ths | {
|
| 665 | e9c71dd1 | ths | CALL_FROM_TB0(do_mulsu); |
| 666 | e9c71dd1 | ths | FORCE_RET(); |
| 667 | e9c71dd1 | ths | } |
| 668 | e9c71dd1 | ths | |
| 669 | e9c71dd1 | ths | void op_macc (void) |
| 670 | e9c71dd1 | ths | {
|
| 671 | e9c71dd1 | ths | CALL_FROM_TB0(do_macc); |
| 672 | e9c71dd1 | ths | FORCE_RET(); |
| 673 | e9c71dd1 | ths | } |
| 674 | e9c71dd1 | ths | |
| 675 | e9c71dd1 | ths | void op_macchi (void) |
| 676 | e9c71dd1 | ths | {
|
| 677 | e9c71dd1 | ths | CALL_FROM_TB0(do_macchi); |
| 678 | e9c71dd1 | ths | FORCE_RET(); |
| 679 | e9c71dd1 | ths | } |
| 680 | e9c71dd1 | ths | |
| 681 | e9c71dd1 | ths | void op_maccu (void) |
| 682 | e9c71dd1 | ths | {
|
| 683 | e9c71dd1 | ths | CALL_FROM_TB0(do_maccu); |
| 684 | e9c71dd1 | ths | FORCE_RET(); |
| 685 | e9c71dd1 | ths | } |
| 686 | e9c71dd1 | ths | void op_macchiu (void) |
| 687 | e9c71dd1 | ths | {
|
| 688 | e9c71dd1 | ths | CALL_FROM_TB0(do_macchiu); |
| 689 | e9c71dd1 | ths | FORCE_RET(); |
| 690 | e9c71dd1 | ths | } |
| 691 | e9c71dd1 | ths | |
| 692 | e9c71dd1 | ths | void op_msac (void) |
| 693 | e9c71dd1 | ths | {
|
| 694 | e9c71dd1 | ths | CALL_FROM_TB0(do_msac); |
| 695 | e9c71dd1 | ths | FORCE_RET(); |
| 696 | e9c71dd1 | ths | } |
| 697 | e9c71dd1 | ths | |
| 698 | e9c71dd1 | ths | void op_msachi (void) |
| 699 | e9c71dd1 | ths | {
|
| 700 | e9c71dd1 | ths | CALL_FROM_TB0(do_msachi); |
| 701 | e9c71dd1 | ths | FORCE_RET(); |
| 702 | e9c71dd1 | ths | } |
| 703 | e9c71dd1 | ths | |
| 704 | e9c71dd1 | ths | void op_msacu (void) |
| 705 | e9c71dd1 | ths | {
|
| 706 | e9c71dd1 | ths | CALL_FROM_TB0(do_msacu); |
| 707 | e9c71dd1 | ths | FORCE_RET(); |
| 708 | e9c71dd1 | ths | } |
| 709 | e9c71dd1 | ths | |
| 710 | e9c71dd1 | ths | void op_msachiu (void) |
| 711 | e9c71dd1 | ths | {
|
| 712 | e9c71dd1 | ths | CALL_FROM_TB0(do_msachiu); |
| 713 | e9c71dd1 | ths | FORCE_RET(); |
| 714 | e9c71dd1 | ths | } |
| 715 | e9c71dd1 | ths | |
| 716 | e9c71dd1 | ths | void op_mulhi (void) |
| 717 | e9c71dd1 | ths | {
|
| 718 | e9c71dd1 | ths | CALL_FROM_TB0(do_mulhi); |
| 719 | e9c71dd1 | ths | FORCE_RET(); |
| 720 | e9c71dd1 | ths | } |
| 721 | e9c71dd1 | ths | |
| 722 | e9c71dd1 | ths | void op_mulhiu (void) |
| 723 | e9c71dd1 | ths | {
|
| 724 | e9c71dd1 | ths | CALL_FROM_TB0(do_mulhiu); |
| 725 | e9c71dd1 | ths | FORCE_RET(); |
| 726 | e9c71dd1 | ths | } |
| 727 | e9c71dd1 | ths | |
| 728 | e9c71dd1 | ths | void op_mulshi (void) |
| 729 | e9c71dd1 | ths | {
|
| 730 | e9c71dd1 | ths | CALL_FROM_TB0(do_mulshi); |
| 731 | e9c71dd1 | ths | FORCE_RET(); |
| 732 | e9c71dd1 | ths | } |
| 733 | e9c71dd1 | ths | |
| 734 | e9c71dd1 | ths | void op_mulshiu (void) |
| 735 | e9c71dd1 | ths | {
|
| 736 | e9c71dd1 | ths | CALL_FROM_TB0(do_mulshiu); |
| 737 | e9c71dd1 | ths | FORCE_RET(); |
| 738 | e9c71dd1 | ths | } |
| 739 | e9c71dd1 | ths | |
| 740 | c570fd16 | ths | #else /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
| 741 | c570fd16 | ths | |
| 742 | aa343735 | ths | static always_inline uint64_t get_HILO (void) |
| 743 | c570fd16 | ths | {
|
| 744 | d0dc7dc3 | ths | return ((uint64_t)env->HI[env->current_tc][0] << 32) | |
| 745 | d0dc7dc3 | ths | ((uint64_t)(uint32_t)env->LO[env->current_tc][0]);
|
| 746 | c570fd16 | ths | } |
| 747 | c570fd16 | ths | |
| 748 | aa343735 | ths | static always_inline void set_HILO (uint64_t HILO) |
| 749 | c570fd16 | ths | {
|
| 750 | d0dc7dc3 | ths | env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); |
| 751 | d0dc7dc3 | ths | env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
| 752 | c570fd16 | ths | } |
| 753 | c570fd16 | ths | |
| 754 | e9c71dd1 | ths | static always_inline void set_HIT0_LO (uint64_t HILO) |
| 755 | e9c71dd1 | ths | {
|
| 756 | d0dc7dc3 | ths | env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); |
| 757 | d0dc7dc3 | ths | T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
| 758 | e9c71dd1 | ths | } |
| 759 | e9c71dd1 | ths | |
| 760 | e9c71dd1 | ths | static always_inline void set_HI_LOT0 (uint64_t HILO) |
| 761 | e9c71dd1 | ths | {
|
| 762 | d0dc7dc3 | ths | T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF); |
| 763 | d0dc7dc3 | ths | env->HI[env->current_tc][0] = (int32_t)(HILO >> 32); |
| 764 | e9c71dd1 | ths | } |
| 765 | e9c71dd1 | ths | |
| 766 | c570fd16 | ths | void op_mult (void) |
| 767 | c570fd16 | ths | {
|
| 768 | c570fd16 | ths | set_HILO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
| 769 | 8f6f6026 | ths | FORCE_RET(); |
| 770 | c570fd16 | ths | } |
| 771 | c570fd16 | ths | |
| 772 | c570fd16 | ths | void op_multu (void) |
| 773 | c570fd16 | ths | {
|
| 774 | c570fd16 | ths | set_HILO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
| 775 | 8f6f6026 | ths | FORCE_RET(); |
| 776 | c570fd16 | ths | } |
| 777 | c570fd16 | ths | |
| 778 | c570fd16 | ths | void op_madd (void) |
| 779 | c570fd16 | ths | {
|
| 780 | c570fd16 | ths | int64_t tmp; |
| 781 | c570fd16 | ths | |
| 782 | c570fd16 | ths | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
| 783 | c570fd16 | ths | set_HILO((int64_t)get_HILO() + tmp); |
| 784 | 8f6f6026 | ths | FORCE_RET(); |
| 785 | c570fd16 | ths | } |
| 786 | c570fd16 | ths | |
| 787 | c570fd16 | ths | void op_maddu (void) |
| 788 | c570fd16 | ths | {
|
| 789 | c570fd16 | ths | uint64_t tmp; |
| 790 | c570fd16 | ths | |
| 791 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
| 792 | c570fd16 | ths | set_HILO(get_HILO() + tmp); |
| 793 | 8f6f6026 | ths | FORCE_RET(); |
| 794 | c570fd16 | ths | } |
| 795 | c570fd16 | ths | |
| 796 | c570fd16 | ths | void op_msub (void) |
| 797 | c570fd16 | ths | {
|
| 798 | c570fd16 | ths | int64_t tmp; |
| 799 | c570fd16 | ths | |
| 800 | c570fd16 | ths | tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
| 801 | c570fd16 | ths | set_HILO((int64_t)get_HILO() - tmp); |
| 802 | 8f6f6026 | ths | FORCE_RET(); |
| 803 | c570fd16 | ths | } |
| 804 | c570fd16 | ths | |
| 805 | c570fd16 | ths | void op_msubu (void) |
| 806 | c570fd16 | ths | {
|
| 807 | c570fd16 | ths | uint64_t tmp; |
| 808 | c570fd16 | ths | |
| 809 | c570fd16 | ths | tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
| 810 | c570fd16 | ths | set_HILO(get_HILO() - tmp); |
| 811 | 8f6f6026 | ths | FORCE_RET(); |
| 812 | c570fd16 | ths | } |
| 813 | e9c71dd1 | ths | |
| 814 | e9c71dd1 | ths | /* Multiplication variants of the vr54xx. */
|
| 815 | e9c71dd1 | ths | void op_muls (void) |
| 816 | e9c71dd1 | ths | {
|
| 817 | e9c71dd1 | ths | set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
|
| 818 | e9c71dd1 | ths | FORCE_RET(); |
| 819 | e9c71dd1 | ths | } |
| 820 | e9c71dd1 | ths | |
| 821 | e9c71dd1 | ths | void op_mulsu (void) |
| 822 | e9c71dd1 | ths | {
|
| 823 | e9c71dd1 | ths | set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
|
| 824 | e9c71dd1 | ths | FORCE_RET(); |
| 825 | e9c71dd1 | ths | } |
| 826 | e9c71dd1 | ths | |
| 827 | e9c71dd1 | ths | void op_macc (void) |
| 828 | e9c71dd1 | ths | {
|
| 829 | e9c71dd1 | ths | set_HI_LOT0(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
| 830 | e9c71dd1 | ths | FORCE_RET(); |
| 831 | e9c71dd1 | ths | } |
| 832 | e9c71dd1 | ths | |
| 833 | e9c71dd1 | ths | void op_macchi (void) |
| 834 | e9c71dd1 | ths | {
|
| 835 | e9c71dd1 | ths | set_HIT0_LO(get_HILO() + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
| 836 | e9c71dd1 | ths | FORCE_RET(); |
| 837 | e9c71dd1 | ths | } |
| 838 | e9c71dd1 | ths | |
| 839 | e9c71dd1 | ths | void op_maccu (void) |
| 840 | e9c71dd1 | ths | {
|
| 841 | e9c71dd1 | ths | set_HI_LOT0(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
| 842 | e9c71dd1 | ths | FORCE_RET(); |
| 843 | e9c71dd1 | ths | } |
| 844 | e9c71dd1 | ths | |
| 845 | e9c71dd1 | ths | void op_macchiu (void) |
| 846 | e9c71dd1 | ths | {
|
| 847 | e9c71dd1 | ths | set_HIT0_LO(get_HILO() + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
| 848 | e9c71dd1 | ths | FORCE_RET(); |
| 849 | e9c71dd1 | ths | } |
| 850 | e9c71dd1 | ths | |
| 851 | e9c71dd1 | ths | void op_msac (void) |
| 852 | e9c71dd1 | ths | {
|
| 853 | e9c71dd1 | ths | set_HI_LOT0(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
| 854 | e9c71dd1 | ths | FORCE_RET(); |
| 855 | e9c71dd1 | ths | } |
| 856 | e9c71dd1 | ths | |
| 857 | e9c71dd1 | ths | void op_msachi (void) |
| 858 | e9c71dd1 | ths | {
|
| 859 | e9c71dd1 | ths | set_HIT0_LO(get_HILO() - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1)); |
| 860 | e9c71dd1 | ths | FORCE_RET(); |
| 861 | e9c71dd1 | ths | } |
| 862 | e9c71dd1 | ths | |
| 863 | e9c71dd1 | ths | void op_msacu (void) |
| 864 | e9c71dd1 | ths | {
|
| 865 | e9c71dd1 | ths | set_HI_LOT0(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
| 866 | e9c71dd1 | ths | FORCE_RET(); |
| 867 | e9c71dd1 | ths | } |
| 868 | e9c71dd1 | ths | |
| 869 | e9c71dd1 | ths | void op_msachiu (void) |
| 870 | e9c71dd1 | ths | {
|
| 871 | e9c71dd1 | ths | set_HIT0_LO(get_HILO() - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1)); |
| 872 | e9c71dd1 | ths | FORCE_RET(); |
| 873 | e9c71dd1 | ths | } |
| 874 | e9c71dd1 | ths | |
| 875 | e9c71dd1 | ths | void op_mulhi (void) |
| 876 | e9c71dd1 | ths | {
|
| 877 | e9c71dd1 | ths | set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1); |
| 878 | e9c71dd1 | ths | FORCE_RET(); |
| 879 | e9c71dd1 | ths | } |
| 880 | e9c71dd1 | ths | |
| 881 | e9c71dd1 | ths | void op_mulhiu (void) |
| 882 | e9c71dd1 | ths | {
|
| 883 | e9c71dd1 | ths | set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1); |
| 884 | e9c71dd1 | ths | FORCE_RET(); |
| 885 | e9c71dd1 | ths | } |
| 886 | e9c71dd1 | ths | |
| 887 | e9c71dd1 | ths | void op_mulshi (void) |
| 888 | e9c71dd1 | ths | {
|
| 889 | e9c71dd1 | ths | set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
|
| 890 | e9c71dd1 | ths | FORCE_RET(); |
| 891 | e9c71dd1 | ths | } |
| 892 | e9c71dd1 | ths | |
| 893 | e9c71dd1 | ths | void op_mulshiu (void) |
| 894 | e9c71dd1 | ths | {
|
| 895 | e9c71dd1 | ths | set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
|
| 896 | e9c71dd1 | ths | FORCE_RET(); |
| 897 | e9c71dd1 | ths | } |
| 898 | e9c71dd1 | ths | |
| 899 | c570fd16 | ths | #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */ |
| 900 | c570fd16 | ths | |
| 901 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
| 902 | c570fd16 | ths | void op_dmult (void) |
| 903 | c570fd16 | ths | {
|
| 904 | d0dc7dc3 | ths | CALL_FROM_TB4(muls64, &(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1); |
| 905 | 8f6f6026 | ths | FORCE_RET(); |
| 906 | c570fd16 | ths | } |
| 907 | c570fd16 | ths | |
| 908 | c570fd16 | ths | void op_dmultu (void) |
| 909 | c570fd16 | ths | {
|
| 910 | d0dc7dc3 | ths | CALL_FROM_TB4(mulu64, &(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1); |
| 911 | 8f6f6026 | ths | FORCE_RET(); |
| 912 | c570fd16 | ths | } |
| 913 | 6af0bf9c | bellard | #endif
|
| 914 | 6af0bf9c | bellard | |
| 915 | 6af0bf9c | bellard | /* Conditional moves */
|
| 916 | 6af0bf9c | bellard | void op_movn (void) |
| 917 | 6af0bf9c | bellard | {
|
| 918 | 6af0bf9c | bellard | if (T1 != 0) |
| 919 | d0dc7dc3 | ths | env->gpr[env->current_tc][PARAM1] = T0; |
| 920 | 8f6f6026 | ths | FORCE_RET(); |
| 921 | 6af0bf9c | bellard | } |
| 922 | 6af0bf9c | bellard | |
| 923 | 6af0bf9c | bellard | void op_movz (void) |
| 924 | 6af0bf9c | bellard | {
|
| 925 | 6af0bf9c | bellard | if (T1 == 0) |
| 926 | d0dc7dc3 | ths | env->gpr[env->current_tc][PARAM1] = T0; |
| 927 | 8f6f6026 | ths | FORCE_RET(); |
| 928 | 6af0bf9c | bellard | } |
| 929 | 6af0bf9c | bellard | |
| 930 | 7a387fff | ths | void op_movf (void) |
| 931 | 7a387fff | ths | {
|
| 932 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1))
|
| 933 | 5a5012ec | ths | T0 = T1; |
| 934 | 8f6f6026 | ths | FORCE_RET(); |
| 935 | 7a387fff | ths | } |
| 936 | 7a387fff | ths | |
| 937 | 7a387fff | ths | void op_movt (void) |
| 938 | 7a387fff | ths | {
|
| 939 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1)
|
| 940 | 5a5012ec | ths | T0 = T1; |
| 941 | 8f6f6026 | ths | FORCE_RET(); |
| 942 | 7a387fff | ths | } |
| 943 | 7a387fff | ths | |
| 944 | 6af0bf9c | bellard | /* Tests */
|
| 945 | 6af0bf9c | bellard | #define OP_COND(name, cond) \
|
| 946 | 6af0bf9c | bellard | void glue(op_, name) (void) \ |
| 947 | 6af0bf9c | bellard | { \
|
| 948 | 6af0bf9c | bellard | if (cond) { \
|
| 949 | 6af0bf9c | bellard | T0 = 1; \
|
| 950 | 6af0bf9c | bellard | } else { \
|
| 951 | 6af0bf9c | bellard | T0 = 0; \
|
| 952 | 6af0bf9c | bellard | } \ |
| 953 | 8f6f6026 | ths | FORCE_RET(); \ |
| 954 | 6af0bf9c | bellard | } |
| 955 | 6af0bf9c | bellard | |
| 956 | 6af0bf9c | bellard | OP_COND(eq, T0 == T1); |
| 957 | 6af0bf9c | bellard | OP_COND(ne, T0 != T1); |
| 958 | f469b9db | ths | OP_COND(ge, (target_long)T0 >= (target_long)T1); |
| 959 | 6af0bf9c | bellard | OP_COND(geu, T0 >= T1); |
| 960 | f469b9db | ths | OP_COND(lt, (target_long)T0 < (target_long)T1); |
| 961 | 6af0bf9c | bellard | OP_COND(ltu, T0 < T1); |
| 962 | f469b9db | ths | OP_COND(gez, (target_long)T0 >= 0);
|
| 963 | f469b9db | ths | OP_COND(gtz, (target_long)T0 > 0);
|
| 964 | f469b9db | ths | OP_COND(lez, (target_long)T0 <= 0);
|
| 965 | f469b9db | ths | OP_COND(ltz, (target_long)T0 < 0);
|
| 966 | 6af0bf9c | bellard | |
| 967 | 7a387fff | ths | /* Branches */
|
| 968 | 6af0bf9c | bellard | /* Branch to register */
|
| 969 | 6af0bf9c | bellard | void op_save_breg_target (void) |
| 970 | 6af0bf9c | bellard | {
|
| 971 | 39454628 | ths | env->btarget = T1; |
| 972 | 8f6f6026 | ths | FORCE_RET(); |
| 973 | 6af0bf9c | bellard | } |
| 974 | 6af0bf9c | bellard | |
| 975 | 6af0bf9c | bellard | void op_breg (void) |
| 976 | 6af0bf9c | bellard | {
|
| 977 | 39454628 | ths | env->PC[env->current_tc] = env->btarget; |
| 978 | 8f6f6026 | ths | FORCE_RET(); |
| 979 | 6af0bf9c | bellard | } |
| 980 | 6af0bf9c | bellard | |
| 981 | 6af0bf9c | bellard | void op_save_btarget (void) |
| 982 | 6af0bf9c | bellard | {
|
| 983 | 6af0bf9c | bellard | env->btarget = PARAM1; |
| 984 | 8f6f6026 | ths | FORCE_RET(); |
| 985 | 6af0bf9c | bellard | } |
| 986 | 6af0bf9c | bellard | |
| 987 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
| 988 | 9b9e4393 | ths | void op_save_btarget64 (void) |
| 989 | 9b9e4393 | ths | {
|
| 990 | 9b9e4393 | ths | env->btarget = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
|
| 991 | 8f6f6026 | ths | FORCE_RET(); |
| 992 | 9b9e4393 | ths | } |
| 993 | 9b9e4393 | ths | #endif
|
| 994 | 9b9e4393 | ths | |
| 995 | 6af0bf9c | bellard | /* Conditional branch */
|
| 996 | 6af0bf9c | bellard | void op_set_bcond (void) |
| 997 | 6af0bf9c | bellard | {
|
| 998 | 39454628 | ths | env->bcond = T0; |
| 999 | 8f6f6026 | ths | FORCE_RET(); |
| 1000 | 6af0bf9c | bellard | } |
| 1001 | 6af0bf9c | bellard | |
| 1002 | 39454628 | ths | void op_jnz_bcond (void) |
| 1003 | 6af0bf9c | bellard | {
|
| 1004 | 39454628 | ths | if (env->bcond)
|
| 1005 | c53be334 | bellard | GOTO_LABEL_PARAM(1);
|
| 1006 | 8f6f6026 | ths | FORCE_RET(); |
| 1007 | 6af0bf9c | bellard | } |
| 1008 | 6af0bf9c | bellard | |
| 1009 | 6af0bf9c | bellard | /* CP0 functions */
|
| 1010 | 873eb012 | ths | void op_mfc0_index (void) |
| 1011 | 6af0bf9c | bellard | {
|
| 1012 | 9c2149c8 | ths | T0 = env->CP0_Index; |
| 1013 | 8f6f6026 | ths | FORCE_RET(); |
| 1014 | 873eb012 | ths | } |
| 1015 | 873eb012 | ths | |
| 1016 | ead9360e | ths | void op_mfc0_mvpcontrol (void) |
| 1017 | ead9360e | ths | {
|
| 1018 | ead9360e | ths | T0 = env->mvp->CP0_MVPControl; |
| 1019 | 8f6f6026 | ths | FORCE_RET(); |
| 1020 | ead9360e | ths | } |
| 1021 | ead9360e | ths | |
| 1022 | ead9360e | ths | void op_mfc0_mvpconf0 (void) |
| 1023 | ead9360e | ths | {
|
| 1024 | ead9360e | ths | T0 = env->mvp->CP0_MVPConf0; |
| 1025 | 8f6f6026 | ths | FORCE_RET(); |
| 1026 | ead9360e | ths | } |
| 1027 | ead9360e | ths | |
| 1028 | ead9360e | ths | void op_mfc0_mvpconf1 (void) |
| 1029 | ead9360e | ths | {
|
| 1030 | ead9360e | ths | T0 = env->mvp->CP0_MVPConf1; |
| 1031 | 8f6f6026 | ths | FORCE_RET(); |
| 1032 | ead9360e | ths | } |
| 1033 | ead9360e | ths | |
| 1034 | 873eb012 | ths | void op_mfc0_random (void) |
| 1035 | 873eb012 | ths | {
|
| 1036 | 873eb012 | ths | CALL_FROM_TB0(do_mfc0_random); |
| 1037 | 8f6f6026 | ths | FORCE_RET(); |
| 1038 | 873eb012 | ths | } |
| 1039 | 873eb012 | ths | |
| 1040 | ead9360e | ths | void op_mfc0_vpecontrol (void) |
| 1041 | ead9360e | ths | {
|
| 1042 | ead9360e | ths | T0 = env->CP0_VPEControl; |
| 1043 | 8f6f6026 | ths | FORCE_RET(); |
| 1044 | ead9360e | ths | } |
| 1045 | ead9360e | ths | |
| 1046 | ead9360e | ths | void op_mfc0_vpeconf0 (void) |
| 1047 | ead9360e | ths | {
|
| 1048 | ead9360e | ths | T0 = env->CP0_VPEConf0; |
| 1049 | 8f6f6026 | ths | FORCE_RET(); |
| 1050 | ead9360e | ths | } |
| 1051 | ead9360e | ths | |
| 1052 | ead9360e | ths | void op_mfc0_vpeconf1 (void) |
| 1053 | ead9360e | ths | {
|
| 1054 | ead9360e | ths | T0 = env->CP0_VPEConf1; |
| 1055 | 8f6f6026 | ths | FORCE_RET(); |
| 1056 | ead9360e | ths | } |
| 1057 | ead9360e | ths | |
| 1058 | ead9360e | ths | void op_mfc0_yqmask (void) |
| 1059 | ead9360e | ths | {
|
| 1060 | ead9360e | ths | T0 = env->CP0_YQMask; |
| 1061 | 8f6f6026 | ths | FORCE_RET(); |
| 1062 | ead9360e | ths | } |
| 1063 | ead9360e | ths | |
| 1064 | ead9360e | ths | void op_mfc0_vpeschedule (void) |
| 1065 | ead9360e | ths | {
|
| 1066 | ead9360e | ths | T0 = env->CP0_VPESchedule; |
| 1067 | 8f6f6026 | ths | FORCE_RET(); |
| 1068 | ead9360e | ths | } |
| 1069 | ead9360e | ths | |
| 1070 | ead9360e | ths | void op_mfc0_vpeschefback (void) |
| 1071 | ead9360e | ths | {
|
| 1072 | ead9360e | ths | T0 = env->CP0_VPEScheFBack; |
| 1073 | 8f6f6026 | ths | FORCE_RET(); |
| 1074 | ead9360e | ths | } |
| 1075 | ead9360e | ths | |
| 1076 | ead9360e | ths | void op_mfc0_vpeopt (void) |
| 1077 | ead9360e | ths | {
|
| 1078 | ead9360e | ths | T0 = env->CP0_VPEOpt; |
| 1079 | 8f6f6026 | ths | FORCE_RET(); |
| 1080 | ead9360e | ths | } |
| 1081 | ead9360e | ths | |
| 1082 | 873eb012 | ths | void op_mfc0_entrylo0 (void) |
| 1083 | 873eb012 | ths | {
|
| 1084 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryLo0; |
| 1085 | 8f6f6026 | ths | FORCE_RET(); |
| 1086 | 873eb012 | ths | } |
| 1087 | 873eb012 | ths | |
| 1088 | ead9360e | ths | void op_mfc0_tcstatus (void) |
| 1089 | ead9360e | ths | {
|
| 1090 | ead9360e | ths | T0 = env->CP0_TCStatus[env->current_tc]; |
| 1091 | 8f6f6026 | ths | FORCE_RET(); |
| 1092 | ead9360e | ths | } |
| 1093 | ead9360e | ths | |
| 1094 | ead9360e | ths | void op_mftc0_tcstatus(void) |
| 1095 | ead9360e | ths | {
|
| 1096 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1097 | ead9360e | ths | |
| 1098 | ead9360e | ths | T0 = env->CP0_TCStatus[other_tc]; |
| 1099 | 8f6f6026 | ths | FORCE_RET(); |
| 1100 | ead9360e | ths | } |
| 1101 | ead9360e | ths | |
| 1102 | ead9360e | ths | void op_mfc0_tcbind (void) |
| 1103 | ead9360e | ths | {
|
| 1104 | ead9360e | ths | T0 = env->CP0_TCBind[env->current_tc]; |
| 1105 | 8f6f6026 | ths | FORCE_RET(); |
| 1106 | ead9360e | ths | } |
| 1107 | ead9360e | ths | |
| 1108 | ead9360e | ths | void op_mftc0_tcbind(void) |
| 1109 | ead9360e | ths | {
|
| 1110 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1111 | ead9360e | ths | |
| 1112 | ead9360e | ths | T0 = env->CP0_TCBind[other_tc]; |
| 1113 | 8f6f6026 | ths | FORCE_RET(); |
| 1114 | ead9360e | ths | } |
| 1115 | ead9360e | ths | |
| 1116 | ead9360e | ths | void op_mfc0_tcrestart (void) |
| 1117 | ead9360e | ths | {
|
| 1118 | ead9360e | ths | T0 = env->PC[env->current_tc]; |
| 1119 | 8f6f6026 | ths | FORCE_RET(); |
| 1120 | ead9360e | ths | } |
| 1121 | ead9360e | ths | |
| 1122 | ead9360e | ths | void op_mftc0_tcrestart(void) |
| 1123 | ead9360e | ths | {
|
| 1124 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1125 | ead9360e | ths | |
| 1126 | ead9360e | ths | T0 = env->PC[other_tc]; |
| 1127 | 8f6f6026 | ths | FORCE_RET(); |
| 1128 | ead9360e | ths | } |
| 1129 | ead9360e | ths | |
| 1130 | ead9360e | ths | void op_mfc0_tchalt (void) |
| 1131 | ead9360e | ths | {
|
| 1132 | ead9360e | ths | T0 = env->CP0_TCHalt[env->current_tc]; |
| 1133 | 8f6f6026 | ths | FORCE_RET(); |
| 1134 | ead9360e | ths | } |
| 1135 | ead9360e | ths | |
| 1136 | ead9360e | ths | void op_mftc0_tchalt(void) |
| 1137 | ead9360e | ths | {
|
| 1138 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1139 | ead9360e | ths | |
| 1140 | ead9360e | ths | T0 = env->CP0_TCHalt[other_tc]; |
| 1141 | 8f6f6026 | ths | FORCE_RET(); |
| 1142 | ead9360e | ths | } |
| 1143 | ead9360e | ths | |
| 1144 | ead9360e | ths | void op_mfc0_tccontext (void) |
| 1145 | ead9360e | ths | {
|
| 1146 | ead9360e | ths | T0 = env->CP0_TCContext[env->current_tc]; |
| 1147 | 8f6f6026 | ths | FORCE_RET(); |
| 1148 | ead9360e | ths | } |
| 1149 | ead9360e | ths | |
| 1150 | ead9360e | ths | void op_mftc0_tccontext(void) |
| 1151 | ead9360e | ths | {
|
| 1152 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1153 | ead9360e | ths | |
| 1154 | ead9360e | ths | T0 = env->CP0_TCContext[other_tc]; |
| 1155 | 8f6f6026 | ths | FORCE_RET(); |
| 1156 | ead9360e | ths | } |
| 1157 | ead9360e | ths | |
| 1158 | ead9360e | ths | void op_mfc0_tcschedule (void) |
| 1159 | ead9360e | ths | {
|
| 1160 | ead9360e | ths | T0 = env->CP0_TCSchedule[env->current_tc]; |
| 1161 | 8f6f6026 | ths | FORCE_RET(); |
| 1162 | ead9360e | ths | } |
| 1163 | ead9360e | ths | |
| 1164 | ead9360e | ths | void op_mftc0_tcschedule(void) |
| 1165 | ead9360e | ths | {
|
| 1166 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1167 | ead9360e | ths | |
| 1168 | ead9360e | ths | T0 = env->CP0_TCSchedule[other_tc]; |
| 1169 | 8f6f6026 | ths | FORCE_RET(); |
| 1170 | ead9360e | ths | } |
| 1171 | ead9360e | ths | |
| 1172 | ead9360e | ths | void op_mfc0_tcschefback (void) |
| 1173 | ead9360e | ths | {
|
| 1174 | ead9360e | ths | T0 = env->CP0_TCScheFBack[env->current_tc]; |
| 1175 | 8f6f6026 | ths | FORCE_RET(); |
| 1176 | ead9360e | ths | } |
| 1177 | ead9360e | ths | |
| 1178 | ead9360e | ths | void op_mftc0_tcschefback(void) |
| 1179 | ead9360e | ths | {
|
| 1180 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1181 | ead9360e | ths | |
| 1182 | ead9360e | ths | T0 = env->CP0_TCScheFBack[other_tc]; |
| 1183 | 8f6f6026 | ths | FORCE_RET(); |
| 1184 | ead9360e | ths | } |
| 1185 | ead9360e | ths | |
| 1186 | 873eb012 | ths | void op_mfc0_entrylo1 (void) |
| 1187 | 873eb012 | ths | {
|
| 1188 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryLo1; |
| 1189 | 8f6f6026 | ths | FORCE_RET(); |
| 1190 | 873eb012 | ths | } |
| 1191 | 873eb012 | ths | |
| 1192 | 873eb012 | ths | void op_mfc0_context (void) |
| 1193 | 873eb012 | ths | {
|
| 1194 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_Context; |
| 1195 | 8f6f6026 | ths | FORCE_RET(); |
| 1196 | 873eb012 | ths | } |
| 1197 | 873eb012 | ths | |
| 1198 | 873eb012 | ths | void op_mfc0_pagemask (void) |
| 1199 | 873eb012 | ths | {
|
| 1200 | 9c2149c8 | ths | T0 = env->CP0_PageMask; |
| 1201 | 8f6f6026 | ths | FORCE_RET(); |
| 1202 | 873eb012 | ths | } |
| 1203 | 873eb012 | ths | |
| 1204 | 7a387fff | ths | void op_mfc0_pagegrain (void) |
| 1205 | 7a387fff | ths | {
|
| 1206 | 9c2149c8 | ths | T0 = env->CP0_PageGrain; |
| 1207 | 8f6f6026 | ths | FORCE_RET(); |
| 1208 | 7a387fff | ths | } |
| 1209 | 7a387fff | ths | |
| 1210 | 873eb012 | ths | void op_mfc0_wired (void) |
| 1211 | 873eb012 | ths | {
|
| 1212 | 9c2149c8 | ths | T0 = env->CP0_Wired; |
| 1213 | 8f6f6026 | ths | FORCE_RET(); |
| 1214 | 873eb012 | ths | } |
| 1215 | 873eb012 | ths | |
| 1216 | ead9360e | ths | void op_mfc0_srsconf0 (void) |
| 1217 | ead9360e | ths | {
|
| 1218 | ead9360e | ths | T0 = env->CP0_SRSConf0; |
| 1219 | 8f6f6026 | ths | FORCE_RET(); |
| 1220 | ead9360e | ths | } |
| 1221 | ead9360e | ths | |
| 1222 | ead9360e | ths | void op_mfc0_srsconf1 (void) |
| 1223 | ead9360e | ths | {
|
| 1224 | ead9360e | ths | T0 = env->CP0_SRSConf1; |
| 1225 | 8f6f6026 | ths | FORCE_RET(); |
| 1226 | ead9360e | ths | } |
| 1227 | ead9360e | ths | |
| 1228 | ead9360e | ths | void op_mfc0_srsconf2 (void) |
| 1229 | ead9360e | ths | {
|
| 1230 | ead9360e | ths | T0 = env->CP0_SRSConf2; |
| 1231 | 8f6f6026 | ths | FORCE_RET(); |
| 1232 | ead9360e | ths | } |
| 1233 | ead9360e | ths | |
| 1234 | ead9360e | ths | void op_mfc0_srsconf3 (void) |
| 1235 | ead9360e | ths | {
|
| 1236 | ead9360e | ths | T0 = env->CP0_SRSConf3; |
| 1237 | 8f6f6026 | ths | FORCE_RET(); |
| 1238 | ead9360e | ths | } |
| 1239 | ead9360e | ths | |
| 1240 | ead9360e | ths | void op_mfc0_srsconf4 (void) |
| 1241 | ead9360e | ths | {
|
| 1242 | ead9360e | ths | T0 = env->CP0_SRSConf4; |
| 1243 | 8f6f6026 | ths | FORCE_RET(); |
| 1244 | ead9360e | ths | } |
| 1245 | ead9360e | ths | |
| 1246 | 7a387fff | ths | void op_mfc0_hwrena (void) |
| 1247 | 7a387fff | ths | {
|
| 1248 | 9c2149c8 | ths | T0 = env->CP0_HWREna; |
| 1249 | 8f6f6026 | ths | FORCE_RET(); |
| 1250 | 7a387fff | ths | } |
| 1251 | 7a387fff | ths | |
| 1252 | 873eb012 | ths | void op_mfc0_badvaddr (void) |
| 1253 | 873eb012 | ths | {
|
| 1254 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_BadVAddr; |
| 1255 | 8f6f6026 | ths | FORCE_RET(); |
| 1256 | 873eb012 | ths | } |
| 1257 | 873eb012 | ths | |
| 1258 | 873eb012 | ths | void op_mfc0_count (void) |
| 1259 | 873eb012 | ths | {
|
| 1260 | 873eb012 | ths | CALL_FROM_TB0(do_mfc0_count); |
| 1261 | 8f6f6026 | ths | FORCE_RET(); |
| 1262 | 873eb012 | ths | } |
| 1263 | 873eb012 | ths | |
| 1264 | 873eb012 | ths | void op_mfc0_entryhi (void) |
| 1265 | 873eb012 | ths | {
|
| 1266 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EntryHi; |
| 1267 | 8f6f6026 | ths | FORCE_RET(); |
| 1268 | 873eb012 | ths | } |
| 1269 | 873eb012 | ths | |
| 1270 | ead9360e | ths | void op_mftc0_entryhi(void) |
| 1271 | ead9360e | ths | {
|
| 1272 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1273 | ead9360e | ths | |
| 1274 | ead9360e | ths | T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff); |
| 1275 | 8f6f6026 | ths | FORCE_RET(); |
| 1276 | ead9360e | ths | } |
| 1277 | ead9360e | ths | |
| 1278 | 873eb012 | ths | void op_mfc0_compare (void) |
| 1279 | 873eb012 | ths | {
|
| 1280 | 9c2149c8 | ths | T0 = env->CP0_Compare; |
| 1281 | 8f6f6026 | ths | FORCE_RET(); |
| 1282 | 873eb012 | ths | } |
| 1283 | 873eb012 | ths | |
| 1284 | 873eb012 | ths | void op_mfc0_status (void) |
| 1285 | 873eb012 | ths | {
|
| 1286 | 9c2149c8 | ths | T0 = env->CP0_Status; |
| 1287 | 8f6f6026 | ths | FORCE_RET(); |
| 1288 | 873eb012 | ths | } |
| 1289 | 873eb012 | ths | |
| 1290 | ead9360e | ths | void op_mftc0_status(void) |
| 1291 | ead9360e | ths | {
|
| 1292 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1293 | ead9360e | ths | uint32_t tcstatus = env->CP0_TCStatus[other_tc]; |
| 1294 | ead9360e | ths | |
| 1295 | ead9360e | ths | T0 = env->CP0_Status & ~0xf1000018;
|
| 1296 | ead9360e | ths | T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
|
| 1297 | ead9360e | ths | T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
|
| 1298 | 623a930e | ths | T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
|
| 1299 | 8f6f6026 | ths | FORCE_RET(); |
| 1300 | ead9360e | ths | } |
| 1301 | ead9360e | ths | |
| 1302 | 7a387fff | ths | void op_mfc0_intctl (void) |
| 1303 | 7a387fff | ths | {
|
| 1304 | 9c2149c8 | ths | T0 = env->CP0_IntCtl; |
| 1305 | 8f6f6026 | ths | FORCE_RET(); |
| 1306 | 7a387fff | ths | } |
| 1307 | 7a387fff | ths | |
| 1308 | 7a387fff | ths | void op_mfc0_srsctl (void) |
| 1309 | 7a387fff | ths | {
|
| 1310 | 9c2149c8 | ths | T0 = env->CP0_SRSCtl; |
| 1311 | 8f6f6026 | ths | FORCE_RET(); |
| 1312 | 9c2149c8 | ths | } |
| 1313 | 9c2149c8 | ths | |
| 1314 | 9c2149c8 | ths | void op_mfc0_srsmap (void) |
| 1315 | 9c2149c8 | ths | {
|
| 1316 | 9c2149c8 | ths | T0 = env->CP0_SRSMap; |
| 1317 | 8f6f6026 | ths | FORCE_RET(); |
| 1318 | 7a387fff | ths | } |
| 1319 | 7a387fff | ths | |
| 1320 | 873eb012 | ths | void op_mfc0_cause (void) |
| 1321 | 873eb012 | ths | {
|
| 1322 | 9c2149c8 | ths | T0 = env->CP0_Cause; |
| 1323 | 8f6f6026 | ths | FORCE_RET(); |
| 1324 | 873eb012 | ths | } |
| 1325 | 873eb012 | ths | |
| 1326 | 873eb012 | ths | void op_mfc0_epc (void) |
| 1327 | 873eb012 | ths | {
|
| 1328 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_EPC; |
| 1329 | 8f6f6026 | ths | FORCE_RET(); |
| 1330 | 873eb012 | ths | } |
| 1331 | 873eb012 | ths | |
| 1332 | 873eb012 | ths | void op_mfc0_prid (void) |
| 1333 | 873eb012 | ths | {
|
| 1334 | 9c2149c8 | ths | T0 = env->CP0_PRid; |
| 1335 | 8f6f6026 | ths | FORCE_RET(); |
| 1336 | 873eb012 | ths | } |
| 1337 | 873eb012 | ths | |
| 1338 | 7a387fff | ths | void op_mfc0_ebase (void) |
| 1339 | 7a387fff | ths | {
|
| 1340 | b29a0341 | ths | T0 = env->CP0_EBase; |
| 1341 | 8f6f6026 | ths | FORCE_RET(); |
| 1342 | 7a387fff | ths | } |
| 1343 | 7a387fff | ths | |
| 1344 | 873eb012 | ths | void op_mfc0_config0 (void) |
| 1345 | 873eb012 | ths | {
|
| 1346 | 9c2149c8 | ths | T0 = env->CP0_Config0; |
| 1347 | 8f6f6026 | ths | FORCE_RET(); |
| 1348 | 873eb012 | ths | } |
| 1349 | 873eb012 | ths | |
| 1350 | 873eb012 | ths | void op_mfc0_config1 (void) |
| 1351 | 873eb012 | ths | {
|
| 1352 | 9c2149c8 | ths | T0 = env->CP0_Config1; |
| 1353 | 8f6f6026 | ths | FORCE_RET(); |
| 1354 | 873eb012 | ths | } |
| 1355 | 873eb012 | ths | |
| 1356 | 7a387fff | ths | void op_mfc0_config2 (void) |
| 1357 | 7a387fff | ths | {
|
| 1358 | 9c2149c8 | ths | T0 = env->CP0_Config2; |
| 1359 | 8f6f6026 | ths | FORCE_RET(); |
| 1360 | 7a387fff | ths | } |
| 1361 | 7a387fff | ths | |
| 1362 | 7a387fff | ths | void op_mfc0_config3 (void) |
| 1363 | 7a387fff | ths | {
|
| 1364 | 9c2149c8 | ths | T0 = env->CP0_Config3; |
| 1365 | 8f6f6026 | ths | FORCE_RET(); |
| 1366 | 7a387fff | ths | } |
| 1367 | 7a387fff | ths | |
| 1368 | e397ee33 | ths | void op_mfc0_config6 (void) |
| 1369 | e397ee33 | ths | {
|
| 1370 | e397ee33 | ths | T0 = env->CP0_Config6; |
| 1371 | 8f6f6026 | ths | FORCE_RET(); |
| 1372 | e397ee33 | ths | } |
| 1373 | e397ee33 | ths | |
| 1374 | e397ee33 | ths | void op_mfc0_config7 (void) |
| 1375 | e397ee33 | ths | {
|
| 1376 | e397ee33 | ths | T0 = env->CP0_Config7; |
| 1377 | 8f6f6026 | ths | FORCE_RET(); |
| 1378 | e397ee33 | ths | } |
| 1379 | e397ee33 | ths | |
| 1380 | 873eb012 | ths | void op_mfc0_lladdr (void) |
| 1381 | 873eb012 | ths | {
|
| 1382 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_LLAddr >> 4;
|
| 1383 | 8f6f6026 | ths | FORCE_RET(); |
| 1384 | 873eb012 | ths | } |
| 1385 | 873eb012 | ths | |
| 1386 | fd88b6ab | ths | void op_mfc0_watchlo (void) |
| 1387 | 873eb012 | ths | {
|
| 1388 | fd88b6ab | ths | T0 = (int32_t)env->CP0_WatchLo[PARAM1]; |
| 1389 | 8f6f6026 | ths | FORCE_RET(); |
| 1390 | 873eb012 | ths | } |
| 1391 | 873eb012 | ths | |
| 1392 | fd88b6ab | ths | void op_mfc0_watchhi (void) |
| 1393 | 873eb012 | ths | {
|
| 1394 | fd88b6ab | ths | T0 = env->CP0_WatchHi[PARAM1]; |
| 1395 | 8f6f6026 | ths | FORCE_RET(); |
| 1396 | 873eb012 | ths | } |
| 1397 | 873eb012 | ths | |
| 1398 | 7a387fff | ths | void op_mfc0_xcontext (void) |
| 1399 | 7a387fff | ths | {
|
| 1400 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_XContext; |
| 1401 | 8f6f6026 | ths | FORCE_RET(); |
| 1402 | 7a387fff | ths | } |
| 1403 | 7a387fff | ths | |
| 1404 | 7a387fff | ths | void op_mfc0_framemask (void) |
| 1405 | 7a387fff | ths | {
|
| 1406 | 7a387fff | ths | T0 = env->CP0_Framemask; |
| 1407 | 8f6f6026 | ths | FORCE_RET(); |
| 1408 | 7a387fff | ths | } |
| 1409 | 7a387fff | ths | |
| 1410 | 873eb012 | ths | void op_mfc0_debug (void) |
| 1411 | 873eb012 | ths | {
|
| 1412 | 9c2149c8 | ths | T0 = env->CP0_Debug; |
| 1413 | 873eb012 | ths | if (env->hflags & MIPS_HFLAG_DM)
|
| 1414 | 873eb012 | ths | T0 |= 1 << CP0DB_DM;
|
| 1415 | 8f6f6026 | ths | FORCE_RET(); |
| 1416 | 873eb012 | ths | } |
| 1417 | 873eb012 | ths | |
| 1418 | ead9360e | ths | void op_mftc0_debug(void) |
| 1419 | ead9360e | ths | {
|
| 1420 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1421 | ead9360e | ths | |
| 1422 | ead9360e | ths | /* XXX: Might be wrong, check with EJTAG spec. */
|
| 1423 | ead9360e | ths | T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
| 1424 | ead9360e | ths | (env->CP0_Debug_tcstatus[other_tc] & |
| 1425 | ead9360e | ths | ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
| 1426 | 8f6f6026 | ths | FORCE_RET(); |
| 1427 | ead9360e | ths | } |
| 1428 | ead9360e | ths | |
| 1429 | 873eb012 | ths | void op_mfc0_depc (void) |
| 1430 | 873eb012 | ths | {
|
| 1431 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_DEPC; |
| 1432 | 8f6f6026 | ths | FORCE_RET(); |
| 1433 | 873eb012 | ths | } |
| 1434 | 873eb012 | ths | |
| 1435 | 7a387fff | ths | void op_mfc0_performance0 (void) |
| 1436 | 7a387fff | ths | {
|
| 1437 | 9c2149c8 | ths | T0 = env->CP0_Performance0; |
| 1438 | 8f6f6026 | ths | FORCE_RET(); |
| 1439 | 7a387fff | ths | } |
| 1440 | 7a387fff | ths | |
| 1441 | 873eb012 | ths | void op_mfc0_taglo (void) |
| 1442 | 873eb012 | ths | {
|
| 1443 | 9c2149c8 | ths | T0 = env->CP0_TagLo; |
| 1444 | 8f6f6026 | ths | FORCE_RET(); |
| 1445 | 873eb012 | ths | } |
| 1446 | 873eb012 | ths | |
| 1447 | 873eb012 | ths | void op_mfc0_datalo (void) |
| 1448 | 873eb012 | ths | {
|
| 1449 | 9c2149c8 | ths | T0 = env->CP0_DataLo; |
| 1450 | 8f6f6026 | ths | FORCE_RET(); |
| 1451 | 873eb012 | ths | } |
| 1452 | 873eb012 | ths | |
| 1453 | 7a387fff | ths | void op_mfc0_taghi (void) |
| 1454 | 7a387fff | ths | {
|
| 1455 | 9c2149c8 | ths | T0 = env->CP0_TagHi; |
| 1456 | 8f6f6026 | ths | FORCE_RET(); |
| 1457 | 7a387fff | ths | } |
| 1458 | 7a387fff | ths | |
| 1459 | 7a387fff | ths | void op_mfc0_datahi (void) |
| 1460 | 7a387fff | ths | {
|
| 1461 | 9c2149c8 | ths | T0 = env->CP0_DataHi; |
| 1462 | 8f6f6026 | ths | FORCE_RET(); |
| 1463 | 7a387fff | ths | } |
| 1464 | 7a387fff | ths | |
| 1465 | 873eb012 | ths | void op_mfc0_errorepc (void) |
| 1466 | 873eb012 | ths | {
|
| 1467 | 9c2149c8 | ths | T0 = (int32_t)env->CP0_ErrorEPC; |
| 1468 | 8f6f6026 | ths | FORCE_RET(); |
| 1469 | 873eb012 | ths | } |
| 1470 | 873eb012 | ths | |
| 1471 | 873eb012 | ths | void op_mfc0_desave (void) |
| 1472 | 873eb012 | ths | {
|
| 1473 | 9c2149c8 | ths | T0 = env->CP0_DESAVE; |
| 1474 | 8f6f6026 | ths | FORCE_RET(); |
| 1475 | 6af0bf9c | bellard | } |
| 1476 | 6af0bf9c | bellard | |
| 1477 | 8c0fdd85 | ths | void op_mtc0_index (void) |
| 1478 | 6af0bf9c | bellard | {
|
| 1479 | 60445285 | ths | int num = 1; |
| 1480 | 60445285 | ths | unsigned int tmp = env->tlb->nb_tlb; |
| 1481 | 60445285 | ths | |
| 1482 | 60445285 | ths | do {
|
| 1483 | 60445285 | ths | tmp >>= 1;
|
| 1484 | 60445285 | ths | num <<= 1;
|
| 1485 | 60445285 | ths | } while (tmp);
|
| 1486 | 60445285 | ths | env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1)); |
| 1487 | 8f6f6026 | ths | FORCE_RET(); |
| 1488 | ead9360e | ths | } |
| 1489 | ead9360e | ths | |
| 1490 | ead9360e | ths | void op_mtc0_mvpcontrol (void) |
| 1491 | ead9360e | ths | {
|
| 1492 | ead9360e | ths | uint32_t mask = 0;
|
| 1493 | ead9360e | ths | uint32_t newval; |
| 1494 | ead9360e | ths | |
| 1495 | ead9360e | ths | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) |
| 1496 | ead9360e | ths | mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | |
| 1497 | ead9360e | ths | (1 << CP0MVPCo_EVP);
|
| 1498 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 1499 | ead9360e | ths | mask |= (1 << CP0MVPCo_STLB);
|
| 1500 | ead9360e | ths | newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask); |
| 1501 | ead9360e | ths | |
| 1502 | ead9360e | ths | // TODO: Enable/disable shared TLB, enable/disable VPEs.
|
| 1503 | ead9360e | ths | |
| 1504 | ead9360e | ths | env->mvp->CP0_MVPControl = newval; |
| 1505 | 8f6f6026 | ths | FORCE_RET(); |
| 1506 | ead9360e | ths | } |
| 1507 | ead9360e | ths | |
| 1508 | ead9360e | ths | void op_mtc0_vpecontrol (void) |
| 1509 | ead9360e | ths | {
|
| 1510 | ead9360e | ths | uint32_t mask; |
| 1511 | ead9360e | ths | uint32_t newval; |
| 1512 | ead9360e | ths | |
| 1513 | ead9360e | ths | mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | |
| 1514 | ead9360e | ths | (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); |
| 1515 | ead9360e | ths | newval = (env->CP0_VPEControl & ~mask) | (T0 & mask); |
| 1516 | ead9360e | ths | |
| 1517 | ead9360e | ths | /* Yield scheduler intercept not implemented. */
|
| 1518 | ead9360e | ths | /* Gating storage scheduler intercept not implemented. */
|
| 1519 | ead9360e | ths | |
| 1520 | ead9360e | ths | // TODO: Enable/disable TCs.
|
| 1521 | ead9360e | ths | |
| 1522 | ead9360e | ths | env->CP0_VPEControl = newval; |
| 1523 | 8f6f6026 | ths | FORCE_RET(); |
| 1524 | ead9360e | ths | } |
| 1525 | ead9360e | ths | |
| 1526 | ead9360e | ths | void op_mtc0_vpeconf0 (void) |
| 1527 | ead9360e | ths | {
|
| 1528 | ead9360e | ths | uint32_t mask = 0;
|
| 1529 | ead9360e | ths | uint32_t newval; |
| 1530 | ead9360e | ths | |
| 1531 | ead9360e | ths | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { |
| 1532 | ead9360e | ths | if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) |
| 1533 | ead9360e | ths | mask |= (0xff << CP0VPEC0_XTC);
|
| 1534 | ead9360e | ths | mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); |
| 1535 | ead9360e | ths | } |
| 1536 | ead9360e | ths | newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask); |
| 1537 | ead9360e | ths | |
| 1538 | ead9360e | ths | // TODO: TC exclusive handling due to ERL/EXL.
|
| 1539 | ead9360e | ths | |
| 1540 | ead9360e | ths | env->CP0_VPEConf0 = newval; |
| 1541 | 8f6f6026 | ths | FORCE_RET(); |
| 1542 | ead9360e | ths | } |
| 1543 | ead9360e | ths | |
| 1544 | ead9360e | ths | void op_mtc0_vpeconf1 (void) |
| 1545 | ead9360e | ths | {
|
| 1546 | ead9360e | ths | uint32_t mask = 0;
|
| 1547 | ead9360e | ths | uint32_t newval; |
| 1548 | ead9360e | ths | |
| 1549 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 1550 | ead9360e | ths | mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | |
| 1551 | ead9360e | ths | (0xff << CP0VPEC1_NCP1);
|
| 1552 | ead9360e | ths | newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask); |
| 1553 | ead9360e | ths | |
| 1554 | ead9360e | ths | /* UDI not implemented. */
|
| 1555 | ead9360e | ths | /* CP2 not implemented. */
|
| 1556 | ead9360e | ths | |
| 1557 | ead9360e | ths | // TODO: Handle FPU (CP1) binding.
|
| 1558 | ead9360e | ths | |
| 1559 | ead9360e | ths | env->CP0_VPEConf1 = newval; |
| 1560 | 8f6f6026 | ths | FORCE_RET(); |
| 1561 | ead9360e | ths | } |
| 1562 | ead9360e | ths | |
| 1563 | ead9360e | ths | void op_mtc0_yqmask (void) |
| 1564 | ead9360e | ths | {
|
| 1565 | ead9360e | ths | /* Yield qualifier inputs not implemented. */
|
| 1566 | ead9360e | ths | env->CP0_YQMask = 0x00000000;
|
| 1567 | 8f6f6026 | ths | FORCE_RET(); |
| 1568 | ead9360e | ths | } |
| 1569 | ead9360e | ths | |
| 1570 | ead9360e | ths | void op_mtc0_vpeschedule (void) |
| 1571 | ead9360e | ths | {
|
| 1572 | ead9360e | ths | env->CP0_VPESchedule = T0; |
| 1573 | 8f6f6026 | ths | FORCE_RET(); |
| 1574 | ead9360e | ths | } |
| 1575 | ead9360e | ths | |
| 1576 | ead9360e | ths | void op_mtc0_vpeschefback (void) |
| 1577 | ead9360e | ths | {
|
| 1578 | ead9360e | ths | env->CP0_VPEScheFBack = T0; |
| 1579 | 8f6f6026 | ths | FORCE_RET(); |
| 1580 | ead9360e | ths | } |
| 1581 | ead9360e | ths | |
| 1582 | ead9360e | ths | void op_mtc0_vpeopt (void) |
| 1583 | ead9360e | ths | {
|
| 1584 | ead9360e | ths | env->CP0_VPEOpt = T0 & 0x0000ffff;
|
| 1585 | 8f6f6026 | ths | FORCE_RET(); |
| 1586 | 8c0fdd85 | ths | } |
| 1587 | 8c0fdd85 | ths | |
| 1588 | 8c0fdd85 | ths | void op_mtc0_entrylo0 (void) |
| 1589 | 8c0fdd85 | ths | {
|
| 1590 | 6d35524c | ths | /* Large physaddr (PABITS) not implemented */
|
| 1591 | 7a387fff | ths | /* 1k pages not implemented */
|
| 1592 | f1b0aa5d | ths | env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
|
| 1593 | 8f6f6026 | ths | FORCE_RET(); |
| 1594 | 8c0fdd85 | ths | } |
| 1595 | 8c0fdd85 | ths | |
| 1596 | ead9360e | ths | void op_mtc0_tcstatus (void) |
| 1597 | ead9360e | ths | {
|
| 1598 | ead9360e | ths | uint32_t mask = env->CP0_TCStatus_rw_bitmask; |
| 1599 | ead9360e | ths | uint32_t newval; |
| 1600 | ead9360e | ths | |
| 1601 | ead9360e | ths | newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask); |
| 1602 | ead9360e | ths | |
| 1603 | ead9360e | ths | // TODO: Sync with CP0_Status.
|
| 1604 | ead9360e | ths | |
| 1605 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] = newval; |
| 1606 | 8f6f6026 | ths | FORCE_RET(); |
| 1607 | ead9360e | ths | } |
| 1608 | ead9360e | ths | |
| 1609 | ead9360e | ths | void op_mttc0_tcstatus (void) |
| 1610 | ead9360e | ths | {
|
| 1611 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1612 | ead9360e | ths | |
| 1613 | ead9360e | ths | // TODO: Sync with CP0_Status.
|
| 1614 | ead9360e | ths | |
| 1615 | ead9360e | ths | env->CP0_TCStatus[other_tc] = T0; |
| 1616 | 8f6f6026 | ths | FORCE_RET(); |
| 1617 | ead9360e | ths | } |
| 1618 | ead9360e | ths | |
| 1619 | ead9360e | ths | void op_mtc0_tcbind (void) |
| 1620 | ead9360e | ths | {
|
| 1621 | ead9360e | ths | uint32_t mask = (1 << CP0TCBd_TBE);
|
| 1622 | ead9360e | ths | uint32_t newval; |
| 1623 | ead9360e | ths | |
| 1624 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 1625 | ead9360e | ths | mask |= (1 << CP0TCBd_CurVPE);
|
| 1626 | ead9360e | ths | newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask); |
| 1627 | ead9360e | ths | env->CP0_TCBind[env->current_tc] = newval; |
| 1628 | 8f6f6026 | ths | FORCE_RET(); |
| 1629 | ead9360e | ths | } |
| 1630 | ead9360e | ths | |
| 1631 | ead9360e | ths | void op_mttc0_tcbind (void) |
| 1632 | ead9360e | ths | {
|
| 1633 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1634 | ead9360e | ths | uint32_t mask = (1 << CP0TCBd_TBE);
|
| 1635 | ead9360e | ths | uint32_t newval; |
| 1636 | ead9360e | ths | |
| 1637 | ead9360e | ths | if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) |
| 1638 | ead9360e | ths | mask |= (1 << CP0TCBd_CurVPE);
|
| 1639 | ead9360e | ths | newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask); |
| 1640 | ead9360e | ths | env->CP0_TCBind[other_tc] = newval; |
| 1641 | 8f6f6026 | ths | FORCE_RET(); |
| 1642 | ead9360e | ths | } |
| 1643 | ead9360e | ths | |
| 1644 | ead9360e | ths | void op_mtc0_tcrestart (void) |
| 1645 | ead9360e | ths | {
|
| 1646 | ead9360e | ths | env->PC[env->current_tc] = T0; |
| 1647 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
|
| 1648 | ead9360e | ths | env->CP0_LLAddr = 0ULL;
|
| 1649 | ead9360e | ths | /* MIPS16 not implemented. */
|
| 1650 | 8f6f6026 | ths | FORCE_RET(); |
| 1651 | ead9360e | ths | } |
| 1652 | ead9360e | ths | |
| 1653 | ead9360e | ths | void op_mttc0_tcrestart (void) |
| 1654 | ead9360e | ths | {
|
| 1655 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1656 | ead9360e | ths | |
| 1657 | ead9360e | ths | env->PC[other_tc] = T0; |
| 1658 | ead9360e | ths | env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
|
| 1659 | ead9360e | ths | env->CP0_LLAddr = 0ULL;
|
| 1660 | ead9360e | ths | /* MIPS16 not implemented. */
|
| 1661 | 8f6f6026 | ths | FORCE_RET(); |
| 1662 | ead9360e | ths | } |
| 1663 | ead9360e | ths | |
| 1664 | ead9360e | ths | void op_mtc0_tchalt (void) |
| 1665 | ead9360e | ths | {
|
| 1666 | ead9360e | ths | env->CP0_TCHalt[env->current_tc] = T0 & 0x1;
|
| 1667 | ead9360e | ths | |
| 1668 | ead9360e | ths | // TODO: Halt TC / Restart (if allocated+active) TC.
|
| 1669 | ead9360e | ths | |
| 1670 | 8f6f6026 | ths | FORCE_RET(); |
| 1671 | ead9360e | ths | } |
| 1672 | ead9360e | ths | |
| 1673 | ead9360e | ths | void op_mttc0_tchalt (void) |
| 1674 | ead9360e | ths | {
|
| 1675 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1676 | ead9360e | ths | |
| 1677 | ead9360e | ths | // TODO: Halt TC / Restart (if allocated+active) TC.
|
| 1678 | ead9360e | ths | |
| 1679 | ead9360e | ths | env->CP0_TCHalt[other_tc] = T0; |
| 1680 | 8f6f6026 | ths | FORCE_RET(); |
| 1681 | ead9360e | ths | } |
| 1682 | ead9360e | ths | |
| 1683 | ead9360e | ths | void op_mtc0_tccontext (void) |
| 1684 | ead9360e | ths | {
|
| 1685 | ead9360e | ths | env->CP0_TCContext[env->current_tc] = T0; |
| 1686 | 8f6f6026 | ths | FORCE_RET(); |
| 1687 | ead9360e | ths | } |
| 1688 | ead9360e | ths | |
| 1689 | ead9360e | ths | void op_mttc0_tccontext (void) |
| 1690 | ead9360e | ths | {
|
| 1691 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1692 | ead9360e | ths | |
| 1693 | ead9360e | ths | env->CP0_TCContext[other_tc] = T0; |
| 1694 | 8f6f6026 | ths | FORCE_RET(); |
| 1695 | ead9360e | ths | } |
| 1696 | ead9360e | ths | |
| 1697 | ead9360e | ths | void op_mtc0_tcschedule (void) |
| 1698 | ead9360e | ths | {
|
| 1699 | ead9360e | ths | env->CP0_TCSchedule[env->current_tc] = T0; |
| 1700 | 8f6f6026 | ths | FORCE_RET(); |
| 1701 | ead9360e | ths | } |
| 1702 | ead9360e | ths | |
| 1703 | ead9360e | ths | void op_mttc0_tcschedule (void) |
| 1704 | ead9360e | ths | {
|
| 1705 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1706 | ead9360e | ths | |
| 1707 | ead9360e | ths | env->CP0_TCSchedule[other_tc] = T0; |
| 1708 | 8f6f6026 | ths | FORCE_RET(); |
| 1709 | ead9360e | ths | } |
| 1710 | ead9360e | ths | |
| 1711 | ead9360e | ths | void op_mtc0_tcschefback (void) |
| 1712 | ead9360e | ths | {
|
| 1713 | ead9360e | ths | env->CP0_TCScheFBack[env->current_tc] = T0; |
| 1714 | 8f6f6026 | ths | FORCE_RET(); |
| 1715 | ead9360e | ths | } |
| 1716 | ead9360e | ths | |
| 1717 | ead9360e | ths | void op_mttc0_tcschefback (void) |
| 1718 | ead9360e | ths | {
|
| 1719 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1720 | ead9360e | ths | |
| 1721 | ead9360e | ths | env->CP0_TCScheFBack[other_tc] = T0; |
| 1722 | 8f6f6026 | ths | FORCE_RET(); |
| 1723 | ead9360e | ths | } |
| 1724 | ead9360e | ths | |
| 1725 | 8c0fdd85 | ths | void op_mtc0_entrylo1 (void) |
| 1726 | 8c0fdd85 | ths | {
|
| 1727 | 6d35524c | ths | /* Large physaddr (PABITS) not implemented */
|
| 1728 | 7a387fff | ths | /* 1k pages not implemented */
|
| 1729 | f1b0aa5d | ths | env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
|
| 1730 | 8f6f6026 | ths | FORCE_RET(); |
| 1731 | 8c0fdd85 | ths | } |
| 1732 | 8c0fdd85 | ths | |
| 1733 | 8c0fdd85 | ths | void op_mtc0_context (void) |
| 1734 | 8c0fdd85 | ths | {
|
| 1735 | 534ce69f | ths | env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF); |
| 1736 | 8f6f6026 | ths | FORCE_RET(); |
| 1737 | 8c0fdd85 | ths | } |
| 1738 | 8c0fdd85 | ths | |
| 1739 | 8c0fdd85 | ths | void op_mtc0_pagemask (void) |
| 1740 | 8c0fdd85 | ths | {
|
| 1741 | 7a387fff | ths | /* 1k pages not implemented */
|
| 1742 | f2e9ebef | ths | env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); |
| 1743 | 8f6f6026 | ths | FORCE_RET(); |
| 1744 | 7a387fff | ths | } |
| 1745 | 7a387fff | ths | |
| 1746 | 7a387fff | ths | void op_mtc0_pagegrain (void) |
| 1747 | 7a387fff | ths | {
|
| 1748 | 7a387fff | ths | /* SmartMIPS not implemented */
|
| 1749 | 6d35524c | ths | /* Large physaddr (PABITS) not implemented */
|
| 1750 | 7a387fff | ths | /* 1k pages not implemented */
|
| 1751 | 7a387fff | ths | env->CP0_PageGrain = 0;
|
| 1752 | 8f6f6026 | ths | FORCE_RET(); |
| 1753 | 8c0fdd85 | ths | } |
| 1754 | 8c0fdd85 | ths | |
| 1755 | 8c0fdd85 | ths | void op_mtc0_wired (void) |
| 1756 | 8c0fdd85 | ths | {
|
| 1757 | ead9360e | ths | env->CP0_Wired = T0 % env->tlb->nb_tlb; |
| 1758 | 8f6f6026 | ths | FORCE_RET(); |
| 1759 | ead9360e | ths | } |
| 1760 | ead9360e | ths | |
| 1761 | ead9360e | ths | void op_mtc0_srsconf0 (void) |
| 1762 | ead9360e | ths | {
|
| 1763 | ead9360e | ths | env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask; |
| 1764 | 8f6f6026 | ths | FORCE_RET(); |
| 1765 | ead9360e | ths | } |
| 1766 | ead9360e | ths | |
| 1767 | ead9360e | ths | void op_mtc0_srsconf1 (void) |
| 1768 | ead9360e | ths | {
|
| 1769 | ead9360e | ths | env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask; |
| 1770 | 8f6f6026 | ths | FORCE_RET(); |
| 1771 | ead9360e | ths | } |
| 1772 | ead9360e | ths | |
| 1773 | ead9360e | ths | void op_mtc0_srsconf2 (void) |
| 1774 | ead9360e | ths | {
|
| 1775 | ead9360e | ths | env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask; |
| 1776 | 8f6f6026 | ths | FORCE_RET(); |
| 1777 | ead9360e | ths | } |
| 1778 | ead9360e | ths | |
| 1779 | ead9360e | ths | void op_mtc0_srsconf3 (void) |
| 1780 | ead9360e | ths | {
|
| 1781 | ead9360e | ths | env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask; |
| 1782 | 8f6f6026 | ths | FORCE_RET(); |
| 1783 | ead9360e | ths | } |
| 1784 | ead9360e | ths | |
| 1785 | ead9360e | ths | void op_mtc0_srsconf4 (void) |
| 1786 | ead9360e | ths | {
|
| 1787 | ead9360e | ths | env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask; |
| 1788 | 8f6f6026 | ths | FORCE_RET(); |
| 1789 | 7a387fff | ths | } |
| 1790 | 7a387fff | ths | |
| 1791 | 7a387fff | ths | void op_mtc0_hwrena (void) |
| 1792 | 7a387fff | ths | {
|
| 1793 | 7a387fff | ths | env->CP0_HWREna = T0 & 0x0000000F;
|
| 1794 | 8f6f6026 | ths | FORCE_RET(); |
| 1795 | 8c0fdd85 | ths | } |
| 1796 | 8c0fdd85 | ths | |
| 1797 | 8c0fdd85 | ths | void op_mtc0_count (void) |
| 1798 | 8c0fdd85 | ths | {
|
| 1799 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_store_count, env, T0); |
| 1800 | 8f6f6026 | ths | FORCE_RET(); |
| 1801 | 8c0fdd85 | ths | } |
| 1802 | 8c0fdd85 | ths | |
| 1803 | 8c0fdd85 | ths | void op_mtc0_entryhi (void) |
| 1804 | 8c0fdd85 | ths | {
|
| 1805 | 0feef828 | ths | target_ulong old, val; |
| 1806 | 8c0fdd85 | ths | |
| 1807 | 7a387fff | ths | /* 1k pages not implemented */
|
| 1808 | 100ce988 | ths | val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF); |
| 1809 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
| 1810 | e034e2c3 | ths | val &= env->SEGMask; |
| 1811 | 100ce988 | ths | #endif
|
| 1812 | 8c0fdd85 | ths | old = env->CP0_EntryHi; |
| 1813 | 8c0fdd85 | ths | env->CP0_EntryHi = val; |
| 1814 | ead9360e | ths | if (env->CP0_Config3 & (1 << CP0C3_MT)) { |
| 1815 | ead9360e | ths | uint32_t tcst = env->CP0_TCStatus[env->current_tc] & ~0xff;
|
| 1816 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] = tcst | (val & 0xff);
|
| 1817 | ead9360e | ths | } |
| 1818 | 8c0fdd85 | ths | /* If the ASID changes, flush qemu's TLB. */
|
| 1819 | 8c0fdd85 | ths | if ((old & 0xFF) != (val & 0xFF)) |
| 1820 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_tlb_flush, env, 1);
|
| 1821 | 8f6f6026 | ths | FORCE_RET(); |
| 1822 | 8c0fdd85 | ths | } |
| 1823 | 8c0fdd85 | ths | |
| 1824 | ead9360e | ths | void op_mttc0_entryhi(void) |
| 1825 | ead9360e | ths | {
|
| 1826 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1827 | ead9360e | ths | |
| 1828 | ead9360e | ths | env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff); |
| 1829 | ead9360e | ths | env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff); |
| 1830 | 8f6f6026 | ths | FORCE_RET(); |
| 1831 | ead9360e | ths | } |
| 1832 | ead9360e | ths | |
| 1833 | 8c0fdd85 | ths | void op_mtc0_compare (void) |
| 1834 | 8c0fdd85 | ths | {
|
| 1835 | 8c0fdd85 | ths | CALL_FROM_TB2(cpu_mips_store_compare, env, T0); |
| 1836 | 8f6f6026 | ths | FORCE_RET(); |
| 1837 | 8c0fdd85 | ths | } |
| 1838 | 8c0fdd85 | ths | |
| 1839 | 8c0fdd85 | ths | void op_mtc0_status (void) |
| 1840 | 8c0fdd85 | ths | {
|
| 1841 | 4de9b249 | ths | uint32_t val, old; |
| 1842 | ead9360e | ths | uint32_t mask = env->CP0_Status_rw_bitmask; |
| 1843 | 8c0fdd85 | ths | |
| 1844 | f1b0aa5d | ths | val = T0 & mask; |
| 1845 | 8c0fdd85 | ths | old = env->CP0_Status; |
| 1846 | 5a5012ec | ths | env->CP0_Status = (env->CP0_Status & ~mask) | val; |
| 1847 | 08fa4bab | ths | CALL_FROM_TB1(compute_hflags, env); |
| 1848 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
| 1849 | f41c52f1 | ths | CALL_FROM_TB2(do_mtc0_status_debug, old, val); |
| 1850 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
| 1851 | 8f6f6026 | ths | FORCE_RET(); |
| 1852 | 8c0fdd85 | ths | } |
| 1853 | 8c0fdd85 | ths | |
| 1854 | ead9360e | ths | void op_mttc0_status(void) |
| 1855 | ead9360e | ths | {
|
| 1856 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1857 | ead9360e | ths | uint32_t tcstatus = env->CP0_TCStatus[other_tc]; |
| 1858 | ead9360e | ths | |
| 1859 | ead9360e | ths | env->CP0_Status = T0 & ~0xf1000018;
|
| 1860 | ead9360e | ths | tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0)); |
| 1861 | ead9360e | ths | tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX)); |
| 1862 | 623a930e | ths | tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU)); |
| 1863 | ead9360e | ths | env->CP0_TCStatus[other_tc] = tcstatus; |
| 1864 | 8f6f6026 | ths | FORCE_RET(); |
| 1865 | ead9360e | ths | } |
| 1866 | ead9360e | ths | |
| 1867 | 7a387fff | ths | void op_mtc0_intctl (void) |
| 1868 | 7a387fff | ths | {
|
| 1869 | 42532189 | ths | /* vectored interrupts not implemented, no performance counters. */
|
| 1870 | 42532189 | ths | env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0); |
| 1871 | 8f6f6026 | ths | FORCE_RET(); |
| 1872 | 7a387fff | ths | } |
| 1873 | 7a387fff | ths | |
| 1874 | 7a387fff | ths | void op_mtc0_srsctl (void) |
| 1875 | 7a387fff | ths | {
|
| 1876 | ead9360e | ths | uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); |
| 1877 | ead9360e | ths | env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask); |
| 1878 | 8f6f6026 | ths | FORCE_RET(); |
| 1879 | 7a387fff | ths | } |
| 1880 | 7a387fff | ths | |
| 1881 | 9c2149c8 | ths | void op_mtc0_srsmap (void) |
| 1882 | 9c2149c8 | ths | {
|
| 1883 | ead9360e | ths | env->CP0_SRSMap = T0; |
| 1884 | 8f6f6026 | ths | FORCE_RET(); |
| 1885 | 9c2149c8 | ths | } |
| 1886 | 9c2149c8 | ths | |
| 1887 | 8c0fdd85 | ths | void op_mtc0_cause (void) |
| 1888 | 8c0fdd85 | ths | {
|
| 1889 | 39d51eb8 | ths | uint32_t mask = 0x00C00300;
|
| 1890 | 42532189 | ths | uint32_t old = env->CP0_Cause; |
| 1891 | 39d51eb8 | ths | |
| 1892 | e189e748 | ths | if (env->insn_flags & ISA_MIPS32R2)
|
| 1893 | 39d51eb8 | ths | mask |= 1 << CP0Ca_DC;
|
| 1894 | 39d51eb8 | ths | |
| 1895 | e58c8ba5 | ths | env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask); |
| 1896 | 8c0fdd85 | ths | |
| 1897 | 42532189 | ths | if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { |
| 1898 | 42532189 | ths | if (env->CP0_Cause & (1 << CP0Ca_DC)) |
| 1899 | 42532189 | ths | CALL_FROM_TB1(cpu_mips_stop_count, env); |
| 1900 | 42532189 | ths | else
|
| 1901 | 42532189 | ths | CALL_FROM_TB1(cpu_mips_start_count, env); |
| 1902 | 42532189 | ths | } |
| 1903 | 42532189 | ths | |
| 1904 | 4de9b249 | ths | /* Handle the software interrupt as an hardware one, as they
|
| 1905 | 4de9b249 | ths | are very similar */
|
| 1906 | 4de9b249 | ths | if (T0 & CP0Ca_IP_mask) {
|
| 1907 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
| 1908 | 8c0fdd85 | ths | } |
| 1909 | 8f6f6026 | ths | FORCE_RET(); |
| 1910 | 8c0fdd85 | ths | } |
| 1911 | 8c0fdd85 | ths | |
| 1912 | 8c0fdd85 | ths | void op_mtc0_epc (void) |
| 1913 | 8c0fdd85 | ths | {
|
| 1914 | f1b0aa5d | ths | env->CP0_EPC = T0; |
| 1915 | 8f6f6026 | ths | FORCE_RET(); |
| 1916 | 8c0fdd85 | ths | } |
| 1917 | 8c0fdd85 | ths | |
| 1918 | 7a387fff | ths | void op_mtc0_ebase (void) |
| 1919 | 7a387fff | ths | {
|
| 1920 | 7a387fff | ths | /* vectored interrupts not implemented */
|
| 1921 | 7a387fff | ths | /* Multi-CPU not implemented */
|
| 1922 | b29a0341 | ths | env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000); |
| 1923 | 8f6f6026 | ths | FORCE_RET(); |
| 1924 | 7a387fff | ths | } |
| 1925 | 7a387fff | ths | |
| 1926 | 8c0fdd85 | ths | void op_mtc0_config0 (void) |
| 1927 | 8c0fdd85 | ths | {
|
| 1928 | 7bfd934a | ths | env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007); |
| 1929 | 8f6f6026 | ths | FORCE_RET(); |
| 1930 | 8c0fdd85 | ths | } |
| 1931 | 8c0fdd85 | ths | |
| 1932 | 7a387fff | ths | void op_mtc0_config2 (void) |
| 1933 | 7a387fff | ths | {
|
| 1934 | 7a387fff | ths | /* tertiary/secondary caches not implemented */
|
| 1935 | 7a387fff | ths | env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
|
| 1936 | 8f6f6026 | ths | FORCE_RET(); |
| 1937 | 7a387fff | ths | } |
| 1938 | 7a387fff | ths | |
| 1939 | fd88b6ab | ths | void op_mtc0_watchlo (void) |
| 1940 | 8c0fdd85 | ths | {
|
| 1941 | 4e7a4a4e | ths | /* Watch exceptions for instructions, data loads, data stores
|
| 1942 | 4e7a4a4e | ths | not implemented. */
|
| 1943 | fd88b6ab | ths | env->CP0_WatchLo[PARAM1] = (T0 & ~0x7);
|
| 1944 | 8f6f6026 | ths | FORCE_RET(); |
| 1945 | 8c0fdd85 | ths | } |
| 1946 | 8c0fdd85 | ths | |
| 1947 | fd88b6ab | ths | void op_mtc0_watchhi (void) |
| 1948 | 8c0fdd85 | ths | {
|
| 1949 | fd88b6ab | ths | env->CP0_WatchHi[PARAM1] = (T0 & 0x40FF0FF8);
|
| 1950 | fd88b6ab | ths | env->CP0_WatchHi[PARAM1] &= ~(env->CP0_WatchHi[PARAM1] & T0 & 0x7);
|
| 1951 | 8f6f6026 | ths | FORCE_RET(); |
| 1952 | 8c0fdd85 | ths | } |
| 1953 | 8c0fdd85 | ths | |
| 1954 | ead9360e | ths | void op_mtc0_xcontext (void) |
| 1955 | ead9360e | ths | {
|
| 1956 | ead9360e | ths | target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1; |
| 1957 | ead9360e | ths | env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask); |
| 1958 | 8f6f6026 | ths | FORCE_RET(); |
| 1959 | ead9360e | ths | } |
| 1960 | ead9360e | ths | |
| 1961 | 7a387fff | ths | void op_mtc0_framemask (void) |
| 1962 | 7a387fff | ths | {
|
| 1963 | 7a387fff | ths | env->CP0_Framemask = T0; /* XXX */
|
| 1964 | 8f6f6026 | ths | FORCE_RET(); |
| 1965 | 7a387fff | ths | } |
| 1966 | 7a387fff | ths | |
| 1967 | 8c0fdd85 | ths | void op_mtc0_debug (void) |
| 1968 | 8c0fdd85 | ths | {
|
| 1969 | 8c0fdd85 | ths | env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120); |
| 1970 | 8c0fdd85 | ths | if (T0 & (1 << CP0DB_DM)) |
| 1971 | 8c0fdd85 | ths | env->hflags |= MIPS_HFLAG_DM; |
| 1972 | 8c0fdd85 | ths | else
|
| 1973 | 8c0fdd85 | ths | env->hflags &= ~MIPS_HFLAG_DM; |
| 1974 | 8f6f6026 | ths | FORCE_RET(); |
| 1975 | 8c0fdd85 | ths | } |
| 1976 | 8c0fdd85 | ths | |
| 1977 | ead9360e | ths | void op_mttc0_debug(void) |
| 1978 | ead9360e | ths | {
|
| 1979 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 1980 | ead9360e | ths | |
| 1981 | ead9360e | ths | /* XXX: Might be wrong, check with EJTAG spec. */
|
| 1982 | ead9360e | ths | env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); |
| 1983 | ead9360e | ths | env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | |
| 1984 | ead9360e | ths | (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); |
| 1985 | 8f6f6026 | ths | FORCE_RET(); |
| 1986 | ead9360e | ths | } |
| 1987 | ead9360e | ths | |
| 1988 | 8c0fdd85 | ths | void op_mtc0_depc (void) |
| 1989 | 8c0fdd85 | ths | {
|
| 1990 | f1b0aa5d | ths | env->CP0_DEPC = T0; |
| 1991 | 8f6f6026 | ths | FORCE_RET(); |
| 1992 | 8c0fdd85 | ths | } |
| 1993 | 8c0fdd85 | ths | |
| 1994 | 7a387fff | ths | void op_mtc0_performance0 (void) |
| 1995 | 7a387fff | ths | {
|
| 1996 | 1b6fd0bc | ths | env->CP0_Performance0 = T0 & 0x000007ff;
|
| 1997 | 8f6f6026 | ths | FORCE_RET(); |
| 1998 | 7a387fff | ths | } |
| 1999 | 7a387fff | ths | |
| 2000 | 8c0fdd85 | ths | void op_mtc0_taglo (void) |
| 2001 | 8c0fdd85 | ths | {
|
| 2002 | 9c2149c8 | ths | env->CP0_TagLo = T0 & 0xFFFFFCF6;
|
| 2003 | 8f6f6026 | ths | FORCE_RET(); |
| 2004 | 8c0fdd85 | ths | } |
| 2005 | 8c0fdd85 | ths | |
| 2006 | 7a387fff | ths | void op_mtc0_datalo (void) |
| 2007 | 7a387fff | ths | {
|
| 2008 | 7a387fff | ths | env->CP0_DataLo = T0; /* XXX */
|
| 2009 | 8f6f6026 | ths | FORCE_RET(); |
| 2010 | 7a387fff | ths | } |
| 2011 | 7a387fff | ths | |
| 2012 | 7a387fff | ths | void op_mtc0_taghi (void) |
| 2013 | 7a387fff | ths | {
|
| 2014 | 7a387fff | ths | env->CP0_TagHi = T0; /* XXX */
|
| 2015 | 8f6f6026 | ths | FORCE_RET(); |
| 2016 | 7a387fff | ths | } |
| 2017 | 7a387fff | ths | |
| 2018 | 7a387fff | ths | void op_mtc0_datahi (void) |
| 2019 | 7a387fff | ths | {
|
| 2020 | 7a387fff | ths | env->CP0_DataHi = T0; /* XXX */
|
| 2021 | 8f6f6026 | ths | FORCE_RET(); |
| 2022 | 7a387fff | ths | } |
| 2023 | 7a387fff | ths | |
| 2024 | 8c0fdd85 | ths | void op_mtc0_errorepc (void) |
| 2025 | 8c0fdd85 | ths | {
|
| 2026 | f1b0aa5d | ths | env->CP0_ErrorEPC = T0; |
| 2027 | 8f6f6026 | ths | FORCE_RET(); |
| 2028 | 8c0fdd85 | ths | } |
| 2029 | 8c0fdd85 | ths | |
| 2030 | 8c0fdd85 | ths | void op_mtc0_desave (void) |
| 2031 | 8c0fdd85 | ths | {
|
| 2032 | 8c0fdd85 | ths | env->CP0_DESAVE = T0; |
| 2033 | 8f6f6026 | ths | FORCE_RET(); |
| 2034 | 6af0bf9c | bellard | } |
| 2035 | 6af0bf9c | bellard | |
| 2036 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
| 2037 | ead9360e | ths | void op_dmfc0_yqmask (void) |
| 2038 | f1b0aa5d | ths | {
|
| 2039 | ead9360e | ths | T0 = env->CP0_YQMask; |
| 2040 | 8f6f6026 | ths | FORCE_RET(); |
| 2041 | ead9360e | ths | } |
| 2042 | ead9360e | ths | |
| 2043 | ead9360e | ths | void op_dmfc0_vpeschedule (void) |
| 2044 | ead9360e | ths | {
|
| 2045 | ead9360e | ths | T0 = env->CP0_VPESchedule; |
| 2046 | 8f6f6026 | ths | FORCE_RET(); |
| 2047 | ead9360e | ths | } |
| 2048 | ead9360e | ths | |
| 2049 | ead9360e | ths | void op_dmfc0_vpeschefback (void) |
| 2050 | ead9360e | ths | {
|
| 2051 | ead9360e | ths | T0 = env->CP0_VPEScheFBack; |
| 2052 | 8f6f6026 | ths | FORCE_RET(); |
| 2053 | f1b0aa5d | ths | } |
| 2054 | f1b0aa5d | ths | |
| 2055 | 9c2149c8 | ths | void op_dmfc0_entrylo0 (void) |
| 2056 | 9c2149c8 | ths | {
|
| 2057 | 9c2149c8 | ths | T0 = env->CP0_EntryLo0; |
| 2058 | 8f6f6026 | ths | FORCE_RET(); |
| 2059 | 9c2149c8 | ths | } |
| 2060 | 9c2149c8 | ths | |
| 2061 | ead9360e | ths | void op_dmfc0_tcrestart (void) |
| 2062 | ead9360e | ths | {
|
| 2063 | ead9360e | ths | T0 = env->PC[env->current_tc]; |
| 2064 | 8f6f6026 | ths | FORCE_RET(); |
| 2065 | ead9360e | ths | } |
| 2066 | ead9360e | ths | |
| 2067 | ead9360e | ths | void op_dmfc0_tchalt (void) |
| 2068 | ead9360e | ths | {
|
| 2069 | ead9360e | ths | T0 = env->CP0_TCHalt[env->current_tc]; |
| 2070 | 8f6f6026 | ths | FORCE_RET(); |
| 2071 | ead9360e | ths | } |
| 2072 | ead9360e | ths | |
| 2073 | ead9360e | ths | void op_dmfc0_tccontext (void) |
| 2074 | ead9360e | ths | {
|
| 2075 | ead9360e | ths | T0 = env->CP0_TCContext[env->current_tc]; |
| 2076 | 8f6f6026 | ths | FORCE_RET(); |
| 2077 | ead9360e | ths | } |
| 2078 | ead9360e | ths | |
| 2079 | ead9360e | ths | void op_dmfc0_tcschedule (void) |
| 2080 | ead9360e | ths | {
|
| 2081 | ead9360e | ths | T0 = env->CP0_TCSchedule[env->current_tc]; |
| 2082 | 8f6f6026 | ths | FORCE_RET(); |
| 2083 | ead9360e | ths | } |
| 2084 | ead9360e | ths | |
| 2085 | ead9360e | ths | void op_dmfc0_tcschefback (void) |
| 2086 | ead9360e | ths | {
|
| 2087 | ead9360e | ths | T0 = env->CP0_TCScheFBack[env->current_tc]; |
| 2088 | 8f6f6026 | ths | FORCE_RET(); |
| 2089 | ead9360e | ths | } |
| 2090 | ead9360e | ths | |
| 2091 | 9c2149c8 | ths | void op_dmfc0_entrylo1 (void) |
| 2092 | 9c2149c8 | ths | {
|
| 2093 | 9c2149c8 | ths | T0 = env->CP0_EntryLo1; |
| 2094 | 8f6f6026 | ths | FORCE_RET(); |
| 2095 | 9c2149c8 | ths | } |
| 2096 | 9c2149c8 | ths | |
| 2097 | 9c2149c8 | ths | void op_dmfc0_context (void) |
| 2098 | 9c2149c8 | ths | {
|
| 2099 | 9c2149c8 | ths | T0 = env->CP0_Context; |
| 2100 | 8f6f6026 | ths | FORCE_RET(); |
| 2101 | 9c2149c8 | ths | } |
| 2102 | 9c2149c8 | ths | |
| 2103 | 9c2149c8 | ths | void op_dmfc0_badvaddr (void) |
| 2104 | 9c2149c8 | ths | {
|
| 2105 | 9c2149c8 | ths | T0 = env->CP0_BadVAddr; |
| 2106 | 8f6f6026 | ths | FORCE_RET(); |
| 2107 | 9c2149c8 | ths | } |
| 2108 | 9c2149c8 | ths | |
| 2109 | 9c2149c8 | ths | void op_dmfc0_entryhi (void) |
| 2110 | 9c2149c8 | ths | {
|
| 2111 | 9c2149c8 | ths | T0 = env->CP0_EntryHi; |
| 2112 | 8f6f6026 | ths | FORCE_RET(); |
| 2113 | 9c2149c8 | ths | } |
| 2114 | 9c2149c8 | ths | |
| 2115 | 9c2149c8 | ths | void op_dmfc0_epc (void) |
| 2116 | 9c2149c8 | ths | {
|
| 2117 | 9c2149c8 | ths | T0 = env->CP0_EPC; |
| 2118 | 8f6f6026 | ths | FORCE_RET(); |
| 2119 | 9c2149c8 | ths | } |
| 2120 | 9c2149c8 | ths | |
| 2121 | 9c2149c8 | ths | void op_dmfc0_lladdr (void) |
| 2122 | 9c2149c8 | ths | {
|
| 2123 | 9c2149c8 | ths | T0 = env->CP0_LLAddr >> 4;
|
| 2124 | 8f6f6026 | ths | FORCE_RET(); |
| 2125 | 9c2149c8 | ths | } |
| 2126 | 9c2149c8 | ths | |
| 2127 | fd88b6ab | ths | void op_dmfc0_watchlo (void) |
| 2128 | 9c2149c8 | ths | {
|
| 2129 | fd88b6ab | ths | T0 = env->CP0_WatchLo[PARAM1]; |
| 2130 | 8f6f6026 | ths | FORCE_RET(); |
| 2131 | 9c2149c8 | ths | } |
| 2132 | 9c2149c8 | ths | |
| 2133 | 9c2149c8 | ths | void op_dmfc0_xcontext (void) |
| 2134 | 9c2149c8 | ths | {
|
| 2135 | 9c2149c8 | ths | T0 = env->CP0_XContext; |
| 2136 | 8f6f6026 | ths | FORCE_RET(); |
| 2137 | 9c2149c8 | ths | } |
| 2138 | 9c2149c8 | ths | |
| 2139 | 9c2149c8 | ths | void op_dmfc0_depc (void) |
| 2140 | 9c2149c8 | ths | {
|
| 2141 | 9c2149c8 | ths | T0 = env->CP0_DEPC; |
| 2142 | 8f6f6026 | ths | FORCE_RET(); |
| 2143 | 9c2149c8 | ths | } |
| 2144 | 9c2149c8 | ths | |
| 2145 | 9c2149c8 | ths | void op_dmfc0_errorepc (void) |
| 2146 | 9c2149c8 | ths | {
|
| 2147 | 9c2149c8 | ths | T0 = env->CP0_ErrorEPC; |
| 2148 | 8f6f6026 | ths | FORCE_RET(); |
| 2149 | 9c2149c8 | ths | } |
| 2150 | d26bc211 | ths | #endif /* TARGET_MIPS64 */ |
| 2151 | 9c2149c8 | ths | |
| 2152 | ead9360e | ths | /* MIPS MT functions */
|
| 2153 | ead9360e | ths | void op_mftgpr(void) |
| 2154 | ead9360e | ths | {
|
| 2155 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 2156 | ead9360e | ths | |
| 2157 | 5b2808bf | ths | T0 = env->gpr[other_tc][PARAM1]; |
| 2158 | 8f6f6026 | ths | FORCE_RET(); |
| 2159 | ead9360e | ths | } |
| 2160 | ead9360e | ths | |
| 2161 | ead9360e | ths | void op_mftlo(void) |
| 2162 | ead9360e | ths | {
|
| 2163 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 2164 | ead9360e | ths | |
| 2165 | 5b2808bf | ths | T0 = env->LO[other_tc][PARAM1]; |
| 2166 | 8f6f6026 | ths | FORCE_RET(); |
| 2167 | ead9360e | ths | } |
| 2168 | ead9360e | ths | |
| 2169 | ead9360e | ths | void op_mfthi(void) |
| 2170 | ead9360e | ths | {
|
| 2171 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 2172 | ead9360e | ths | |
| 2173 | 5b2808bf | ths | T0 = env->HI[other_tc][PARAM1]; |
| 2174 | 8f6f6026 | ths | FORCE_RET(); |
| 2175 | ead9360e | ths | } |
| 2176 | ead9360e | ths | |
| 2177 | ead9360e | ths | void op_mftacx(void) |
| 2178 | ead9360e | ths | {
|
| 2179 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 2180 | ead9360e | ths | |
| 2181 | 5b2808bf | ths | T0 = env->ACX[other_tc][PARAM1]; |
| 2182 | 8f6f6026 | ths | FORCE_RET(); |
| 2183 | ead9360e | ths | } |
| 2184 | ead9360e | ths | |
| 2185 | ead9360e | ths | void op_mftdsp(void) |
| 2186 | ead9360e | ths | {
|
| 2187 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 2188 | ead9360e | ths | |
| 2189 | ead9360e | ths | T0 = env->DSPControl[other_tc]; |
| 2190 | 8f6f6026 | ths | FORCE_RET(); |
| 2191 | ead9360e | ths | } |
| 2192 | ead9360e | ths | |
| 2193 | ead9360e | ths | void op_mttgpr(void) |
| 2194 | ead9360e | ths | {
|
| 2195 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 2196 | ead9360e | ths | |
| 2197 | 5b2808bf | ths | T0 = env->gpr[other_tc][PARAM1]; |
| 2198 | 8f6f6026 | ths | FORCE_RET(); |
| 2199 | ead9360e | ths | } |
| 2200 | ead9360e | ths | |
| 2201 | ead9360e | ths | void op_mttlo(void) |
| 2202 | ead9360e | ths | {
|
| 2203 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 2204 | ead9360e | ths | |
| 2205 | 5b2808bf | ths | T0 = env->LO[other_tc][PARAM1]; |
| 2206 | 8f6f6026 | ths | FORCE_RET(); |
| 2207 | ead9360e | ths | } |
| 2208 | ead9360e | ths | |
| 2209 | ead9360e | ths | void op_mtthi(void) |
| 2210 | ead9360e | ths | {
|
| 2211 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 2212 | ead9360e | ths | |
| 2213 | 5b2808bf | ths | T0 = env->HI[other_tc][PARAM1]; |
| 2214 | 8f6f6026 | ths | FORCE_RET(); |
| 2215 | ead9360e | ths | } |
| 2216 | ead9360e | ths | |
| 2217 | ead9360e | ths | void op_mttacx(void) |
| 2218 | ead9360e | ths | {
|
| 2219 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 2220 | ead9360e | ths | |
| 2221 | 5b2808bf | ths | T0 = env->ACX[other_tc][PARAM1]; |
| 2222 | 8f6f6026 | ths | FORCE_RET(); |
| 2223 | ead9360e | ths | } |
| 2224 | ead9360e | ths | |
| 2225 | ead9360e | ths | void op_mttdsp(void) |
| 2226 | ead9360e | ths | {
|
| 2227 | ead9360e | ths | int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); |
| 2228 | ead9360e | ths | |
| 2229 | ead9360e | ths | T0 = env->DSPControl[other_tc]; |
| 2230 | 8f6f6026 | ths | FORCE_RET(); |
| 2231 | ead9360e | ths | } |
| 2232 | ead9360e | ths | |
| 2233 | ead9360e | ths | |
| 2234 | ead9360e | ths | void op_dmt(void) |
| 2235 | ead9360e | ths | {
|
| 2236 | ead9360e | ths | // TODO
|
| 2237 | ead9360e | ths | T0 = 0;
|
| 2238 | ead9360e | ths | // rt = T0
|
| 2239 | 8f6f6026 | ths | FORCE_RET(); |
| 2240 | ead9360e | ths | } |
| 2241 | ead9360e | ths | |
| 2242 | ead9360e | ths | void op_emt(void) |
| 2243 | ead9360e | ths | {
|
| 2244 | ead9360e | ths | // TODO
|
| 2245 | ead9360e | ths | T0 = 0;
|
| 2246 | ead9360e | ths | // rt = T0
|
| 2247 | 8f6f6026 | ths | FORCE_RET(); |
| 2248 | ead9360e | ths | } |
| 2249 | ead9360e | ths | |
| 2250 | ead9360e | ths | void op_dvpe(void) |
| 2251 | ead9360e | ths | {
|
| 2252 | ead9360e | ths | // TODO
|
| 2253 | ead9360e | ths | T0 = 0;
|
| 2254 | ead9360e | ths | // rt = T0
|
| 2255 | 8f6f6026 | ths | FORCE_RET(); |
| 2256 | ead9360e | ths | } |
| 2257 | ead9360e | ths | |
| 2258 | ead9360e | ths | void op_evpe(void) |
| 2259 | ead9360e | ths | {
|
| 2260 | ead9360e | ths | // TODO
|
| 2261 | ead9360e | ths | T0 = 0;
|
| 2262 | ead9360e | ths | // rt = T0
|
| 2263 | 8f6f6026 | ths | FORCE_RET(); |
| 2264 | ead9360e | ths | } |
| 2265 | ead9360e | ths | |
| 2266 | ead9360e | ths | void op_fork(void) |
| 2267 | ead9360e | ths | {
|
| 2268 | ead9360e | ths | // T0 = rt, T1 = rs
|
| 2269 | ead9360e | ths | T0 = 0;
|
| 2270 | ead9360e | ths | // TODO: store to TC register
|
| 2271 | 8f6f6026 | ths | FORCE_RET(); |
| 2272 | ead9360e | ths | } |
| 2273 | ead9360e | ths | |
| 2274 | ead9360e | ths | void op_yield(void) |
| 2275 | ead9360e | ths | {
|
| 2276 | ead9360e | ths | if (T0 < 0) { |
| 2277 | ead9360e | ths | /* No scheduling policy implemented. */
|
| 2278 | ead9360e | ths | if (T0 != -2) { |
| 2279 | ead9360e | ths | if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && |
| 2280 | ead9360e | ths | env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
|
| 2281 | ead9360e | ths | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
| 2282 | ead9360e | ths | env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
|
| 2283 | ead9360e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); |
| 2284 | ead9360e | ths | } |
| 2285 | ead9360e | ths | } |
| 2286 | ead9360e | ths | } else if (T0 == 0) { |
| 2287 | ead9360e | ths | if (0 /* TODO: TC underflow */) { |
| 2288 | ead9360e | ths | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
| 2289 | ead9360e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); |
| 2290 | ead9360e | ths | } else {
|
| 2291 | ead9360e | ths | // TODO: Deallocate TC
|
| 2292 | ead9360e | ths | } |
| 2293 | ead9360e | ths | } else if (T0 > 0) { |
| 2294 | ead9360e | ths | /* Yield qualifier inputs not implemented. */
|
| 2295 | ead9360e | ths | env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
|
| 2296 | ead9360e | ths | env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
|
| 2297 | ead9360e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_THREAD); |
| 2298 | ead9360e | ths | } |
| 2299 | ead9360e | ths | T0 = env->CP0_YQMask; |
| 2300 | 8f6f6026 | ths | FORCE_RET(); |
| 2301 | ead9360e | ths | } |
| 2302 | ead9360e | ths | |
| 2303 | 5a5012ec | ths | /* CP1 functions */
|
| 2304 | 6ea83fed | bellard | #if 0
|
| 2305 | 6ea83fed | bellard | # define DEBUG_FPU_STATE() CALL_FROM_TB1(dump_fpu, env)
|
| 2306 | 6ea83fed | bellard | #else
|
| 2307 | 6ea83fed | bellard | # define DEBUG_FPU_STATE() do { } while(0) |
| 2308 | 6ea83fed | bellard | #endif
|
| 2309 | 6ea83fed | bellard | |
| 2310 | 5a5012ec | ths | void op_cfc1 (void) |
| 2311 | 5a5012ec | ths | {
|
| 2312 | ead9360e | ths | CALL_FROM_TB1(do_cfc1, PARAM1); |
| 2313 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2314 | 8f6f6026 | ths | FORCE_RET(); |
| 2315 | 5a5012ec | ths | } |
| 2316 | 5a5012ec | ths | |
| 2317 | 5a5012ec | ths | void op_ctc1 (void) |
| 2318 | 5a5012ec | ths | {
|
| 2319 | ead9360e | ths | CALL_FROM_TB1(do_ctc1, PARAM1); |
| 2320 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2321 | 8f6f6026 | ths | FORCE_RET(); |
| 2322 | 6ea83fed | bellard | } |
| 2323 | 6ea83fed | bellard | |
| 2324 | 6ea83fed | bellard | void op_mfc1 (void) |
| 2325 | 6ea83fed | bellard | {
|
| 2326 | 6ad38722 | ths | T0 = (int32_t)WT0; |
| 2327 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2328 | 8f6f6026 | ths | FORCE_RET(); |
| 2329 | 6ea83fed | bellard | } |
| 2330 | 6ea83fed | bellard | |
| 2331 | 6ea83fed | bellard | void op_mtc1 (void) |
| 2332 | 6ea83fed | bellard | {
|
| 2333 | 6ea83fed | bellard | WT0 = T0; |
| 2334 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2335 | 8f6f6026 | ths | FORCE_RET(); |
| 2336 | 6ea83fed | bellard | } |
| 2337 | 6ea83fed | bellard | |
| 2338 | 5a5012ec | ths | void op_dmfc1 (void) |
| 2339 | 5a5012ec | ths | {
|
| 2340 | 5a5012ec | ths | T0 = DT0; |
| 2341 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2342 | 8f6f6026 | ths | FORCE_RET(); |
| 2343 | 5a5012ec | ths | } |
| 2344 | 5a5012ec | ths | |
| 2345 | 5a5012ec | ths | void op_dmtc1 (void) |
| 2346 | 5a5012ec | ths | {
|
| 2347 | 5a5012ec | ths | DT0 = T0; |
| 2348 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2349 | 8f6f6026 | ths | FORCE_RET(); |
| 2350 | 5a5012ec | ths | } |
| 2351 | 5a5012ec | ths | |
| 2352 | 5a5012ec | ths | void op_mfhc1 (void) |
| 2353 | 5a5012ec | ths | {
|
| 2354 | 6ad38722 | ths | T0 = (int32_t)WTH0; |
| 2355 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2356 | 8f6f6026 | ths | FORCE_RET(); |
| 2357 | 5a5012ec | ths | } |
| 2358 | 5a5012ec | ths | |
| 2359 | 5a5012ec | ths | void op_mthc1 (void) |
| 2360 | 5a5012ec | ths | {
|
| 2361 | 5a5012ec | ths | WTH0 = T0; |
| 2362 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2363 | 8f6f6026 | ths | FORCE_RET(); |
| 2364 | 5a5012ec | ths | } |
| 2365 | 5a5012ec | ths | |
| 2366 | 6ea83fed | bellard | /* Float support.
|
| 2367 | 6ea83fed | bellard | Single precition routines have a "s" suffix, double precision a
|
| 2368 | 5a5012ec | ths | "d" suffix, 32bit integer "w", 64bit integer "l", paired singe "ps",
|
| 2369 | 5a5012ec | ths | paired single lowwer "pl", paired single upper "pu". */
|
| 2370 | 6ea83fed | bellard | |
| 2371 | 6ea83fed | bellard | #define FLOAT_OP(name, p) void OPPROTO op_float_##name##_##p(void) |
| 2372 | 6ea83fed | bellard | |
| 2373 | dd016883 | bellard | FLOAT_OP(cvtd, s) |
| 2374 | dd016883 | bellard | {
|
| 2375 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtd_s); |
| 2376 | dd016883 | bellard | DEBUG_FPU_STATE(); |
| 2377 | 8f6f6026 | ths | FORCE_RET(); |
| 2378 | dd016883 | bellard | } |
| 2379 | 6ea83fed | bellard | FLOAT_OP(cvtd, w) |
| 2380 | 6ea83fed | bellard | {
|
| 2381 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtd_w); |
| 2382 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2383 | 8f6f6026 | ths | FORCE_RET(); |
| 2384 | 5a5012ec | ths | } |
| 2385 | 5a5012ec | ths | FLOAT_OP(cvtd, l) |
| 2386 | 5a5012ec | ths | {
|
| 2387 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtd_l); |
| 2388 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2389 | 8f6f6026 | ths | FORCE_RET(); |
| 2390 | 5a5012ec | ths | } |
| 2391 | 5a5012ec | ths | FLOAT_OP(cvtl, d) |
| 2392 | 5a5012ec | ths | {
|
| 2393 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtl_d); |
| 2394 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2395 | 8f6f6026 | ths | FORCE_RET(); |
| 2396 | 5a5012ec | ths | } |
| 2397 | 5a5012ec | ths | FLOAT_OP(cvtl, s) |
| 2398 | 5a5012ec | ths | {
|
| 2399 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtl_s); |
| 2400 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2401 | 8f6f6026 | ths | FORCE_RET(); |
| 2402 | 5a5012ec | ths | } |
| 2403 | 5a5012ec | ths | FLOAT_OP(cvtps, s) |
| 2404 | 5a5012ec | ths | {
|
| 2405 | 5a5012ec | ths | WT2 = WT0; |
| 2406 | 5a5012ec | ths | WTH2 = WT1; |
| 2407 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2408 | 8f6f6026 | ths | FORCE_RET(); |
| 2409 | 5a5012ec | ths | } |
| 2410 | 5a5012ec | ths | FLOAT_OP(cvtps, pw) |
| 2411 | 5a5012ec | ths | {
|
| 2412 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtps_pw); |
| 2413 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2414 | 8f6f6026 | ths | FORCE_RET(); |
| 2415 | 5a5012ec | ths | } |
| 2416 | 5a5012ec | ths | FLOAT_OP(cvtpw, ps) |
| 2417 | 5a5012ec | ths | {
|
| 2418 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtpw_ps); |
| 2419 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2420 | 8f6f6026 | ths | FORCE_RET(); |
| 2421 | 6ea83fed | bellard | } |
| 2422 | dd016883 | bellard | FLOAT_OP(cvts, d) |
| 2423 | dd016883 | bellard | {
|
| 2424 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_d); |
| 2425 | dd016883 | bellard | DEBUG_FPU_STATE(); |
| 2426 | 8f6f6026 | ths | FORCE_RET(); |
| 2427 | dd016883 | bellard | } |
| 2428 | 6ea83fed | bellard | FLOAT_OP(cvts, w) |
| 2429 | 6ea83fed | bellard | {
|
| 2430 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_w); |
| 2431 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2432 | 8f6f6026 | ths | FORCE_RET(); |
| 2433 | 5a5012ec | ths | } |
| 2434 | 5a5012ec | ths | FLOAT_OP(cvts, l) |
| 2435 | 5a5012ec | ths | {
|
| 2436 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_l); |
| 2437 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2438 | 8f6f6026 | ths | FORCE_RET(); |
| 2439 | 5a5012ec | ths | } |
| 2440 | 5a5012ec | ths | FLOAT_OP(cvts, pl) |
| 2441 | 5a5012ec | ths | {
|
| 2442 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_pl); |
| 2443 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2444 | 8f6f6026 | ths | FORCE_RET(); |
| 2445 | 5a5012ec | ths | } |
| 2446 | 5a5012ec | ths | FLOAT_OP(cvts, pu) |
| 2447 | 5a5012ec | ths | {
|
| 2448 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvts_pu); |
| 2449 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2450 | 8f6f6026 | ths | FORCE_RET(); |
| 2451 | 6ea83fed | bellard | } |
| 2452 | 6ea83fed | bellard | FLOAT_OP(cvtw, s) |
| 2453 | 6ea83fed | bellard | {
|
| 2454 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtw_s); |
| 2455 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2456 | 8f6f6026 | ths | FORCE_RET(); |
| 2457 | 6ea83fed | bellard | } |
| 2458 | 6ea83fed | bellard | FLOAT_OP(cvtw, d) |
| 2459 | 6ea83fed | bellard | {
|
| 2460 | fd4a04eb | ths | CALL_FROM_TB0(do_float_cvtw_d); |
| 2461 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2462 | 8f6f6026 | ths | FORCE_RET(); |
| 2463 | 5a5012ec | ths | } |
| 2464 | 5a5012ec | ths | |
| 2465 | 5a5012ec | ths | FLOAT_OP(pll, ps) |
| 2466 | 5a5012ec | ths | {
|
| 2467 | 5a5012ec | ths | DT2 = ((uint64_t)WT0 << 32) | WT1;
|
| 2468 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2469 | 8f6f6026 | ths | FORCE_RET(); |
| 2470 | 5a5012ec | ths | } |
| 2471 | 5a5012ec | ths | FLOAT_OP(plu, ps) |
| 2472 | 5a5012ec | ths | {
|
| 2473 | 5a5012ec | ths | DT2 = ((uint64_t)WT0 << 32) | WTH1;
|
| 2474 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2475 | 8f6f6026 | ths | FORCE_RET(); |
| 2476 | 5a5012ec | ths | } |
| 2477 | 5a5012ec | ths | FLOAT_OP(pul, ps) |
| 2478 | 5a5012ec | ths | {
|
| 2479 | 5a5012ec | ths | DT2 = ((uint64_t)WTH0 << 32) | WT1;
|
| 2480 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2481 | 8f6f6026 | ths | FORCE_RET(); |
| 2482 | 5a5012ec | ths | } |
| 2483 | 5a5012ec | ths | FLOAT_OP(puu, ps) |
| 2484 | 5a5012ec | ths | {
|
| 2485 | 5a5012ec | ths | DT2 = ((uint64_t)WTH0 << 32) | WTH1;
|
| 2486 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2487 | 8f6f6026 | ths | FORCE_RET(); |
| 2488 | 6ea83fed | bellard | } |
| 2489 | 6ea83fed | bellard | |
| 2490 | fd4a04eb | ths | #define FLOAT_ROUNDOP(op, ttype, stype) \
|
| 2491 | fd4a04eb | ths | FLOAT_OP(op ## ttype, stype) \ |
| 2492 | fd4a04eb | ths | { \
|
| 2493 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## op ## ttype ## _ ## stype); \ |
| 2494 | fd4a04eb | ths | DEBUG_FPU_STATE(); \ |
| 2495 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2496 | 6ea83fed | bellard | } |
| 2497 | 6ea83fed | bellard | |
| 2498 | fd4a04eb | ths | FLOAT_ROUNDOP(round, l, d) |
| 2499 | fd4a04eb | ths | FLOAT_ROUNDOP(round, l, s) |
| 2500 | fd4a04eb | ths | FLOAT_ROUNDOP(round, w, d) |
| 2501 | fd4a04eb | ths | FLOAT_ROUNDOP(round, w, s) |
| 2502 | 6ea83fed | bellard | |
| 2503 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, l, d) |
| 2504 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, l, s) |
| 2505 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, w, d) |
| 2506 | fd4a04eb | ths | FLOAT_ROUNDOP(trunc, w, s) |
| 2507 | 6ea83fed | bellard | |
| 2508 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, l, d) |
| 2509 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, l, s) |
| 2510 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, w, d) |
| 2511 | fd4a04eb | ths | FLOAT_ROUNDOP(ceil, w, s) |
| 2512 | fd4a04eb | ths | |
| 2513 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, l, d) |
| 2514 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, l, s) |
| 2515 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, w, d) |
| 2516 | fd4a04eb | ths | FLOAT_ROUNDOP(floor, w, s) |
| 2517 | fd4a04eb | ths | #undef FLOAR_ROUNDOP
|
| 2518 | 6ea83fed | bellard | |
| 2519 | 5a5012ec | ths | FLOAT_OP(movf, d) |
| 2520 | 5a5012ec | ths | {
|
| 2521 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1))
|
| 2522 | 5a5012ec | ths | DT2 = DT0; |
| 2523 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2524 | 8f6f6026 | ths | FORCE_RET(); |
| 2525 | 5a5012ec | ths | } |
| 2526 | 5a5012ec | ths | FLOAT_OP(movf, s) |
| 2527 | 5a5012ec | ths | {
|
| 2528 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1))
|
| 2529 | 5a5012ec | ths | WT2 = WT0; |
| 2530 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2531 | 8f6f6026 | ths | FORCE_RET(); |
| 2532 | 5a5012ec | ths | } |
| 2533 | 5a5012ec | ths | FLOAT_OP(movf, ps) |
| 2534 | 5a5012ec | ths | {
|
| 2535 | ead9360e | ths | if (!(env->fpu->fcr31 & PARAM1)) {
|
| 2536 | 5a5012ec | ths | WT2 = WT0; |
| 2537 | 5a5012ec | ths | WTH2 = WTH0; |
| 2538 | 5a5012ec | ths | } |
| 2539 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2540 | 8f6f6026 | ths | FORCE_RET(); |
| 2541 | 5a5012ec | ths | } |
| 2542 | 5a5012ec | ths | FLOAT_OP(movt, d) |
| 2543 | 5a5012ec | ths | {
|
| 2544 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1)
|
| 2545 | 5a5012ec | ths | DT2 = DT0; |
| 2546 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2547 | 8f6f6026 | ths | FORCE_RET(); |
| 2548 | 5a5012ec | ths | } |
| 2549 | 5a5012ec | ths | FLOAT_OP(movt, s) |
| 2550 | 5a5012ec | ths | {
|
| 2551 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1)
|
| 2552 | 5a5012ec | ths | WT2 = WT0; |
| 2553 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2554 | 8f6f6026 | ths | FORCE_RET(); |
| 2555 | 5a5012ec | ths | } |
| 2556 | 5a5012ec | ths | FLOAT_OP(movt, ps) |
| 2557 | 5a5012ec | ths | {
|
| 2558 | ead9360e | ths | if (env->fpu->fcr31 & PARAM1) {
|
| 2559 | 5a5012ec | ths | WT2 = WT0; |
| 2560 | 5a5012ec | ths | WTH2 = WTH0; |
| 2561 | 5a5012ec | ths | } |
| 2562 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2563 | 8f6f6026 | ths | FORCE_RET(); |
| 2564 | 5a5012ec | ths | } |
| 2565 | 5a5012ec | ths | FLOAT_OP(movz, d) |
| 2566 | 5a5012ec | ths | {
|
| 2567 | 5a5012ec | ths | if (!T0)
|
| 2568 | 5a5012ec | ths | DT2 = DT0; |
| 2569 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2570 | 8f6f6026 | ths | FORCE_RET(); |
| 2571 | 5a5012ec | ths | } |
| 2572 | 5a5012ec | ths | FLOAT_OP(movz, s) |
| 2573 | 5a5012ec | ths | {
|
| 2574 | 5a5012ec | ths | if (!T0)
|
| 2575 | 5a5012ec | ths | WT2 = WT0; |
| 2576 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2577 | 8f6f6026 | ths | FORCE_RET(); |
| 2578 | 5a5012ec | ths | } |
| 2579 | 5a5012ec | ths | FLOAT_OP(movz, ps) |
| 2580 | 5a5012ec | ths | {
|
| 2581 | 5a5012ec | ths | if (!T0) {
|
| 2582 | 5a5012ec | ths | WT2 = WT0; |
| 2583 | 5a5012ec | ths | WTH2 = WTH0; |
| 2584 | 5a5012ec | ths | } |
| 2585 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2586 | 8f6f6026 | ths | FORCE_RET(); |
| 2587 | 5a5012ec | ths | } |
| 2588 | 5a5012ec | ths | FLOAT_OP(movn, d) |
| 2589 | 5a5012ec | ths | {
|
| 2590 | 5a5012ec | ths | if (T0)
|
| 2591 | 5a5012ec | ths | DT2 = DT0; |
| 2592 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2593 | 8f6f6026 | ths | FORCE_RET(); |
| 2594 | 5a5012ec | ths | } |
| 2595 | 5a5012ec | ths | FLOAT_OP(movn, s) |
| 2596 | 5a5012ec | ths | {
|
| 2597 | 5a5012ec | ths | if (T0)
|
| 2598 | 5a5012ec | ths | WT2 = WT0; |
| 2599 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2600 | 8f6f6026 | ths | FORCE_RET(); |
| 2601 | 5a5012ec | ths | } |
| 2602 | 5a5012ec | ths | FLOAT_OP(movn, ps) |
| 2603 | 5a5012ec | ths | {
|
| 2604 | 5a5012ec | ths | if (T0) {
|
| 2605 | 5a5012ec | ths | WT2 = WT0; |
| 2606 | 5a5012ec | ths | WTH2 = WTH0; |
| 2607 | 5a5012ec | ths | } |
| 2608 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2609 | 8f6f6026 | ths | FORCE_RET(); |
| 2610 | 5a5012ec | ths | } |
| 2611 | 5a5012ec | ths | |
| 2612 | 57fa1fb3 | ths | /* operations calling helpers, for s, d and ps */
|
| 2613 | 8f6f6026 | ths | #define FLOAT_HOP(name) \
|
| 2614 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
| 2615 | 6ea83fed | bellard | { \
|
| 2616 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## name ## _d); \ |
| 2617 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
| 2618 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2619 | 6ea83fed | bellard | } \ |
| 2620 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
| 2621 | 6ea83fed | bellard | { \
|
| 2622 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## name ## _s); \ |
| 2623 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
| 2624 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2625 | 5a5012ec | ths | } \ |
| 2626 | 5a5012ec | ths | FLOAT_OP(name, ps) \ |
| 2627 | 5a5012ec | ths | { \
|
| 2628 | fd4a04eb | ths | CALL_FROM_TB0(do_float_ ## name ## _ps); \ |
| 2629 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
| 2630 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2631 | 6ea83fed | bellard | } |
| 2632 | 57fa1fb3 | ths | FLOAT_HOP(add) |
| 2633 | 57fa1fb3 | ths | FLOAT_HOP(sub) |
| 2634 | 57fa1fb3 | ths | FLOAT_HOP(mul) |
| 2635 | 57fa1fb3 | ths | FLOAT_HOP(div) |
| 2636 | 57fa1fb3 | ths | FLOAT_HOP(recip2) |
| 2637 | 57fa1fb3 | ths | FLOAT_HOP(rsqrt2) |
| 2638 | 57fa1fb3 | ths | FLOAT_HOP(rsqrt1) |
| 2639 | 57fa1fb3 | ths | FLOAT_HOP(recip1) |
| 2640 | 57fa1fb3 | ths | #undef FLOAT_HOP
|
| 2641 | 57fa1fb3 | ths | |
| 2642 | 57fa1fb3 | ths | /* operations calling helpers, for s and d */
|
| 2643 | 57fa1fb3 | ths | #define FLOAT_HOP(name) \
|
| 2644 | 57fa1fb3 | ths | FLOAT_OP(name, d) \ |
| 2645 | 57fa1fb3 | ths | { \
|
| 2646 | 57fa1fb3 | ths | CALL_FROM_TB0(do_float_ ## name ## _d); \ |
| 2647 | 57fa1fb3 | ths | DEBUG_FPU_STATE(); \ |
| 2648 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2649 | 57fa1fb3 | ths | } \ |
| 2650 | 57fa1fb3 | ths | FLOAT_OP(name, s) \ |
| 2651 | 57fa1fb3 | ths | { \
|
| 2652 | 57fa1fb3 | ths | CALL_FROM_TB0(do_float_ ## name ## _s); \ |
| 2653 | 57fa1fb3 | ths | DEBUG_FPU_STATE(); \ |
| 2654 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2655 | 57fa1fb3 | ths | } |
| 2656 | 57fa1fb3 | ths | FLOAT_HOP(rsqrt) |
| 2657 | 57fa1fb3 | ths | FLOAT_HOP(recip) |
| 2658 | 57fa1fb3 | ths | #undef FLOAT_HOP
|
| 2659 | 6ea83fed | bellard | |
| 2660 | 57fa1fb3 | ths | /* operations calling helpers, for ps */
|
| 2661 | 57fa1fb3 | ths | #define FLOAT_HOP(name) \
|
| 2662 | 57fa1fb3 | ths | FLOAT_OP(name, ps) \ |
| 2663 | 57fa1fb3 | ths | { \
|
| 2664 | 57fa1fb3 | ths | CALL_FROM_TB0(do_float_ ## name ## _ps); \ |
| 2665 | 57fa1fb3 | ths | DEBUG_FPU_STATE(); \ |
| 2666 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2667 | fbcc6828 | ths | } |
| 2668 | 57fa1fb3 | ths | FLOAT_HOP(addr) |
| 2669 | 57fa1fb3 | ths | FLOAT_HOP(mulr) |
| 2670 | 57fa1fb3 | ths | #undef FLOAT_HOP
|
| 2671 | fbcc6828 | ths | |
| 2672 | 5a5012ec | ths | /* ternary operations */
|
| 2673 | 5a5012ec | ths | #define FLOAT_TERNOP(name1, name2) \
|
| 2674 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, d) \ |
| 2675 | 5a5012ec | ths | { \
|
| 2676 | ead9360e | ths | FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \ |
| 2677 | ead9360e | ths | FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \ |
| 2678 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
| 2679 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2680 | 5a5012ec | ths | } \ |
| 2681 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, s) \ |
| 2682 | 5a5012ec | ths | { \
|
| 2683 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
| 2684 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
| 2685 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
| 2686 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2687 | 5a5012ec | ths | } \ |
| 2688 | 5a5012ec | ths | FLOAT_OP(name1 ## name2, ps) \ |
| 2689 | 5a5012ec | ths | { \
|
| 2690 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
| 2691 | ead9360e | ths | FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \ |
| 2692 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
| 2693 | ead9360e | ths | FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \ |
| 2694 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
| 2695 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2696 | 5a5012ec | ths | } |
| 2697 | 5a5012ec | ths | FLOAT_TERNOP(mul, add) |
| 2698 | 5a5012ec | ths | FLOAT_TERNOP(mul, sub) |
| 2699 | 5a5012ec | ths | #undef FLOAT_TERNOP
|
| 2700 | 5a5012ec | ths | |
| 2701 | fbcc6828 | ths | /* negated ternary operations */
|
| 2702 | fbcc6828 | ths | #define FLOAT_NTERNOP(name1, name2) \
|
| 2703 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, d) \ |
| 2704 | fbcc6828 | ths | { \
|
| 2705 | ead9360e | ths | FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status); \ |
| 2706 | ead9360e | ths | FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status); \ |
| 2707 | 5747c073 | pbrook | FDT2 = float64_chs(FDT2); \ |
| 2708 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
| 2709 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2710 | fbcc6828 | ths | } \ |
| 2711 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, s) \ |
| 2712 | fbcc6828 | ths | { \
|
| 2713 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
| 2714 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
| 2715 | 5747c073 | pbrook | FST2 = float32_chs(FST2); \ |
| 2716 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
| 2717 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2718 | fbcc6828 | ths | } \ |
| 2719 | fbcc6828 | ths | FLOAT_OP(n ## name1 ## name2, ps) \ |
| 2720 | fbcc6828 | ths | { \
|
| 2721 | ead9360e | ths | FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status); \ |
| 2722 | ead9360e | ths | FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \ |
| 2723 | ead9360e | ths | FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status); \ |
| 2724 | ead9360e | ths | FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \ |
| 2725 | 5747c073 | pbrook | FST2 = float32_chs(FST2); \ |
| 2726 | 5747c073 | pbrook | FSTH2 = float32_chs(FSTH2); \ |
| 2727 | fbcc6828 | ths | DEBUG_FPU_STATE(); \ |
| 2728 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2729 | fbcc6828 | ths | } |
| 2730 | fbcc6828 | ths | FLOAT_NTERNOP(mul, add) |
| 2731 | fbcc6828 | ths | FLOAT_NTERNOP(mul, sub) |
| 2732 | fbcc6828 | ths | #undef FLOAT_NTERNOP
|
| 2733 | fbcc6828 | ths | |
| 2734 | 6ea83fed | bellard | /* unary operations, modifying fp status */
|
| 2735 | 6ea83fed | bellard | #define FLOAT_UNOP(name) \
|
| 2736 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
| 2737 | 6ea83fed | bellard | { \
|
| 2738 | 8f6f6026 | ths | FDT2 = float64_ ## name(FDT0, &env->fpu->fp_status); \ |
| 2739 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
| 2740 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2741 | 6ea83fed | bellard | } \ |
| 2742 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
| 2743 | 6ea83fed | bellard | { \
|
| 2744 | 8f6f6026 | ths | FST2 = float32_ ## name(FST0, &env->fpu->fp_status); \ |
| 2745 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
| 2746 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2747 | 6ea83fed | bellard | } |
| 2748 | 6ea83fed | bellard | FLOAT_UNOP(sqrt) |
| 2749 | 6ea83fed | bellard | #undef FLOAT_UNOP
|
| 2750 | 6ea83fed | bellard | |
| 2751 | 6ea83fed | bellard | /* unary operations, not modifying fp status */
|
| 2752 | 6ea83fed | bellard | #define FLOAT_UNOP(name) \
|
| 2753 | 6ea83fed | bellard | FLOAT_OP(name, d) \ |
| 2754 | 6ea83fed | bellard | { \
|
| 2755 | 6ea83fed | bellard | FDT2 = float64_ ## name(FDT0); \ |
| 2756 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
| 2757 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2758 | 6ea83fed | bellard | } \ |
| 2759 | 6ea83fed | bellard | FLOAT_OP(name, s) \ |
| 2760 | 6ea83fed | bellard | { \
|
| 2761 | 6ea83fed | bellard | FST2 = float32_ ## name(FST0); \ |
| 2762 | 6ea83fed | bellard | DEBUG_FPU_STATE(); \ |
| 2763 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2764 | 5a5012ec | ths | } \ |
| 2765 | 5a5012ec | ths | FLOAT_OP(name, ps) \ |
| 2766 | 5a5012ec | ths | { \
|
| 2767 | 5a5012ec | ths | FST2 = float32_ ## name(FST0); \ |
| 2768 | 5a5012ec | ths | FSTH2 = float32_ ## name(FSTH0); \ |
| 2769 | 5a5012ec | ths | DEBUG_FPU_STATE(); \ |
| 2770 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2771 | 6ea83fed | bellard | } |
| 2772 | 6ea83fed | bellard | FLOAT_UNOP(abs) |
| 2773 | 6ea83fed | bellard | FLOAT_UNOP(chs) |
| 2774 | 6ea83fed | bellard | #undef FLOAT_UNOP
|
| 2775 | 6ea83fed | bellard | |
| 2776 | 6ea83fed | bellard | FLOAT_OP(mov, d) |
| 2777 | 6ea83fed | bellard | {
|
| 2778 | 6ea83fed | bellard | FDT2 = FDT0; |
| 2779 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2780 | 8f6f6026 | ths | FORCE_RET(); |
| 2781 | 6ea83fed | bellard | } |
| 2782 | 6ea83fed | bellard | FLOAT_OP(mov, s) |
| 2783 | 6ea83fed | bellard | {
|
| 2784 | 6ea83fed | bellard | FST2 = FST0; |
| 2785 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2786 | 8f6f6026 | ths | FORCE_RET(); |
| 2787 | 6ea83fed | bellard | } |
| 2788 | 5a5012ec | ths | FLOAT_OP(mov, ps) |
| 2789 | 5a5012ec | ths | {
|
| 2790 | 5a5012ec | ths | FST2 = FST0; |
| 2791 | 5a5012ec | ths | FSTH2 = FSTH0; |
| 2792 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2793 | 8f6f6026 | ths | FORCE_RET(); |
| 2794 | 5a5012ec | ths | } |
| 2795 | 5a5012ec | ths | FLOAT_OP(alnv, ps) |
| 2796 | 5a5012ec | ths | {
|
| 2797 | 5a5012ec | ths | switch (T0 & 0x7) { |
| 2798 | 5a5012ec | ths | case 0: |
| 2799 | 5a5012ec | ths | FST2 = FST0; |
| 2800 | 5a5012ec | ths | FSTH2 = FSTH0; |
| 2801 | 5a5012ec | ths | break;
|
| 2802 | 5a5012ec | ths | case 4: |
| 2803 | 5a5012ec | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
| 2804 | 5a5012ec | ths | FSTH2 = FST0; |
| 2805 | 5a5012ec | ths | FST2 = FSTH1; |
| 2806 | 5a5012ec | ths | #else
|
| 2807 | 5a5012ec | ths | FSTH2 = FST1; |
| 2808 | 5a5012ec | ths | FST2 = FSTH0; |
| 2809 | 5a5012ec | ths | #endif
|
| 2810 | 5a5012ec | ths | break;
|
| 2811 | 5a5012ec | ths | default: /* unpredictable */ |
| 2812 | 5a5012ec | ths | break;
|
| 2813 | 5a5012ec | ths | } |
| 2814 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2815 | 8f6f6026 | ths | FORCE_RET(); |
| 2816 | 5a5012ec | ths | } |
| 2817 | 6ea83fed | bellard | |
| 2818 | 6ea83fed | bellard | #ifdef CONFIG_SOFTFLOAT
|
| 2819 | 6ea83fed | bellard | #define clear_invalid() do { \ |
| 2820 | ead9360e | ths | int flags = get_float_exception_flags(&env->fpu->fp_status); \
|
| 2821 | 6ea83fed | bellard | flags &= ~float_flag_invalid; \ |
| 2822 | 8f6f6026 | ths | set_float_exception_flags(flags, &env->fpu->fp_status); \ |
| 2823 | 6ea83fed | bellard | } while(0) |
| 2824 | 6ea83fed | bellard | #else
|
| 2825 | 6ea83fed | bellard | #define clear_invalid() do { } while(0) |
| 2826 | 6ea83fed | bellard | #endif
|
| 2827 | 6ea83fed | bellard | |
| 2828 | 6ea83fed | bellard | extern void dump_fpu_s(CPUState *env); |
| 2829 | 6ea83fed | bellard | |
| 2830 | fd4a04eb | ths | #define CMP_OP(fmt, op) \
|
| 2831 | fd4a04eb | ths | void OPPROTO op_cmp ## _ ## fmt ## _ ## op(void) \ |
| 2832 | fd4a04eb | ths | { \
|
| 2833 | fd4a04eb | ths | CALL_FROM_TB1(do_cmp ## _ ## fmt ## _ ## op, PARAM1); \ |
| 2834 | fd4a04eb | ths | DEBUG_FPU_STATE(); \ |
| 2835 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2836 | fd4a04eb | ths | } \ |
| 2837 | fd4a04eb | ths | void OPPROTO op_cmpabs ## _ ## fmt ## _ ## op(void) \ |
| 2838 | fd4a04eb | ths | { \
|
| 2839 | fd4a04eb | ths | CALL_FROM_TB1(do_cmpabs ## _ ## fmt ## _ ## op, PARAM1); \ |
| 2840 | fd4a04eb | ths | DEBUG_FPU_STATE(); \ |
| 2841 | 8f6f6026 | ths | FORCE_RET(); \ |
| 2842 | fd4a04eb | ths | } |
| 2843 | fd4a04eb | ths | #define CMP_OPS(op) \
|
| 2844 | fd4a04eb | ths | CMP_OP(d, op) \ |
| 2845 | fd4a04eb | ths | CMP_OP(s, op) \ |
| 2846 | fd4a04eb | ths | CMP_OP(ps, op) |
| 2847 | fd4a04eb | ths | |
| 2848 | fd4a04eb | ths | CMP_OPS(f) |
| 2849 | fd4a04eb | ths | CMP_OPS(un) |
| 2850 | fd4a04eb | ths | CMP_OPS(eq) |
| 2851 | fd4a04eb | ths | CMP_OPS(ueq) |
| 2852 | fd4a04eb | ths | CMP_OPS(olt) |
| 2853 | fd4a04eb | ths | CMP_OPS(ult) |
| 2854 | fd4a04eb | ths | CMP_OPS(ole) |
| 2855 | fd4a04eb | ths | CMP_OPS(ule) |
| 2856 | fd4a04eb | ths | CMP_OPS(sf) |
| 2857 | fd4a04eb | ths | CMP_OPS(ngle) |
| 2858 | fd4a04eb | ths | CMP_OPS(seq) |
| 2859 | fd4a04eb | ths | CMP_OPS(ngl) |
| 2860 | fd4a04eb | ths | CMP_OPS(lt) |
| 2861 | fd4a04eb | ths | CMP_OPS(nge) |
| 2862 | fd4a04eb | ths | CMP_OPS(le) |
| 2863 | fd4a04eb | ths | CMP_OPS(ngt) |
| 2864 | fd4a04eb | ths | #undef CMP_OPS
|
| 2865 | fd4a04eb | ths | #undef CMP_OP
|
| 2866 | 6ea83fed | bellard | |
| 2867 | 6ea83fed | bellard | void op_bc1f (void) |
| 2868 | 6ea83fed | bellard | {
|
| 2869 | ead9360e | ths | T0 = !!(~GET_FP_COND(env->fpu) & (0x1 << PARAM1));
|
| 2870 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2871 | 8f6f6026 | ths | FORCE_RET(); |
| 2872 | 5a5012ec | ths | } |
| 2873 | fd4a04eb | ths | void op_bc1any2f (void) |
| 2874 | 5a5012ec | ths | {
|
| 2875 | ead9360e | ths | T0 = !!(~GET_FP_COND(env->fpu) & (0x3 << PARAM1));
|
| 2876 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2877 | 8f6f6026 | ths | FORCE_RET(); |
| 2878 | 5a5012ec | ths | } |
| 2879 | fd4a04eb | ths | void op_bc1any4f (void) |
| 2880 | 5a5012ec | ths | {
|
| 2881 | ead9360e | ths | T0 = !!(~GET_FP_COND(env->fpu) & (0xf << PARAM1));
|
| 2882 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2883 | 8f6f6026 | ths | FORCE_RET(); |
| 2884 | 6ea83fed | bellard | } |
| 2885 | 6ea83fed | bellard | |
| 2886 | 6ea83fed | bellard | void op_bc1t (void) |
| 2887 | 6ea83fed | bellard | {
|
| 2888 | ead9360e | ths | T0 = !!(GET_FP_COND(env->fpu) & (0x1 << PARAM1));
|
| 2889 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2890 | 8f6f6026 | ths | FORCE_RET(); |
| 2891 | 5a5012ec | ths | } |
| 2892 | fd4a04eb | ths | void op_bc1any2t (void) |
| 2893 | 5a5012ec | ths | {
|
| 2894 | ead9360e | ths | T0 = !!(GET_FP_COND(env->fpu) & (0x3 << PARAM1));
|
| 2895 | 5a5012ec | ths | DEBUG_FPU_STATE(); |
| 2896 | 8f6f6026 | ths | FORCE_RET(); |
| 2897 | 5a5012ec | ths | } |
| 2898 | fd4a04eb | ths | void op_bc1any4t (void) |
| 2899 | 5a5012ec | ths | {
|
| 2900 | ead9360e | ths | T0 = !!(GET_FP_COND(env->fpu) & (0xf << PARAM1));
|
| 2901 | 6ea83fed | bellard | DEBUG_FPU_STATE(); |
| 2902 | 8f6f6026 | ths | FORCE_RET(); |
| 2903 | 6ea83fed | bellard | } |
| 2904 | 6ea83fed | bellard | |
| 2905 | 6af0bf9c | bellard | void op_tlbwi (void) |
| 2906 | 6af0bf9c | bellard | {
|
| 2907 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbwi); |
| 2908 | 8f6f6026 | ths | FORCE_RET(); |
| 2909 | 6af0bf9c | bellard | } |
| 2910 | 6af0bf9c | bellard | |
| 2911 | 6af0bf9c | bellard | void op_tlbwr (void) |
| 2912 | 6af0bf9c | bellard | {
|
| 2913 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbwr); |
| 2914 | 8f6f6026 | ths | FORCE_RET(); |
| 2915 | 6af0bf9c | bellard | } |
| 2916 | 6af0bf9c | bellard | |
| 2917 | 6af0bf9c | bellard | void op_tlbp (void) |
| 2918 | 6af0bf9c | bellard | {
|
| 2919 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbp); |
| 2920 | 8f6f6026 | ths | FORCE_RET(); |
| 2921 | 6af0bf9c | bellard | } |
| 2922 | 6af0bf9c | bellard | |
| 2923 | 6af0bf9c | bellard | void op_tlbr (void) |
| 2924 | 6af0bf9c | bellard | {
|
| 2925 | ead9360e | ths | CALL_FROM_TB0(env->tlb->do_tlbr); |
| 2926 | 8f6f6026 | ths | FORCE_RET(); |
| 2927 | 6af0bf9c | bellard | } |
| 2928 | 6af0bf9c | bellard | |
| 2929 | 6af0bf9c | bellard | /* Specials */
|
| 2930 | 6f5b89a0 | ths | #if defined (CONFIG_USER_ONLY)
|
| 2931 | 6f5b89a0 | ths | void op_tls_value (void) |
| 2932 | 6f5b89a0 | ths | {
|
| 2933 | 5a5012ec | ths | T0 = env->tls_value; |
| 2934 | 6f5b89a0 | ths | } |
| 2935 | 6f5b89a0 | ths | #endif
|
| 2936 | 6f5b89a0 | ths | |
| 2937 | 6af0bf9c | bellard | void op_pmon (void) |
| 2938 | 6af0bf9c | bellard | {
|
| 2939 | 6af0bf9c | bellard | CALL_FROM_TB1(do_pmon, PARAM1); |
| 2940 | 8f6f6026 | ths | FORCE_RET(); |
| 2941 | 7a387fff | ths | } |
| 2942 | 7a387fff | ths | |
| 2943 | 7a387fff | ths | void op_di (void) |
| 2944 | 7a387fff | ths | {
|
| 2945 | 7a387fff | ths | T0 = env->CP0_Status; |
| 2946 | 4de9b249 | ths | env->CP0_Status = T0 & ~(1 << CP0St_IE);
|
| 2947 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
| 2948 | 8f6f6026 | ths | FORCE_RET(); |
| 2949 | 7a387fff | ths | } |
| 2950 | 7a387fff | ths | |
| 2951 | 7a387fff | ths | void op_ei (void) |
| 2952 | 7a387fff | ths | {
|
| 2953 | 7a387fff | ths | T0 = env->CP0_Status; |
| 2954 | 4de9b249 | ths | env->CP0_Status = T0 | (1 << CP0St_IE);
|
| 2955 | 4de9b249 | ths | CALL_FROM_TB1(cpu_mips_update_irq, env); |
| 2956 | 8f6f6026 | ths | FORCE_RET(); |
| 2957 | 6af0bf9c | bellard | } |
| 2958 | 6af0bf9c | bellard | |
| 2959 | 6af0bf9c | bellard | void op_trap (void) |
| 2960 | 6af0bf9c | bellard | {
|
| 2961 | 6af0bf9c | bellard | if (T0) {
|
| 2962 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_TRAP); |
| 2963 | 6af0bf9c | bellard | } |
| 2964 | 8f6f6026 | ths | FORCE_RET(); |
| 2965 | 6af0bf9c | bellard | } |
| 2966 | 6af0bf9c | bellard | |
| 2967 | 4ad40f36 | bellard | void op_debug (void) |
| 2968 | 4ad40f36 | bellard | {
|
| 2969 | 7a387fff | ths | CALL_FROM_TB1(do_raise_exception, EXCP_DEBUG); |
| 2970 | 8f6f6026 | ths | FORCE_RET(); |
| 2971 | 4ad40f36 | bellard | } |
| 2972 | 4ad40f36 | bellard | |
| 2973 | f41c52f1 | ths | void debug_pre_eret (void); |
| 2974 | f41c52f1 | ths | void debug_post_eret (void); |
| 2975 | 6af0bf9c | bellard | void op_eret (void) |
| 2976 | 6af0bf9c | bellard | {
|
| 2977 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
| 2978 | f41c52f1 | ths | CALL_FROM_TB0(debug_pre_eret); |
| 2979 | 24c7b0e3 | ths | if (env->CP0_Status & (1 << CP0St_ERL)) { |
| 2980 | ead9360e | ths | env->PC[env->current_tc] = env->CP0_ErrorEPC; |
| 2981 | 24c7b0e3 | ths | env->CP0_Status &= ~(1 << CP0St_ERL);
|
| 2982 | 51e11d9e | bellard | } else {
|
| 2983 | ead9360e | ths | env->PC[env->current_tc] = env->CP0_EPC; |
| 2984 | 24c7b0e3 | ths | env->CP0_Status &= ~(1 << CP0St_EXL);
|
| 2985 | 51e11d9e | bellard | } |
| 2986 | 08fa4bab | ths | CALL_FROM_TB1(compute_hflags, env); |
| 2987 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
| 2988 | f41c52f1 | ths | CALL_FROM_TB0(debug_post_eret); |
| 2989 | 6af0bf9c | bellard | env->CP0_LLAddr = 1;
|
| 2990 | 8f6f6026 | ths | FORCE_RET(); |
| 2991 | 6af0bf9c | bellard | } |
| 2992 | 6af0bf9c | bellard | |
| 2993 | 6af0bf9c | bellard | void op_deret (void) |
| 2994 | 6af0bf9c | bellard | {
|
| 2995 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
| 2996 | f41c52f1 | ths | CALL_FROM_TB0(debug_pre_eret); |
| 2997 | ead9360e | ths | env->PC[env->current_tc] = env->CP0_DEPC; |
| 2998 | 08fa4bab | ths | env->hflags &= MIPS_HFLAG_DM; |
| 2999 | 08fa4bab | ths | CALL_FROM_TB1(compute_hflags, env); |
| 3000 | f41c52f1 | ths | if (loglevel & CPU_LOG_EXEC)
|
| 3001 | f41c52f1 | ths | CALL_FROM_TB0(debug_post_eret); |
| 3002 | 24c7b0e3 | ths | env->CP0_LLAddr = 1;
|
| 3003 | 8f6f6026 | ths | FORCE_RET(); |
| 3004 | 7a387fff | ths | } |
| 3005 | 7a387fff | ths | |
| 3006 | 7a387fff | ths | void op_rdhwr_cpunum(void) |
| 3007 | 7a387fff | ths | {
|
| 3008 | 387a8fe5 | ths | if ((env->hflags & MIPS_HFLAG_CP0) ||
|
| 3009 | 387a8fe5 | ths | (env->CP0_HWREna & (1 << 0))) |
| 3010 | 1579a72e | ths | T0 = env->CP0_EBase & 0x3ff;
|
| 3011 | 7a387fff | ths | else
|
| 3012 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
| 3013 | 8f6f6026 | ths | FORCE_RET(); |
| 3014 | 7a387fff | ths | } |
| 3015 | 7a387fff | ths | |
| 3016 | 7a387fff | ths | void op_rdhwr_synci_step(void) |
| 3017 | 7a387fff | ths | {
|
| 3018 | 387a8fe5 | ths | if ((env->hflags & MIPS_HFLAG_CP0) ||
|
| 3019 | 387a8fe5 | ths | (env->CP0_HWREna & (1 << 1))) |
| 3020 | 1579a72e | ths | T0 = env->SYNCI_Step; |
| 3021 | 7a387fff | ths | else
|
| 3022 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
| 3023 | 8f6f6026 | ths | FORCE_RET(); |
| 3024 | 7a387fff | ths | } |
| 3025 | 7a387fff | ths | |
| 3026 | 7a387fff | ths | void op_rdhwr_cc(void) |
| 3027 | 7a387fff | ths | {
|
| 3028 | 387a8fe5 | ths | if ((env->hflags & MIPS_HFLAG_CP0) ||
|
| 3029 | 387a8fe5 | ths | (env->CP0_HWREna & (1 << 2))) |
| 3030 | 1579a72e | ths | T0 = env->CP0_Count; |
| 3031 | 7a387fff | ths | else
|
| 3032 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
| 3033 | 8f6f6026 | ths | FORCE_RET(); |
| 3034 | 7a387fff | ths | } |
| 3035 | 7a387fff | ths | |
| 3036 | 7a387fff | ths | void op_rdhwr_ccres(void) |
| 3037 | 7a387fff | ths | {
|
| 3038 | 387a8fe5 | ths | if ((env->hflags & MIPS_HFLAG_CP0) ||
|
| 3039 | 387a8fe5 | ths | (env->CP0_HWREna & (1 << 3))) |
| 3040 | 1579a72e | ths | T0 = env->CCRes; |
| 3041 | 7a387fff | ths | else
|
| 3042 | 1579a72e | ths | CALL_FROM_TB1(do_raise_exception, EXCP_RI); |
| 3043 | 8f6f6026 | ths | FORCE_RET(); |
| 3044 | 1579a72e | ths | } |
| 3045 | 1579a72e | ths | |
| 3046 | 6af0bf9c | bellard | void op_save_state (void) |
| 3047 | 6af0bf9c | bellard | {
|
| 3048 | 6af0bf9c | bellard | env->hflags = PARAM1; |
| 3049 | 8f6f6026 | ths | FORCE_RET(); |
| 3050 | 6af0bf9c | bellard | } |
| 3051 | 6af0bf9c | bellard | |
| 3052 | 6af0bf9c | bellard | void op_save_pc (void) |
| 3053 | 6af0bf9c | bellard | {
|
| 3054 | ead9360e | ths | env->PC[env->current_tc] = PARAM1; |
| 3055 | 8f6f6026 | ths | FORCE_RET(); |
| 3056 | 6af0bf9c | bellard | } |
| 3057 | 6af0bf9c | bellard | |
| 3058 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
| 3059 | 9b9e4393 | ths | void op_save_pc64 (void) |
| 3060 | 9b9e4393 | ths | {
|
| 3061 | ead9360e | ths | env->PC[env->current_tc] = ((uint64_t)PARAM1 << 32) | (uint32_t)PARAM2;
|
| 3062 | 8f6f6026 | ths | FORCE_RET(); |
| 3063 | 9b9e4393 | ths | } |
| 3064 | 9b9e4393 | ths | #endif
|
| 3065 | 9b9e4393 | ths | |
| 3066 | 16c00cb2 | ths | void op_interrupt_restart (void) |
| 3067 | 16c00cb2 | ths | {
|
| 3068 | 16c00cb2 | ths | if (!(env->CP0_Status & (1 << CP0St_EXL)) && |
| 3069 | 16c00cb2 | ths | !(env->CP0_Status & (1 << CP0St_ERL)) &&
|
| 3070 | 16c00cb2 | ths | !(env->hflags & MIPS_HFLAG_DM) && |
| 3071 | 16c00cb2 | ths | (env->CP0_Status & (1 << CP0St_IE)) &&
|
| 3072 | 16c00cb2 | ths | (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask)) {
|
| 3073 | 16c00cb2 | ths | env->CP0_Cause &= ~(0x1f << CP0Ca_EC);
|
| 3074 | 16c00cb2 | ths | CALL_FROM_TB1(do_raise_exception, EXCP_EXT_INTERRUPT); |
| 3075 | 16c00cb2 | ths | } |
| 3076 | 8f6f6026 | ths | FORCE_RET(); |
| 3077 | 16c00cb2 | ths | } |
| 3078 | 16c00cb2 | ths | |
| 3079 | 6af0bf9c | bellard | void op_raise_exception (void) |
| 3080 | 6af0bf9c | bellard | {
|
| 3081 | 6af0bf9c | bellard | CALL_FROM_TB1(do_raise_exception, PARAM1); |
| 3082 | 8f6f6026 | ths | FORCE_RET(); |
| 3083 | 6af0bf9c | bellard | } |
| 3084 | 6af0bf9c | bellard | |
| 3085 | 6af0bf9c | bellard | void op_raise_exception_err (void) |
| 3086 | 6af0bf9c | bellard | {
|
| 3087 | 6af0bf9c | bellard | CALL_FROM_TB2(do_raise_exception_err, PARAM1, PARAM2); |
| 3088 | 8f6f6026 | ths | FORCE_RET(); |
| 3089 | 6af0bf9c | bellard | } |
| 3090 | 6af0bf9c | bellard | |
| 3091 | 4ad40f36 | bellard | void op_wait (void) |
| 3092 | 4ad40f36 | bellard | {
|
| 3093 | 4ad40f36 | bellard | env->halted = 1;
|
| 3094 | 4ad40f36 | bellard | CALL_FROM_TB1(do_raise_exception, EXCP_HLT); |
| 3095 | 8f6f6026 | ths | FORCE_RET(); |
| 3096 | 7a387fff | ths | } |
| 3097 | 7a387fff | ths | |
| 3098 | 7a387fff | ths | /* Bitfield operations. */
|
| 3099 | 7a387fff | ths | void op_ext(void) |
| 3100 | 7a387fff | ths | {
|
| 3101 | 7a387fff | ths | unsigned int pos = PARAM1; |
| 3102 | 7a387fff | ths | unsigned int size = PARAM2; |
| 3103 | 7a387fff | ths | |
| 3104 | c6d6dd7c | ths | T0 = (int32_t)((T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0)); |
| 3105 | 8f6f6026 | ths | FORCE_RET(); |
| 3106 | 7a387fff | ths | } |
| 3107 | 7a387fff | ths | |
| 3108 | 7a387fff | ths | void op_ins(void) |
| 3109 | 7a387fff | ths | {
|
| 3110 | 7a387fff | ths | unsigned int pos = PARAM1; |
| 3111 | 7a387fff | ths | unsigned int size = PARAM2; |
| 3112 | f757d6ff | ths | target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos; |
| 3113 | 7a387fff | ths | |
| 3114 | c6d6dd7c | ths | T0 = (int32_t)((T0 & ~mask) | ((T1 << pos) & mask)); |
| 3115 | 8f6f6026 | ths | FORCE_RET(); |
| 3116 | 7a387fff | ths | } |
| 3117 | 7a387fff | ths | |
| 3118 | 7a387fff | ths | void op_wsbh(void) |
| 3119 | 7a387fff | ths | {
|
| 3120 | c6d6dd7c | ths | T0 = (int32_t)(((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF)); |
| 3121 | 8f6f6026 | ths | FORCE_RET(); |
| 3122 | 7a387fff | ths | } |
| 3123 | 7a387fff | ths | |
| 3124 | d26bc211 | ths | #if defined(TARGET_MIPS64)
|
| 3125 | c570fd16 | ths | void op_dext(void) |
| 3126 | c570fd16 | ths | {
|
| 3127 | c570fd16 | ths | unsigned int pos = PARAM1; |
| 3128 | c570fd16 | ths | unsigned int size = PARAM2; |
| 3129 | c570fd16 | ths | |
| 3130 | c6d6dd7c | ths | T0 = (T1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL); |
| 3131 | 8f6f6026 | ths | FORCE_RET(); |
| 3132 | c570fd16 | ths | } |
| 3133 | c570fd16 | ths | |
| 3134 | c570fd16 | ths | void op_dins(void) |
| 3135 | c570fd16 | ths | {
|
| 3136 | c570fd16 | ths | unsigned int pos = PARAM1; |
| 3137 | c570fd16 | ths | unsigned int size = PARAM2; |
| 3138 | c6d6dd7c | ths | target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos; |
| 3139 | c570fd16 | ths | |
| 3140 | 171b31e7 | ths | T0 = (T0 & ~mask) | ((T1 << pos) & mask); |
| 3141 | 8f6f6026 | ths | FORCE_RET(); |
| 3142 | c570fd16 | ths | } |
| 3143 | c570fd16 | ths | |
| 3144 | 7a387fff | ths | void op_dsbh(void) |
| 3145 | 7a387fff | ths | {
|
| 3146 | 7a387fff | ths | T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL); |
| 3147 | 8f6f6026 | ths | FORCE_RET(); |
| 3148 | 7a387fff | ths | } |
| 3149 | 7a387fff | ths | |
| 3150 | 7a387fff | ths | void op_dshd(void) |
| 3151 | 7a387fff | ths | {
|
| 3152 | c6d6dd7c | ths | T1 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL); |
| 3153 | c6d6dd7c | ths | T0 = (T1 << 32) | (T1 >> 32); |
| 3154 | 8f6f6026 | ths | FORCE_RET(); |
| 3155 | 7a387fff | ths | } |
| 3156 | c570fd16 | ths | #endif
|
| 3157 | 7a387fff | ths | |
| 3158 | 7a387fff | ths | void op_seb(void) |
| 3159 | 7a387fff | ths | {
|
| 3160 | 7a387fff | ths | T0 = ((T1 & 0xFF) ^ 0x80) - 0x80; |
| 3161 | 8f6f6026 | ths | FORCE_RET(); |
| 3162 | 7a387fff | ths | } |
| 3163 | 7a387fff | ths | |
| 3164 | 7a387fff | ths | void op_seh(void) |
| 3165 | 7a387fff | ths | {
|
| 3166 | 7a387fff | ths | T0 = ((T1 & 0xFFFF) ^ 0x8000) - 0x8000; |
| 3167 | 8f6f6026 | ths | FORCE_RET(); |
| 3168 | 4ad40f36 | bellard | } |