Revision 8d3a8c1e
| b/hw/openpic.c | ||
|---|---|---|
| 472 | 472 |
opp->glbc = 0x00000000; |
| 473 | 473 |
} |
| 474 | 474 |
|
| 475 |
static inline uint32_t read_IRQreg (openpic_t *opp, int n_IRQ, uint32_t reg)
|
|
| 475 |
static inline uint32_t read_IRQreg_ide(openpic_t *opp, int n_IRQ)
|
|
| 476 | 476 |
{
|
| 477 |
uint32_t retval; |
|
| 478 |
|
|
| 479 |
switch (reg) {
|
|
| 480 |
case IRQ_IPVP: |
|
| 481 |
retval = opp->src[n_IRQ].ipvp; |
|
| 482 |
break; |
|
| 483 |
case IRQ_IDE: |
|
| 484 |
retval = opp->src[n_IRQ].ide; |
|
| 485 |
break; |
|
| 486 |
} |
|
| 477 |
return opp->src[n_IRQ].ide; |
|
| 478 |
} |
|
| 487 | 479 |
|
| 488 |
return retval; |
|
| 480 |
static inline uint32_t read_IRQreg_ipvp(openpic_t *opp, int n_IRQ) |
|
| 481 |
{
|
|
| 482 |
return opp->src[n_IRQ].ipvp; |
|
| 489 | 483 |
} |
| 490 | 484 |
|
| 491 | 485 |
static inline void write_IRQreg (openpic_t *opp, int n_IRQ, |
| ... | ... | |
| 523 | 517 |
|
| 524 | 518 |
switch (offset) {
|
| 525 | 519 |
case DBL_IPVP_OFFSET: |
| 526 |
retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
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|
| 520 |
retval = read_IRQreg_ipvp(opp, IRQ_DBL0 + n_dbl);
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|
| 527 | 521 |
break; |
| 528 | 522 |
case DBL_IDE_OFFSET: |
| 529 |
retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
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|
| 523 |
retval = read_IRQreg_ide(opp, IRQ_DBL0 + n_dbl);
|
|
| 530 | 524 |
break; |
| 531 | 525 |
case DBL_DMR_OFFSET: |
| 532 | 526 |
retval = opp->doorbells[n_dbl].dmr; |
| ... | ... | |
| 564 | 558 |
retval = opp->mailboxes[n_mbx].mbr; |
| 565 | 559 |
break; |
| 566 | 560 |
case MBX_IVPR_OFFSET: |
| 567 |
retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP);
|
|
| 561 |
retval = read_IRQreg_ipvp(opp, IRQ_MBX0 + n_mbx);
|
|
| 568 | 562 |
break; |
| 569 | 563 |
case MBX_DMR_OFFSET: |
| 570 |
retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE);
|
|
| 564 |
retval = read_IRQreg_ide(opp, IRQ_MBX0 + n_mbx);
|
|
| 571 | 565 |
break; |
| 572 | 566 |
} |
| 573 | 567 |
|
| ... | ... | |
| 695 | 689 |
{
|
| 696 | 690 |
int idx; |
| 697 | 691 |
idx = (addr - 0x10A0) >> 4; |
| 698 |
retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP);
|
|
| 692 |
retval = read_IRQreg_ipvp(opp, opp->irq_ipi0 + idx);
|
|
| 699 | 693 |
} |
| 700 | 694 |
break; |
| 701 | 695 |
case 0x10E0: /* SPVE */ |
| ... | ... | |
| 765 | 759 |
retval = opp->timers[idx].tibc; |
| 766 | 760 |
break; |
| 767 | 761 |
case 0x20: /* TIPV */ |
| 768 |
retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP);
|
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| 762 |
retval = read_IRQreg_ipvp(opp, opp->irq_tim0 + idx);
|
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| 769 | 763 |
break; |
| 770 | 764 |
case 0x30: /* TIDE */ |
| 771 |
retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE);
|
|
| 765 |
retval = read_IRQreg_ide(opp, opp->irq_tim0 + idx);
|
|
| 772 | 766 |
break; |
| 773 | 767 |
} |
| 774 | 768 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
| ... | ... | |
| 809 | 803 |
idx = addr >> 5; |
| 810 | 804 |
if (addr & 0x10) {
|
| 811 | 805 |
/* EXDE / IFEDE / IEEDE */ |
| 812 |
retval = read_IRQreg(opp, idx, IRQ_IDE);
|
|
| 806 |
retval = read_IRQreg_ide(opp, idx);
|
|
| 813 | 807 |
} else {
|
| 814 | 808 |
/* EXVP / IFEVP / IEEVP */ |
| 815 |
retval = read_IRQreg(opp, idx, IRQ_IPVP);
|
|
| 809 |
retval = read_IRQreg_ipvp(opp, idx);
|
|
| 816 | 810 |
} |
| 817 | 811 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
| 818 | 812 |
|
| ... | ... | |
| 1368 | 1362 |
retval = mpp->timers[idx].tibc; |
| 1369 | 1363 |
break; |
| 1370 | 1364 |
case 0x20: /* TIPV */ |
| 1371 |
retval = read_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IPVP);
|
|
| 1365 |
retval = read_IRQreg_ipvp(mpp, MPIC_TMR_IRQ + idx);
|
|
| 1372 | 1366 |
break; |
| 1373 | 1367 |
case 0x30: /* TIDR */ |
| 1374 | 1368 |
if ((addr &0xF0) == 0XF0) |
| 1375 | 1369 |
retval = mpp->dst[cpu].tfrr; |
| 1376 | 1370 |
else |
| 1377 |
retval = read_IRQreg(mpp, MPIC_TMR_IRQ + idx, IRQ_IDE);
|
|
| 1371 |
retval = read_IRQreg_ide(mpp, MPIC_TMR_IRQ + idx);
|
|
| 1378 | 1372 |
break; |
| 1379 | 1373 |
} |
| 1380 | 1374 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
| ... | ... | |
| 1421 | 1415 |
idx += (addr & 0xFFF0) >> 5; |
| 1422 | 1416 |
if (addr & 0x10) {
|
| 1423 | 1417 |
/* EXDE / IFEDE / IEEDE */ |
| 1424 |
retval = read_IRQreg(mpp, idx, IRQ_IDE);
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| 1418 |
retval = read_IRQreg_ide(mpp, idx);
|
|
| 1425 | 1419 |
} else {
|
| 1426 | 1420 |
/* EXVP / IFEVP / IEEVP */ |
| 1427 |
retval = read_IRQreg(mpp, idx, IRQ_IPVP);
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| 1421 |
retval = read_IRQreg_ipvp(mpp, idx);
|
|
| 1428 | 1422 |
} |
| 1429 | 1423 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
| 1430 | 1424 |
} |
| ... | ... | |
| 1471 | 1465 |
idx += (addr & 0xFFF0) >> 5; |
| 1472 | 1466 |
if (addr & 0x10) {
|
| 1473 | 1467 |
/* EXDE / IFEDE / IEEDE */ |
| 1474 |
retval = read_IRQreg(mpp, idx, IRQ_IDE);
|
|
| 1468 |
retval = read_IRQreg_ide(mpp, idx);
|
|
| 1475 | 1469 |
} else {
|
| 1476 | 1470 |
/* EXVP / IFEVP / IEEVP */ |
| 1477 |
retval = read_IRQreg(mpp, idx, IRQ_IPVP);
|
|
| 1471 |
retval = read_IRQreg_ipvp(mpp, idx);
|
|
| 1478 | 1472 |
} |
| 1479 | 1473 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
| 1480 | 1474 |
} |
| ... | ... | |
| 1521 | 1515 |
idx += (addr & 0xFFF0) >> 5; |
| 1522 | 1516 |
if (addr & 0x10) {
|
| 1523 | 1517 |
/* EXDE / IFEDE / IEEDE */ |
| 1524 |
retval = read_IRQreg(mpp, idx, IRQ_IDE);
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|
| 1518 |
retval = read_IRQreg_ide(mpp, idx);
|
|
| 1525 | 1519 |
} else {
|
| 1526 | 1520 |
/* EXVP / IFEVP / IEEVP */ |
| 1527 |
retval = read_IRQreg(mpp, idx, IRQ_IPVP);
|
|
| 1521 |
retval = read_IRQreg_ipvp(mpp, idx);
|
|
| 1528 | 1522 |
} |
| 1529 | 1523 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
| 1530 | 1524 |
} |
| ... | ... | |
| 1570 | 1564 |
idx += (addr & 0xFFF0) >> 5; |
| 1571 | 1565 |
if (addr & 0x10) {
|
| 1572 | 1566 |
/* EXDE / IFEDE / IEEDE */ |
| 1573 |
retval = read_IRQreg(mpp, idx, IRQ_IDE);
|
|
| 1567 |
retval = read_IRQreg_ide(mpp, idx);
|
|
| 1574 | 1568 |
} else {
|
| 1575 | 1569 |
/* EXVP / IFEVP / IEEVP */ |
| 1576 |
retval = read_IRQreg(mpp, idx, IRQ_IPVP);
|
|
| 1570 |
retval = read_IRQreg_ipvp(mpp, idx);
|
|
| 1577 | 1571 |
} |
| 1578 | 1572 |
DPRINTF("%s: => %08x\n", __func__, retval);
|
| 1579 | 1573 |
} |
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