Revision 8d43d7e5 hw/gt64xxx.c
| b/hw/gt64xxx.c | ||
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| 229 | 229 |
target_phys_addr_t regname ##_length; \ |
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MemoryRegion regname ##_mem |
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#define TYPE_GT64120_PCI_HOST_BRIDGE "gt64120" |
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#define GT64120_PCI_HOST_BRIDGE(obj) \ |
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OBJECT_CHECK(GT64120State, (obj), TYPE_GT64120_PCI_HOST_BRIDGE) |
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typedef struct GT64120State {
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SysBusDevice busdev; |
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PCIHostState pci; |
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uint32_t regs[GT_REGS]; |
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PCI_MAPPING_ENTRY(PCI0IO); |
| 237 | 242 |
PCI_MAPPING_ENTRY(ISD); |
| ... | ... | |
| 1083 | 1088 |
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PCIBus *gt64120_register(qemu_irq *pic) |
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{
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SysBusDevice *s; |
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GT64120State *d; |
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PCIHostState *phb; |
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DeviceState *dev; |
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dev = qdev_create(NULL, "gt64120");
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dev = qdev_create(NULL, TYPE_GT64120_PCI_HOST_BRIDGE);
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qdev_init_nofail(dev); |
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s = sysbus_from_qdev(dev);
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d = FROM_SYSBUS(GT64120State, s);
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d->pci.bus = pci_register_bus(&d->busdev.qdev, "pci",
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gt64120_pci_set_irq, gt64120_pci_map_irq,
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pic,
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get_system_memory(),
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get_system_io(),
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PCI_DEVFN(18, 0), 4);
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d = GT64120_PCI_HOST_BRIDGE(dev);
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phb = &d->pci;
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phb->bus = pci_register_bus(dev, "pci",
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gt64120_pci_set_irq, gt64120_pci_map_irq, |
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pic, |
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get_system_memory(), |
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get_system_io(), |
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PCI_DEVFN(18, 0), 4); |
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memory_region_init_io(&d->ISD_mem, &isd_mem_ops, d, "isd-mem", 0x1000); |
| 1101 | 1106 |
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pci_create_simple(d->pci.bus, PCI_DEVFN(0, 0), "gt64120_pci");
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return d->pci.bus;
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pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
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return phb->bus;
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} |
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static int gt64120_init(SysBusDevice *dev) |
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{
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GT64120State *s; |
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s = FROM_SYSBUS(GT64120State, dev);
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s = GT64120_PCI_HOST_BRIDGE(dev);
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/* FIXME: This value is computed from registers during reset, but some |
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devices (e.g. VGA card) need to know it when they are registered. |
| ... | ... | |
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} |
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static const TypeInfo gt64120_info = {
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.name = "gt64120",
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.name = TYPE_GT64120_PCI_HOST_BRIDGE,
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.parent = TYPE_SYS_BUS_DEVICE, |
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.instance_size = sizeof(GT64120State), |
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.class_init = gt64120_class_init, |
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