Revision 8da3ff18 hw/eepro100.c

b/hw/eepro100.c
1392 1392
static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1393 1393
{
1394 1394
    EEPRO100State *s = opaque;
1395
    addr -= s->region[0];
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    //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
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    eepro100_write1(s, addr, val);
1398 1397
}
......
1400 1399
static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1401 1400
{
1402 1401
    EEPRO100State *s = opaque;
1403
    addr -= s->region[0];
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    //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1405 1403
    eepro100_write2(s, addr, val);
1406 1404
}
......
1408 1406
static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1409 1407
{
1410 1408
    EEPRO100State *s = opaque;
1411
    addr -= s->region[0];
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    //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1413 1410
    eepro100_write4(s, addr, val);
1414 1411
}
......
1416 1413
static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1417 1414
{
1418 1415
    EEPRO100State *s = opaque;
1419
    addr -= s->region[0];
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    //~ logout("addr=%s\n", regname(addr));
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    return eepro100_read1(s, addr);
1422 1418
}
......
1424 1420
static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1425 1421
{
1426 1422
    EEPRO100State *s = opaque;
1427
    addr -= s->region[0];
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    //~ logout("addr=%s\n", regname(addr));
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    return eepro100_read2(s, addr);
1430 1425
}
......
1432 1427
static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1433 1428
{
1434 1429
    EEPRO100State *s = opaque;
1435
    addr -= s->region[0];
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    //~ logout("addr=%s\n", regname(addr));
1437 1431
    return eepro100_read4(s, addr);
1438 1432
}

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