Revision 8da3ff18 hw/omap.h
b/hw/omap.h | ||
---|---|---|
890 | 890 |
|
891 | 891 |
struct omap_lcd_panel_s *lcd; |
892 | 892 |
|
893 |
target_phys_addr_t ulpd_pm_base; |
|
894 | 893 |
uint32_t ulpd_pm_regs[21]; |
895 | 894 |
int64_t ulpd_gauge_start; |
896 | 895 |
|
897 |
target_phys_addr_t pin_cfg_base; |
|
898 | 896 |
uint32_t func_mux_ctrl[14]; |
899 | 897 |
uint32_t comp_mode_ctrl[1]; |
900 | 898 |
uint32_t pull_dwn_ctrl[4]; |
... | ... | |
905 | 903 |
int compat1509; |
906 | 904 |
|
907 | 905 |
uint32_t mpui_ctrl; |
908 |
target_phys_addr_t mpui_base; |
|
909 | 906 |
|
910 | 907 |
struct omap_tipb_bridge_s *private_tipb; |
911 | 908 |
struct omap_tipb_bridge_s *public_tipb; |
912 | 909 |
|
913 |
target_phys_addr_t tcmi_base; |
|
914 | 910 |
uint32_t tcmi_regs[17]; |
915 | 911 |
|
916 | 912 |
struct dpll_ctl_s { |
917 |
target_phys_addr_t base; |
|
918 | 913 |
uint16_t mode; |
919 | 914 |
omap_clk dpll; |
920 | 915 |
} dpll[3]; |
921 | 916 |
|
922 | 917 |
omap_clk clks; |
923 | 918 |
struct { |
924 |
target_phys_addr_t mpu_base; |
|
925 |
target_phys_addr_t dsp_base; |
|
926 |
|
|
927 | 919 |
int cold_start; |
928 | 920 |
int clocking_scheme; |
929 | 921 |
uint16_t arm_ckctl; |
... | ... | |
944 | 936 |
|
945 | 937 |
struct omap_gp_timer_s *gptimer[12]; |
946 | 938 |
|
947 |
target_phys_addr_t tap_base; |
|
948 |
|
|
949 | 939 |
struct omap_synctimer_s { |
950 |
target_phys_addr_t base; |
|
951 | 940 |
uint32_t val; |
952 | 941 |
uint16_t readh; |
953 | 942 |
} synctimer; |
Also available in: Unified diff