Revision 8da3ff18 hw/omap_dss.c
| b/hw/omap_dss.c | ||
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| 24 | 24 |
#include "omap.h" |
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|
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struct omap_dss_s {
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target_phys_addr_t diss_base; |
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target_phys_addr_t disc_base; |
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target_phys_addr_t rfbi_base; |
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target_phys_addr_t venc_base; |
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target_phys_addr_t im3_base; |
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qemu_irq irq; |
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qemu_irq drq; |
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DisplayState *state; |
| ... | ... | |
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static uint32_t omap_diss_read(void *opaque, target_phys_addr_t addr) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->diss_base; |
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switch (offset) {
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switch (addr) {
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case 0x00: /* DSS_REVISIONNUMBER */ |
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return 0x20; |
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|
| ... | ... | |
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uint32_t value) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->diss_base; |
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switch (offset) {
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switch (addr) {
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case 0x00: /* DSS_REVISIONNUMBER */ |
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case 0x14: /* DSS_SYSSTATUS */ |
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case 0x50: /* DSS_PSA_LCD_REG_1 */ |
| ... | ... | |
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static uint32_t omap_disc_read(void *opaque, target_phys_addr_t addr) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->disc_base; |
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switch (offset) {
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switch (addr) {
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case 0x000: /* DISPC_REVISION */ |
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return 0x20; |
| 262 | 254 |
|
| ... | ... | |
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uint32_t value) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->disc_base; |
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switch (offset) {
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switch (addr) {
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case 0x010: /* DISPC_SYSCONFIG */ |
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if (value & 2) /* SOFTRESET */ |
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omap_dss_reset(s); |
| ... | ... | |
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static uint32_t omap_rfbi_read(void *opaque, target_phys_addr_t addr) |
| 668 | 659 |
{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->rfbi_base; |
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switch (offset) {
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switch (addr) {
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case 0x00: /* RFBI_REVISION */ |
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return 0x10; |
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|
| ... | ... | |
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uint32_t value) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->rfbi_base; |
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switch (offset) {
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switch (addr) {
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case 0x10: /* RFBI_SYSCONFIG */ |
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if (value & 2) /* SOFTRESET */ |
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omap_rfbi_reset(s); |
| ... | ... | |
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|
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static uint32_t omap_venc_read(void *opaque, target_phys_addr_t addr) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->venc_base; |
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switch (offset) {
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switch (addr) {
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case 0x00: /* REV_ID */ |
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case 0x04: /* STATUS */ |
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case 0x08: /* F_CONTROL */ |
| ... | ... | |
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static void omap_venc_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->venc_base; |
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switch (offset) {
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switch (addr) {
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case 0x08: /* F_CONTROL */ |
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case 0x10: /* VIDOUT_CTRL */ |
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case 0x14: /* SYNC_CTRL */ |
| ... | ... | |
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|
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static uint32_t omap_im3_read(void *opaque, target_phys_addr_t addr) |
| 993 | 976 |
{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->im3_base; |
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switch (offset) {
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switch (addr) {
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case 0x0a8: /* SBIMERRLOGA */ |
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case 0x0b0: /* SBIMERRLOG */ |
| 1000 | 980 |
case 0x190: /* SBIMSTATE */ |
| ... | ... | |
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static void omap_im3_write(void *opaque, target_phys_addr_t addr, |
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uint32_t value) |
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{
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struct omap_dss_s *s = (struct omap_dss_s *) opaque; |
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int offset = addr - s->im3_base; |
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switch (offset) {
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switch (addr) {
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| 1023 | 1000 |
case 0x0b0: /* SBIMERRLOG */ |
| 1024 | 1001 |
case 0x190: /* SBIMSTATE */ |
| 1025 | 1002 |
case 0x198: /* SBTMSTATE_L */ |
| ... | ... | |
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omap_venc1_writefn, s); |
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iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn, |
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omap_im3_writefn, s); |
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s->diss_base = omap_l4_attach(ta, 0, iomemtype[0]); |
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s->disc_base = omap_l4_attach(ta, 1, iomemtype[1]); |
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s->rfbi_base = omap_l4_attach(ta, 2, iomemtype[2]); |
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s->venc_base = omap_l4_attach(ta, 3, iomemtype[3]); |
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s->im3_base = l3_base; |
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cpu_register_physical_memory(s->im3_base, 0x1000, iomemtype[4]); |
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omap_l4_attach(ta, 0, iomemtype[0]); |
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omap_l4_attach(ta, 1, iomemtype[1]); |
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omap_l4_attach(ta, 3, iomemtype[3]); |
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cpu_register_physical_memory(l3_base, 0x1000, iomemtype[4]); |
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| 1079 | 1054 |
|
| 1080 | 1055 |
#if 0 |
| 1081 | 1056 |
if (ds) |
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