Revision 8da3ff18 hw/stellaris.c
| b/hw/stellaris.c | ||
|---|---|---|
| 57 | 57 |
uint32_t rtc; |
| 58 | 58 |
int64_t tick[2]; |
| 59 | 59 |
struct gptm_state *opaque[2]; |
| 60 |
uint32_t base; |
|
| 61 | 60 |
QEMUTimer *timer[2]; |
| 62 | 61 |
/* The timers have an alternate output used to trigger the ADC. */ |
| 63 | 62 |
qemu_irq trigger; |
| ... | ... | |
| 148 | 147 |
{
|
| 149 | 148 |
gptm_state *s = (gptm_state *)opaque; |
| 150 | 149 |
|
| 151 |
offset -= s->base; |
|
| 152 | 150 |
switch (offset) {
|
| 153 | 151 |
case 0x00: /* CFG */ |
| 154 | 152 |
return s->config; |
| ... | ... | |
| 198 | 196 |
gptm_state *s = (gptm_state *)opaque; |
| 199 | 197 |
uint32_t oldval; |
| 200 | 198 |
|
| 201 |
offset -= s->base; |
|
| 202 | 199 |
/* The timers should be disabled before changing the configuration. |
| 203 | 200 |
We take advantage of this and defer everything until the timer |
| 204 | 201 |
is enabled. */ |
| ... | ... | |
| 351 | 348 |
gptm_state *s; |
| 352 | 349 |
|
| 353 | 350 |
s = (gptm_state *)qemu_mallocz(sizeof(gptm_state)); |
| 354 |
s->base = base; |
|
| 355 | 351 |
s->irq = irq; |
| 356 | 352 |
s->trigger = trigger; |
| 357 | 353 |
s->opaque[0] = s->opaque[1] = s; |
| ... | ... | |
| 368 | 364 |
/* System controller. */ |
| 369 | 365 |
|
| 370 | 366 |
typedef struct {
|
| 371 |
uint32_t base; |
|
| 372 | 367 |
uint32_t pborctl; |
| 373 | 368 |
uint32_t ldopctl; |
| 374 | 369 |
uint32_t int_status; |
| ... | ... | |
| 433 | 428 |
{
|
| 434 | 429 |
ssys_state *s = (ssys_state *)opaque; |
| 435 | 430 |
|
| 436 |
offset -= s->base; |
|
| 437 | 431 |
switch (offset) {
|
| 438 | 432 |
case 0x000: /* DID0 */ |
| 439 | 433 |
return s->board->did0; |
| ... | ... | |
| 520 | 514 |
{
|
| 521 | 515 |
ssys_state *s = (ssys_state *)opaque; |
| 522 | 516 |
|
| 523 |
offset -= s->base; |
|
| 524 | 517 |
switch (offset) {
|
| 525 | 518 |
case 0x030: /* PBORCTL */ |
| 526 | 519 |
s->pborctl = value & 0xffff; |
| ... | ... | |
| 672 | 665 |
ssys_state *s; |
| 673 | 666 |
|
| 674 | 667 |
s = (ssys_state *)qemu_mallocz(sizeof(ssys_state)); |
| 675 |
s->base = base; |
|
| 676 | 668 |
s->irq = irq; |
| 677 | 669 |
s->board = board; |
| 678 | 670 |
/* Most devices come preprogrammed with a MAC address in the user data. */ |
| ... | ... | |
| 692 | 684 |
typedef struct {
|
| 693 | 685 |
i2c_bus *bus; |
| 694 | 686 |
qemu_irq irq; |
| 695 |
uint32_t base; |
|
| 696 | 687 |
uint32_t msa; |
| 697 | 688 |
uint32_t mcs; |
| 698 | 689 |
uint32_t mdr; |
| ... | ... | |
| 714 | 705 |
{
|
| 715 | 706 |
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
| 716 | 707 |
|
| 717 |
offset -= s->base; |
|
| 718 | 708 |
switch (offset) {
|
| 719 | 709 |
case 0x00: /* MSA */ |
| 720 | 710 |
return s->msa; |
| ... | ... | |
| 753 | 743 |
{
|
| 754 | 744 |
stellaris_i2c_state *s = (stellaris_i2c_state *)opaque; |
| 755 | 745 |
|
| 756 |
offset -= s->base; |
|
| 757 | 746 |
switch (offset) {
|
| 758 | 747 |
case 0x00: /* MSA */ |
| 759 | 748 |
s->msa = value & 0xff; |
| ... | ... | |
| 890 | 879 |
int iomemtype; |
| 891 | 880 |
|
| 892 | 881 |
s = (stellaris_i2c_state *)qemu_mallocz(sizeof(stellaris_i2c_state)); |
| 893 |
s->base = base; |
|
| 894 | 882 |
s->irq = irq; |
| 895 | 883 |
s->bus = bus; |
| 896 | 884 |
|
| ... | ... | |
| 919 | 907 |
|
| 920 | 908 |
typedef struct |
| 921 | 909 |
{
|
| 922 |
uint32_t base; |
|
| 923 | 910 |
uint32_t actss; |
| 924 | 911 |
uint32_t ris; |
| 925 | 912 |
uint32_t im; |
| ... | ... | |
| 1013 | 1000 |
stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
| 1014 | 1001 |
|
| 1015 | 1002 |
/* TODO: Implement this. */ |
| 1016 |
offset -= s->base; |
|
| 1017 | 1003 |
if (offset >= 0x40 && offset < 0xc0) {
|
| 1018 | 1004 |
int n; |
| 1019 | 1005 |
n = (offset - 0x40) >> 5; |
| ... | ... | |
| 1062 | 1048 |
stellaris_adc_state *s = (stellaris_adc_state *)opaque; |
| 1063 | 1049 |
|
| 1064 | 1050 |
/* TODO: Implement this. */ |
| 1065 |
offset -= s->base; |
|
| 1066 | 1051 |
if (offset >= 0x40 && offset < 0xc0) {
|
| 1067 | 1052 |
int n; |
| 1068 | 1053 |
n = (offset - 0x40) >> 5; |
| ... | ... | |
| 1194 | 1179 |
qemu_irq *qi; |
| 1195 | 1180 |
|
| 1196 | 1181 |
s = (stellaris_adc_state *)qemu_mallocz(sizeof(stellaris_adc_state)); |
| 1197 |
s->base = base; |
|
| 1198 | 1182 |
s->irq = irq; |
| 1199 | 1183 |
|
| 1200 | 1184 |
iomemtype = cpu_register_io_memory(0, stellaris_adc_readfn, |
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