root / hw / sun4c_intctl.c @ 8e00128d
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1 | ee76f82e | blueswir1 | /*
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2 | ee76f82e | blueswir1 | * QEMU Sparc Sun4c interrupt controller emulation
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3 | ee76f82e | blueswir1 | *
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4 | ee76f82e | blueswir1 | * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
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5 | ee76f82e | blueswir1 | *
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6 | ee76f82e | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | ee76f82e | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
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8 | ee76f82e | blueswir1 | * in the Software without restriction, including without limitation the rights
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9 | ee76f82e | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | ee76f82e | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
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11 | ee76f82e | blueswir1 | * furnished to do so, subject to the following conditions:
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12 | ee76f82e | blueswir1 | *
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13 | ee76f82e | blueswir1 | * The above copyright notice and this permission notice shall be included in
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14 | ee76f82e | blueswir1 | * all copies or substantial portions of the Software.
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15 | ee76f82e | blueswir1 | *
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16 | ee76f82e | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | ee76f82e | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | ee76f82e | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | ee76f82e | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | ee76f82e | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | ee76f82e | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | ee76f82e | blueswir1 | * THE SOFTWARE.
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23 | ee76f82e | blueswir1 | */
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24 | e32cba29 | Blue Swirl | |
25 | ee76f82e | blueswir1 | #include "hw.h" |
26 | ee76f82e | blueswir1 | #include "sun4m.h" |
27 | 376253ec | aliguori | #include "monitor.h" |
28 | e32cba29 | Blue Swirl | #include "sysbus.h" |
29 | e32cba29 | Blue Swirl | |
30 | ee76f82e | blueswir1 | //#define DEBUG_IRQ_COUNT
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31 | ee76f82e | blueswir1 | //#define DEBUG_IRQ
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32 | ee76f82e | blueswir1 | |
33 | ee76f82e | blueswir1 | #ifdef DEBUG_IRQ
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34 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...) \
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35 | 001faf32 | Blue Swirl | do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0) |
36 | ee76f82e | blueswir1 | #else
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37 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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38 | ee76f82e | blueswir1 | #endif
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39 | ee76f82e | blueswir1 | |
40 | ee76f82e | blueswir1 | /*
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41 | ee76f82e | blueswir1 | * Registers of interrupt controller in sun4c.
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42 | ee76f82e | blueswir1 | *
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43 | ee76f82e | blueswir1 | */
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44 | ee76f82e | blueswir1 | |
45 | ee76f82e | blueswir1 | #define MAX_PILS 16 |
46 | ee76f82e | blueswir1 | |
47 | ee76f82e | blueswir1 | typedef struct Sun4c_INTCTLState { |
48 | e32cba29 | Blue Swirl | SysBusDevice busdev; |
49 | ee76f82e | blueswir1 | #ifdef DEBUG_IRQ_COUNT
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50 | ee76f82e | blueswir1 | uint64_t irq_count; |
51 | ee76f82e | blueswir1 | #endif
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52 | e32cba29 | Blue Swirl | qemu_irq cpu_irqs[MAX_PILS]; |
53 | ee76f82e | blueswir1 | const uint32_t *intbit_to_level;
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54 | ee76f82e | blueswir1 | uint32_t pil_out; |
55 | ee76f82e | blueswir1 | uint8_t reg; |
56 | ee76f82e | blueswir1 | uint8_t pending; |
57 | ee76f82e | blueswir1 | } Sun4c_INTCTLState; |
58 | ee76f82e | blueswir1 | |
59 | e64d7d59 | blueswir1 | #define INTCTL_SIZE 1 |
60 | ee76f82e | blueswir1 | |
61 | ee76f82e | blueswir1 | static void sun4c_check_interrupts(void *opaque); |
62 | ee76f82e | blueswir1 | |
63 | c227f099 | Anthony Liguori | static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr) |
64 | ee76f82e | blueswir1 | { |
65 | ee76f82e | blueswir1 | Sun4c_INTCTLState *s = opaque; |
66 | ee76f82e | blueswir1 | uint32_t ret; |
67 | ee76f82e | blueswir1 | |
68 | ee76f82e | blueswir1 | ret = s->reg; |
69 | ee76f82e | blueswir1 | DPRINTF("read reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
70 | ee76f82e | blueswir1 | |
71 | ee76f82e | blueswir1 | return ret;
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72 | ee76f82e | blueswir1 | } |
73 | ee76f82e | blueswir1 | |
74 | c227f099 | Anthony Liguori | static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr, |
75 | 77f193da | blueswir1 | uint32_t val) |
76 | ee76f82e | blueswir1 | { |
77 | ee76f82e | blueswir1 | Sun4c_INTCTLState *s = opaque; |
78 | ee76f82e | blueswir1 | |
79 | ee76f82e | blueswir1 | DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
80 | ee76f82e | blueswir1 | val &= 0xbf;
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81 | ee76f82e | blueswir1 | s->reg = val; |
82 | ee76f82e | blueswir1 | sun4c_check_interrupts(s); |
83 | ee76f82e | blueswir1 | } |
84 | ee76f82e | blueswir1 | |
85 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const sun4c_intctl_mem_read[3] = { |
86 | ee76f82e | blueswir1 | sun4c_intctl_mem_readb, |
87 | 7c560456 | blueswir1 | NULL,
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88 | 7c560456 | blueswir1 | NULL,
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89 | ee76f82e | blueswir1 | }; |
90 | ee76f82e | blueswir1 | |
91 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const sun4c_intctl_mem_write[3] = { |
92 | ee76f82e | blueswir1 | sun4c_intctl_mem_writeb, |
93 | 7c560456 | blueswir1 | NULL,
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94 | 7c560456 | blueswir1 | NULL,
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95 | ee76f82e | blueswir1 | }; |
96 | ee76f82e | blueswir1 | |
97 | 376253ec | aliguori | void sun4c_pic_info(Monitor *mon, void *opaque) |
98 | ee76f82e | blueswir1 | { |
99 | ee76f82e | blueswir1 | Sun4c_INTCTLState *s = opaque; |
100 | ee76f82e | blueswir1 | |
101 | 376253ec | aliguori | monitor_printf(mon, "master: pending 0x%2.2x, enabled 0x%2.2x\n",
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102 | 376253ec | aliguori | s->pending, s->reg); |
103 | ee76f82e | blueswir1 | } |
104 | ee76f82e | blueswir1 | |
105 | 376253ec | aliguori | void sun4c_irq_info(Monitor *mon, void *opaque) |
106 | ee76f82e | blueswir1 | { |
107 | ee76f82e | blueswir1 | #ifndef DEBUG_IRQ_COUNT
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108 | 376253ec | aliguori | monitor_printf(mon, "irq statistic code not compiled.\n");
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109 | ee76f82e | blueswir1 | #else
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110 | ee76f82e | blueswir1 | Sun4c_INTCTLState *s = opaque; |
111 | ee76f82e | blueswir1 | int64_t count; |
112 | ee76f82e | blueswir1 | |
113 | 376253ec | aliguori | monitor_printf(mon, "IRQ statistics:\n");
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114 | 0bf9e31a | Blue Swirl | count = s->irq_count; |
115 | ee76f82e | blueswir1 | if (count > 0) |
116 | 0bf9e31a | Blue Swirl | monitor_printf(mon, " %" PRId64 "\n", count); |
117 | ee76f82e | blueswir1 | #endif
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118 | ee76f82e | blueswir1 | } |
119 | ee76f82e | blueswir1 | |
120 | ee76f82e | blueswir1 | static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, }; |
121 | ee76f82e | blueswir1 | |
122 | ee76f82e | blueswir1 | static void sun4c_check_interrupts(void *opaque) |
123 | ee76f82e | blueswir1 | { |
124 | ee76f82e | blueswir1 | Sun4c_INTCTLState *s = opaque; |
125 | ee76f82e | blueswir1 | uint32_t pil_pending; |
126 | ee76f82e | blueswir1 | unsigned int i; |
127 | ee76f82e | blueswir1 | |
128 | ee76f82e | blueswir1 | pil_pending = 0;
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129 | ee76f82e | blueswir1 | if (s->pending && !(s->reg & 0x80000000)) { |
130 | ee76f82e | blueswir1 | for (i = 0; i < 8; i++) { |
131 | ee76f82e | blueswir1 | if (s->pending & (1 << i)) |
132 | ee76f82e | blueswir1 | pil_pending |= 1 << intbit_to_level[i];
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133 | ee76f82e | blueswir1 | } |
134 | ee76f82e | blueswir1 | } |
135 | ee76f82e | blueswir1 | |
136 | ee76f82e | blueswir1 | for (i = 0; i < MAX_PILS; i++) { |
137 | ee76f82e | blueswir1 | if (pil_pending & (1 << i)) { |
138 | ee76f82e | blueswir1 | if (!(s->pil_out & (1 << i))) |
139 | ee76f82e | blueswir1 | qemu_irq_raise(s->cpu_irqs[i]); |
140 | ee76f82e | blueswir1 | } else {
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141 | ee76f82e | blueswir1 | if (s->pil_out & (1 << i)) |
142 | ee76f82e | blueswir1 | qemu_irq_lower(s->cpu_irqs[i]); |
143 | ee76f82e | blueswir1 | } |
144 | ee76f82e | blueswir1 | } |
145 | ee76f82e | blueswir1 | s->pil_out = pil_pending; |
146 | ee76f82e | blueswir1 | } |
147 | ee76f82e | blueswir1 | |
148 | ee76f82e | blueswir1 | /*
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149 | ee76f82e | blueswir1 | * "irq" here is the bit number in the system interrupt register
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150 | ee76f82e | blueswir1 | */
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151 | ee76f82e | blueswir1 | static void sun4c_set_irq(void *opaque, int irq, int level) |
152 | ee76f82e | blueswir1 | { |
153 | ee76f82e | blueswir1 | Sun4c_INTCTLState *s = opaque; |
154 | ee76f82e | blueswir1 | uint32_t mask = 1 << irq;
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155 | ee76f82e | blueswir1 | uint32_t pil = intbit_to_level[irq]; |
156 | ee76f82e | blueswir1 | |
157 | ee76f82e | blueswir1 | DPRINTF("Set irq %d -> pil %d level %d\n", irq, pil,
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158 | ee76f82e | blueswir1 | level); |
159 | ee76f82e | blueswir1 | if (pil > 0) { |
160 | ee76f82e | blueswir1 | if (level) {
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161 | ee76f82e | blueswir1 | #ifdef DEBUG_IRQ_COUNT
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162 | 0bf9e31a | Blue Swirl | s->irq_count++; |
163 | ee76f82e | blueswir1 | #endif
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164 | ee76f82e | blueswir1 | s->pending |= mask; |
165 | ee76f82e | blueswir1 | } else {
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166 | ee76f82e | blueswir1 | s->pending &= ~mask; |
167 | ee76f82e | blueswir1 | } |
168 | ee76f82e | blueswir1 | sun4c_check_interrupts(s); |
169 | ee76f82e | blueswir1 | } |
170 | ee76f82e | blueswir1 | } |
171 | ee76f82e | blueswir1 | |
172 | 9902571d | Blue Swirl | static const VMStateDescription vmstate_sun4c_intctl = { |
173 | 9902571d | Blue Swirl | .name ="sun4c_intctl",
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174 | 9902571d | Blue Swirl | .version_id = 1,
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175 | 9902571d | Blue Swirl | .minimum_version_id = 1,
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176 | 9902571d | Blue Swirl | .minimum_version_id_old = 1,
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177 | 9902571d | Blue Swirl | .fields = (VMStateField []) { |
178 | 9902571d | Blue Swirl | VMSTATE_UINT8(reg, Sun4c_INTCTLState), |
179 | 9902571d | Blue Swirl | VMSTATE_UINT8(pending, Sun4c_INTCTLState), |
180 | 9902571d | Blue Swirl | VMSTATE_END_OF_LIST() |
181 | 9902571d | Blue Swirl | } |
182 | 9902571d | Blue Swirl | }; |
183 | ee76f82e | blueswir1 | |
184 | 9a2070d3 | Blue Swirl | static void sun4c_intctl_reset(DeviceState *d) |
185 | ee76f82e | blueswir1 | { |
186 | 9a2070d3 | Blue Swirl | Sun4c_INTCTLState *s = container_of(d, Sun4c_INTCTLState, busdev.qdev); |
187 | ee76f82e | blueswir1 | |
188 | ee76f82e | blueswir1 | s->reg = 1;
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189 | ee76f82e | blueswir1 | s->pending = 0;
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190 | ee76f82e | blueswir1 | } |
191 | ee76f82e | blueswir1 | |
192 | 81a322d4 | Gerd Hoffmann | static int sun4c_intctl_init1(SysBusDevice *dev) |
193 | e32cba29 | Blue Swirl | { |
194 | e32cba29 | Blue Swirl | Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev); |
195 | e32cba29 | Blue Swirl | int io_memory;
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196 | e32cba29 | Blue Swirl | unsigned int i; |
197 | ee76f82e | blueswir1 | |
198 | e32cba29 | Blue Swirl | io_memory = cpu_register_io_memory(sun4c_intctl_mem_read, |
199 | e32cba29 | Blue Swirl | sun4c_intctl_mem_write, s); |
200 | e32cba29 | Blue Swirl | sysbus_init_mmio(dev, INTCTL_SIZE, io_memory); |
201 | e32cba29 | Blue Swirl | qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
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202 | e32cba29 | Blue Swirl | |
203 | e32cba29 | Blue Swirl | for (i = 0; i < MAX_PILS; i++) { |
204 | e32cba29 | Blue Swirl | sysbus_init_irq(dev, &s->cpu_irqs[i]); |
205 | e32cba29 | Blue Swirl | } |
206 | 9a2070d3 | Blue Swirl | |
207 | 81a322d4 | Gerd Hoffmann | return 0; |
208 | ee76f82e | blueswir1 | } |
209 | e32cba29 | Blue Swirl | |
210 | e32cba29 | Blue Swirl | static SysBusDeviceInfo sun4c_intctl_info = {
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211 | e32cba29 | Blue Swirl | .init = sun4c_intctl_init1, |
212 | e32cba29 | Blue Swirl | .qdev.name = "sun4c_intctl",
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213 | e32cba29 | Blue Swirl | .qdev.size = sizeof(Sun4c_INTCTLState),
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214 | 9a2070d3 | Blue Swirl | .qdev.vmsd = &vmstate_sun4c_intctl, |
215 | 9a2070d3 | Blue Swirl | .qdev.reset = sun4c_intctl_reset, |
216 | e32cba29 | Blue Swirl | }; |
217 | e32cba29 | Blue Swirl | |
218 | e32cba29 | Blue Swirl | static void sun4c_intctl_register_devices(void) |
219 | e32cba29 | Blue Swirl | { |
220 | e32cba29 | Blue Swirl | sysbus_register_withprop(&sun4c_intctl_info); |
221 | e32cba29 | Blue Swirl | } |
222 | e32cba29 | Blue Swirl | |
223 | e32cba29 | Blue Swirl | device_init(sun4c_intctl_register_devices) |