root / hw / ppc4xx_pci.c @ 8e9f18b6
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1 | 825bb581 | aurel32 | /*
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2 | 825bb581 | aurel32 | * This program is free software; you can redistribute it and/or modify
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3 | 825bb581 | aurel32 | * it under the terms of the GNU General Public License, version 2, as
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4 | 825bb581 | aurel32 | * published by the Free Software Foundation.
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5 | 825bb581 | aurel32 | *
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6 | 825bb581 | aurel32 | * This program is distributed in the hope that it will be useful,
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7 | 825bb581 | aurel32 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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8 | 825bb581 | aurel32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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9 | 825bb581 | aurel32 | * GNU General Public License for more details.
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10 | 825bb581 | aurel32 | *
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11 | 825bb581 | aurel32 | * You should have received a copy of the GNU General Public License
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12 | 8167ee88 | Blue Swirl | * along with this program; if not, see <http://www.gnu.org/licenses/>.
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13 | 825bb581 | aurel32 | *
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14 | 825bb581 | aurel32 | * Copyright IBM Corp. 2008
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15 | 825bb581 | aurel32 | *
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16 | 825bb581 | aurel32 | * Authors: Hollis Blanchard <hollisb@us.ibm.com>
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17 | 825bb581 | aurel32 | */
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18 | 825bb581 | aurel32 | |
19 | 825bb581 | aurel32 | /* This file implements emulation of the 32-bit PCI controller found in some
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20 | 825bb581 | aurel32 | * 4xx SoCs, such as the 440EP. */
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21 | 825bb581 | aurel32 | |
22 | 825bb581 | aurel32 | #include "hw.h" |
23 | 0c34a5d7 | aurel32 | #include "ppc.h" |
24 | 0c34a5d7 | aurel32 | #include "ppc4xx.h" |
25 | 825bb581 | aurel32 | #include "pci.h" |
26 | 825bb581 | aurel32 | #include "pci_host.h" |
27 | 1e39101c | Avi Kivity | #include "exec-memory.h" |
28 | 825bb581 | aurel32 | |
29 | 825bb581 | aurel32 | #undef DEBUG
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30 | 825bb581 | aurel32 | #ifdef DEBUG
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31 | 825bb581 | aurel32 | #define DPRINTF(fmt, ...) do { printf(fmt, ## __VA_ARGS__); } while (0) |
32 | 825bb581 | aurel32 | #else
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33 | 001faf32 | Blue Swirl | #define DPRINTF(fmt, ...)
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34 | 825bb581 | aurel32 | #endif /* DEBUG */ |
35 | 825bb581 | aurel32 | |
36 | 825bb581 | aurel32 | struct PCIMasterMap {
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37 | 825bb581 | aurel32 | uint32_t la; |
38 | 825bb581 | aurel32 | uint32_t ma; |
39 | 825bb581 | aurel32 | uint32_t pcila; |
40 | 825bb581 | aurel32 | uint32_t pciha; |
41 | 825bb581 | aurel32 | }; |
42 | 825bb581 | aurel32 | |
43 | 825bb581 | aurel32 | struct PCITargetMap {
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44 | 825bb581 | aurel32 | uint32_t ms; |
45 | 825bb581 | aurel32 | uint32_t la; |
46 | 825bb581 | aurel32 | }; |
47 | 825bb581 | aurel32 | |
48 | 42c281a2 | Andreas Färber | #define PPC4xx_PCI_HOST_BRIDGE(obj) \
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49 | 42c281a2 | Andreas Färber | OBJECT_CHECK(PPC4xxPCIState, (obj), TYPE_PPC4xx_PCI_HOST_BRIDGE) |
50 | 42c281a2 | Andreas Färber | |
51 | 825bb581 | aurel32 | #define PPC4xx_PCI_NR_PMMS 3 |
52 | 825bb581 | aurel32 | #define PPC4xx_PCI_NR_PTMS 2 |
53 | 825bb581 | aurel32 | |
54 | 825bb581 | aurel32 | struct PPC4xxPCIState {
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55 | 67c332fd | Andreas Färber | PCIHostState parent_obj; |
56 | 623f7c21 | Alexander Graf | |
57 | 825bb581 | aurel32 | struct PCIMasterMap pmm[PPC4xx_PCI_NR_PMMS];
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58 | 825bb581 | aurel32 | struct PCITargetMap ptm[PPC4xx_PCI_NR_PTMS];
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59 | 623f7c21 | Alexander Graf | qemu_irq irq[4];
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60 | 825bb581 | aurel32 | |
61 | 623f7c21 | Alexander Graf | MemoryRegion container; |
62 | 623f7c21 | Alexander Graf | MemoryRegion iomem; |
63 | 825bb581 | aurel32 | }; |
64 | 825bb581 | aurel32 | typedef struct PPC4xxPCIState PPC4xxPCIState; |
65 | 825bb581 | aurel32 | |
66 | 825bb581 | aurel32 | #define PCIC0_CFGADDR 0x0 |
67 | 825bb581 | aurel32 | #define PCIC0_CFGDATA 0x4 |
68 | 825bb581 | aurel32 | |
69 | 825bb581 | aurel32 | /* PLB Memory Map (PMM) registers specify which PLB addresses are translated to
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70 | 825bb581 | aurel32 | * PCI accesses. */
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71 | 825bb581 | aurel32 | #define PCIL0_PMM0LA 0x0 |
72 | 825bb581 | aurel32 | #define PCIL0_PMM0MA 0x4 |
73 | 825bb581 | aurel32 | #define PCIL0_PMM0PCILA 0x8 |
74 | 825bb581 | aurel32 | #define PCIL0_PMM0PCIHA 0xc |
75 | 825bb581 | aurel32 | #define PCIL0_PMM1LA 0x10 |
76 | 825bb581 | aurel32 | #define PCIL0_PMM1MA 0x14 |
77 | 825bb581 | aurel32 | #define PCIL0_PMM1PCILA 0x18 |
78 | 825bb581 | aurel32 | #define PCIL0_PMM1PCIHA 0x1c |
79 | 825bb581 | aurel32 | #define PCIL0_PMM2LA 0x20 |
80 | 825bb581 | aurel32 | #define PCIL0_PMM2MA 0x24 |
81 | 825bb581 | aurel32 | #define PCIL0_PMM2PCILA 0x28 |
82 | 825bb581 | aurel32 | #define PCIL0_PMM2PCIHA 0x2c |
83 | 825bb581 | aurel32 | |
84 | 825bb581 | aurel32 | /* PCI Target Map (PTM) registers specify which PCI addresses are translated to
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85 | 825bb581 | aurel32 | * PLB accesses. */
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86 | 825bb581 | aurel32 | #define PCIL0_PTM1MS 0x30 |
87 | 825bb581 | aurel32 | #define PCIL0_PTM1LA 0x34 |
88 | 825bb581 | aurel32 | #define PCIL0_PTM2MS 0x38 |
89 | 825bb581 | aurel32 | #define PCIL0_PTM2LA 0x3c |
90 | 623f7c21 | Alexander Graf | #define PCI_REG_BASE 0x800000 |
91 | 825bb581 | aurel32 | #define PCI_REG_SIZE 0x40 |
92 | 825bb581 | aurel32 | |
93 | 623f7c21 | Alexander Graf | #define PCI_ALL_SIZE (PCI_REG_BASE + PCI_REG_SIZE)
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94 | 825bb581 | aurel32 | |
95 | da726e5e | Avi Kivity | static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr, |
96 | da726e5e | Avi Kivity | unsigned size)
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97 | 825bb581 | aurel32 | { |
98 | 825bb581 | aurel32 | PPC4xxPCIState *ppc4xx_pci = opaque; |
99 | 67c332fd | Andreas Färber | PCIHostState *phb = PCI_HOST_BRIDGE(ppc4xx_pci); |
100 | 825bb581 | aurel32 | |
101 | 67c332fd | Andreas Färber | return phb->config_reg;
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102 | 825bb581 | aurel32 | } |
103 | 825bb581 | aurel32 | |
104 | da726e5e | Avi Kivity | static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr, |
105 | da726e5e | Avi Kivity | uint64_t value, unsigned size)
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106 | 825bb581 | aurel32 | { |
107 | 825bb581 | aurel32 | PPC4xxPCIState *ppc4xx_pci = opaque; |
108 | 67c332fd | Andreas Färber | PCIHostState *phb = PCI_HOST_BRIDGE(ppc4xx_pci); |
109 | 825bb581 | aurel32 | |
110 | 67c332fd | Andreas Färber | phb->config_reg = value & ~0x3;
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111 | 825bb581 | aurel32 | } |
112 | 825bb581 | aurel32 | |
113 | da726e5e | Avi Kivity | static const MemoryRegionOps pci4xx_cfgaddr_ops = { |
114 | da726e5e | Avi Kivity | .read = pci4xx_cfgaddr_read, |
115 | da726e5e | Avi Kivity | .write = pci4xx_cfgaddr_write, |
116 | da726e5e | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
117 | 825bb581 | aurel32 | }; |
118 | 825bb581 | aurel32 | |
119 | c227f099 | Anthony Liguori | static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset, |
120 | da726e5e | Avi Kivity | uint64_t value, unsigned size)
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121 | 825bb581 | aurel32 | { |
122 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
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123 | 825bb581 | aurel32 | |
124 | 825bb581 | aurel32 | /* We ignore all target attempts at PCI configuration, effectively
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125 | 825bb581 | aurel32 | * assuming a bidirectional 1:1 mapping of PLB and PCI space. */
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126 | 825bb581 | aurel32 | |
127 | 825bb581 | aurel32 | switch (offset) {
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128 | 825bb581 | aurel32 | case PCIL0_PMM0LA:
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129 | 825bb581 | aurel32 | pci->pmm[0].la = value;
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130 | 825bb581 | aurel32 | break;
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131 | 825bb581 | aurel32 | case PCIL0_PMM0MA:
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132 | 825bb581 | aurel32 | pci->pmm[0].ma = value;
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133 | 825bb581 | aurel32 | break;
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134 | 825bb581 | aurel32 | case PCIL0_PMM0PCIHA:
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135 | 825bb581 | aurel32 | pci->pmm[0].pciha = value;
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136 | 825bb581 | aurel32 | break;
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137 | 825bb581 | aurel32 | case PCIL0_PMM0PCILA:
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138 | 825bb581 | aurel32 | pci->pmm[0].pcila = value;
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139 | 825bb581 | aurel32 | break;
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140 | 825bb581 | aurel32 | |
141 | 825bb581 | aurel32 | case PCIL0_PMM1LA:
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142 | 825bb581 | aurel32 | pci->pmm[1].la = value;
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143 | 825bb581 | aurel32 | break;
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144 | 825bb581 | aurel32 | case PCIL0_PMM1MA:
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145 | 825bb581 | aurel32 | pci->pmm[1].ma = value;
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146 | 825bb581 | aurel32 | break;
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147 | 825bb581 | aurel32 | case PCIL0_PMM1PCIHA:
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148 | 825bb581 | aurel32 | pci->pmm[1].pciha = value;
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149 | 825bb581 | aurel32 | break;
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150 | 825bb581 | aurel32 | case PCIL0_PMM1PCILA:
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151 | 825bb581 | aurel32 | pci->pmm[1].pcila = value;
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152 | 825bb581 | aurel32 | break;
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153 | 825bb581 | aurel32 | |
154 | 825bb581 | aurel32 | case PCIL0_PMM2LA:
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155 | 825bb581 | aurel32 | pci->pmm[2].la = value;
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156 | 825bb581 | aurel32 | break;
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157 | 825bb581 | aurel32 | case PCIL0_PMM2MA:
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158 | 825bb581 | aurel32 | pci->pmm[2].ma = value;
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159 | 825bb581 | aurel32 | break;
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160 | 825bb581 | aurel32 | case PCIL0_PMM2PCIHA:
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161 | 825bb581 | aurel32 | pci->pmm[2].pciha = value;
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162 | 825bb581 | aurel32 | break;
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163 | 825bb581 | aurel32 | case PCIL0_PMM2PCILA:
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164 | 825bb581 | aurel32 | pci->pmm[2].pcila = value;
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165 | 825bb581 | aurel32 | break;
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166 | 825bb581 | aurel32 | |
167 | 825bb581 | aurel32 | case PCIL0_PTM1MS:
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168 | 825bb581 | aurel32 | pci->ptm[0].ms = value;
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169 | 825bb581 | aurel32 | break;
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170 | 825bb581 | aurel32 | case PCIL0_PTM1LA:
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171 | 825bb581 | aurel32 | pci->ptm[0].la = value;
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172 | 825bb581 | aurel32 | break;
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173 | 825bb581 | aurel32 | case PCIL0_PTM2MS:
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174 | 825bb581 | aurel32 | pci->ptm[1].ms = value;
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175 | 825bb581 | aurel32 | break;
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176 | 825bb581 | aurel32 | case PCIL0_PTM2LA:
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177 | 825bb581 | aurel32 | pci->ptm[1].la = value;
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178 | 825bb581 | aurel32 | break;
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179 | 825bb581 | aurel32 | |
180 | 825bb581 | aurel32 | default:
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181 | 825bb581 | aurel32 | printf("%s: unhandled PCI internal register 0x%lx\n", __func__,
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182 | 825bb581 | aurel32 | (unsigned long)offset); |
183 | 825bb581 | aurel32 | break;
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184 | 825bb581 | aurel32 | } |
185 | 825bb581 | aurel32 | } |
186 | 825bb581 | aurel32 | |
187 | da726e5e | Avi Kivity | static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset, |
188 | da726e5e | Avi Kivity | unsigned size)
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189 | 825bb581 | aurel32 | { |
190 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
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191 | 825bb581 | aurel32 | uint32_t value; |
192 | 825bb581 | aurel32 | |
193 | 825bb581 | aurel32 | switch (offset) {
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194 | 825bb581 | aurel32 | case PCIL0_PMM0LA:
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195 | 825bb581 | aurel32 | value = pci->pmm[0].la;
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196 | 825bb581 | aurel32 | break;
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197 | 825bb581 | aurel32 | case PCIL0_PMM0MA:
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198 | 825bb581 | aurel32 | value = pci->pmm[0].ma;
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199 | 825bb581 | aurel32 | break;
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200 | 825bb581 | aurel32 | case PCIL0_PMM0PCIHA:
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201 | 825bb581 | aurel32 | value = pci->pmm[0].pciha;
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202 | 825bb581 | aurel32 | break;
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203 | 825bb581 | aurel32 | case PCIL0_PMM0PCILA:
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204 | 825bb581 | aurel32 | value = pci->pmm[0].pcila;
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205 | 825bb581 | aurel32 | break;
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206 | 825bb581 | aurel32 | |
207 | 825bb581 | aurel32 | case PCIL0_PMM1LA:
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208 | 825bb581 | aurel32 | value = pci->pmm[1].la;
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209 | 825bb581 | aurel32 | break;
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210 | 825bb581 | aurel32 | case PCIL0_PMM1MA:
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211 | 825bb581 | aurel32 | value = pci->pmm[1].ma;
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212 | 825bb581 | aurel32 | break;
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213 | 825bb581 | aurel32 | case PCIL0_PMM1PCIHA:
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214 | 825bb581 | aurel32 | value = pci->pmm[1].pciha;
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215 | 825bb581 | aurel32 | break;
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216 | 825bb581 | aurel32 | case PCIL0_PMM1PCILA:
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217 | 825bb581 | aurel32 | value = pci->pmm[1].pcila;
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218 | 825bb581 | aurel32 | break;
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219 | 825bb581 | aurel32 | |
220 | 825bb581 | aurel32 | case PCIL0_PMM2LA:
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221 | 825bb581 | aurel32 | value = pci->pmm[2].la;
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222 | 825bb581 | aurel32 | break;
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223 | 825bb581 | aurel32 | case PCIL0_PMM2MA:
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224 | 825bb581 | aurel32 | value = pci->pmm[2].ma;
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225 | 825bb581 | aurel32 | break;
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226 | 825bb581 | aurel32 | case PCIL0_PMM2PCIHA:
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227 | 825bb581 | aurel32 | value = pci->pmm[2].pciha;
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228 | 825bb581 | aurel32 | break;
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229 | 825bb581 | aurel32 | case PCIL0_PMM2PCILA:
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230 | 825bb581 | aurel32 | value = pci->pmm[2].pcila;
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231 | 825bb581 | aurel32 | break;
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232 | 825bb581 | aurel32 | |
233 | 825bb581 | aurel32 | case PCIL0_PTM1MS:
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234 | 825bb581 | aurel32 | value = pci->ptm[0].ms;
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235 | 825bb581 | aurel32 | break;
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236 | 825bb581 | aurel32 | case PCIL0_PTM1LA:
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237 | 825bb581 | aurel32 | value = pci->ptm[0].la;
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238 | 825bb581 | aurel32 | break;
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239 | 825bb581 | aurel32 | case PCIL0_PTM2MS:
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240 | 825bb581 | aurel32 | value = pci->ptm[1].ms;
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241 | 825bb581 | aurel32 | break;
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242 | 825bb581 | aurel32 | case PCIL0_PTM2LA:
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243 | 825bb581 | aurel32 | value = pci->ptm[1].la;
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244 | 825bb581 | aurel32 | break;
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245 | 825bb581 | aurel32 | |
246 | 825bb581 | aurel32 | default:
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247 | 825bb581 | aurel32 | printf("%s: invalid PCI internal register 0x%lx\n", __func__,
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248 | 825bb581 | aurel32 | (unsigned long)offset); |
249 | 825bb581 | aurel32 | value = 0;
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250 | 825bb581 | aurel32 | } |
251 | 825bb581 | aurel32 | |
252 | 825bb581 | aurel32 | return value;
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253 | 825bb581 | aurel32 | } |
254 | 825bb581 | aurel32 | |
255 | da726e5e | Avi Kivity | static const MemoryRegionOps pci_reg_ops = { |
256 | da726e5e | Avi Kivity | .read = ppc4xx_pci_reg_read4, |
257 | da726e5e | Avi Kivity | .write = ppc4xx_pci_reg_write4, |
258 | da726e5e | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
259 | 825bb581 | aurel32 | }; |
260 | 825bb581 | aurel32 | |
261 | 825bb581 | aurel32 | static void ppc4xx_pci_reset(void *opaque) |
262 | 825bb581 | aurel32 | { |
263 | 825bb581 | aurel32 | struct PPC4xxPCIState *pci = opaque;
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264 | 825bb581 | aurel32 | |
265 | 825bb581 | aurel32 | memset(pci->pmm, 0, sizeof(pci->pmm)); |
266 | 825bb581 | aurel32 | memset(pci->ptm, 0, sizeof(pci->ptm)); |
267 | 825bb581 | aurel32 | } |
268 | 825bb581 | aurel32 | |
269 | 825bb581 | aurel32 | /* On Bamboo, all pins from each slot are tied to a single board IRQ. This
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270 | 825bb581 | aurel32 | * may need further refactoring for other boards. */
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271 | 825bb581 | aurel32 | static int ppc4xx_pci_map_irq(PCIDevice *pci_dev, int irq_num) |
272 | 825bb581 | aurel32 | { |
273 | 825bb581 | aurel32 | int slot = pci_dev->devfn >> 3; |
274 | 825bb581 | aurel32 | |
275 | 825bb581 | aurel32 | DPRINTF("%s: devfn %x irq %d -> %d\n", __func__,
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276 | 825bb581 | aurel32 | pci_dev->devfn, irq_num, slot); |
277 | 825bb581 | aurel32 | |
278 | 825bb581 | aurel32 | return slot - 1; |
279 | 825bb581 | aurel32 | } |
280 | 825bb581 | aurel32 | |
281 | 5d4e84c8 | Juan Quintela | static void ppc4xx_pci_set_irq(void *opaque, int irq_num, int level) |
282 | 825bb581 | aurel32 | { |
283 | 5d4e84c8 | Juan Quintela | qemu_irq *pci_irqs = opaque; |
284 | 5d4e84c8 | Juan Quintela | |
285 | 825bb581 | aurel32 | DPRINTF("%s: PCI irq %d\n", __func__, irq_num);
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286 | d49bc1fb | Alexander Graf | if (irq_num < 0) { |
287 | d49bc1fb | Alexander Graf | fprintf(stderr, "%s: PCI irq %d\n", __func__, irq_num);
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288 | d49bc1fb | Alexander Graf | return;
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289 | d49bc1fb | Alexander Graf | } |
290 | 825bb581 | aurel32 | qemu_set_irq(pci_irqs[irq_num], level); |
291 | 825bb581 | aurel32 | } |
292 | 825bb581 | aurel32 | |
293 | b605f222 | Juan Quintela | static const VMStateDescription vmstate_pci_master_map = { |
294 | b605f222 | Juan Quintela | .name = "pci_master_map",
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295 | b605f222 | Juan Quintela | .version_id = 0,
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296 | b605f222 | Juan Quintela | .minimum_version_id = 0,
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297 | b605f222 | Juan Quintela | .minimum_version_id_old = 0,
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298 | b605f222 | Juan Quintela | .fields = (VMStateField[]) { |
299 | b605f222 | Juan Quintela | VMSTATE_UINT32(la, struct PCIMasterMap),
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300 | b605f222 | Juan Quintela | VMSTATE_UINT32(ma, struct PCIMasterMap),
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301 | b605f222 | Juan Quintela | VMSTATE_UINT32(pcila, struct PCIMasterMap),
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302 | b605f222 | Juan Quintela | VMSTATE_UINT32(pciha, struct PCIMasterMap),
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303 | b605f222 | Juan Quintela | VMSTATE_END_OF_LIST() |
304 | 825bb581 | aurel32 | } |
305 | b605f222 | Juan Quintela | }; |
306 | 825bb581 | aurel32 | |
307 | b605f222 | Juan Quintela | static const VMStateDescription vmstate_pci_target_map = { |
308 | b605f222 | Juan Quintela | .name = "pci_target_map",
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309 | b605f222 | Juan Quintela | .version_id = 0,
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310 | b605f222 | Juan Quintela | .minimum_version_id = 0,
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311 | b605f222 | Juan Quintela | .minimum_version_id_old = 0,
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312 | b605f222 | Juan Quintela | .fields = (VMStateField[]) { |
313 | b605f222 | Juan Quintela | VMSTATE_UINT32(ms, struct PCITargetMap),
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314 | b605f222 | Juan Quintela | VMSTATE_UINT32(la, struct PCITargetMap),
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315 | b605f222 | Juan Quintela | VMSTATE_END_OF_LIST() |
316 | 825bb581 | aurel32 | } |
317 | b605f222 | Juan Quintela | }; |
318 | 825bb581 | aurel32 | |
319 | b605f222 | Juan Quintela | static const VMStateDescription vmstate_ppc4xx_pci = { |
320 | b605f222 | Juan Quintela | .name = "ppc4xx_pci",
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321 | b605f222 | Juan Quintela | .version_id = 1,
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322 | b605f222 | Juan Quintela | .minimum_version_id = 1,
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323 | b605f222 | Juan Quintela | .minimum_version_id_old = 1,
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324 | b605f222 | Juan Quintela | .fields = (VMStateField[]) { |
325 | b605f222 | Juan Quintela | VMSTATE_STRUCT_ARRAY(pmm, PPC4xxPCIState, PPC4xx_PCI_NR_PMMS, 1,
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326 | b605f222 | Juan Quintela | vmstate_pci_master_map, |
327 | b605f222 | Juan Quintela | struct PCIMasterMap),
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328 | b605f222 | Juan Quintela | VMSTATE_STRUCT_ARRAY(ptm, PPC4xxPCIState, PPC4xx_PCI_NR_PTMS, 1,
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329 | b605f222 | Juan Quintela | vmstate_pci_target_map, |
330 | b605f222 | Juan Quintela | struct PCITargetMap),
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331 | b605f222 | Juan Quintela | VMSTATE_END_OF_LIST() |
332 | 825bb581 | aurel32 | } |
333 | b605f222 | Juan Quintela | }; |
334 | 825bb581 | aurel32 | |
335 | 825bb581 | aurel32 | /* XXX Interrupt acknowledge cycles not supported. */
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336 | 623f7c21 | Alexander Graf | static int ppc4xx_pcihost_initfn(SysBusDevice *dev) |
337 | 623f7c21 | Alexander Graf | { |
338 | 623f7c21 | Alexander Graf | PPC4xxPCIState *s; |
339 | 623f7c21 | Alexander Graf | PCIHostState *h; |
340 | 623f7c21 | Alexander Graf | PCIBus *b; |
341 | 623f7c21 | Alexander Graf | int i;
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342 | 623f7c21 | Alexander Graf | |
343 | 8558d942 | Andreas Färber | h = PCI_HOST_BRIDGE(dev); |
344 | 42c281a2 | Andreas Färber | s = PPC4xx_PCI_HOST_BRIDGE(dev); |
345 | 623f7c21 | Alexander Graf | |
346 | 623f7c21 | Alexander Graf | for (i = 0; i < ARRAY_SIZE(s->irq); i++) { |
347 | 623f7c21 | Alexander Graf | sysbus_init_irq(dev, &s->irq[i]); |
348 | 623f7c21 | Alexander Graf | } |
349 | 623f7c21 | Alexander Graf | |
350 | 42c281a2 | Andreas Färber | b = pci_register_bus(DEVICE(dev), NULL, ppc4xx_pci_set_irq,
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351 | 623f7c21 | Alexander Graf | ppc4xx_pci_map_irq, s->irq, get_system_memory(), |
352 | 623f7c21 | Alexander Graf | get_system_io(), 0, 4); |
353 | 42c281a2 | Andreas Färber | h->bus = b; |
354 | 623f7c21 | Alexander Graf | |
355 | 623f7c21 | Alexander Graf | pci_create_simple(b, 0, "ppc4xx-host-bridge"); |
356 | 623f7c21 | Alexander Graf | |
357 | 623f7c21 | Alexander Graf | /* XXX split into 2 memory regions, one for config space, one for regs */
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358 | 623f7c21 | Alexander Graf | memory_region_init(&s->container, "pci-container", PCI_ALL_SIZE);
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359 | 623f7c21 | Alexander Graf | memory_region_init_io(&h->conf_mem, &pci_host_conf_le_ops, h, |
360 | 623f7c21 | Alexander Graf | "pci-conf-idx", 4); |
361 | 623f7c21 | Alexander Graf | memory_region_init_io(&h->data_mem, &pci_host_data_le_ops, h, |
362 | 623f7c21 | Alexander Graf | "pci-conf-data", 4); |
363 | 623f7c21 | Alexander Graf | memory_region_init_io(&s->iomem, &pci_reg_ops, s, |
364 | 623f7c21 | Alexander Graf | "pci.reg", PCI_REG_SIZE);
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365 | 623f7c21 | Alexander Graf | memory_region_add_subregion(&s->container, PCIC0_CFGADDR, &h->conf_mem); |
366 | 623f7c21 | Alexander Graf | memory_region_add_subregion(&s->container, PCIC0_CFGDATA, &h->data_mem); |
367 | 623f7c21 | Alexander Graf | memory_region_add_subregion(&s->container, PCI_REG_BASE, &s->iomem); |
368 | 623f7c21 | Alexander Graf | sysbus_init_mmio(dev, &s->container); |
369 | 623f7c21 | Alexander Graf | qemu_register_reset(ppc4xx_pci_reset, s); |
370 | 623f7c21 | Alexander Graf | |
371 | 623f7c21 | Alexander Graf | return 0; |
372 | 623f7c21 | Alexander Graf | } |
373 | 623f7c21 | Alexander Graf | |
374 | 40021f08 | Anthony Liguori | static void ppc4xx_host_bridge_class_init(ObjectClass *klass, void *data) |
375 | 40021f08 | Anthony Liguori | { |
376 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
377 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
378 | 40021f08 | Anthony Liguori | |
379 | 39bffca2 | Anthony Liguori | dc->desc = "Host bridge";
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380 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_IBM; |
381 | 40021f08 | Anthony Liguori | k->device_id = PCI_DEVICE_ID_IBM_440GX; |
382 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_BRIDGE_OTHER; |
383 | 40021f08 | Anthony Liguori | } |
384 | 40021f08 | Anthony Liguori | |
385 | 4240abff | Andreas Färber | static const TypeInfo ppc4xx_host_bridge_info = { |
386 | 39bffca2 | Anthony Liguori | .name = "ppc4xx-host-bridge",
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387 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
388 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PCIDevice),
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389 | 39bffca2 | Anthony Liguori | .class_init = ppc4xx_host_bridge_class_init, |
390 | 623f7c21 | Alexander Graf | }; |
391 | 623f7c21 | Alexander Graf | |
392 | 999e12bb | Anthony Liguori | static void ppc4xx_pcihost_class_init(ObjectClass *klass, void *data) |
393 | 999e12bb | Anthony Liguori | { |
394 | 999e12bb | Anthony Liguori | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
395 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
396 | 999e12bb | Anthony Liguori | |
397 | 999e12bb | Anthony Liguori | k->init = ppc4xx_pcihost_initfn; |
398 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_ppc4xx_pci; |
399 | 999e12bb | Anthony Liguori | } |
400 | 999e12bb | Anthony Liguori | |
401 | 4240abff | Andreas Färber | static const TypeInfo ppc4xx_pcihost_info = { |
402 | 42c281a2 | Andreas Färber | .name = TYPE_PPC4xx_PCI_HOST_BRIDGE, |
403 | 8558d942 | Andreas Färber | .parent = TYPE_PCI_HOST_BRIDGE, |
404 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(PPC4xxPCIState),
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405 | 39bffca2 | Anthony Liguori | .class_init = ppc4xx_pcihost_class_init, |
406 | 623f7c21 | Alexander Graf | }; |
407 | 623f7c21 | Alexander Graf | |
408 | 83f7d43a | Andreas Färber | static void ppc4xx_pci_register_types(void) |
409 | 825bb581 | aurel32 | { |
410 | 39bffca2 | Anthony Liguori | type_register_static(&ppc4xx_pcihost_info); |
411 | 39bffca2 | Anthony Liguori | type_register_static(&ppc4xx_host_bridge_info); |
412 | 825bb581 | aurel32 | } |
413 | 83f7d43a | Andreas Färber | |
414 | 83f7d43a | Andreas Färber | type_init(ppc4xx_pci_register_types) |