root / hw / lan9118.c @ 8ec68b06
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1 | 2a424990 | Paul Brook | /*
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2 | 2a424990 | Paul Brook | * SMSC LAN9118 Ethernet interface emulation
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3 | 2a424990 | Paul Brook | *
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4 | 2a424990 | Paul Brook | * Copyright (c) 2009 CodeSourcery, LLC.
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5 | 2a424990 | Paul Brook | * Written by Paul Brook
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6 | 2a424990 | Paul Brook | *
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7 | 2a424990 | Paul Brook | * This code is licenced under the GNU GPL v2
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8 | 2a424990 | Paul Brook | */
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9 | 2a424990 | Paul Brook | |
10 | 2a424990 | Paul Brook | #include "sysbus.h" |
11 | 2a424990 | Paul Brook | #include "net.h" |
12 | 2a424990 | Paul Brook | #include "devices.h" |
13 | 2a424990 | Paul Brook | /* For crc32 */
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14 | 2a424990 | Paul Brook | #include <zlib.h> |
15 | 2a424990 | Paul Brook | |
16 | 2a424990 | Paul Brook | //#define DEBUG_LAN9118
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17 | 2a424990 | Paul Brook | |
18 | 2a424990 | Paul Brook | #ifdef DEBUG_LAN9118
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19 | 2a424990 | Paul Brook | #define DPRINTF(fmt, ...) \
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20 | 2a424990 | Paul Brook | do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0) |
21 | 2a424990 | Paul Brook | #define BADF(fmt, ...) \
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22 | 2a424990 | Paul Brook | do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0) |
23 | 2a424990 | Paul Brook | #else
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24 | 2a424990 | Paul Brook | #define DPRINTF(fmt, ...) do {} while(0) |
25 | 2a424990 | Paul Brook | #define BADF(fmt, ...) \
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26 | 2a424990 | Paul Brook | do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0) |
27 | 2a424990 | Paul Brook | #endif
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28 | 2a424990 | Paul Brook | |
29 | 2a424990 | Paul Brook | #define CSR_ID_REV 0x50 |
30 | 2a424990 | Paul Brook | #define CSR_IRQ_CFG 0x54 |
31 | 2a424990 | Paul Brook | #define CSR_INT_STS 0x58 |
32 | 2a424990 | Paul Brook | #define CSR_INT_EN 0x5c |
33 | 2a424990 | Paul Brook | #define CSR_BYTE_TEST 0x64 |
34 | 2a424990 | Paul Brook | #define CSR_FIFO_INT 0x68 |
35 | 2a424990 | Paul Brook | #define CSR_RX_CFG 0x6c |
36 | 2a424990 | Paul Brook | #define CSR_TX_CFG 0x70 |
37 | 2a424990 | Paul Brook | #define CSR_HW_CFG 0x74 |
38 | 2a424990 | Paul Brook | #define CSR_RX_DP_CTRL 0x78 |
39 | 2a424990 | Paul Brook | #define CSR_RX_FIFO_INF 0x7c |
40 | 2a424990 | Paul Brook | #define CSR_TX_FIFO_INF 0x80 |
41 | 2a424990 | Paul Brook | #define CSR_PMT_CTRL 0x84 |
42 | 2a424990 | Paul Brook | #define CSR_GPIO_CFG 0x88 |
43 | 209bf965 | Paul Brook | #define CSR_GPT_CFG 0x8c |
44 | 209bf965 | Paul Brook | #define CSR_GPT_CNT 0x90 |
45 | 2a424990 | Paul Brook | #define CSR_WORD_SWAP 0x98 |
46 | 2a424990 | Paul Brook | #define CSR_FREE_RUN 0x9c |
47 | 2a424990 | Paul Brook | #define CSR_RX_DROP 0xa0 |
48 | 2a424990 | Paul Brook | #define CSR_MAC_CSR_CMD 0xa4 |
49 | 2a424990 | Paul Brook | #define CSR_MAC_CSR_DATA 0xa8 |
50 | 2a424990 | Paul Brook | #define CSR_AFC_CFG 0xac |
51 | 2a424990 | Paul Brook | #define CSR_E2P_CMD 0xb0 |
52 | 2a424990 | Paul Brook | #define CSR_E2P_DATA 0xb4 |
53 | 2a424990 | Paul Brook | |
54 | 2a424990 | Paul Brook | /* IRQ_CFG */
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55 | 209bf965 | Paul Brook | #define IRQ_INT 0x00001000 |
56 | 2a424990 | Paul Brook | #define IRQ_EN 0x00000100 |
57 | 2a424990 | Paul Brook | #define IRQ_POL 0x00000010 |
58 | 2a424990 | Paul Brook | #define IRQ_TYPE 0x00000001 |
59 | 2a424990 | Paul Brook | |
60 | 2a424990 | Paul Brook | /* INT_STS/INT_EN */
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61 | 2a424990 | Paul Brook | #define SW_INT 0x80000000 |
62 | 2a424990 | Paul Brook | #define TXSTOP_INT 0x02000000 |
63 | 2a424990 | Paul Brook | #define RXSTOP_INT 0x01000000 |
64 | 2a424990 | Paul Brook | #define RXDFH_INT 0x00800000 |
65 | 2a424990 | Paul Brook | #define TX_IOC_INT 0x00200000 |
66 | 2a424990 | Paul Brook | #define RXD_INT 0x00100000 |
67 | 2a424990 | Paul Brook | #define GPT_INT 0x00080000 |
68 | 2a424990 | Paul Brook | #define PHY_INT 0x00040000 |
69 | 2a424990 | Paul Brook | #define PME_INT 0x00020000 |
70 | 2a424990 | Paul Brook | #define TXSO_INT 0x00010000 |
71 | 2a424990 | Paul Brook | #define RWT_INT 0x00008000 |
72 | 2a424990 | Paul Brook | #define RXE_INT 0x00004000 |
73 | 2a424990 | Paul Brook | #define TXE_INT 0x00002000 |
74 | 2a424990 | Paul Brook | #define TDFU_INT 0x00000800 |
75 | 2a424990 | Paul Brook | #define TDFO_INT 0x00000400 |
76 | 2a424990 | Paul Brook | #define TDFA_INT 0x00000200 |
77 | 2a424990 | Paul Brook | #define TSFF_INT 0x00000100 |
78 | 2a424990 | Paul Brook | #define TSFL_INT 0x00000080 |
79 | 2a424990 | Paul Brook | #define RXDF_INT 0x00000040 |
80 | 2a424990 | Paul Brook | #define RDFL_INT 0x00000020 |
81 | 2a424990 | Paul Brook | #define RSFF_INT 0x00000010 |
82 | 2a424990 | Paul Brook | #define RSFL_INT 0x00000008 |
83 | 2a424990 | Paul Brook | #define GPIO2_INT 0x00000004 |
84 | 2a424990 | Paul Brook | #define GPIO1_INT 0x00000002 |
85 | 2a424990 | Paul Brook | #define GPIO0_INT 0x00000001 |
86 | 2a424990 | Paul Brook | #define RESERVED_INT 0x7c001000 |
87 | 2a424990 | Paul Brook | |
88 | 2a424990 | Paul Brook | #define MAC_CR 1 |
89 | 2a424990 | Paul Brook | #define MAC_ADDRH 2 |
90 | 2a424990 | Paul Brook | #define MAC_ADDRL 3 |
91 | 2a424990 | Paul Brook | #define MAC_HASHH 4 |
92 | 2a424990 | Paul Brook | #define MAC_HASHL 5 |
93 | 2a424990 | Paul Brook | #define MAC_MII_ACC 6 |
94 | 2a424990 | Paul Brook | #define MAC_MII_DATA 7 |
95 | 2a424990 | Paul Brook | #define MAC_FLOW 8 |
96 | 2a424990 | Paul Brook | #define MAC_VLAN1 9 /* TODO */ |
97 | 2a424990 | Paul Brook | #define MAC_VLAN2 10 /* TODO */ |
98 | 2a424990 | Paul Brook | #define MAC_WUFF 11 /* TODO */ |
99 | 2a424990 | Paul Brook | #define MAC_WUCSR 12 /* TODO */ |
100 | 2a424990 | Paul Brook | |
101 | 2a424990 | Paul Brook | #define MAC_CR_RXALL 0x80000000 |
102 | 2a424990 | Paul Brook | #define MAC_CR_RCVOWN 0x00800000 |
103 | 2a424990 | Paul Brook | #define MAC_CR_LOOPBK 0x00200000 |
104 | 2a424990 | Paul Brook | #define MAC_CR_FDPX 0x00100000 |
105 | 2a424990 | Paul Brook | #define MAC_CR_MCPAS 0x00080000 |
106 | 2a424990 | Paul Brook | #define MAC_CR_PRMS 0x00040000 |
107 | 2a424990 | Paul Brook | #define MAC_CR_INVFILT 0x00020000 |
108 | 2a424990 | Paul Brook | #define MAC_CR_PASSBAD 0x00010000 |
109 | 2a424990 | Paul Brook | #define MAC_CR_HO 0x00008000 |
110 | 2a424990 | Paul Brook | #define MAC_CR_HPFILT 0x00002000 |
111 | 2a424990 | Paul Brook | #define MAC_CR_LCOLL 0x00001000 |
112 | 2a424990 | Paul Brook | #define MAC_CR_BCAST 0x00000800 |
113 | 2a424990 | Paul Brook | #define MAC_CR_DISRTY 0x00000400 |
114 | 2a424990 | Paul Brook | #define MAC_CR_PADSTR 0x00000100 |
115 | 2a424990 | Paul Brook | #define MAC_CR_BOLMT 0x000000c0 |
116 | 2a424990 | Paul Brook | #define MAC_CR_DFCHK 0x00000020 |
117 | 2a424990 | Paul Brook | #define MAC_CR_TXEN 0x00000008 |
118 | 2a424990 | Paul Brook | #define MAC_CR_RXEN 0x00000004 |
119 | 2a424990 | Paul Brook | #define MAC_CR_RESERVED 0x7f404213 |
120 | 2a424990 | Paul Brook | |
121 | 209bf965 | Paul Brook | #define PHY_INT_ENERGYON 0x80 |
122 | 209bf965 | Paul Brook | #define PHY_INT_AUTONEG_COMPLETE 0x40 |
123 | 209bf965 | Paul Brook | #define PHY_INT_FAULT 0x20 |
124 | 209bf965 | Paul Brook | #define PHY_INT_DOWN 0x10 |
125 | 209bf965 | Paul Brook | #define PHY_INT_AUTONEG_LP 0x08 |
126 | 209bf965 | Paul Brook | #define PHY_INT_PARFAULT 0x04 |
127 | 209bf965 | Paul Brook | #define PHY_INT_AUTONEG_PAGE 0x02 |
128 | 209bf965 | Paul Brook | |
129 | 209bf965 | Paul Brook | #define GPT_TIMER_EN 0x20000000 |
130 | 209bf965 | Paul Brook | |
131 | 2a424990 | Paul Brook | enum tx_state {
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132 | 2a424990 | Paul Brook | TX_IDLE, |
133 | 2a424990 | Paul Brook | TX_B, |
134 | 2a424990 | Paul Brook | TX_DATA |
135 | 2a424990 | Paul Brook | }; |
136 | 2a424990 | Paul Brook | |
137 | 2a424990 | Paul Brook | typedef struct { |
138 | 2a424990 | Paul Brook | enum tx_state state;
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139 | 2a424990 | Paul Brook | uint32_t cmd_a; |
140 | 2a424990 | Paul Brook | uint32_t cmd_b; |
141 | 2a424990 | Paul Brook | int buffer_size;
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142 | 2a424990 | Paul Brook | int offset;
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143 | 2a424990 | Paul Brook | int pad;
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144 | 2a424990 | Paul Brook | int fifo_used;
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145 | 2a424990 | Paul Brook | int len;
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146 | 2a424990 | Paul Brook | uint8_t data[2048];
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147 | 2a424990 | Paul Brook | } LAN9118Packet; |
148 | 2a424990 | Paul Brook | |
149 | 2a424990 | Paul Brook | typedef struct { |
150 | 2a424990 | Paul Brook | SysBusDevice busdev; |
151 | 83b9f88c | Mark McLoughlin | NICState *nic; |
152 | 2a424990 | Paul Brook | NICConf conf; |
153 | 2a424990 | Paul Brook | qemu_irq irq; |
154 | 2a424990 | Paul Brook | int mmio_index;
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155 | 209bf965 | Paul Brook | ptimer_state *timer; |
156 | 2a424990 | Paul Brook | |
157 | 2a424990 | Paul Brook | uint32_t irq_cfg; |
158 | 2a424990 | Paul Brook | uint32_t int_sts; |
159 | 2a424990 | Paul Brook | uint32_t int_en; |
160 | 2a424990 | Paul Brook | uint32_t fifo_int; |
161 | 2a424990 | Paul Brook | uint32_t rx_cfg; |
162 | 2a424990 | Paul Brook | uint32_t tx_cfg; |
163 | 2a424990 | Paul Brook | uint32_t hw_cfg; |
164 | 2a424990 | Paul Brook | uint32_t pmt_ctrl; |
165 | 2a424990 | Paul Brook | uint32_t gpio_cfg; |
166 | 209bf965 | Paul Brook | uint32_t gpt_cfg; |
167 | 2a424990 | Paul Brook | uint32_t word_swap; |
168 | 2a424990 | Paul Brook | uint32_t free_timer_start; |
169 | 2a424990 | Paul Brook | uint32_t mac_cmd; |
170 | 2a424990 | Paul Brook | uint32_t mac_data; |
171 | 2a424990 | Paul Brook | uint32_t afc_cfg; |
172 | 2a424990 | Paul Brook | uint32_t e2p_cmd; |
173 | 2a424990 | Paul Brook | uint32_t e2p_data; |
174 | 2a424990 | Paul Brook | |
175 | 2a424990 | Paul Brook | uint32_t mac_cr; |
176 | 2a424990 | Paul Brook | uint32_t mac_hashh; |
177 | 2a424990 | Paul Brook | uint32_t mac_hashl; |
178 | 2a424990 | Paul Brook | uint32_t mac_mii_acc; |
179 | 2a424990 | Paul Brook | uint32_t mac_mii_data; |
180 | 2a424990 | Paul Brook | uint32_t mac_flow; |
181 | 2a424990 | Paul Brook | |
182 | 2a424990 | Paul Brook | uint32_t phy_status; |
183 | 2a424990 | Paul Brook | uint32_t phy_control; |
184 | 2a424990 | Paul Brook | uint32_t phy_advertise; |
185 | 209bf965 | Paul Brook | uint32_t phy_int; |
186 | 209bf965 | Paul Brook | uint32_t phy_int_mask; |
187 | 2a424990 | Paul Brook | |
188 | 2a424990 | Paul Brook | int eeprom_writable;
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189 | 2a424990 | Paul Brook | uint8_t eeprom[8];
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190 | 2a424990 | Paul Brook | |
191 | 2a424990 | Paul Brook | int tx_fifo_size;
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192 | 2a424990 | Paul Brook | LAN9118Packet *txp; |
193 | 2a424990 | Paul Brook | LAN9118Packet tx_packet; |
194 | 2a424990 | Paul Brook | |
195 | 2a424990 | Paul Brook | int tx_status_fifo_used;
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196 | 2a424990 | Paul Brook | int tx_status_fifo_head;
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197 | 2a424990 | Paul Brook | uint32_t tx_status_fifo[512];
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198 | 2a424990 | Paul Brook | |
199 | 2a424990 | Paul Brook | int rx_status_fifo_size;
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200 | 2a424990 | Paul Brook | int rx_status_fifo_used;
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201 | 2a424990 | Paul Brook | int rx_status_fifo_head;
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202 | 2a424990 | Paul Brook | uint32_t rx_status_fifo[896];
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203 | 2a424990 | Paul Brook | int rx_fifo_size;
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204 | 2a424990 | Paul Brook | int rx_fifo_used;
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205 | 2a424990 | Paul Brook | int rx_fifo_head;
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206 | 2a424990 | Paul Brook | uint32_t rx_fifo[3360];
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207 | 2a424990 | Paul Brook | int rx_packet_size_head;
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208 | 2a424990 | Paul Brook | int rx_packet_size_tail;
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209 | 2a424990 | Paul Brook | int rx_packet_size[1024]; |
210 | 2a424990 | Paul Brook | |
211 | 2a424990 | Paul Brook | int rxp_offset;
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212 | 2a424990 | Paul Brook | int rxp_size;
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213 | 2a424990 | Paul Brook | int rxp_pad;
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214 | 2a424990 | Paul Brook | } lan9118_state; |
215 | 2a424990 | Paul Brook | |
216 | 2a424990 | Paul Brook | static void lan9118_update(lan9118_state *s) |
217 | 2a424990 | Paul Brook | { |
218 | 2a424990 | Paul Brook | int level;
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219 | 2a424990 | Paul Brook | |
220 | 2a424990 | Paul Brook | /* TODO: Implement FIFO level IRQs. */
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221 | 2a424990 | Paul Brook | level = (s->int_sts & s->int_en) != 0;
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222 | 209bf965 | Paul Brook | if (level) {
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223 | 209bf965 | Paul Brook | s->irq_cfg |= IRQ_INT; |
224 | 209bf965 | Paul Brook | } else {
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225 | 209bf965 | Paul Brook | s->irq_cfg &= ~IRQ_INT; |
226 | 209bf965 | Paul Brook | } |
227 | 2a424990 | Paul Brook | if ((s->irq_cfg & IRQ_EN) == 0) { |
228 | 2a424990 | Paul Brook | level = 0;
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229 | 2a424990 | Paul Brook | } |
230 | 2a424990 | Paul Brook | qemu_set_irq(s->irq, level); |
231 | 2a424990 | Paul Brook | } |
232 | 2a424990 | Paul Brook | |
233 | 2a424990 | Paul Brook | static void lan9118_mac_changed(lan9118_state *s) |
234 | 2a424990 | Paul Brook | { |
235 | 83b9f88c | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
236 | 2a424990 | Paul Brook | } |
237 | 2a424990 | Paul Brook | |
238 | 2a424990 | Paul Brook | static void lan9118_reload_eeprom(lan9118_state *s) |
239 | 2a424990 | Paul Brook | { |
240 | 2a424990 | Paul Brook | int i;
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241 | 2a424990 | Paul Brook | if (s->eeprom[0] != 0xa5) { |
242 | 2a424990 | Paul Brook | s->e2p_cmd &= ~0x10;
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243 | 2a424990 | Paul Brook | DPRINTF("MACADDR load failed\n");
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244 | 2a424990 | Paul Brook | return;
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245 | 2a424990 | Paul Brook | } |
246 | 2a424990 | Paul Brook | for (i = 0; i < 6; i++) { |
247 | 2a424990 | Paul Brook | s->conf.macaddr.a[i] = s->eeprom[i + 1];
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248 | 2a424990 | Paul Brook | } |
249 | 2a424990 | Paul Brook | s->e2p_cmd |= 0x10;
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250 | 2a424990 | Paul Brook | DPRINTF("MACADDR loaded from eeprom\n");
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251 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
252 | 2a424990 | Paul Brook | } |
253 | 2a424990 | Paul Brook | |
254 | 209bf965 | Paul Brook | static void phy_update_irq(lan9118_state *s) |
255 | 209bf965 | Paul Brook | { |
256 | 209bf965 | Paul Brook | if (s->phy_int & s->phy_int_mask) {
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257 | 209bf965 | Paul Brook | s->int_sts |= PHY_INT; |
258 | 209bf965 | Paul Brook | } else {
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259 | 209bf965 | Paul Brook | s->int_sts &= ~PHY_INT; |
260 | 209bf965 | Paul Brook | } |
261 | 209bf965 | Paul Brook | lan9118_update(s); |
262 | 209bf965 | Paul Brook | } |
263 | 209bf965 | Paul Brook | |
264 | 2a424990 | Paul Brook | static void phy_update_link(lan9118_state *s) |
265 | 2a424990 | Paul Brook | { |
266 | 2a424990 | Paul Brook | /* Autonegotiation status mirrors link status. */
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267 | 83b9f88c | Mark McLoughlin | if (s->nic->nc.link_down) {
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268 | 2a424990 | Paul Brook | s->phy_status &= ~0x0024;
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269 | 209bf965 | Paul Brook | s->phy_int |= PHY_INT_DOWN; |
270 | 2a424990 | Paul Brook | } else {
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271 | 2a424990 | Paul Brook | s->phy_status |= 0x0024;
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272 | 209bf965 | Paul Brook | s->phy_int |= PHY_INT_ENERGYON; |
273 | 209bf965 | Paul Brook | s->phy_int |= PHY_INT_AUTONEG_COMPLETE; |
274 | 2a424990 | Paul Brook | } |
275 | 209bf965 | Paul Brook | phy_update_irq(s); |
276 | 2a424990 | Paul Brook | } |
277 | 2a424990 | Paul Brook | |
278 | 83b9f88c | Mark McLoughlin | static void lan9118_set_link(VLANClientState *nc) |
279 | 2a424990 | Paul Brook | { |
280 | 83b9f88c | Mark McLoughlin | phy_update_link(DO_UPCAST(NICState, nc, nc)->opaque); |
281 | 2a424990 | Paul Brook | } |
282 | 2a424990 | Paul Brook | |
283 | 2a424990 | Paul Brook | static void phy_reset(lan9118_state *s) |
284 | 2a424990 | Paul Brook | { |
285 | 209bf965 | Paul Brook | s->phy_status = 0x7809;
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286 | 2a424990 | Paul Brook | s->phy_control = 0x3000;
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287 | 2a424990 | Paul Brook | s->phy_advertise = 0x01e1;
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288 | 209bf965 | Paul Brook | s->phy_int_mask = 0;
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289 | 209bf965 | Paul Brook | s->phy_int = 0;
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290 | 2a424990 | Paul Brook | phy_update_link(s); |
291 | 2a424990 | Paul Brook | } |
292 | 2a424990 | Paul Brook | |
293 | 2a424990 | Paul Brook | static void lan9118_reset(DeviceState *d) |
294 | 2a424990 | Paul Brook | { |
295 | 2a424990 | Paul Brook | lan9118_state *s = FROM_SYSBUS(lan9118_state, sysbus_from_qdev(d)); |
296 | 2a424990 | Paul Brook | |
297 | 2a424990 | Paul Brook | s->irq_cfg &= ~(IRQ_TYPE | IRQ_POL); |
298 | 2a424990 | Paul Brook | s->int_sts = 0;
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299 | 2a424990 | Paul Brook | s->int_en = 0;
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300 | 2a424990 | Paul Brook | s->fifo_int = 0x48000000;
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301 | 2a424990 | Paul Brook | s->rx_cfg = 0;
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302 | 2a424990 | Paul Brook | s->tx_cfg = 0;
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303 | 2a424990 | Paul Brook | s->hw_cfg = 0x00050000;
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304 | 2a424990 | Paul Brook | s->pmt_ctrl &= 0x45;
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305 | 2a424990 | Paul Brook | s->gpio_cfg = 0;
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306 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
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307 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
308 | 2a424990 | Paul Brook | s->txp->cmd_a = 0xffffffffu;
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309 | 2a424990 | Paul Brook | s->txp->cmd_b = 0xffffffffu;
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310 | 2a424990 | Paul Brook | s->txp->len = 0;
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311 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
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312 | 2a424990 | Paul Brook | s->tx_fifo_size = 4608;
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313 | 2a424990 | Paul Brook | s->tx_status_fifo_used = 0;
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314 | 2a424990 | Paul Brook | s->rx_status_fifo_size = 704;
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315 | 2a424990 | Paul Brook | s->rx_fifo_size = 2640;
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316 | 2a424990 | Paul Brook | s->rx_fifo_used = 0;
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317 | 2a424990 | Paul Brook | s->rx_status_fifo_size = 176;
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318 | 2a424990 | Paul Brook | s->rx_status_fifo_used = 0;
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319 | 2a424990 | Paul Brook | s->rxp_offset = 0;
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320 | 2a424990 | Paul Brook | s->rxp_size = 0;
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321 | 2a424990 | Paul Brook | s->rxp_pad = 0;
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322 | 2a424990 | Paul Brook | s->rx_packet_size_tail = s->rx_packet_size_head; |
323 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
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324 | 2a424990 | Paul Brook | s->mac_cmd = 0;
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325 | 2a424990 | Paul Brook | s->mac_data = 0;
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326 | 2a424990 | Paul Brook | s->afc_cfg = 0;
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327 | 2a424990 | Paul Brook | s->e2p_cmd = 0;
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328 | 2a424990 | Paul Brook | s->e2p_data = 0;
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329 | 2a424990 | Paul Brook | s->free_timer_start = qemu_get_clock(vm_clock) / 40;
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330 | 2a424990 | Paul Brook | |
331 | 209bf965 | Paul Brook | ptimer_stop(s->timer); |
332 | 209bf965 | Paul Brook | ptimer_set_count(s->timer, 0xffff);
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333 | 209bf965 | Paul Brook | s->gpt_cfg = 0xffff;
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334 | 209bf965 | Paul Brook | |
335 | 2a424990 | Paul Brook | s->mac_cr = MAC_CR_PRMS; |
336 | 2a424990 | Paul Brook | s->mac_hashh = 0;
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337 | 2a424990 | Paul Brook | s->mac_hashl = 0;
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338 | 2a424990 | Paul Brook | s->mac_mii_acc = 0;
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339 | 2a424990 | Paul Brook | s->mac_mii_data = 0;
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340 | 2a424990 | Paul Brook | s->mac_flow = 0;
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341 | 2a424990 | Paul Brook | |
342 | 2a424990 | Paul Brook | phy_reset(s); |
343 | 2a424990 | Paul Brook | |
344 | 2a424990 | Paul Brook | s->eeprom_writable = 0;
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345 | 2a424990 | Paul Brook | lan9118_reload_eeprom(s); |
346 | 2a424990 | Paul Brook | } |
347 | 2a424990 | Paul Brook | |
348 | 83b9f88c | Mark McLoughlin | static int lan9118_can_receive(VLANClientState *nc) |
349 | 2a424990 | Paul Brook | { |
350 | 2a424990 | Paul Brook | return 1; |
351 | 2a424990 | Paul Brook | } |
352 | 2a424990 | Paul Brook | |
353 | 2a424990 | Paul Brook | static void rx_fifo_push(lan9118_state *s, uint32_t val) |
354 | 2a424990 | Paul Brook | { |
355 | 2a424990 | Paul Brook | int fifo_pos;
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356 | 2a424990 | Paul Brook | fifo_pos = s->rx_fifo_head + s->rx_fifo_used; |
357 | 2a424990 | Paul Brook | if (fifo_pos >= s->rx_fifo_size)
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358 | 2a424990 | Paul Brook | fifo_pos -= s->rx_fifo_size; |
359 | 2a424990 | Paul Brook | s->rx_fifo[fifo_pos] = val; |
360 | 2a424990 | Paul Brook | s->rx_fifo_used++; |
361 | 2a424990 | Paul Brook | } |
362 | 2a424990 | Paul Brook | |
363 | 2a424990 | Paul Brook | /* Return nonzero if the packet is accepted by the filter. */
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364 | 2a424990 | Paul Brook | static int lan9118_filter(lan9118_state *s, const uint8_t *addr) |
365 | 2a424990 | Paul Brook | { |
366 | 2a424990 | Paul Brook | int multicast;
|
367 | 2a424990 | Paul Brook | uint32_t hash; |
368 | 2a424990 | Paul Brook | |
369 | 2a424990 | Paul Brook | if (s->mac_cr & MAC_CR_PRMS) {
|
370 | 2a424990 | Paul Brook | return 1; |
371 | 2a424990 | Paul Brook | } |
372 | 2a424990 | Paul Brook | if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff && |
373 | 2a424990 | Paul Brook | addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) { |
374 | 2a424990 | Paul Brook | return (s->mac_cr & MAC_CR_BCAST) == 0; |
375 | 2a424990 | Paul Brook | } |
376 | 2a424990 | Paul Brook | |
377 | 2a424990 | Paul Brook | multicast = addr[0] & 1; |
378 | 2a424990 | Paul Brook | if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
|
379 | 2a424990 | Paul Brook | return 1; |
380 | 2a424990 | Paul Brook | } |
381 | 2a424990 | Paul Brook | if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0 |
382 | 2a424990 | Paul Brook | : (s->mac_cr & MAC_CR_HO) == 0) {
|
383 | 2a424990 | Paul Brook | /* Exact matching. */
|
384 | 2a424990 | Paul Brook | hash = memcmp(addr, s->conf.macaddr.a, 6);
|
385 | 2a424990 | Paul Brook | if (s->mac_cr & MAC_CR_INVFILT) {
|
386 | 2a424990 | Paul Brook | return hash != 0; |
387 | 2a424990 | Paul Brook | } else {
|
388 | 2a424990 | Paul Brook | return hash == 0; |
389 | 2a424990 | Paul Brook | } |
390 | 2a424990 | Paul Brook | } else {
|
391 | 2a424990 | Paul Brook | /* Hash matching */
|
392 | 2a424990 | Paul Brook | hash = (crc32(~0, addr, 6) >> 26); |
393 | 2a424990 | Paul Brook | if (hash & 0x20) { |
394 | 2a424990 | Paul Brook | return (s->mac_hashh >> (hash & 0x1f)) & 1; |
395 | 2a424990 | Paul Brook | } else {
|
396 | 2a424990 | Paul Brook | return (s->mac_hashl >> (hash & 0x1f)) & 1; |
397 | 2a424990 | Paul Brook | } |
398 | 2a424990 | Paul Brook | } |
399 | 2a424990 | Paul Brook | } |
400 | 2a424990 | Paul Brook | |
401 | 83b9f88c | Mark McLoughlin | static ssize_t lan9118_receive(VLANClientState *nc, const uint8_t *buf, |
402 | 2a424990 | Paul Brook | size_t size) |
403 | 2a424990 | Paul Brook | { |
404 | 83b9f88c | Mark McLoughlin | lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
405 | 2a424990 | Paul Brook | int fifo_len;
|
406 | 2a424990 | Paul Brook | int offset;
|
407 | 2a424990 | Paul Brook | int src_pos;
|
408 | 2a424990 | Paul Brook | int n;
|
409 | 2a424990 | Paul Brook | int filter;
|
410 | 2a424990 | Paul Brook | uint32_t val; |
411 | 2a424990 | Paul Brook | uint32_t crc; |
412 | 2a424990 | Paul Brook | uint32_t status; |
413 | 2a424990 | Paul Brook | |
414 | 2a424990 | Paul Brook | if ((s->mac_cr & MAC_CR_RXEN) == 0) { |
415 | 2a424990 | Paul Brook | return -1; |
416 | 2a424990 | Paul Brook | } |
417 | 2a424990 | Paul Brook | |
418 | 2a424990 | Paul Brook | if (size >= 2048 || size < 14) { |
419 | 2a424990 | Paul Brook | return -1; |
420 | 2a424990 | Paul Brook | } |
421 | 2a424990 | Paul Brook | |
422 | 2a424990 | Paul Brook | /* TODO: Implement FIFO overflow notification. */
|
423 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
|
424 | 2a424990 | Paul Brook | return -1; |
425 | 2a424990 | Paul Brook | } |
426 | 2a424990 | Paul Brook | |
427 | 2a424990 | Paul Brook | filter = lan9118_filter(s, buf); |
428 | 2a424990 | Paul Brook | if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) { |
429 | 2a424990 | Paul Brook | return size;
|
430 | 2a424990 | Paul Brook | } |
431 | 2a424990 | Paul Brook | |
432 | 2a424990 | Paul Brook | offset = (s->rx_cfg >> 8) & 0x1f; |
433 | 2a424990 | Paul Brook | n = offset & 3;
|
434 | 2a424990 | Paul Brook | fifo_len = (size + n + 3) >> 2; |
435 | 2a424990 | Paul Brook | /* Add a word for the CRC. */
|
436 | 2a424990 | Paul Brook | fifo_len++; |
437 | 2a424990 | Paul Brook | if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
|
438 | 2a424990 | Paul Brook | return -1; |
439 | 2a424990 | Paul Brook | } |
440 | 2a424990 | Paul Brook | |
441 | 2a424990 | Paul Brook | DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
|
442 | 2a424990 | Paul Brook | (int)size, fifo_len, filter ? "pass" : "fail"); |
443 | 2a424990 | Paul Brook | val = 0;
|
444 | 2a424990 | Paul Brook | crc = bswap32(crc32(~0, buf, size));
|
445 | 2a424990 | Paul Brook | for (src_pos = 0; src_pos < size; src_pos++) { |
446 | 2a424990 | Paul Brook | val = (val >> 8) | ((uint32_t)buf[src_pos] << 24); |
447 | 2a424990 | Paul Brook | n++; |
448 | 2a424990 | Paul Brook | if (n == 4) { |
449 | 2a424990 | Paul Brook | n = 0;
|
450 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
451 | 2a424990 | Paul Brook | val = 0;
|
452 | 2a424990 | Paul Brook | } |
453 | 2a424990 | Paul Brook | } |
454 | 2a424990 | Paul Brook | if (n) {
|
455 | 2a424990 | Paul Brook | val >>= ((4 - n) * 8); |
456 | 2a424990 | Paul Brook | val |= crc << (n * 8);
|
457 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
458 | 2a424990 | Paul Brook | val = crc >> ((4 - n) * 8); |
459 | 2a424990 | Paul Brook | rx_fifo_push(s, val); |
460 | 2a424990 | Paul Brook | } else {
|
461 | 2a424990 | Paul Brook | rx_fifo_push(s, crc); |
462 | 2a424990 | Paul Brook | } |
463 | 2a424990 | Paul Brook | n = s->rx_status_fifo_head + s->rx_status_fifo_used; |
464 | 2a424990 | Paul Brook | if (n >= s->rx_status_fifo_size) {
|
465 | 2a424990 | Paul Brook | n -= s->rx_status_fifo_size; |
466 | 2a424990 | Paul Brook | } |
467 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_tail] = fifo_len; |
468 | 2a424990 | Paul Brook | s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023; |
469 | 2a424990 | Paul Brook | s->rx_status_fifo_used++; |
470 | 2a424990 | Paul Brook | |
471 | 2a424990 | Paul Brook | status = (size + 4) << 16; |
472 | 2a424990 | Paul Brook | if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff && |
473 | 2a424990 | Paul Brook | buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) { |
474 | 2a424990 | Paul Brook | status |= 0x00002000;
|
475 | 2a424990 | Paul Brook | } else if (buf[0] & 1) { |
476 | 2a424990 | Paul Brook | status |= 0x00000400;
|
477 | 2a424990 | Paul Brook | } |
478 | 2a424990 | Paul Brook | if (!filter) {
|
479 | 2a424990 | Paul Brook | status |= 0x40000000;
|
480 | 2a424990 | Paul Brook | } |
481 | 2a424990 | Paul Brook | s->rx_status_fifo[n] = status; |
482 | 2a424990 | Paul Brook | |
483 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) { |
484 | 2a424990 | Paul Brook | s->int_sts |= RSFL_INT; |
485 | 2a424990 | Paul Brook | } |
486 | 2a424990 | Paul Brook | lan9118_update(s); |
487 | 2a424990 | Paul Brook | |
488 | 2a424990 | Paul Brook | return size;
|
489 | 2a424990 | Paul Brook | } |
490 | 2a424990 | Paul Brook | |
491 | 2a424990 | Paul Brook | static uint32_t rx_fifo_pop(lan9118_state *s)
|
492 | 2a424990 | Paul Brook | { |
493 | 2a424990 | Paul Brook | int n;
|
494 | 2a424990 | Paul Brook | uint32_t val; |
495 | 2a424990 | Paul Brook | |
496 | 2a424990 | Paul Brook | if (s->rxp_size == 0 && s->rxp_pad == 0) { |
497 | 2a424990 | Paul Brook | s->rxp_size = s->rx_packet_size[s->rx_packet_size_head]; |
498 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
499 | 2a424990 | Paul Brook | if (s->rxp_size != 0) { |
500 | 2a424990 | Paul Brook | s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023; |
501 | 2a424990 | Paul Brook | s->rxp_offset = (s->rx_cfg >> 10) & 7; |
502 | 2a424990 | Paul Brook | n = s->rxp_offset + s->rxp_size; |
503 | 2a424990 | Paul Brook | switch (s->rx_cfg >> 30) { |
504 | 2a424990 | Paul Brook | case 1: |
505 | 2a424990 | Paul Brook | n = (-n) & 3;
|
506 | 2a424990 | Paul Brook | break;
|
507 | 2a424990 | Paul Brook | case 2: |
508 | 2a424990 | Paul Brook | n = (-n) & 7;
|
509 | 2a424990 | Paul Brook | break;
|
510 | 2a424990 | Paul Brook | default:
|
511 | 2a424990 | Paul Brook | n = 0;
|
512 | 2a424990 | Paul Brook | break;
|
513 | 2a424990 | Paul Brook | } |
514 | 2a424990 | Paul Brook | s->rxp_pad = n; |
515 | 2a424990 | Paul Brook | DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
|
516 | 2a424990 | Paul Brook | s->rxp_size, s->rxp_offset, s->rxp_pad); |
517 | 2a424990 | Paul Brook | } |
518 | 2a424990 | Paul Brook | } |
519 | 2a424990 | Paul Brook | if (s->rxp_offset > 0) { |
520 | 2a424990 | Paul Brook | s->rxp_offset--; |
521 | 2a424990 | Paul Brook | val = 0;
|
522 | 2a424990 | Paul Brook | } else if (s->rxp_size > 0) { |
523 | 2a424990 | Paul Brook | s->rxp_size--; |
524 | 2a424990 | Paul Brook | val = s->rx_fifo[s->rx_fifo_head++]; |
525 | 2a424990 | Paul Brook | if (s->rx_fifo_head >= s->rx_fifo_size) {
|
526 | 2a424990 | Paul Brook | s->rx_fifo_head -= s->rx_fifo_size; |
527 | 2a424990 | Paul Brook | } |
528 | 2a424990 | Paul Brook | s->rx_fifo_used--; |
529 | 2a424990 | Paul Brook | } else if (s->rxp_pad > 0) { |
530 | 2a424990 | Paul Brook | s->rxp_pad--; |
531 | 2a424990 | Paul Brook | val = 0;
|
532 | 2a424990 | Paul Brook | } else {
|
533 | 2a424990 | Paul Brook | DPRINTF("RX underflow\n");
|
534 | 2a424990 | Paul Brook | s->int_sts |= RXE_INT; |
535 | 2a424990 | Paul Brook | val = 0;
|
536 | 2a424990 | Paul Brook | } |
537 | 2a424990 | Paul Brook | lan9118_update(s); |
538 | 2a424990 | Paul Brook | return val;
|
539 | 2a424990 | Paul Brook | } |
540 | 2a424990 | Paul Brook | |
541 | 2a424990 | Paul Brook | static void do_tx_packet(lan9118_state *s) |
542 | 2a424990 | Paul Brook | { |
543 | 2a424990 | Paul Brook | int n;
|
544 | 2a424990 | Paul Brook | uint32_t status; |
545 | 2a424990 | Paul Brook | |
546 | 2a424990 | Paul Brook | /* FIXME: Honor TX disable, and allow queueing of packets. */
|
547 | 2a424990 | Paul Brook | if (s->phy_control & 0x4000) { |
548 | 2a424990 | Paul Brook | /* This assumes the receive routine doesn't touch the VLANClient. */
|
549 | 83b9f88c | Mark McLoughlin | lan9118_receive(&s->nic->nc, s->txp->data, s->txp->len); |
550 | 2a424990 | Paul Brook | } else {
|
551 | 83b9f88c | Mark McLoughlin | qemu_send_packet(&s->nic->nc, s->txp->data, s->txp->len); |
552 | 2a424990 | Paul Brook | } |
553 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
554 | 2a424990 | Paul Brook | |
555 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used == 512) { |
556 | 2a424990 | Paul Brook | /* Status FIFO full */
|
557 | 2a424990 | Paul Brook | return;
|
558 | 2a424990 | Paul Brook | } |
559 | 2a424990 | Paul Brook | /* Add entry to status FIFO. */
|
560 | 2a424990 | Paul Brook | status = s->txp->cmd_b & 0xffff0000u;
|
561 | 2a424990 | Paul Brook | DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len); |
562 | 2a424990 | Paul Brook | n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
|
563 | 2a424990 | Paul Brook | s->tx_status_fifo[n] = status; |
564 | 2a424990 | Paul Brook | s->tx_status_fifo_used++; |
565 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used == 512) { |
566 | 2a424990 | Paul Brook | s->int_sts |= TSFF_INT; |
567 | 2a424990 | Paul Brook | /* TODO: Stop transmission. */
|
568 | 2a424990 | Paul Brook | } |
569 | 2a424990 | Paul Brook | } |
570 | 2a424990 | Paul Brook | |
571 | 2a424990 | Paul Brook | static uint32_t rx_status_fifo_pop(lan9118_state *s)
|
572 | 2a424990 | Paul Brook | { |
573 | 2a424990 | Paul Brook | uint32_t val; |
574 | 2a424990 | Paul Brook | |
575 | 2a424990 | Paul Brook | val = s->rx_status_fifo[s->rx_status_fifo_head]; |
576 | 2a424990 | Paul Brook | if (s->rx_status_fifo_used != 0) { |
577 | 2a424990 | Paul Brook | s->rx_status_fifo_used--; |
578 | 2a424990 | Paul Brook | s->rx_status_fifo_head++; |
579 | 2a424990 | Paul Brook | if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
|
580 | 2a424990 | Paul Brook | s->rx_status_fifo_head -= s->rx_status_fifo_size; |
581 | 2a424990 | Paul Brook | } |
582 | 2a424990 | Paul Brook | /* ??? What value should be returned when the FIFO is empty? */
|
583 | 2a424990 | Paul Brook | DPRINTF("RX status pop 0x%08x\n", val);
|
584 | 2a424990 | Paul Brook | } |
585 | 2a424990 | Paul Brook | return val;
|
586 | 2a424990 | Paul Brook | } |
587 | 2a424990 | Paul Brook | |
588 | 2a424990 | Paul Brook | static uint32_t tx_status_fifo_pop(lan9118_state *s)
|
589 | 2a424990 | Paul Brook | { |
590 | 2a424990 | Paul Brook | uint32_t val; |
591 | 2a424990 | Paul Brook | |
592 | 2a424990 | Paul Brook | val = s->tx_status_fifo[s->tx_status_fifo_head]; |
593 | 2a424990 | Paul Brook | if (s->tx_status_fifo_used != 0) { |
594 | 2a424990 | Paul Brook | s->tx_status_fifo_used--; |
595 | 2a424990 | Paul Brook | s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511; |
596 | 2a424990 | Paul Brook | /* ??? What value should be returned when the FIFO is empty? */
|
597 | 2a424990 | Paul Brook | } |
598 | 2a424990 | Paul Brook | return val;
|
599 | 2a424990 | Paul Brook | } |
600 | 2a424990 | Paul Brook | |
601 | 2a424990 | Paul Brook | static void tx_fifo_push(lan9118_state *s, uint32_t val) |
602 | 2a424990 | Paul Brook | { |
603 | 2a424990 | Paul Brook | int n;
|
604 | 2a424990 | Paul Brook | |
605 | 2a424990 | Paul Brook | if (s->txp->fifo_used == s->tx_fifo_size) {
|
606 | 2a424990 | Paul Brook | s->int_sts |= TDFO_INT; |
607 | 2a424990 | Paul Brook | return;
|
608 | 2a424990 | Paul Brook | } |
609 | 2a424990 | Paul Brook | switch (s->txp->state) {
|
610 | 2a424990 | Paul Brook | case TX_IDLE:
|
611 | 2a424990 | Paul Brook | s->txp->cmd_a = val & 0x831f37ff;
|
612 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
613 | 2a424990 | Paul Brook | s->txp->state = TX_B; |
614 | 2a424990 | Paul Brook | break;
|
615 | 2a424990 | Paul Brook | case TX_B:
|
616 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x2000) { |
617 | 2a424990 | Paul Brook | /* First segment */
|
618 | 2a424990 | Paul Brook | s->txp->cmd_b = val; |
619 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
620 | 2a424990 | Paul Brook | s->txp->buffer_size = s->txp->cmd_a & 0x7ff;
|
621 | 2a424990 | Paul Brook | s->txp->offset = (s->txp->cmd_a >> 16) & 0x1f; |
622 | 2a424990 | Paul Brook | /* End alignment does not include command words. */
|
623 | 2a424990 | Paul Brook | n = (s->txp->buffer_size + s->txp->offset + 3) >> 2; |
624 | 2a424990 | Paul Brook | switch ((n >> 24) & 3) { |
625 | 2a424990 | Paul Brook | case 1: |
626 | 2a424990 | Paul Brook | n = (-n) & 3;
|
627 | 2a424990 | Paul Brook | break;
|
628 | 2a424990 | Paul Brook | case 2: |
629 | 2a424990 | Paul Brook | n = (-n) & 7;
|
630 | 2a424990 | Paul Brook | break;
|
631 | 2a424990 | Paul Brook | default:
|
632 | 2a424990 | Paul Brook | n = 0;
|
633 | 2a424990 | Paul Brook | } |
634 | 2a424990 | Paul Brook | s->txp->pad = n; |
635 | 2a424990 | Paul Brook | s->txp->len = 0;
|
636 | 2a424990 | Paul Brook | } |
637 | 2a424990 | Paul Brook | DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
|
638 | 2a424990 | Paul Brook | s->txp->buffer_size, s->txp->offset, s->txp->pad, |
639 | 2a424990 | Paul Brook | s->txp->cmd_a); |
640 | 2a424990 | Paul Brook | s->txp->state = TX_DATA; |
641 | 2a424990 | Paul Brook | break;
|
642 | 2a424990 | Paul Brook | case TX_DATA:
|
643 | 2a424990 | Paul Brook | if (s->txp->offset >= 4) { |
644 | 2a424990 | Paul Brook | s->txp->offset -= 4;
|
645 | 2a424990 | Paul Brook | break;
|
646 | 2a424990 | Paul Brook | } |
647 | 2a424990 | Paul Brook | if (s->txp->buffer_size <= 0 && s->txp->pad != 0) { |
648 | 2a424990 | Paul Brook | s->txp->pad--; |
649 | 2a424990 | Paul Brook | } else {
|
650 | 2a424990 | Paul Brook | n = 4;
|
651 | 2a424990 | Paul Brook | while (s->txp->offset) {
|
652 | 2a424990 | Paul Brook | val >>= 8;
|
653 | 2a424990 | Paul Brook | n--; |
654 | 2a424990 | Paul Brook | s->txp->offset--; |
655 | 2a424990 | Paul Brook | } |
656 | 2a424990 | Paul Brook | /* Documentation is somewhat unclear on the ordering of bytes
|
657 | 2a424990 | Paul Brook | in FIFO words. Empirical results show it to be little-endian.
|
658 | 2a424990 | Paul Brook | */
|
659 | 2a424990 | Paul Brook | /* TODO: FIFO overflow checking. */
|
660 | 2a424990 | Paul Brook | while (n--) {
|
661 | 2a424990 | Paul Brook | s->txp->data[s->txp->len] = val & 0xff;
|
662 | 2a424990 | Paul Brook | s->txp->len++; |
663 | 2a424990 | Paul Brook | val >>= 8;
|
664 | 2a424990 | Paul Brook | s->txp->buffer_size--; |
665 | 2a424990 | Paul Brook | } |
666 | 2a424990 | Paul Brook | s->txp->fifo_used++; |
667 | 2a424990 | Paul Brook | } |
668 | 2a424990 | Paul Brook | if (s->txp->buffer_size <= 0 && s->txp->pad == 0) { |
669 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x1000) { |
670 | 2a424990 | Paul Brook | do_tx_packet(s); |
671 | 2a424990 | Paul Brook | } |
672 | 2a424990 | Paul Brook | if (s->txp->cmd_a & 0x80000000) { |
673 | 2a424990 | Paul Brook | s->int_sts |= TX_IOC_INT; |
674 | 2a424990 | Paul Brook | } |
675 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
676 | 2a424990 | Paul Brook | } |
677 | 2a424990 | Paul Brook | break;
|
678 | 2a424990 | Paul Brook | } |
679 | 2a424990 | Paul Brook | } |
680 | 2a424990 | Paul Brook | |
681 | 2a424990 | Paul Brook | static uint32_t do_phy_read(lan9118_state *s, int reg) |
682 | 2a424990 | Paul Brook | { |
683 | 209bf965 | Paul Brook | uint32_t val; |
684 | 209bf965 | Paul Brook | |
685 | 2a424990 | Paul Brook | switch (reg) {
|
686 | 2a424990 | Paul Brook | case 0: /* Basic Control */ |
687 | 2a424990 | Paul Brook | return s->phy_control;
|
688 | 2a424990 | Paul Brook | case 1: /* Basic Status */ |
689 | 2a424990 | Paul Brook | return s->phy_status;
|
690 | 2a424990 | Paul Brook | case 2: /* ID1 */ |
691 | 2a424990 | Paul Brook | return 0x0007; |
692 | 2a424990 | Paul Brook | case 3: /* ID2 */ |
693 | 2a424990 | Paul Brook | return 0xc0d1; |
694 | 2a424990 | Paul Brook | case 4: /* Auto-neg advertisment */ |
695 | 2a424990 | Paul Brook | return s->phy_advertise;
|
696 | 2a424990 | Paul Brook | case 5: /* Auto-neg Link Partner Ability */ |
697 | 2a424990 | Paul Brook | return 0x0f71; |
698 | 2a424990 | Paul Brook | case 6: /* Auto-neg Expansion */ |
699 | 2a424990 | Paul Brook | return 1; |
700 | 2a424990 | Paul Brook | /* TODO 17, 18, 27, 29, 30, 31 */
|
701 | 209bf965 | Paul Brook | case 29: /* Interrupt source. */ |
702 | 209bf965 | Paul Brook | val = s->phy_int; |
703 | 209bf965 | Paul Brook | s->phy_int = 0;
|
704 | 209bf965 | Paul Brook | phy_update_irq(s); |
705 | 209bf965 | Paul Brook | return val;
|
706 | 209bf965 | Paul Brook | case 30: /* Interrupt mask */ |
707 | 209bf965 | Paul Brook | return s->phy_int_mask;
|
708 | 2a424990 | Paul Brook | default:
|
709 | 2a424990 | Paul Brook | BADF("PHY read reg %d\n", reg);
|
710 | 2a424990 | Paul Brook | return 0; |
711 | 2a424990 | Paul Brook | } |
712 | 2a424990 | Paul Brook | } |
713 | 2a424990 | Paul Brook | |
714 | 2a424990 | Paul Brook | static void do_phy_write(lan9118_state *s, int reg, uint32_t val) |
715 | 2a424990 | Paul Brook | { |
716 | 2a424990 | Paul Brook | switch (reg) {
|
717 | 2a424990 | Paul Brook | case 0: /* Basic Control */ |
718 | 2a424990 | Paul Brook | if (val & 0x8000) { |
719 | 2a424990 | Paul Brook | phy_reset(s); |
720 | 2a424990 | Paul Brook | break;
|
721 | 2a424990 | Paul Brook | } |
722 | 2a424990 | Paul Brook | s->phy_control = val & 0x7980;
|
723 | 2a424990 | Paul Brook | /* Complete autonegotiation imediately. */
|
724 | 2a424990 | Paul Brook | if (val & 0x1000) { |
725 | 2a424990 | Paul Brook | s->phy_status |= 0x0020;
|
726 | 2a424990 | Paul Brook | } |
727 | 2a424990 | Paul Brook | break;
|
728 | 2a424990 | Paul Brook | case 4: /* Auto-neg advertisment */ |
729 | 2a424990 | Paul Brook | s->phy_advertise = (val & 0x2d7f) | 0x80; |
730 | 2a424990 | Paul Brook | break;
|
731 | 209bf965 | Paul Brook | /* TODO 17, 18, 27, 31 */
|
732 | 209bf965 | Paul Brook | case 30: /* Interrupt mask */ |
733 | 209bf965 | Paul Brook | s->phy_int_mask = val & 0xff;
|
734 | 209bf965 | Paul Brook | phy_update_irq(s); |
735 | 209bf965 | Paul Brook | break;
|
736 | 2a424990 | Paul Brook | default:
|
737 | 2a424990 | Paul Brook | BADF("PHY write reg %d = 0x%04x\n", reg, val);
|
738 | 2a424990 | Paul Brook | } |
739 | 2a424990 | Paul Brook | } |
740 | 2a424990 | Paul Brook | |
741 | 2a424990 | Paul Brook | static void do_mac_write(lan9118_state *s, int reg, uint32_t val) |
742 | 2a424990 | Paul Brook | { |
743 | 2a424990 | Paul Brook | switch (reg) {
|
744 | 2a424990 | Paul Brook | case MAC_CR:
|
745 | 2a424990 | Paul Brook | if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) { |
746 | 2a424990 | Paul Brook | s->int_sts |= RXSTOP_INT; |
747 | 2a424990 | Paul Brook | } |
748 | 2a424990 | Paul Brook | s->mac_cr = val & ~MAC_CR_RESERVED; |
749 | 2a424990 | Paul Brook | DPRINTF("MAC_CR: %08x\n", val);
|
750 | 2a424990 | Paul Brook | break;
|
751 | 2a424990 | Paul Brook | case MAC_ADDRH:
|
752 | 2a424990 | Paul Brook | s->conf.macaddr.a[4] = val & 0xff; |
753 | 2a424990 | Paul Brook | s->conf.macaddr.a[5] = (val >> 8) & 0xff; |
754 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
755 | 2a424990 | Paul Brook | break;
|
756 | 2a424990 | Paul Brook | case MAC_ADDRL:
|
757 | 2a424990 | Paul Brook | s->conf.macaddr.a[0] = val & 0xff; |
758 | 2a424990 | Paul Brook | s->conf.macaddr.a[1] = (val >> 8) & 0xff; |
759 | 2a424990 | Paul Brook | s->conf.macaddr.a[2] = (val >> 16) & 0xff; |
760 | 2a424990 | Paul Brook | s->conf.macaddr.a[3] = (val >> 24) & 0xff; |
761 | 2a424990 | Paul Brook | lan9118_mac_changed(s); |
762 | 2a424990 | Paul Brook | break;
|
763 | 2a424990 | Paul Brook | case MAC_HASHH:
|
764 | 2a424990 | Paul Brook | s->mac_hashh = val; |
765 | 2a424990 | Paul Brook | break;
|
766 | 2a424990 | Paul Brook | case MAC_HASHL:
|
767 | 2a424990 | Paul Brook | s->mac_hashl = val; |
768 | 2a424990 | Paul Brook | break;
|
769 | 2a424990 | Paul Brook | case MAC_MII_ACC:
|
770 | 2a424990 | Paul Brook | s->mac_mii_acc = val & 0xffc2;
|
771 | 2a424990 | Paul Brook | if (val & 2) { |
772 | 2a424990 | Paul Brook | DPRINTF("PHY write %d = 0x%04x\n",
|
773 | 2a424990 | Paul Brook | (val >> 6) & 0x1f, s->mac_mii_data); |
774 | 2a424990 | Paul Brook | do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data); |
775 | 2a424990 | Paul Brook | } else {
|
776 | 2a424990 | Paul Brook | s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f); |
777 | 2a424990 | Paul Brook | DPRINTF("PHY read %d = 0x%04x\n",
|
778 | 2a424990 | Paul Brook | (val >> 6) & 0x1f, s->mac_mii_data); |
779 | 2a424990 | Paul Brook | } |
780 | 2a424990 | Paul Brook | break;
|
781 | 2a424990 | Paul Brook | case MAC_MII_DATA:
|
782 | 2a424990 | Paul Brook | s->mac_mii_data = val & 0xffff;
|
783 | 2a424990 | Paul Brook | break;
|
784 | 2a424990 | Paul Brook | case MAC_FLOW:
|
785 | 2a424990 | Paul Brook | s->mac_flow = val & 0xffff0000;
|
786 | 2a424990 | Paul Brook | break;
|
787 | 2a424990 | Paul Brook | default:
|
788 | 2a424990 | Paul Brook | hw_error("lan9118: Unimplemented MAC register write: %d = 0x%x\n",
|
789 | 2a424990 | Paul Brook | s->mac_cmd & 0xf, val);
|
790 | 2a424990 | Paul Brook | } |
791 | 2a424990 | Paul Brook | } |
792 | 2a424990 | Paul Brook | |
793 | 2a424990 | Paul Brook | static uint32_t do_mac_read(lan9118_state *s, int reg) |
794 | 2a424990 | Paul Brook | { |
795 | 2a424990 | Paul Brook | switch (reg) {
|
796 | 2a424990 | Paul Brook | case MAC_CR:
|
797 | 2a424990 | Paul Brook | return s->mac_cr;
|
798 | 2a424990 | Paul Brook | case MAC_ADDRH:
|
799 | 2a424990 | Paul Brook | return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8); |
800 | 2a424990 | Paul Brook | case MAC_ADDRL:
|
801 | 2a424990 | Paul Brook | return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8) |
802 | 2a424990 | Paul Brook | | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24); |
803 | 2a424990 | Paul Brook | case MAC_HASHH:
|
804 | 2a424990 | Paul Brook | return s->mac_hashh;
|
805 | 2a424990 | Paul Brook | break;
|
806 | 2a424990 | Paul Brook | case MAC_HASHL:
|
807 | 2a424990 | Paul Brook | return s->mac_hashl;
|
808 | 2a424990 | Paul Brook | break;
|
809 | 2a424990 | Paul Brook | case MAC_MII_ACC:
|
810 | 2a424990 | Paul Brook | return s->mac_mii_acc;
|
811 | 2a424990 | Paul Brook | case MAC_MII_DATA:
|
812 | 2a424990 | Paul Brook | return s->mac_mii_data;
|
813 | 2a424990 | Paul Brook | case MAC_FLOW:
|
814 | 2a424990 | Paul Brook | return s->mac_flow;
|
815 | 2a424990 | Paul Brook | default:
|
816 | 2a424990 | Paul Brook | hw_error("lan9118: Unimplemented MAC register read: %d\n",
|
817 | 2a424990 | Paul Brook | s->mac_cmd & 0xf);
|
818 | 2a424990 | Paul Brook | } |
819 | 2a424990 | Paul Brook | } |
820 | 2a424990 | Paul Brook | |
821 | 2a424990 | Paul Brook | static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr) |
822 | 2a424990 | Paul Brook | { |
823 | 2a424990 | Paul Brook | s->e2p_cmd = (s->e2p_cmd & 0x10) | (cmd << 28) | addr; |
824 | 2a424990 | Paul Brook | switch (cmd) {
|
825 | 2a424990 | Paul Brook | case 0: |
826 | 2a424990 | Paul Brook | s->e2p_data = s->eeprom[addr]; |
827 | 2a424990 | Paul Brook | DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
|
828 | 2a424990 | Paul Brook | break;
|
829 | 2a424990 | Paul Brook | case 1: |
830 | 2a424990 | Paul Brook | s->eeprom_writable = 0;
|
831 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write Disable\n");
|
832 | 2a424990 | Paul Brook | break;
|
833 | 2a424990 | Paul Brook | case 2: /* EWEN */ |
834 | 2a424990 | Paul Brook | s->eeprom_writable = 1;
|
835 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write Enable\n");
|
836 | 2a424990 | Paul Brook | break;
|
837 | 2a424990 | Paul Brook | case 3: /* WRITE */ |
838 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
839 | 2a424990 | Paul Brook | s->eeprom[addr] &= s->e2p_data; |
840 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
|
841 | 2a424990 | Paul Brook | } else {
|
842 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write %d (ignored)\n", addr);
|
843 | 2a424990 | Paul Brook | } |
844 | 2a424990 | Paul Brook | break;
|
845 | 2a424990 | Paul Brook | case 4: /* WRAL */ |
846 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
847 | 2a424990 | Paul Brook | for (addr = 0; addr < 128; addr++) { |
848 | 2a424990 | Paul Brook | s->eeprom[addr] &= s->e2p_data; |
849 | 2a424990 | Paul Brook | } |
850 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
|
851 | 2a424990 | Paul Brook | } else {
|
852 | 2a424990 | Paul Brook | DPRINTF("EEPROM Write All (ignored)\n");
|
853 | 2a424990 | Paul Brook | } |
854 | 2a424990 | Paul Brook | case 5: /* ERASE */ |
855 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
856 | 2a424990 | Paul Brook | s->eeprom[addr] = 0xff;
|
857 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase %d\n", addr);
|
858 | 2a424990 | Paul Brook | } else {
|
859 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase %d (ignored)\n", addr);
|
860 | 2a424990 | Paul Brook | } |
861 | 2a424990 | Paul Brook | break;
|
862 | 2a424990 | Paul Brook | case 6: /* ERAL */ |
863 | 2a424990 | Paul Brook | if (s->eeprom_writable) {
|
864 | 2a424990 | Paul Brook | memset(s->eeprom, 0xff, 128); |
865 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase All\n");
|
866 | 2a424990 | Paul Brook | } else {
|
867 | 2a424990 | Paul Brook | DPRINTF("EEPROM Erase All (ignored)\n");
|
868 | 2a424990 | Paul Brook | } |
869 | 2a424990 | Paul Brook | break;
|
870 | 2a424990 | Paul Brook | case 7: /* RELOAD */ |
871 | 2a424990 | Paul Brook | lan9118_reload_eeprom(s); |
872 | 2a424990 | Paul Brook | break;
|
873 | 2a424990 | Paul Brook | } |
874 | 2a424990 | Paul Brook | } |
875 | 2a424990 | Paul Brook | |
876 | 209bf965 | Paul Brook | static void lan9118_tick(void *opaque) |
877 | 209bf965 | Paul Brook | { |
878 | 209bf965 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
879 | 209bf965 | Paul Brook | if (s->int_en & GPT_INT) {
|
880 | 209bf965 | Paul Brook | s->int_sts |= GPT_INT; |
881 | 209bf965 | Paul Brook | } |
882 | 209bf965 | Paul Brook | lan9118_update(s); |
883 | 209bf965 | Paul Brook | } |
884 | 209bf965 | Paul Brook | |
885 | 2a424990 | Paul Brook | static void lan9118_writel(void *opaque, target_phys_addr_t offset, |
886 | 2a424990 | Paul Brook | uint32_t val) |
887 | 2a424990 | Paul Brook | { |
888 | 2a424990 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
889 | 2a424990 | Paul Brook | offset &= 0xff;
|
890 | 2a424990 | Paul Brook | |
891 | 2a424990 | Paul Brook | //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
|
892 | 2a424990 | Paul Brook | if (offset >= 0x20 && offset < 0x40) { |
893 | 2a424990 | Paul Brook | /* TX FIFO */
|
894 | 2a424990 | Paul Brook | tx_fifo_push(s, val); |
895 | 2a424990 | Paul Brook | return;
|
896 | 2a424990 | Paul Brook | } |
897 | 2a424990 | Paul Brook | switch (offset) {
|
898 | 2a424990 | Paul Brook | case CSR_IRQ_CFG:
|
899 | 2a424990 | Paul Brook | /* TODO: Implement interrupt deassertion intervals. */
|
900 | 209bf965 | Paul Brook | s->irq_cfg = (s->irq_cfg & IRQ_INT) | (val & IRQ_EN); |
901 | 2a424990 | Paul Brook | break;
|
902 | 2a424990 | Paul Brook | case CSR_INT_STS:
|
903 | 2a424990 | Paul Brook | s->int_sts &= ~val; |
904 | 2a424990 | Paul Brook | break;
|
905 | 2a424990 | Paul Brook | case CSR_INT_EN:
|
906 | 2a424990 | Paul Brook | s->int_en = val & ~RESERVED_INT; |
907 | 2a424990 | Paul Brook | s->int_sts |= val & SW_INT; |
908 | 2a424990 | Paul Brook | break;
|
909 | 2a424990 | Paul Brook | case CSR_FIFO_INT:
|
910 | 2a424990 | Paul Brook | DPRINTF("FIFO INT levels %08x\n", val);
|
911 | 2a424990 | Paul Brook | s->fifo_int = val; |
912 | 2a424990 | Paul Brook | break;
|
913 | 2a424990 | Paul Brook | case CSR_RX_CFG:
|
914 | 2a424990 | Paul Brook | if (val & 0x8000) { |
915 | 2a424990 | Paul Brook | /* RX_DUMP */
|
916 | 2a424990 | Paul Brook | s->rx_fifo_used = 0;
|
917 | 2a424990 | Paul Brook | s->rx_status_fifo_used = 0;
|
918 | 2a424990 | Paul Brook | s->rx_packet_size_tail = s->rx_packet_size_head; |
919 | 2a424990 | Paul Brook | s->rx_packet_size[s->rx_packet_size_head] = 0;
|
920 | 2a424990 | Paul Brook | } |
921 | 2a424990 | Paul Brook | s->rx_cfg = val & 0xcfff1ff0;
|
922 | 2a424990 | Paul Brook | break;
|
923 | 2a424990 | Paul Brook | case CSR_TX_CFG:
|
924 | 2a424990 | Paul Brook | if (val & 0x8000) { |
925 | 2a424990 | Paul Brook | s->tx_status_fifo_used = 0;
|
926 | 2a424990 | Paul Brook | } |
927 | 2a424990 | Paul Brook | if (val & 0x4000) { |
928 | 2a424990 | Paul Brook | s->txp->state = TX_IDLE; |
929 | 2a424990 | Paul Brook | s->txp->fifo_used = 0;
|
930 | 2a424990 | Paul Brook | s->txp->cmd_a = 0xffffffff;
|
931 | 2a424990 | Paul Brook | } |
932 | 2a424990 | Paul Brook | s->tx_cfg = val & 6;
|
933 | 2a424990 | Paul Brook | break;
|
934 | 2a424990 | Paul Brook | case CSR_HW_CFG:
|
935 | 2a424990 | Paul Brook | if (val & 1) { |
936 | 2a424990 | Paul Brook | /* SRST */
|
937 | 2a424990 | Paul Brook | lan9118_reset(&s->busdev.qdev); |
938 | 2a424990 | Paul Brook | } else {
|
939 | 2a424990 | Paul Brook | s->hw_cfg = val & 0x003f300;
|
940 | 2a424990 | Paul Brook | } |
941 | 2a424990 | Paul Brook | break;
|
942 | 2a424990 | Paul Brook | case CSR_RX_DP_CTRL:
|
943 | 2a424990 | Paul Brook | if (val & 0x80000000) { |
944 | 2a424990 | Paul Brook | /* Skip forward to next packet. */
|
945 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
946 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
947 | 2a424990 | Paul Brook | if (s->rxp_size == 0) { |
948 | 2a424990 | Paul Brook | /* Pop a word to start the next packet. */
|
949 | 2a424990 | Paul Brook | rx_fifo_pop(s); |
950 | 2a424990 | Paul Brook | s->rxp_pad = 0;
|
951 | 2a424990 | Paul Brook | s->rxp_offset = 0;
|
952 | 2a424990 | Paul Brook | } |
953 | 2a424990 | Paul Brook | s->rx_fifo_head += s->rxp_size; |
954 | 2a424990 | Paul Brook | if (s->rx_fifo_head >= s->rx_fifo_size) {
|
955 | 2a424990 | Paul Brook | s->rx_fifo_head -= s->rx_fifo_size; |
956 | 2a424990 | Paul Brook | } |
957 | 2a424990 | Paul Brook | } |
958 | 2a424990 | Paul Brook | break;
|
959 | 2a424990 | Paul Brook | case CSR_PMT_CTRL:
|
960 | 2a424990 | Paul Brook | if (val & 0x400) { |
961 | 2a424990 | Paul Brook | phy_reset(s); |
962 | 2a424990 | Paul Brook | } |
963 | 2a424990 | Paul Brook | s->pmt_ctrl &= ~0x34e;
|
964 | 2a424990 | Paul Brook | s->pmt_ctrl |= (val & 0x34e);
|
965 | 2a424990 | Paul Brook | break;
|
966 | 2a424990 | Paul Brook | case CSR_GPIO_CFG:
|
967 | 2a424990 | Paul Brook | /* Probably just enabling LEDs. */
|
968 | 2a424990 | Paul Brook | s->gpio_cfg = val & 0x7777071f;
|
969 | 2a424990 | Paul Brook | break;
|
970 | 209bf965 | Paul Brook | case CSR_GPT_CFG:
|
971 | 209bf965 | Paul Brook | if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) {
|
972 | 209bf965 | Paul Brook | if (val & GPT_TIMER_EN) {
|
973 | 209bf965 | Paul Brook | ptimer_set_count(s->timer, val & 0xffff);
|
974 | 209bf965 | Paul Brook | ptimer_run(s->timer, 0);
|
975 | 209bf965 | Paul Brook | } else {
|
976 | 209bf965 | Paul Brook | ptimer_stop(s->timer); |
977 | 209bf965 | Paul Brook | ptimer_set_count(s->timer, 0xffff);
|
978 | 209bf965 | Paul Brook | } |
979 | 209bf965 | Paul Brook | } |
980 | 209bf965 | Paul Brook | s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff);
|
981 | 209bf965 | Paul Brook | break;
|
982 | 2a424990 | Paul Brook | case CSR_WORD_SWAP:
|
983 | 2a424990 | Paul Brook | /* Ignored because we're in 32-bit mode. */
|
984 | 2a424990 | Paul Brook | s->word_swap = val; |
985 | 2a424990 | Paul Brook | break;
|
986 | 2a424990 | Paul Brook | case CSR_MAC_CSR_CMD:
|
987 | 2a424990 | Paul Brook | s->mac_cmd = val & 0x4000000f;
|
988 | 2a424990 | Paul Brook | if (val & 0x80000000) { |
989 | 2a424990 | Paul Brook | if (val & 0x40000000) { |
990 | 2a424990 | Paul Brook | s->mac_data = do_mac_read(s, val & 0xf);
|
991 | 2a424990 | Paul Brook | DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data); |
992 | 2a424990 | Paul Brook | } else {
|
993 | 2a424990 | Paul Brook | DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data); |
994 | 2a424990 | Paul Brook | do_mac_write(s, val & 0xf, s->mac_data);
|
995 | 2a424990 | Paul Brook | } |
996 | 2a424990 | Paul Brook | } |
997 | 2a424990 | Paul Brook | break;
|
998 | 2a424990 | Paul Brook | case CSR_MAC_CSR_DATA:
|
999 | 2a424990 | Paul Brook | s->mac_data = val; |
1000 | 2a424990 | Paul Brook | break;
|
1001 | 2a424990 | Paul Brook | case CSR_AFC_CFG:
|
1002 | 2a424990 | Paul Brook | s->afc_cfg = val & 0x00ffffff;
|
1003 | 2a424990 | Paul Brook | break;
|
1004 | 2a424990 | Paul Brook | case CSR_E2P_CMD:
|
1005 | 2a424990 | Paul Brook | lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0xff); |
1006 | 2a424990 | Paul Brook | break;
|
1007 | 2a424990 | Paul Brook | case CSR_E2P_DATA:
|
1008 | 2a424990 | Paul Brook | s->e2p_data = val & 0xff;
|
1009 | 2a424990 | Paul Brook | break;
|
1010 | 2a424990 | Paul Brook | |
1011 | 2a424990 | Paul Brook | default:
|
1012 | 2a424990 | Paul Brook | hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, val); |
1013 | 2a424990 | Paul Brook | break;
|
1014 | 2a424990 | Paul Brook | } |
1015 | 2a424990 | Paul Brook | lan9118_update(s); |
1016 | 2a424990 | Paul Brook | } |
1017 | 2a424990 | Paul Brook | |
1018 | 2a424990 | Paul Brook | static uint32_t lan9118_readl(void *opaque, target_phys_addr_t offset) |
1019 | 2a424990 | Paul Brook | { |
1020 | 2a424990 | Paul Brook | lan9118_state *s = (lan9118_state *)opaque; |
1021 | 2a424990 | Paul Brook | |
1022 | 2a424990 | Paul Brook | //DPRINTF("Read reg 0x%02x\n", (int)offset);
|
1023 | 2a424990 | Paul Brook | if (offset < 0x20) { |
1024 | 2a424990 | Paul Brook | /* RX FIFO */
|
1025 | 2a424990 | Paul Brook | return rx_fifo_pop(s);
|
1026 | 2a424990 | Paul Brook | } |
1027 | 2a424990 | Paul Brook | switch (offset) {
|
1028 | 2a424990 | Paul Brook | case 0x40: |
1029 | 2a424990 | Paul Brook | return rx_status_fifo_pop(s);
|
1030 | 2a424990 | Paul Brook | case 0x44: |
1031 | 2a424990 | Paul Brook | return s->rx_status_fifo[s->tx_status_fifo_head];
|
1032 | 2a424990 | Paul Brook | case 0x48: |
1033 | 2a424990 | Paul Brook | return tx_status_fifo_pop(s);
|
1034 | 2a424990 | Paul Brook | case 0x4c: |
1035 | 2a424990 | Paul Brook | return s->tx_status_fifo[s->tx_status_fifo_head];
|
1036 | 2a424990 | Paul Brook | case CSR_ID_REV:
|
1037 | 2a424990 | Paul Brook | return 0x01180001; |
1038 | 2a424990 | Paul Brook | case CSR_IRQ_CFG:
|
1039 | 2a424990 | Paul Brook | return s->irq_cfg;
|
1040 | 2a424990 | Paul Brook | case CSR_INT_STS:
|
1041 | 2a424990 | Paul Brook | return s->int_sts;
|
1042 | 2a424990 | Paul Brook | case CSR_INT_EN:
|
1043 | 2a424990 | Paul Brook | return s->int_en;
|
1044 | 2a424990 | Paul Brook | case CSR_BYTE_TEST:
|
1045 | 2a424990 | Paul Brook | return 0x87654321; |
1046 | 2a424990 | Paul Brook | case CSR_FIFO_INT:
|
1047 | 2a424990 | Paul Brook | return s->fifo_int;
|
1048 | 2a424990 | Paul Brook | case CSR_RX_CFG:
|
1049 | 2a424990 | Paul Brook | return s->rx_cfg;
|
1050 | 2a424990 | Paul Brook | case CSR_TX_CFG:
|
1051 | 2a424990 | Paul Brook | return s->tx_cfg;
|
1052 | 2a424990 | Paul Brook | case CSR_HW_CFG:
|
1053 | 2a424990 | Paul Brook | return s->hw_cfg | 0x4; |
1054 | 2a424990 | Paul Brook | case CSR_RX_DP_CTRL:
|
1055 | 2a424990 | Paul Brook | return 0; |
1056 | 2a424990 | Paul Brook | case CSR_RX_FIFO_INF:
|
1057 | 2a424990 | Paul Brook | return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2); |
1058 | 2a424990 | Paul Brook | case CSR_TX_FIFO_INF:
|
1059 | 2a424990 | Paul Brook | return (s->tx_status_fifo_used << 16) |
1060 | 2a424990 | Paul Brook | | (s->tx_fifo_size - s->txp->fifo_used); |
1061 | 2a424990 | Paul Brook | case CSR_PMT_CTRL:
|
1062 | 2a424990 | Paul Brook | return s->pmt_ctrl;
|
1063 | 2a424990 | Paul Brook | case CSR_GPIO_CFG:
|
1064 | 2a424990 | Paul Brook | return s->gpio_cfg;
|
1065 | 209bf965 | Paul Brook | case CSR_GPT_CFG:
|
1066 | 209bf965 | Paul Brook | return s->gpt_cfg;
|
1067 | 209bf965 | Paul Brook | case CSR_GPT_CNT:
|
1068 | 209bf965 | Paul Brook | return ptimer_get_count(s->timer);
|
1069 | 2a424990 | Paul Brook | case CSR_WORD_SWAP:
|
1070 | 2a424990 | Paul Brook | return s->word_swap;
|
1071 | 2a424990 | Paul Brook | case CSR_FREE_RUN:
|
1072 | 2a424990 | Paul Brook | return (qemu_get_clock(vm_clock) / 40) - s->free_timer_start; |
1073 | 2a424990 | Paul Brook | case CSR_RX_DROP:
|
1074 | 2a424990 | Paul Brook | /* TODO: Implement dropped frames counter. */
|
1075 | 2a424990 | Paul Brook | return 0; |
1076 | 2a424990 | Paul Brook | case CSR_MAC_CSR_CMD:
|
1077 | 2a424990 | Paul Brook | return s->mac_cmd;
|
1078 | 2a424990 | Paul Brook | case CSR_MAC_CSR_DATA:
|
1079 | 2a424990 | Paul Brook | return s->mac_data;
|
1080 | 2a424990 | Paul Brook | case CSR_AFC_CFG:
|
1081 | 2a424990 | Paul Brook | return s->afc_cfg;
|
1082 | 2a424990 | Paul Brook | case CSR_E2P_CMD:
|
1083 | 2a424990 | Paul Brook | return s->e2p_cmd;
|
1084 | 2a424990 | Paul Brook | case CSR_E2P_DATA:
|
1085 | 2a424990 | Paul Brook | return s->e2p_data;
|
1086 | 2a424990 | Paul Brook | } |
1087 | 2a424990 | Paul Brook | hw_error("lan9118_read: Bad reg 0x%x\n", (int)offset); |
1088 | 2a424990 | Paul Brook | return 0; |
1089 | 2a424990 | Paul Brook | } |
1090 | 2a424990 | Paul Brook | |
1091 | 2a424990 | Paul Brook | static CPUReadMemoryFunc * const lan9118_readfn[] = { |
1092 | 2a424990 | Paul Brook | lan9118_readl, |
1093 | 2a424990 | Paul Brook | lan9118_readl, |
1094 | 2a424990 | Paul Brook | lan9118_readl |
1095 | 2a424990 | Paul Brook | }; |
1096 | 2a424990 | Paul Brook | |
1097 | 2a424990 | Paul Brook | static CPUWriteMemoryFunc * const lan9118_writefn[] = { |
1098 | 2a424990 | Paul Brook | lan9118_writel, |
1099 | 2a424990 | Paul Brook | lan9118_writel, |
1100 | 2a424990 | Paul Brook | lan9118_writel |
1101 | 2a424990 | Paul Brook | }; |
1102 | 2a424990 | Paul Brook | |
1103 | 83b9f88c | Mark McLoughlin | static void lan9118_cleanup(VLANClientState *nc) |
1104 | 2a424990 | Paul Brook | { |
1105 | 83b9f88c | Mark McLoughlin | lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque; |
1106 | 2a424990 | Paul Brook | |
1107 | 83b9f88c | Mark McLoughlin | s->nic = NULL;
|
1108 | 2a424990 | Paul Brook | } |
1109 | 2a424990 | Paul Brook | |
1110 | 83b9f88c | Mark McLoughlin | static NetClientInfo net_lan9118_info = {
|
1111 | 83b9f88c | Mark McLoughlin | .type = NET_CLIENT_TYPE_NIC, |
1112 | 83b9f88c | Mark McLoughlin | .size = sizeof(NICState),
|
1113 | 83b9f88c | Mark McLoughlin | .can_receive = lan9118_can_receive, |
1114 | 83b9f88c | Mark McLoughlin | .receive = lan9118_receive, |
1115 | 83b9f88c | Mark McLoughlin | .cleanup = lan9118_cleanup, |
1116 | 83b9f88c | Mark McLoughlin | .link_status_changed = lan9118_set_link, |
1117 | 83b9f88c | Mark McLoughlin | }; |
1118 | 83b9f88c | Mark McLoughlin | |
1119 | 2a424990 | Paul Brook | static int lan9118_init1(SysBusDevice *dev) |
1120 | 2a424990 | Paul Brook | { |
1121 | 2a424990 | Paul Brook | lan9118_state *s = FROM_SYSBUS(lan9118_state, dev); |
1122 | 209bf965 | Paul Brook | QEMUBH *bh; |
1123 | 2a424990 | Paul Brook | int i;
|
1124 | 2a424990 | Paul Brook | |
1125 | 2a424990 | Paul Brook | s->mmio_index = cpu_register_io_memory(lan9118_readfn, |
1126 | 2a424990 | Paul Brook | lan9118_writefn, s); |
1127 | 2a424990 | Paul Brook | sysbus_init_mmio(dev, 0x100, s->mmio_index);
|
1128 | 2a424990 | Paul Brook | sysbus_init_irq(dev, &s->irq); |
1129 | 2a424990 | Paul Brook | qemu_macaddr_default_if_unset(&s->conf.macaddr); |
1130 | 2a424990 | Paul Brook | |
1131 | 83b9f88c | Mark McLoughlin | s->nic = qemu_new_nic(&net_lan9118_info, &s->conf, |
1132 | 83b9f88c | Mark McLoughlin | dev->qdev.info->name, dev->qdev.id, s); |
1133 | 83b9f88c | Mark McLoughlin | qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a); |
1134 | 2a424990 | Paul Brook | s->eeprom[0] = 0xa5; |
1135 | 2a424990 | Paul Brook | for (i = 0; i < 6; i++) { |
1136 | 2a424990 | Paul Brook | s->eeprom[i + 1] = s->conf.macaddr.a[i];
|
1137 | 2a424990 | Paul Brook | } |
1138 | 2a424990 | Paul Brook | s->pmt_ctrl = 1;
|
1139 | 2a424990 | Paul Brook | s->txp = &s->tx_packet; |
1140 | 2a424990 | Paul Brook | |
1141 | 209bf965 | Paul Brook | bh = qemu_bh_new(lan9118_tick, s); |
1142 | 209bf965 | Paul Brook | s->timer = ptimer_init(bh); |
1143 | 209bf965 | Paul Brook | ptimer_set_freq(s->timer, 10000);
|
1144 | 209bf965 | Paul Brook | ptimer_set_limit(s->timer, 0xffff, 1); |
1145 | 209bf965 | Paul Brook | |
1146 | 2a424990 | Paul Brook | /* ??? Save/restore. */
|
1147 | 2a424990 | Paul Brook | return 0; |
1148 | 2a424990 | Paul Brook | } |
1149 | 2a424990 | Paul Brook | |
1150 | 2a424990 | Paul Brook | static SysBusDeviceInfo lan9118_info = {
|
1151 | 2a424990 | Paul Brook | .init = lan9118_init1, |
1152 | 2a424990 | Paul Brook | .qdev.name = "lan9118",
|
1153 | 2a424990 | Paul Brook | .qdev.size = sizeof(lan9118_state),
|
1154 | 2a424990 | Paul Brook | .qdev.reset = lan9118_reset, |
1155 | 2a424990 | Paul Brook | .qdev.props = (Property[]) { |
1156 | 2a424990 | Paul Brook | DEFINE_NIC_PROPERTIES(lan9118_state, conf), |
1157 | 2a424990 | Paul Brook | DEFINE_PROP_END_OF_LIST(), |
1158 | 2a424990 | Paul Brook | } |
1159 | 2a424990 | Paul Brook | }; |
1160 | 2a424990 | Paul Brook | |
1161 | 2a424990 | Paul Brook | static void lan9118_register_devices(void) |
1162 | 2a424990 | Paul Brook | { |
1163 | 2a424990 | Paul Brook | sysbus_register_withprop(&lan9118_info); |
1164 | 2a424990 | Paul Brook | } |
1165 | 2a424990 | Paul Brook | |
1166 | 2a424990 | Paul Brook | /* Legacy helper function. Should go away when machine config files are
|
1167 | 2a424990 | Paul Brook | implemented. */
|
1168 | 2a424990 | Paul Brook | void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
|
1169 | 2a424990 | Paul Brook | { |
1170 | 2a424990 | Paul Brook | DeviceState *dev; |
1171 | 2a424990 | Paul Brook | SysBusDevice *s; |
1172 | 2a424990 | Paul Brook | |
1173 | 2a424990 | Paul Brook | qemu_check_nic_model(nd, "lan9118");
|
1174 | 2a424990 | Paul Brook | dev = qdev_create(NULL, "lan9118"); |
1175 | 2a424990 | Paul Brook | qdev_set_nic_properties(dev, nd); |
1176 | 2a424990 | Paul Brook | qdev_init_nofail(dev); |
1177 | 2a424990 | Paul Brook | s = sysbus_from_qdev(dev); |
1178 | 2a424990 | Paul Brook | sysbus_mmio_map(s, 0, base);
|
1179 | 2a424990 | Paul Brook | sysbus_connect_irq(s, 0, irq);
|
1180 | 2a424990 | Paul Brook | } |
1181 | 2a424990 | Paul Brook | |
1182 | 2a424990 | Paul Brook | device_init(lan9118_register_devices) |