root / hw / piix_pci.c @ 8f40c388
History | View | Annotate | Download (12.3 kB)
1 | 502a5395 | pbrook | /*
|
---|---|---|---|
2 | 502a5395 | pbrook | * QEMU i440FX/PIIX3 PCI Bridge Emulation
|
3 | 502a5395 | pbrook | *
|
4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
|
5 | 502a5395 | pbrook | *
|
6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
|
8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
|
9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
|
11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
|
12 | 502a5395 | pbrook | *
|
13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
|
14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
|
15 | 502a5395 | pbrook | *
|
16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 502a5395 | pbrook | * THE SOFTWARE.
|
23 | 502a5395 | pbrook | */
|
24 | 502a5395 | pbrook | |
25 | 502a5395 | pbrook | #include "vl.h" |
26 | 502a5395 | pbrook | typedef uint32_t pci_addr_t;
|
27 | 502a5395 | pbrook | #include "pci_host.h" |
28 | 502a5395 | pbrook | |
29 | 502a5395 | pbrook | typedef PCIHostState I440FXState;
|
30 | 502a5395 | pbrook | |
31 | 502a5395 | pbrook | static void i440fx_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
32 | 502a5395 | pbrook | { |
33 | 502a5395 | pbrook | I440FXState *s = opaque; |
34 | 502a5395 | pbrook | s->config_reg = val; |
35 | 502a5395 | pbrook | } |
36 | 502a5395 | pbrook | |
37 | 502a5395 | pbrook | static uint32_t i440fx_addr_readl(void* opaque, uint32_t addr) |
38 | 502a5395 | pbrook | { |
39 | 502a5395 | pbrook | I440FXState *s = opaque; |
40 | 502a5395 | pbrook | return s->config_reg;
|
41 | 502a5395 | pbrook | } |
42 | 502a5395 | pbrook | |
43 | 502a5395 | pbrook | static void piix3_set_irq(PCIDevice *pci_dev, void *pic, int irq_num, int level); |
44 | 502a5395 | pbrook | |
45 | 502a5395 | pbrook | PCIBus *i440fx_init(void)
|
46 | 502a5395 | pbrook | { |
47 | 502a5395 | pbrook | PCIBus *b; |
48 | 502a5395 | pbrook | PCIDevice *d; |
49 | 502a5395 | pbrook | I440FXState *s; |
50 | 502a5395 | pbrook | |
51 | 502a5395 | pbrook | s = qemu_mallocz(sizeof(I440FXState));
|
52 | 502a5395 | pbrook | b = pci_register_bus(piix3_set_irq, NULL, 0); |
53 | 502a5395 | pbrook | s->bus = b; |
54 | 502a5395 | pbrook | |
55 | 502a5395 | pbrook | register_ioport_write(0xcf8, 4, 4, i440fx_addr_writel, s); |
56 | 502a5395 | pbrook | register_ioport_read(0xcf8, 4, 4, i440fx_addr_readl, s); |
57 | 502a5395 | pbrook | |
58 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s); |
59 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s); |
60 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s); |
61 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s); |
62 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s); |
63 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); |
64 | 502a5395 | pbrook | |
65 | 502a5395 | pbrook | d = pci_register_device(b, "i440FX", sizeof(PCIDevice), 0, |
66 | 502a5395 | pbrook | NULL, NULL); |
67 | 502a5395 | pbrook | |
68 | 502a5395 | pbrook | d->config[0x00] = 0x86; // vendor_id |
69 | 502a5395 | pbrook | d->config[0x01] = 0x80; |
70 | 502a5395 | pbrook | d->config[0x02] = 0x37; // device_id |
71 | 502a5395 | pbrook | d->config[0x03] = 0x12; |
72 | 502a5395 | pbrook | d->config[0x08] = 0x02; // revision |
73 | 502a5395 | pbrook | d->config[0x0a] = 0x00; // class_sub = host2pci |
74 | 502a5395 | pbrook | d->config[0x0b] = 0x06; // class_base = PCI_bridge |
75 | 502a5395 | pbrook | d->config[0x0e] = 0x00; // header_type |
76 | 502a5395 | pbrook | return b;
|
77 | 502a5395 | pbrook | } |
78 | 502a5395 | pbrook | |
79 | 502a5395 | pbrook | /* PIIX3 PCI to ISA bridge */
|
80 | 502a5395 | pbrook | |
81 | 502a5395 | pbrook | static PCIDevice *piix3_dev;
|
82 | 502a5395 | pbrook | |
83 | 502a5395 | pbrook | /* just used for simpler irq handling. */
|
84 | 502a5395 | pbrook | #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32) |
85 | 502a5395 | pbrook | |
86 | 502a5395 | pbrook | static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS]; |
87 | 502a5395 | pbrook | |
88 | 502a5395 | pbrook | /* return the global irq number corresponding to a given device irq
|
89 | 502a5395 | pbrook | pin. We could also use the bus number to have a more precise
|
90 | 502a5395 | pbrook | mapping. */
|
91 | 502a5395 | pbrook | static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num) |
92 | 502a5395 | pbrook | { |
93 | 502a5395 | pbrook | int slot_addend;
|
94 | 502a5395 | pbrook | slot_addend = (pci_dev->devfn >> 3) - 1; |
95 | 502a5395 | pbrook | return (irq_num + slot_addend) & 3; |
96 | 502a5395 | pbrook | } |
97 | 502a5395 | pbrook | |
98 | 502a5395 | pbrook | static inline int get_pci_irq_level(int irq_num) |
99 | 502a5395 | pbrook | { |
100 | 502a5395 | pbrook | int pic_level;
|
101 | 502a5395 | pbrook | #if (PCI_IRQ_WORDS == 2) |
102 | 502a5395 | pbrook | pic_level = ((pci_irq_levels[irq_num][0] |
|
103 | 502a5395 | pbrook | pci_irq_levels[irq_num][1]) != 0); |
104 | 502a5395 | pbrook | #else
|
105 | 502a5395 | pbrook | { |
106 | 502a5395 | pbrook | int i;
|
107 | 502a5395 | pbrook | pic_level = 0;
|
108 | 502a5395 | pbrook | for(i = 0; i < PCI_IRQ_WORDS; i++) { |
109 | 502a5395 | pbrook | if (pci_irq_levels[irq_num][i]) {
|
110 | 502a5395 | pbrook | pic_level = 1;
|
111 | 502a5395 | pbrook | break;
|
112 | 502a5395 | pbrook | } |
113 | 502a5395 | pbrook | } |
114 | 502a5395 | pbrook | } |
115 | 502a5395 | pbrook | #endif
|
116 | 502a5395 | pbrook | return pic_level;
|
117 | 502a5395 | pbrook | } |
118 | 502a5395 | pbrook | |
119 | 502a5395 | pbrook | static void piix3_set_irq(PCIDevice *pci_dev, void *pic, int irq_num, int level) |
120 | 502a5395 | pbrook | { |
121 | 502a5395 | pbrook | int irq_index, shift, pic_irq, pic_level;
|
122 | 502a5395 | pbrook | uint32_t *p; |
123 | 502a5395 | pbrook | |
124 | 502a5395 | pbrook | irq_num = pci_slot_get_pirq(pci_dev, irq_num); |
125 | 502a5395 | pbrook | irq_index = pci_dev->irq_index; |
126 | 502a5395 | pbrook | p = &pci_irq_levels[irq_num][irq_index >> 5];
|
127 | 502a5395 | pbrook | shift = (irq_index & 0x1f);
|
128 | 502a5395 | pbrook | *p = (*p & ~(1 << shift)) | (level << shift);
|
129 | 502a5395 | pbrook | |
130 | 502a5395 | pbrook | /* now we change the pic irq level according to the piix irq mappings */
|
131 | 502a5395 | pbrook | /* XXX: optimize */
|
132 | 502a5395 | pbrook | pic_irq = piix3_dev->config[0x60 + irq_num];
|
133 | 502a5395 | pbrook | if (pic_irq < 16) { |
134 | 502a5395 | pbrook | /* the pic level is the logical OR of all the PCI irqs mapped
|
135 | 502a5395 | pbrook | to it */
|
136 | 502a5395 | pbrook | pic_level = 0;
|
137 | 502a5395 | pbrook | if (pic_irq == piix3_dev->config[0x60]) |
138 | 502a5395 | pbrook | pic_level |= get_pci_irq_level(0);
|
139 | 502a5395 | pbrook | if (pic_irq == piix3_dev->config[0x61]) |
140 | 502a5395 | pbrook | pic_level |= get_pci_irq_level(1);
|
141 | 502a5395 | pbrook | if (pic_irq == piix3_dev->config[0x62]) |
142 | 502a5395 | pbrook | pic_level |= get_pci_irq_level(2);
|
143 | 502a5395 | pbrook | if (pic_irq == piix3_dev->config[0x63]) |
144 | 502a5395 | pbrook | pic_level |= get_pci_irq_level(3);
|
145 | 502a5395 | pbrook | pic_set_irq(pic_irq, pic_level); |
146 | 502a5395 | pbrook | } |
147 | 502a5395 | pbrook | } |
148 | 502a5395 | pbrook | |
149 | 502a5395 | pbrook | static void piix3_reset(PCIDevice *d) |
150 | 502a5395 | pbrook | { |
151 | 502a5395 | pbrook | uint8_t *pci_conf = d->config; |
152 | 502a5395 | pbrook | |
153 | 502a5395 | pbrook | pci_conf[0x04] = 0x07; // master, memory and I/O |
154 | 502a5395 | pbrook | pci_conf[0x05] = 0x00; |
155 | 502a5395 | pbrook | pci_conf[0x06] = 0x00; |
156 | 502a5395 | pbrook | pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
157 | 502a5395 | pbrook | pci_conf[0x4c] = 0x4d; |
158 | 502a5395 | pbrook | pci_conf[0x4e] = 0x03; |
159 | 502a5395 | pbrook | pci_conf[0x4f] = 0x00; |
160 | 502a5395 | pbrook | pci_conf[0x60] = 0x80; |
161 | 502a5395 | pbrook | pci_conf[0x69] = 0x02; |
162 | 502a5395 | pbrook | pci_conf[0x70] = 0x80; |
163 | 502a5395 | pbrook | pci_conf[0x76] = 0x0c; |
164 | 502a5395 | pbrook | pci_conf[0x77] = 0x0c; |
165 | 502a5395 | pbrook | pci_conf[0x78] = 0x02; |
166 | 502a5395 | pbrook | pci_conf[0x79] = 0x00; |
167 | 502a5395 | pbrook | pci_conf[0x80] = 0x00; |
168 | 502a5395 | pbrook | pci_conf[0x82] = 0x00; |
169 | 502a5395 | pbrook | pci_conf[0xa0] = 0x08; |
170 | 502a5395 | pbrook | pci_conf[0xa0] = 0x08; |
171 | 502a5395 | pbrook | pci_conf[0xa2] = 0x00; |
172 | 502a5395 | pbrook | pci_conf[0xa3] = 0x00; |
173 | 502a5395 | pbrook | pci_conf[0xa4] = 0x00; |
174 | 502a5395 | pbrook | pci_conf[0xa5] = 0x00; |
175 | 502a5395 | pbrook | pci_conf[0xa6] = 0x00; |
176 | 502a5395 | pbrook | pci_conf[0xa7] = 0x00; |
177 | 502a5395 | pbrook | pci_conf[0xa8] = 0x0f; |
178 | 502a5395 | pbrook | pci_conf[0xaa] = 0x00; |
179 | 502a5395 | pbrook | pci_conf[0xab] = 0x00; |
180 | 502a5395 | pbrook | pci_conf[0xac] = 0x00; |
181 | 502a5395 | pbrook | pci_conf[0xae] = 0x00; |
182 | 502a5395 | pbrook | } |
183 | 502a5395 | pbrook | |
184 | 1941d19c | bellard | static void piix_save(QEMUFile* f, void *opaque) |
185 | 1941d19c | bellard | { |
186 | 1941d19c | bellard | PCIDevice *d = opaque; |
187 | 1941d19c | bellard | pci_device_save(d, f); |
188 | 1941d19c | bellard | } |
189 | 1941d19c | bellard | |
190 | 1941d19c | bellard | static int piix_load(QEMUFile* f, void *opaque, int version_id) |
191 | 1941d19c | bellard | { |
192 | 1941d19c | bellard | PCIDevice *d = opaque; |
193 | 1941d19c | bellard | if (version_id != 2) |
194 | 1941d19c | bellard | return -EINVAL;
|
195 | 1941d19c | bellard | return pci_device_load(d, f);
|
196 | 1941d19c | bellard | } |
197 | 1941d19c | bellard | |
198 | 502a5395 | pbrook | int piix3_init(PCIBus *bus)
|
199 | 502a5395 | pbrook | { |
200 | 502a5395 | pbrook | PCIDevice *d; |
201 | 502a5395 | pbrook | uint8_t *pci_conf; |
202 | 502a5395 | pbrook | |
203 | 502a5395 | pbrook | d = pci_register_device(bus, "PIIX3", sizeof(PCIDevice), |
204 | 502a5395 | pbrook | -1, NULL, NULL); |
205 | 1941d19c | bellard | register_savevm("PIIX3", 0, 2, piix_save, piix_load, d); |
206 | 502a5395 | pbrook | |
207 | 502a5395 | pbrook | piix3_dev = d; |
208 | 502a5395 | pbrook | pci_conf = d->config; |
209 | 502a5395 | pbrook | |
210 | 502a5395 | pbrook | pci_conf[0x00] = 0x86; // Intel |
211 | 502a5395 | pbrook | pci_conf[0x01] = 0x80; |
212 | 502a5395 | pbrook | pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
213 | 502a5395 | pbrook | pci_conf[0x03] = 0x70; |
214 | 502a5395 | pbrook | pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA |
215 | 502a5395 | pbrook | pci_conf[0x0b] = 0x06; // class_base = PCI_bridge |
216 | 502a5395 | pbrook | pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic |
217 | 502a5395 | pbrook | |
218 | 502a5395 | pbrook | piix3_reset(d); |
219 | 502a5395 | pbrook | return d->devfn;
|
220 | 502a5395 | pbrook | } |
221 | 502a5395 | pbrook | |
222 | 502a5395 | pbrook | /***********************************************************/
|
223 | 502a5395 | pbrook | /* XXX: the following should be moved to the PC BIOS */
|
224 | 502a5395 | pbrook | |
225 | 502a5395 | pbrook | static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
|
226 | 502a5395 | pbrook | { |
227 | 502a5395 | pbrook | return cpu_inb(NULL, addr); |
228 | 502a5395 | pbrook | } |
229 | 502a5395 | pbrook | |
230 | 502a5395 | pbrook | static void isa_outb(uint32_t val, uint32_t addr) |
231 | 502a5395 | pbrook | { |
232 | 502a5395 | pbrook | cpu_outb(NULL, addr, val);
|
233 | 502a5395 | pbrook | } |
234 | 502a5395 | pbrook | |
235 | 502a5395 | pbrook | static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
|
236 | 502a5395 | pbrook | { |
237 | 502a5395 | pbrook | return cpu_inw(NULL, addr); |
238 | 502a5395 | pbrook | } |
239 | 502a5395 | pbrook | |
240 | 502a5395 | pbrook | static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr) |
241 | 502a5395 | pbrook | { |
242 | 502a5395 | pbrook | cpu_outw(NULL, addr, val);
|
243 | 502a5395 | pbrook | } |
244 | 502a5395 | pbrook | |
245 | 502a5395 | pbrook | static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
|
246 | 502a5395 | pbrook | { |
247 | 502a5395 | pbrook | return cpu_inl(NULL, addr); |
248 | 502a5395 | pbrook | } |
249 | 502a5395 | pbrook | |
250 | 502a5395 | pbrook | static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr) |
251 | 502a5395 | pbrook | { |
252 | 502a5395 | pbrook | cpu_outl(NULL, addr, val);
|
253 | 502a5395 | pbrook | } |
254 | 502a5395 | pbrook | |
255 | 502a5395 | pbrook | static uint32_t pci_bios_io_addr;
|
256 | 502a5395 | pbrook | static uint32_t pci_bios_mem_addr;
|
257 | 502a5395 | pbrook | /* host irqs corresponding to PCI irqs A-D */
|
258 | 502a5395 | pbrook | static uint8_t pci_irqs[4] = { 11, 9, 11, 9 }; |
259 | 502a5395 | pbrook | |
260 | 502a5395 | pbrook | static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val) |
261 | 502a5395 | pbrook | { |
262 | 502a5395 | pbrook | PCIBus *s = d->bus; |
263 | 502a5395 | pbrook | addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
264 | 502a5395 | pbrook | pci_data_write(s, addr, val, 4);
|
265 | 502a5395 | pbrook | } |
266 | 502a5395 | pbrook | |
267 | 502a5395 | pbrook | static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val) |
268 | 502a5395 | pbrook | { |
269 | 502a5395 | pbrook | PCIBus *s = d->bus; |
270 | 502a5395 | pbrook | addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
271 | 502a5395 | pbrook | pci_data_write(s, addr, val, 2);
|
272 | 502a5395 | pbrook | } |
273 | 502a5395 | pbrook | |
274 | 502a5395 | pbrook | static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val) |
275 | 502a5395 | pbrook | { |
276 | 502a5395 | pbrook | PCIBus *s = d->bus; |
277 | 502a5395 | pbrook | addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
278 | 502a5395 | pbrook | pci_data_write(s, addr, val, 1);
|
279 | 502a5395 | pbrook | } |
280 | 502a5395 | pbrook | |
281 | 502a5395 | pbrook | static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
|
282 | 502a5395 | pbrook | { |
283 | 502a5395 | pbrook | PCIBus *s = d->bus; |
284 | 502a5395 | pbrook | addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
285 | 502a5395 | pbrook | return pci_data_read(s, addr, 4); |
286 | 502a5395 | pbrook | } |
287 | 502a5395 | pbrook | |
288 | 502a5395 | pbrook | static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
|
289 | 502a5395 | pbrook | { |
290 | 502a5395 | pbrook | PCIBus *s = d->bus; |
291 | 502a5395 | pbrook | addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
292 | 502a5395 | pbrook | return pci_data_read(s, addr, 2); |
293 | 502a5395 | pbrook | } |
294 | 502a5395 | pbrook | |
295 | 502a5395 | pbrook | static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
|
296 | 502a5395 | pbrook | { |
297 | 502a5395 | pbrook | PCIBus *s = d->bus; |
298 | 502a5395 | pbrook | addr |= (pci_bus_num(s) << 16) | (d->devfn << 8); |
299 | 502a5395 | pbrook | return pci_data_read(s, addr, 1); |
300 | 502a5395 | pbrook | } |
301 | 502a5395 | pbrook | |
302 | 502a5395 | pbrook | static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr) |
303 | 502a5395 | pbrook | { |
304 | 502a5395 | pbrook | PCIIORegion *r; |
305 | 502a5395 | pbrook | uint16_t cmd; |
306 | 502a5395 | pbrook | uint32_t ofs; |
307 | 502a5395 | pbrook | |
308 | 502a5395 | pbrook | if ( region_num == PCI_ROM_SLOT ) {
|
309 | 502a5395 | pbrook | ofs = 0x30;
|
310 | 502a5395 | pbrook | }else{
|
311 | 502a5395 | pbrook | ofs = 0x10 + region_num * 4; |
312 | 502a5395 | pbrook | } |
313 | 502a5395 | pbrook | |
314 | 502a5395 | pbrook | pci_config_writel(d, ofs, addr); |
315 | 502a5395 | pbrook | r = &d->io_regions[region_num]; |
316 | 502a5395 | pbrook | |
317 | 502a5395 | pbrook | /* enable memory mappings */
|
318 | 502a5395 | pbrook | cmd = pci_config_readw(d, PCI_COMMAND); |
319 | 502a5395 | pbrook | if ( region_num == PCI_ROM_SLOT )
|
320 | 502a5395 | pbrook | cmd |= 2;
|
321 | 502a5395 | pbrook | else if (r->type & PCI_ADDRESS_SPACE_IO) |
322 | 502a5395 | pbrook | cmd |= 1;
|
323 | 502a5395 | pbrook | else
|
324 | 502a5395 | pbrook | cmd |= 2;
|
325 | 502a5395 | pbrook | pci_config_writew(d, PCI_COMMAND, cmd); |
326 | 502a5395 | pbrook | } |
327 | 502a5395 | pbrook | |
328 | 502a5395 | pbrook | static void pci_bios_init_device(PCIDevice *d) |
329 | 502a5395 | pbrook | { |
330 | 502a5395 | pbrook | int class;
|
331 | 502a5395 | pbrook | PCIIORegion *r; |
332 | 502a5395 | pbrook | uint32_t *paddr; |
333 | 502a5395 | pbrook | int i, pin, pic_irq, vendor_id, device_id;
|
334 | 502a5395 | pbrook | |
335 | 502a5395 | pbrook | class = pci_config_readw(d, PCI_CLASS_DEVICE); |
336 | 502a5395 | pbrook | vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
337 | 502a5395 | pbrook | device_id = pci_config_readw(d, PCI_DEVICE_ID); |
338 | 502a5395 | pbrook | switch(class) {
|
339 | 502a5395 | pbrook | case 0x0101: |
340 | 502a5395 | pbrook | if (vendor_id == 0x8086 && device_id == 0x7010) { |
341 | 502a5395 | pbrook | /* PIIX3 IDE */
|
342 | 502a5395 | pbrook | pci_config_writew(d, 0x40, 0x8000); // enable IDE0 |
343 | 502a5395 | pbrook | pci_config_writew(d, 0x42, 0x8000); // enable IDE1 |
344 | 502a5395 | pbrook | goto default_map;
|
345 | 502a5395 | pbrook | } else {
|
346 | 502a5395 | pbrook | /* IDE: we map it as in ISA mode */
|
347 | 502a5395 | pbrook | pci_set_io_region_addr(d, 0, 0x1f0); |
348 | 502a5395 | pbrook | pci_set_io_region_addr(d, 1, 0x3f4); |
349 | 502a5395 | pbrook | pci_set_io_region_addr(d, 2, 0x170); |
350 | 502a5395 | pbrook | pci_set_io_region_addr(d, 3, 0x374); |
351 | 502a5395 | pbrook | } |
352 | 502a5395 | pbrook | break;
|
353 | 502a5395 | pbrook | case 0x0300: |
354 | 502a5395 | pbrook | if (vendor_id != 0x1234) |
355 | 502a5395 | pbrook | goto default_map;
|
356 | 502a5395 | pbrook | /* VGA: map frame buffer to default Bochs VBE address */
|
357 | 502a5395 | pbrook | pci_set_io_region_addr(d, 0, 0xE0000000); |
358 | 502a5395 | pbrook | break;
|
359 | 502a5395 | pbrook | case 0x0800: |
360 | 502a5395 | pbrook | /* PIC */
|
361 | 502a5395 | pbrook | vendor_id = pci_config_readw(d, PCI_VENDOR_ID); |
362 | 502a5395 | pbrook | device_id = pci_config_readw(d, PCI_DEVICE_ID); |
363 | 502a5395 | pbrook | if (vendor_id == 0x1014) { |
364 | 502a5395 | pbrook | /* IBM */
|
365 | 502a5395 | pbrook | if (device_id == 0x0046 || device_id == 0xFFFF) { |
366 | 502a5395 | pbrook | /* MPIC & MPIC2 */
|
367 | 502a5395 | pbrook | pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000); |
368 | 502a5395 | pbrook | } |
369 | 502a5395 | pbrook | } |
370 | 502a5395 | pbrook | break;
|
371 | 502a5395 | pbrook | case 0xff00: |
372 | 502a5395 | pbrook | if (vendor_id == 0x0106b && |
373 | 502a5395 | pbrook | (device_id == 0x0017 || device_id == 0x0022)) { |
374 | 502a5395 | pbrook | /* macio bridge */
|
375 | 502a5395 | pbrook | pci_set_io_region_addr(d, 0, 0x80800000); |
376 | 502a5395 | pbrook | } |
377 | 502a5395 | pbrook | break;
|
378 | 502a5395 | pbrook | default:
|
379 | 502a5395 | pbrook | default_map:
|
380 | 502a5395 | pbrook | /* default memory mappings */
|
381 | 502a5395 | pbrook | for(i = 0; i < PCI_NUM_REGIONS; i++) { |
382 | 502a5395 | pbrook | r = &d->io_regions[i]; |
383 | 502a5395 | pbrook | if (r->size) {
|
384 | 502a5395 | pbrook | if (r->type & PCI_ADDRESS_SPACE_IO)
|
385 | 502a5395 | pbrook | paddr = &pci_bios_io_addr; |
386 | 502a5395 | pbrook | else
|
387 | 502a5395 | pbrook | paddr = &pci_bios_mem_addr; |
388 | 502a5395 | pbrook | *paddr = (*paddr + r->size - 1) & ~(r->size - 1); |
389 | 502a5395 | pbrook | pci_set_io_region_addr(d, i, *paddr); |
390 | 502a5395 | pbrook | *paddr += r->size; |
391 | 502a5395 | pbrook | } |
392 | 502a5395 | pbrook | } |
393 | 502a5395 | pbrook | break;
|
394 | 502a5395 | pbrook | } |
395 | 502a5395 | pbrook | |
396 | 502a5395 | pbrook | /* map the interrupt */
|
397 | 502a5395 | pbrook | pin = pci_config_readb(d, PCI_INTERRUPT_PIN); |
398 | 502a5395 | pbrook | if (pin != 0) { |
399 | 502a5395 | pbrook | pin = pci_slot_get_pirq(d, pin - 1);
|
400 | 502a5395 | pbrook | pic_irq = pci_irqs[pin]; |
401 | 502a5395 | pbrook | pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq); |
402 | 502a5395 | pbrook | } |
403 | 502a5395 | pbrook | } |
404 | 502a5395 | pbrook | |
405 | 502a5395 | pbrook | /*
|
406 | 502a5395 | pbrook | * This function initializes the PCI devices as a normal PCI BIOS
|
407 | 502a5395 | pbrook | * would do. It is provided just in case the BIOS has no support for
|
408 | 502a5395 | pbrook | * PCI.
|
409 | 502a5395 | pbrook | */
|
410 | 502a5395 | pbrook | void pci_bios_init(void) |
411 | 502a5395 | pbrook | { |
412 | 502a5395 | pbrook | int i, irq;
|
413 | 502a5395 | pbrook | uint8_t elcr[2];
|
414 | 502a5395 | pbrook | |
415 | 502a5395 | pbrook | pci_bios_io_addr = 0xc000;
|
416 | 502a5395 | pbrook | pci_bios_mem_addr = 0xf0000000;
|
417 | 502a5395 | pbrook | |
418 | 502a5395 | pbrook | /* activate IRQ mappings */
|
419 | 502a5395 | pbrook | elcr[0] = 0x00; |
420 | 502a5395 | pbrook | elcr[1] = 0x00; |
421 | 502a5395 | pbrook | for(i = 0; i < 4; i++) { |
422 | 502a5395 | pbrook | irq = pci_irqs[i]; |
423 | 502a5395 | pbrook | /* set to trigger level */
|
424 | 502a5395 | pbrook | elcr[irq >> 3] |= (1 << (irq & 7)); |
425 | 502a5395 | pbrook | /* activate irq remapping in PIIX */
|
426 | 502a5395 | pbrook | pci_config_writeb(piix3_dev, 0x60 + i, irq);
|
427 | 502a5395 | pbrook | } |
428 | 502a5395 | pbrook | isa_outb(elcr[0], 0x4d0); |
429 | 502a5395 | pbrook | isa_outb(elcr[1], 0x4d1); |
430 | 502a5395 | pbrook | |
431 | 502a5395 | pbrook | pci_for_each_device(pci_bios_init_device); |
432 | 502a5395 | pbrook | } |