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# Date Author Comment
b8132eff 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement RST3 group

- access to Special Registers (wsr, rsr);
- access to User Registers (wur, rur);
- misc. operations option (value clamp, sign extension, min, max);
- conditional moves.

Signed-off-by: Max Filippov <>...
3580ecad 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement shifts (ST1 and RST1 groups)

- ST1: SAR (shift amount special register) manipulation, NSA;
- RST1: shifts, 16-bit multiplication.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
809377aa 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement LSAI group

- base + offset load/store operations for 1/2/4 byte values;
- cache operations (not implemented);
- multiprocessor synchronization operations.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
91a5bb76 09/10/2011 07:57 pm Max Filippov

target-xtensa: mark reserved and TBD opcodes

Reserved opcodes must generate illegal instruction exception. Usually
they signal emulation quality problems.
Not implemented opcodes are good to see.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
28067b22 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement SYNC group

All operations in this group are no-ops, because there are no delayed
side effects.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
8ffc2d0d 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement CACHE group

All operations in this group are no-ops, because cache ought to be
transparent to applications. However cache may be abused, then we'll
need to actually implement these opcodes.

Signed-off-by: Max Filippov <>...
bd57fb91 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement conditional jumps

- BZ (comparison to zero);
- BI0 (comparison to signed immediate);
- BI1 (comparison to unsigned immediate);
- B (two registers comparison, bit sets comparison);
- BEQZ.N/BNEZ.N (narrow comparison to zero).

Signed-off-by: Max Filippov <>...
5da4a6a8 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement JX/RET0/CALLX

Group SNM0 (indirect jumps and calls).

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
2af3da91 09/10/2011 07:57 pm Max Filippov

target-xtensa: add special and user registers

Special Registers hold the majority of the state added to the processor
by the options. See ISA, 5.3 for details.

User Registers hold state added in support of designer's TIE and in some
cases of options that Tensilica provides. See ISA, 5.4 for details....
2328826b 09/10/2011 07:57 pm Max Filippov

target-xtensa: add target stubs

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
dedc5eae 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement disas_xtensa_insn

Set up disas_xtensa_insn switch structure, mark required options on high
level groups. Implement arithmetic/bit logic/jump/call0.

Implement code generation loop with single step/breakpoint checking.

Signed-off-by: Max Filippov <>...
67882fd1 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement narrow instructions

Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>
f331fe5e 09/10/2011 07:57 pm Max Filippov

target-xtensa: implement RT0 group

NEG and ABS are the only members of RT0 group.

Signed-off-by: Max Filippov <>
Signed-off-by: Blue Swirl <>