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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation micro-operations for qemu.
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3 | 79aceca5 | bellard | *
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4 | 3fc6c082 | bellard | * Copyright (c) 2003-2005 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | |
21 | a541f297 | bellard | //#define DEBUG_OP
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22 | a541f297 | bellard | |
23 | 79aceca5 | bellard | #include "config.h" |
24 | 79aceca5 | bellard | #include "exec.h" |
25 | 79aceca5 | bellard | |
26 | 79aceca5 | bellard | #define regs (env)
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27 | 79aceca5 | bellard | #define Ts0 (int32_t)T0
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28 | 79aceca5 | bellard | #define Ts1 (int32_t)T1
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29 | 79aceca5 | bellard | #define Ts2 (int32_t)T2
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30 | 79aceca5 | bellard | |
31 | 28b6751f | bellard | #define FT0 (env->ft0)
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32 | fb0eaffc | bellard | #define FT1 (env->ft1)
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33 | fb0eaffc | bellard | #define FT2 (env->ft2)
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34 | fb0eaffc | bellard | |
35 | 9a64fbe4 | bellard | #define PPC_OP(name) void glue(op_, name)(void) |
36 | 79aceca5 | bellard | |
37 | 28b6751f | bellard | #define REG 0 |
38 | 28b6751f | bellard | #include "op_template.h" |
39 | 28b6751f | bellard | |
40 | 28b6751f | bellard | #define REG 1 |
41 | 28b6751f | bellard | #include "op_template.h" |
42 | 28b6751f | bellard | |
43 | 28b6751f | bellard | #define REG 2 |
44 | 28b6751f | bellard | #include "op_template.h" |
45 | 28b6751f | bellard | |
46 | 28b6751f | bellard | #define REG 3 |
47 | 28b6751f | bellard | #include "op_template.h" |
48 | 28b6751f | bellard | |
49 | 28b6751f | bellard | #define REG 4 |
50 | 28b6751f | bellard | #include "op_template.h" |
51 | 28b6751f | bellard | |
52 | 28b6751f | bellard | #define REG 5 |
53 | 28b6751f | bellard | #include "op_template.h" |
54 | 28b6751f | bellard | |
55 | 28b6751f | bellard | #define REG 6 |
56 | 28b6751f | bellard | #include "op_template.h" |
57 | 28b6751f | bellard | |
58 | 28b6751f | bellard | #define REG 7 |
59 | 28b6751f | bellard | #include "op_template.h" |
60 | 28b6751f | bellard | |
61 | 28b6751f | bellard | #define REG 8 |
62 | 28b6751f | bellard | #include "op_template.h" |
63 | 28b6751f | bellard | |
64 | 28b6751f | bellard | #define REG 9 |
65 | 28b6751f | bellard | #include "op_template.h" |
66 | 28b6751f | bellard | |
67 | 28b6751f | bellard | #define REG 10 |
68 | 28b6751f | bellard | #include "op_template.h" |
69 | 28b6751f | bellard | |
70 | 28b6751f | bellard | #define REG 11 |
71 | 28b6751f | bellard | #include "op_template.h" |
72 | 28b6751f | bellard | |
73 | 28b6751f | bellard | #define REG 12 |
74 | 28b6751f | bellard | #include "op_template.h" |
75 | 28b6751f | bellard | |
76 | 28b6751f | bellard | #define REG 13 |
77 | 28b6751f | bellard | #include "op_template.h" |
78 | 28b6751f | bellard | |
79 | 28b6751f | bellard | #define REG 14 |
80 | 28b6751f | bellard | #include "op_template.h" |
81 | 28b6751f | bellard | |
82 | 28b6751f | bellard | #define REG 15 |
83 | 28b6751f | bellard | #include "op_template.h" |
84 | 28b6751f | bellard | |
85 | 28b6751f | bellard | #define REG 16 |
86 | 28b6751f | bellard | #include "op_template.h" |
87 | 28b6751f | bellard | |
88 | 28b6751f | bellard | #define REG 17 |
89 | 28b6751f | bellard | #include "op_template.h" |
90 | 28b6751f | bellard | |
91 | 28b6751f | bellard | #define REG 18 |
92 | 28b6751f | bellard | #include "op_template.h" |
93 | 28b6751f | bellard | |
94 | 28b6751f | bellard | #define REG 19 |
95 | 28b6751f | bellard | #include "op_template.h" |
96 | 28b6751f | bellard | |
97 | 28b6751f | bellard | #define REG 20 |
98 | 28b6751f | bellard | #include "op_template.h" |
99 | 28b6751f | bellard | |
100 | 28b6751f | bellard | #define REG 21 |
101 | 28b6751f | bellard | #include "op_template.h" |
102 | 28b6751f | bellard | |
103 | 28b6751f | bellard | #define REG 22 |
104 | 28b6751f | bellard | #include "op_template.h" |
105 | 28b6751f | bellard | |
106 | 28b6751f | bellard | #define REG 23 |
107 | 28b6751f | bellard | #include "op_template.h" |
108 | 28b6751f | bellard | |
109 | 28b6751f | bellard | #define REG 24 |
110 | 28b6751f | bellard | #include "op_template.h" |
111 | 28b6751f | bellard | |
112 | 28b6751f | bellard | #define REG 25 |
113 | 28b6751f | bellard | #include "op_template.h" |
114 | 28b6751f | bellard | |
115 | 28b6751f | bellard | #define REG 26 |
116 | 28b6751f | bellard | #include "op_template.h" |
117 | 28b6751f | bellard | |
118 | 28b6751f | bellard | #define REG 27 |
119 | 28b6751f | bellard | #include "op_template.h" |
120 | 28b6751f | bellard | |
121 | 28b6751f | bellard | #define REG 28 |
122 | 28b6751f | bellard | #include "op_template.h" |
123 | 28b6751f | bellard | |
124 | 28b6751f | bellard | #define REG 29 |
125 | 28b6751f | bellard | #include "op_template.h" |
126 | 28b6751f | bellard | |
127 | 28b6751f | bellard | #define REG 30 |
128 | 28b6751f | bellard | #include "op_template.h" |
129 | 28b6751f | bellard | |
130 | 28b6751f | bellard | #define REG 31 |
131 | 28b6751f | bellard | #include "op_template.h" |
132 | 28b6751f | bellard | |
133 | 3fc6c082 | bellard | /* PowerPC state maintenance operations */
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134 | 79aceca5 | bellard | /* set_Rc0 */
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135 | 79aceca5 | bellard | PPC_OP(set_Rc0) |
136 | 79aceca5 | bellard | { |
137 | 79aceca5 | bellard | uint32_t tmp; |
138 | 79aceca5 | bellard | |
139 | 79aceca5 | bellard | if (Ts0 < 0) { |
140 | 79aceca5 | bellard | tmp = 0x08;
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141 | 79aceca5 | bellard | } else if (Ts0 > 0) { |
142 | 79aceca5 | bellard | tmp = 0x04;
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143 | 79aceca5 | bellard | } else {
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144 | 79aceca5 | bellard | tmp = 0x02;
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145 | 79aceca5 | bellard | } |
146 | 79aceca5 | bellard | tmp |= xer_ov; |
147 | 9a64fbe4 | bellard | env->crf[0] = tmp;
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148 | 79aceca5 | bellard | RETURN(); |
149 | 79aceca5 | bellard | } |
150 | 79aceca5 | bellard | |
151 | 79aceca5 | bellard | /* reset_Rc0 */
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152 | 79aceca5 | bellard | PPC_OP(reset_Rc0) |
153 | 79aceca5 | bellard | { |
154 | 9a64fbe4 | bellard | env->crf[0] = 0x02 | xer_ov; |
155 | 79aceca5 | bellard | RETURN(); |
156 | 79aceca5 | bellard | } |
157 | 79aceca5 | bellard | |
158 | 79aceca5 | bellard | /* set_Rc0_1 */
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159 | 79aceca5 | bellard | PPC_OP(set_Rc0_1) |
160 | 79aceca5 | bellard | { |
161 | 9a64fbe4 | bellard | env->crf[0] = 0x04 | xer_ov; |
162 | 79aceca5 | bellard | RETURN(); |
163 | 79aceca5 | bellard | } |
164 | 79aceca5 | bellard | |
165 | fb0eaffc | bellard | /* Set Rc1 (for floating point arithmetic) */
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166 | fb0eaffc | bellard | PPC_OP(set_Rc1) |
167 | fb0eaffc | bellard | { |
168 | fb0eaffc | bellard | env->crf[1] = regs->fpscr[7]; |
169 | fb0eaffc | bellard | RETURN(); |
170 | fb0eaffc | bellard | } |
171 | fb0eaffc | bellard | |
172 | 9a64fbe4 | bellard | /* Constants load */
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173 | 79aceca5 | bellard | PPC_OP(set_T0) |
174 | 79aceca5 | bellard | { |
175 | 79aceca5 | bellard | T0 = PARAM(1);
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176 | 79aceca5 | bellard | RETURN(); |
177 | 79aceca5 | bellard | } |
178 | 79aceca5 | bellard | |
179 | 79aceca5 | bellard | PPC_OP(set_T1) |
180 | 79aceca5 | bellard | { |
181 | 79aceca5 | bellard | T1 = PARAM(1);
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182 | 79aceca5 | bellard | RETURN(); |
183 | 79aceca5 | bellard | } |
184 | 79aceca5 | bellard | |
185 | 79aceca5 | bellard | PPC_OP(set_T2) |
186 | 79aceca5 | bellard | { |
187 | 79aceca5 | bellard | T2 = PARAM(1);
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188 | 79aceca5 | bellard | RETURN(); |
189 | 79aceca5 | bellard | } |
190 | 79aceca5 | bellard | |
191 | 9a64fbe4 | bellard | /* Generate exceptions */
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192 | 9fddaa0c | bellard | PPC_OP(raise_exception_err) |
193 | 79aceca5 | bellard | { |
194 | 9fddaa0c | bellard | do_raise_exception_err(PARAM(1), PARAM(2)); |
195 | 9a64fbe4 | bellard | } |
196 | 9a64fbe4 | bellard | |
197 | 9fddaa0c | bellard | PPC_OP(raise_exception) |
198 | 9a64fbe4 | bellard | { |
199 | 9fddaa0c | bellard | do_raise_exception(PARAM(1));
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200 | 9a64fbe4 | bellard | } |
201 | 9a64fbe4 | bellard | |
202 | 9fddaa0c | bellard | PPC_OP(update_nip) |
203 | 9a64fbe4 | bellard | { |
204 | 004bc62c | bellard | env->nip = PARAM(1);
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205 | 9a64fbe4 | bellard | } |
206 | 9a64fbe4 | bellard | |
207 | ea4e754f | bellard | PPC_OP(debug) |
208 | ea4e754f | bellard | { |
209 | ea4e754f | bellard | do_raise_exception(EXCP_DEBUG); |
210 | ea4e754f | bellard | } |
211 | ea4e754f | bellard | |
212 | 9a64fbe4 | bellard | /* Segment registers load and store with immediate index */
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213 | 9a64fbe4 | bellard | PPC_OP(load_srin) |
214 | 9a64fbe4 | bellard | { |
215 | 9a64fbe4 | bellard | T0 = regs->sr[T1 >> 28];
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216 | 9a64fbe4 | bellard | RETURN(); |
217 | 9a64fbe4 | bellard | } |
218 | 9a64fbe4 | bellard | |
219 | 9a64fbe4 | bellard | PPC_OP(store_srin) |
220 | 9a64fbe4 | bellard | { |
221 | 3fc6c082 | bellard | do_store_sr(env, ((uint32_t)T1 >> 28), T0);
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222 | 9a64fbe4 | bellard | RETURN(); |
223 | 9a64fbe4 | bellard | } |
224 | 9a64fbe4 | bellard | |
225 | 9a64fbe4 | bellard | PPC_OP(load_sdr1) |
226 | 9a64fbe4 | bellard | { |
227 | 9a64fbe4 | bellard | T0 = regs->sdr1; |
228 | 79aceca5 | bellard | RETURN(); |
229 | 79aceca5 | bellard | } |
230 | 79aceca5 | bellard | |
231 | 9a64fbe4 | bellard | PPC_OP(store_sdr1) |
232 | 79aceca5 | bellard | { |
233 | 3fc6c082 | bellard | do_store_sdr1(env, T0); |
234 | 79aceca5 | bellard | RETURN(); |
235 | 79aceca5 | bellard | } |
236 | 79aceca5 | bellard | |
237 | 79aceca5 | bellard | PPC_OP(exit_tb) |
238 | 79aceca5 | bellard | { |
239 | 79aceca5 | bellard | EXIT_TB(); |
240 | 79aceca5 | bellard | } |
241 | 79aceca5 | bellard | |
242 | 9a64fbe4 | bellard | /* Load/store special registers */
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243 | 79aceca5 | bellard | PPC_OP(load_cr) |
244 | 79aceca5 | bellard | { |
245 | 3fc6c082 | bellard | T0 = do_load_cr(env); |
246 | 79aceca5 | bellard | RETURN(); |
247 | 79aceca5 | bellard | } |
248 | 79aceca5 | bellard | |
249 | 79aceca5 | bellard | PPC_OP(store_cr) |
250 | 79aceca5 | bellard | { |
251 | 3fc6c082 | bellard | do_store_cr(env, T0, PARAM(1));
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252 | 79aceca5 | bellard | RETURN(); |
253 | 79aceca5 | bellard | } |
254 | 79aceca5 | bellard | |
255 | 79aceca5 | bellard | PPC_OP(load_xer_cr) |
256 | 79aceca5 | bellard | { |
257 | 79aceca5 | bellard | T0 = (xer_so << 3) | (xer_ov << 2) | (xer_ca << 1); |
258 | 79aceca5 | bellard | RETURN(); |
259 | 79aceca5 | bellard | } |
260 | 79aceca5 | bellard | |
261 | 79aceca5 | bellard | PPC_OP(clear_xer_cr) |
262 | 79aceca5 | bellard | { |
263 | 79aceca5 | bellard | xer_so = 0;
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264 | 79aceca5 | bellard | xer_ov = 0;
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265 | 79aceca5 | bellard | xer_ca = 0;
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266 | 79aceca5 | bellard | RETURN(); |
267 | 79aceca5 | bellard | } |
268 | 79aceca5 | bellard | |
269 | 79aceca5 | bellard | PPC_OP(load_xer_bc) |
270 | 79aceca5 | bellard | { |
271 | 9a64fbe4 | bellard | T1 = xer_bc; |
272 | 79aceca5 | bellard | RETURN(); |
273 | 79aceca5 | bellard | } |
274 | 79aceca5 | bellard | |
275 | 79aceca5 | bellard | PPC_OP(load_xer) |
276 | 79aceca5 | bellard | { |
277 | 3fc6c082 | bellard | T0 = do_load_xer(env); |
278 | 79aceca5 | bellard | RETURN(); |
279 | 79aceca5 | bellard | } |
280 | 79aceca5 | bellard | |
281 | 79aceca5 | bellard | PPC_OP(store_xer) |
282 | 79aceca5 | bellard | { |
283 | 3fc6c082 | bellard | do_store_xer(env, T0); |
284 | 79aceca5 | bellard | RETURN(); |
285 | 79aceca5 | bellard | } |
286 | 79aceca5 | bellard | |
287 | 79aceca5 | bellard | PPC_OP(load_msr) |
288 | 79aceca5 | bellard | { |
289 | 3fc6c082 | bellard | T0 = do_load_msr(env); |
290 | 79aceca5 | bellard | RETURN(); |
291 | 79aceca5 | bellard | } |
292 | 79aceca5 | bellard | |
293 | 79aceca5 | bellard | PPC_OP(store_msr) |
294 | 79aceca5 | bellard | { |
295 | 3fc6c082 | bellard | do_store_msr(env, T0); |
296 | 9a64fbe4 | bellard | RETURN(); |
297 | 9a64fbe4 | bellard | } |
298 | 9a64fbe4 | bellard | |
299 | 9a64fbe4 | bellard | /* SPR */
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300 | 9a64fbe4 | bellard | PPC_OP(load_spr) |
301 | 9a64fbe4 | bellard | { |
302 | 9a64fbe4 | bellard | T0 = regs->spr[PARAM(1)];
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303 | 9a64fbe4 | bellard | RETURN(); |
304 | 9a64fbe4 | bellard | } |
305 | 9a64fbe4 | bellard | |
306 | 9a64fbe4 | bellard | PPC_OP(store_spr) |
307 | 9a64fbe4 | bellard | { |
308 | 9a64fbe4 | bellard | regs->spr[PARAM(1)] = T0;
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309 | 79aceca5 | bellard | RETURN(); |
310 | 79aceca5 | bellard | } |
311 | 79aceca5 | bellard | |
312 | 79aceca5 | bellard | PPC_OP(load_lr) |
313 | 79aceca5 | bellard | { |
314 | 9a64fbe4 | bellard | T0 = regs->lr; |
315 | 9a64fbe4 | bellard | RETURN(); |
316 | 9a64fbe4 | bellard | } |
317 | 9a64fbe4 | bellard | |
318 | 9a64fbe4 | bellard | PPC_OP(store_lr) |
319 | 9a64fbe4 | bellard | { |
320 | 9a64fbe4 | bellard | regs->lr = T0; |
321 | 9a64fbe4 | bellard | RETURN(); |
322 | 9a64fbe4 | bellard | } |
323 | 9a64fbe4 | bellard | |
324 | 9a64fbe4 | bellard | PPC_OP(load_ctr) |
325 | 9a64fbe4 | bellard | { |
326 | 9a64fbe4 | bellard | T0 = regs->ctr; |
327 | 9a64fbe4 | bellard | RETURN(); |
328 | 9a64fbe4 | bellard | } |
329 | 9a64fbe4 | bellard | |
330 | 9a64fbe4 | bellard | PPC_OP(store_ctr) |
331 | 9a64fbe4 | bellard | { |
332 | 9a64fbe4 | bellard | regs->ctr = T0; |
333 | 9a64fbe4 | bellard | RETURN(); |
334 | 9a64fbe4 | bellard | } |
335 | 9a64fbe4 | bellard | |
336 | 9fddaa0c | bellard | PPC_OP(load_tbl) |
337 | 9a64fbe4 | bellard | { |
338 | 9fddaa0c | bellard | T0 = cpu_ppc_load_tbl(regs); |
339 | 9a64fbe4 | bellard | RETURN(); |
340 | 9a64fbe4 | bellard | } |
341 | 9a64fbe4 | bellard | |
342 | 9fddaa0c | bellard | PPC_OP(load_tbu) |
343 | 9a64fbe4 | bellard | { |
344 | 9fddaa0c | bellard | T0 = cpu_ppc_load_tbu(regs); |
345 | 9a64fbe4 | bellard | RETURN(); |
346 | 9a64fbe4 | bellard | } |
347 | 9a64fbe4 | bellard | |
348 | 9fddaa0c | bellard | PPC_OP(store_tbl) |
349 | 9a64fbe4 | bellard | { |
350 | 9fddaa0c | bellard | cpu_ppc_store_tbl(regs, T0); |
351 | 79aceca5 | bellard | RETURN(); |
352 | 79aceca5 | bellard | } |
353 | 79aceca5 | bellard | |
354 | 9fddaa0c | bellard | PPC_OP(store_tbu) |
355 | 9a64fbe4 | bellard | { |
356 | 9fddaa0c | bellard | cpu_ppc_store_tbu(regs, T0); |
357 | 9a64fbe4 | bellard | RETURN(); |
358 | 9a64fbe4 | bellard | } |
359 | 9a64fbe4 | bellard | |
360 | 9fddaa0c | bellard | PPC_OP(load_decr) |
361 | 9a64fbe4 | bellard | { |
362 | 9fddaa0c | bellard | T0 = cpu_ppc_load_decr(regs); |
363 | 9a64fbe4 | bellard | } |
364 | 9fddaa0c | bellard | |
365 | 9fddaa0c | bellard | PPC_OP(store_decr) |
366 | 9fddaa0c | bellard | { |
367 | 9fddaa0c | bellard | cpu_ppc_store_decr(regs, T0); |
368 | 9a64fbe4 | bellard | RETURN(); |
369 | 9a64fbe4 | bellard | } |
370 | 9a64fbe4 | bellard | |
371 | 9a64fbe4 | bellard | PPC_OP(load_ibat) |
372 | 9a64fbe4 | bellard | { |
373 | 9a64fbe4 | bellard | T0 = regs->IBAT[PARAM(1)][PARAM(2)]; |
374 | 9a64fbe4 | bellard | } |
375 | 9a64fbe4 | bellard | |
376 | 3fc6c082 | bellard | void op_store_ibatu (void) |
377 | 9a64fbe4 | bellard | { |
378 | 3fc6c082 | bellard | do_store_ibatu(env, PARAM1, T0); |
379 | 3fc6c082 | bellard | RETURN(); |
380 | 3fc6c082 | bellard | } |
381 | 3fc6c082 | bellard | |
382 | 3fc6c082 | bellard | void op_store_ibatl (void) |
383 | 3fc6c082 | bellard | { |
384 | 3fc6c082 | bellard | #if 1 |
385 | 3fc6c082 | bellard | env->IBAT[1][PARAM1] = T0;
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386 | 3fc6c082 | bellard | #else
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387 | 3fc6c082 | bellard | do_store_ibatl(env, PARAM1, T0); |
388 | 3fc6c082 | bellard | #endif
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389 | 3fc6c082 | bellard | RETURN(); |
390 | 9a64fbe4 | bellard | } |
391 | 9a64fbe4 | bellard | |
392 | 9a64fbe4 | bellard | PPC_OP(load_dbat) |
393 | 9a64fbe4 | bellard | { |
394 | 9a64fbe4 | bellard | T0 = regs->DBAT[PARAM(1)][PARAM(2)]; |
395 | 9a64fbe4 | bellard | } |
396 | 9a64fbe4 | bellard | |
397 | 3fc6c082 | bellard | void op_store_dbatu (void) |
398 | 3fc6c082 | bellard | { |
399 | 3fc6c082 | bellard | do_store_dbatu(env, PARAM1, T0); |
400 | 3fc6c082 | bellard | RETURN(); |
401 | 3fc6c082 | bellard | } |
402 | 3fc6c082 | bellard | |
403 | 3fc6c082 | bellard | void op_store_dbatl (void) |
404 | 9a64fbe4 | bellard | { |
405 | 3fc6c082 | bellard | #if 1 |
406 | 3fc6c082 | bellard | env->DBAT[1][PARAM1] = T0;
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407 | 3fc6c082 | bellard | #else
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408 | 3fc6c082 | bellard | do_store_dbatl(env, PARAM1, T0); |
409 | 3fc6c082 | bellard | #endif
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410 | 3fc6c082 | bellard | RETURN(); |
411 | 9a64fbe4 | bellard | } |
412 | 9a64fbe4 | bellard | |
413 | fb0eaffc | bellard | /* FPSCR */
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414 | fb0eaffc | bellard | PPC_OP(load_fpscr) |
415 | fb0eaffc | bellard | { |
416 | 3fc6c082 | bellard | FT0 = do_load_fpscr(env); |
417 | fb0eaffc | bellard | RETURN(); |
418 | fb0eaffc | bellard | } |
419 | fb0eaffc | bellard | |
420 | fb0eaffc | bellard | PPC_OP(store_fpscr) |
421 | fb0eaffc | bellard | { |
422 | 3fc6c082 | bellard | do_store_fpscr(env, FT0, PARAM1); |
423 | fb0eaffc | bellard | RETURN(); |
424 | fb0eaffc | bellard | } |
425 | fb0eaffc | bellard | |
426 | fb0eaffc | bellard | PPC_OP(reset_scrfx) |
427 | fb0eaffc | bellard | { |
428 | fb0eaffc | bellard | regs->fpscr[7] &= ~0x8; |
429 | fb0eaffc | bellard | RETURN(); |
430 | fb0eaffc | bellard | } |
431 | fb0eaffc | bellard | |
432 | 79aceca5 | bellard | /* crf operations */
|
433 | 79aceca5 | bellard | PPC_OP(getbit_T0) |
434 | 79aceca5 | bellard | { |
435 | 79aceca5 | bellard | T0 = (T0 >> PARAM(1)) & 1; |
436 | 79aceca5 | bellard | RETURN(); |
437 | 79aceca5 | bellard | } |
438 | 79aceca5 | bellard | |
439 | 79aceca5 | bellard | PPC_OP(getbit_T1) |
440 | 79aceca5 | bellard | { |
441 | 79aceca5 | bellard | T1 = (T1 >> PARAM(1)) & 1; |
442 | 79aceca5 | bellard | RETURN(); |
443 | 79aceca5 | bellard | } |
444 | 79aceca5 | bellard | |
445 | 79aceca5 | bellard | PPC_OP(setcrfbit) |
446 | 79aceca5 | bellard | { |
447 | 79aceca5 | bellard | T1 = (T1 & PARAM(1)) | (T0 << PARAM(2)); |
448 | 79aceca5 | bellard | RETURN(); |
449 | 79aceca5 | bellard | } |
450 | 79aceca5 | bellard | |
451 | 79aceca5 | bellard | /* Branch */
|
452 | 9a64fbe4 | bellard | #define EIP regs->nip
|
453 | 9a64fbe4 | bellard | |
454 | e98a6e40 | bellard | PPC_OP(setlr) |
455 | e98a6e40 | bellard | { |
456 | e98a6e40 | bellard | regs->lr = PARAM1; |
457 | e98a6e40 | bellard | } |
458 | e98a6e40 | bellard | |
459 | c53be334 | bellard | PPC_OP(goto_tb0) |
460 | e98a6e40 | bellard | { |
461 | c53be334 | bellard | GOTO_TB(op_goto_tb0, PARAM1, 0);
|
462 | c53be334 | bellard | } |
463 | c53be334 | bellard | |
464 | c53be334 | bellard | PPC_OP(goto_tb1) |
465 | c53be334 | bellard | { |
466 | c53be334 | bellard | GOTO_TB(op_goto_tb1, PARAM1, 1);
|
467 | e98a6e40 | bellard | } |
468 | e98a6e40 | bellard | |
469 | e98a6e40 | bellard | PPC_OP(b_T1) |
470 | e98a6e40 | bellard | { |
471 | 89934337 | bellard | regs->nip = T1 & ~3;
|
472 | e98a6e40 | bellard | } |
473 | e98a6e40 | bellard | |
474 | c53be334 | bellard | PPC_OP(jz_T0) |
475 | e98a6e40 | bellard | { |
476 | c53be334 | bellard | if (!T0)
|
477 | c53be334 | bellard | GOTO_LABEL_PARAM(1);
|
478 | e98a6e40 | bellard | RETURN(); |
479 | e98a6e40 | bellard | } |
480 | e98a6e40 | bellard | |
481 | e98a6e40 | bellard | PPC_OP(btest_T1) |
482 | e98a6e40 | bellard | { |
483 | e98a6e40 | bellard | if (T0) {
|
484 | e98a6e40 | bellard | regs->nip = T1 & ~3;
|
485 | e98a6e40 | bellard | } else {
|
486 | e98a6e40 | bellard | regs->nip = PARAM1; |
487 | e98a6e40 | bellard | } |
488 | e98a6e40 | bellard | RETURN(); |
489 | e98a6e40 | bellard | } |
490 | e98a6e40 | bellard | |
491 | e98a6e40 | bellard | PPC_OP(movl_T1_ctr) |
492 | e98a6e40 | bellard | { |
493 | e98a6e40 | bellard | T1 = regs->ctr; |
494 | e98a6e40 | bellard | } |
495 | e98a6e40 | bellard | |
496 | e98a6e40 | bellard | PPC_OP(movl_T1_lr) |
497 | e98a6e40 | bellard | { |
498 | e98a6e40 | bellard | T1 = regs->lr; |
499 | e98a6e40 | bellard | } |
500 | e98a6e40 | bellard | |
501 | e98a6e40 | bellard | /* tests with result in T0 */
|
502 | e98a6e40 | bellard | |
503 | e98a6e40 | bellard | PPC_OP(test_ctr) |
504 | e98a6e40 | bellard | { |
505 | b88e4a9a | bellard | T0 = regs->ctr; |
506 | e98a6e40 | bellard | } |
507 | e98a6e40 | bellard | |
508 | e98a6e40 | bellard | PPC_OP(test_ctr_true) |
509 | e98a6e40 | bellard | { |
510 | e98a6e40 | bellard | T0 = (regs->ctr != 0 && (T0 & PARAM(1)) != 0); |
511 | e98a6e40 | bellard | } |
512 | e98a6e40 | bellard | |
513 | e98a6e40 | bellard | PPC_OP(test_ctr_false) |
514 | e98a6e40 | bellard | { |
515 | e98a6e40 | bellard | T0 = (regs->ctr != 0 && (T0 & PARAM(1)) == 0); |
516 | e98a6e40 | bellard | } |
517 | e98a6e40 | bellard | |
518 | e98a6e40 | bellard | PPC_OP(test_ctrz) |
519 | e98a6e40 | bellard | { |
520 | e98a6e40 | bellard | T0 = (regs->ctr == 0);
|
521 | e98a6e40 | bellard | } |
522 | e98a6e40 | bellard | |
523 | e98a6e40 | bellard | PPC_OP(test_ctrz_true) |
524 | e98a6e40 | bellard | { |
525 | e98a6e40 | bellard | T0 = (regs->ctr == 0 && (T0 & PARAM(1)) != 0); |
526 | e98a6e40 | bellard | } |
527 | e98a6e40 | bellard | |
528 | e98a6e40 | bellard | PPC_OP(test_ctrz_false) |
529 | e98a6e40 | bellard | { |
530 | e98a6e40 | bellard | T0 = (regs->ctr == 0 && (T0 & PARAM(1)) == 0); |
531 | e98a6e40 | bellard | } |
532 | e98a6e40 | bellard | |
533 | e98a6e40 | bellard | PPC_OP(test_true) |
534 | e98a6e40 | bellard | { |
535 | b88e4a9a | bellard | T0 = (T0 & PARAM(1));
|
536 | e98a6e40 | bellard | } |
537 | e98a6e40 | bellard | |
538 | e98a6e40 | bellard | PPC_OP(test_false) |
539 | e98a6e40 | bellard | { |
540 | e98a6e40 | bellard | T0 = ((T0 & PARAM(1)) == 0); |
541 | e98a6e40 | bellard | } |
542 | 79aceca5 | bellard | |
543 | 79aceca5 | bellard | /* CTR maintenance */
|
544 | 79aceca5 | bellard | PPC_OP(dec_ctr) |
545 | 79aceca5 | bellard | { |
546 | 9a64fbe4 | bellard | regs->ctr--; |
547 | 79aceca5 | bellard | RETURN(); |
548 | 79aceca5 | bellard | } |
549 | 79aceca5 | bellard | |
550 | 79aceca5 | bellard | /*** Integer arithmetic ***/
|
551 | 79aceca5 | bellard | /* add */
|
552 | 79aceca5 | bellard | PPC_OP(add) |
553 | 79aceca5 | bellard | { |
554 | 79aceca5 | bellard | T0 += T1; |
555 | 79aceca5 | bellard | RETURN(); |
556 | 79aceca5 | bellard | } |
557 | 79aceca5 | bellard | |
558 | fdabc366 | bellard | void do_addo (void); |
559 | fdabc366 | bellard | void op_addo (void) |
560 | 79aceca5 | bellard | { |
561 | fdabc366 | bellard | do_addo(); |
562 | 79aceca5 | bellard | RETURN(); |
563 | 79aceca5 | bellard | } |
564 | 79aceca5 | bellard | |
565 | 79aceca5 | bellard | /* add carrying */
|
566 | 79aceca5 | bellard | PPC_OP(addc) |
567 | 79aceca5 | bellard | { |
568 | 79aceca5 | bellard | T2 = T0; |
569 | 79aceca5 | bellard | T0 += T1; |
570 | 79aceca5 | bellard | if (T0 < T2) {
|
571 | 79aceca5 | bellard | xer_ca = 1;
|
572 | 79aceca5 | bellard | } else {
|
573 | 79aceca5 | bellard | xer_ca = 0;
|
574 | 79aceca5 | bellard | } |
575 | 79aceca5 | bellard | RETURN(); |
576 | 79aceca5 | bellard | } |
577 | 79aceca5 | bellard | |
578 | fdabc366 | bellard | void do_addco (void); |
579 | fdabc366 | bellard | void op_addco (void) |
580 | 79aceca5 | bellard | { |
581 | fdabc366 | bellard | do_addco(); |
582 | 79aceca5 | bellard | RETURN(); |
583 | 79aceca5 | bellard | } |
584 | 79aceca5 | bellard | |
585 | 79aceca5 | bellard | /* add extended */
|
586 | fdabc366 | bellard | void do_adde (void); |
587 | fdabc366 | bellard | void op_adde (void) |
588 | 79aceca5 | bellard | { |
589 | fdabc366 | bellard | do_adde(); |
590 | 79aceca5 | bellard | } |
591 | 79aceca5 | bellard | |
592 | fdabc366 | bellard | void do_addeo (void); |
593 | 79aceca5 | bellard | PPC_OP(addeo) |
594 | 79aceca5 | bellard | { |
595 | fdabc366 | bellard | do_addeo(); |
596 | 79aceca5 | bellard | RETURN(); |
597 | 79aceca5 | bellard | } |
598 | 79aceca5 | bellard | |
599 | 79aceca5 | bellard | /* add immediate */
|
600 | 79aceca5 | bellard | PPC_OP(addi) |
601 | 79aceca5 | bellard | { |
602 | 79aceca5 | bellard | T0 += PARAM(1);
|
603 | 79aceca5 | bellard | RETURN(); |
604 | 79aceca5 | bellard | } |
605 | 79aceca5 | bellard | |
606 | 79aceca5 | bellard | /* add immediate carrying */
|
607 | 79aceca5 | bellard | PPC_OP(addic) |
608 | 79aceca5 | bellard | { |
609 | 79aceca5 | bellard | T1 = T0; |
610 | 79aceca5 | bellard | T0 += PARAM(1);
|
611 | 79aceca5 | bellard | if (T0 < T1) {
|
612 | 79aceca5 | bellard | xer_ca = 1;
|
613 | 79aceca5 | bellard | } else {
|
614 | 79aceca5 | bellard | xer_ca = 0;
|
615 | 79aceca5 | bellard | } |
616 | 79aceca5 | bellard | RETURN(); |
617 | 79aceca5 | bellard | } |
618 | 79aceca5 | bellard | |
619 | 79aceca5 | bellard | /* add to minus one extended */
|
620 | 79aceca5 | bellard | PPC_OP(addme) |
621 | 79aceca5 | bellard | { |
622 | 79aceca5 | bellard | T1 = T0; |
623 | 79aceca5 | bellard | T0 += xer_ca + (-1);
|
624 | 79aceca5 | bellard | if (T1 != 0) |
625 | 79aceca5 | bellard | xer_ca = 1;
|
626 | 79aceca5 | bellard | RETURN(); |
627 | 79aceca5 | bellard | } |
628 | 79aceca5 | bellard | |
629 | fdabc366 | bellard | void do_addmeo (void); |
630 | fdabc366 | bellard | void op_addmeo (void) |
631 | 79aceca5 | bellard | { |
632 | fdabc366 | bellard | do_addmeo(); |
633 | 79aceca5 | bellard | RETURN(); |
634 | 79aceca5 | bellard | } |
635 | 79aceca5 | bellard | |
636 | 79aceca5 | bellard | /* add to zero extended */
|
637 | 79aceca5 | bellard | PPC_OP(addze) |
638 | 79aceca5 | bellard | { |
639 | 79aceca5 | bellard | T1 = T0; |
640 | 79aceca5 | bellard | T0 += xer_ca; |
641 | 79aceca5 | bellard | if (T0 < T1) {
|
642 | 79aceca5 | bellard | xer_ca = 1;
|
643 | 79aceca5 | bellard | } else {
|
644 | 79aceca5 | bellard | xer_ca = 0;
|
645 | 79aceca5 | bellard | } |
646 | 79aceca5 | bellard | RETURN(); |
647 | 79aceca5 | bellard | } |
648 | 79aceca5 | bellard | |
649 | fdabc366 | bellard | void do_addzeo (void); |
650 | fdabc366 | bellard | void op_addzeo (void) |
651 | 79aceca5 | bellard | { |
652 | fdabc366 | bellard | do_addzeo(); |
653 | 79aceca5 | bellard | RETURN(); |
654 | 79aceca5 | bellard | } |
655 | 79aceca5 | bellard | |
656 | 79aceca5 | bellard | /* divide word */
|
657 | 79aceca5 | bellard | PPC_OP(divw) |
658 | 79aceca5 | bellard | { |
659 | 79aceca5 | bellard | if ((Ts0 == INT32_MIN && Ts1 == -1) || Ts1 == 0) { |
660 | 3cc62370 | bellard | T0 = (int32_t)((-1) * (T0 >> 31)); |
661 | 79aceca5 | bellard | } else {
|
662 | 3cc62370 | bellard | T0 = (Ts0 / Ts1); |
663 | 79aceca5 | bellard | } |
664 | 79aceca5 | bellard | RETURN(); |
665 | 79aceca5 | bellard | } |
666 | 79aceca5 | bellard | |
667 | fdabc366 | bellard | void do_divwo (void); |
668 | fdabc366 | bellard | void op_divwo (void) |
669 | 79aceca5 | bellard | { |
670 | fdabc366 | bellard | do_divwo(); |
671 | 79aceca5 | bellard | RETURN(); |
672 | 79aceca5 | bellard | } |
673 | 79aceca5 | bellard | |
674 | 79aceca5 | bellard | /* divide word unsigned */
|
675 | 79aceca5 | bellard | PPC_OP(divwu) |
676 | 79aceca5 | bellard | { |
677 | 79aceca5 | bellard | if (T1 == 0) { |
678 | 79aceca5 | bellard | T0 = 0;
|
679 | 79aceca5 | bellard | } else {
|
680 | 79aceca5 | bellard | T0 /= T1; |
681 | 79aceca5 | bellard | } |
682 | 79aceca5 | bellard | RETURN(); |
683 | 79aceca5 | bellard | } |
684 | 79aceca5 | bellard | |
685 | fdabc366 | bellard | void do_divwuo (void); |
686 | fdabc366 | bellard | void op_divwuo (void) |
687 | 79aceca5 | bellard | { |
688 | fdabc366 | bellard | do_divwuo(); |
689 | 79aceca5 | bellard | RETURN(); |
690 | 79aceca5 | bellard | } |
691 | 79aceca5 | bellard | |
692 | 79aceca5 | bellard | /* multiply high word */
|
693 | 79aceca5 | bellard | PPC_OP(mulhw) |
694 | 79aceca5 | bellard | { |
695 | 3cc62370 | bellard | T0 = ((int64_t)Ts0 * (int64_t)Ts1) >> 32;
|
696 | 79aceca5 | bellard | RETURN(); |
697 | 79aceca5 | bellard | } |
698 | 79aceca5 | bellard | |
699 | 79aceca5 | bellard | /* multiply high word unsigned */
|
700 | 79aceca5 | bellard | PPC_OP(mulhwu) |
701 | 79aceca5 | bellard | { |
702 | 79aceca5 | bellard | T0 = ((uint64_t)T0 * (uint64_t)T1) >> 32;
|
703 | 79aceca5 | bellard | RETURN(); |
704 | 79aceca5 | bellard | } |
705 | 79aceca5 | bellard | |
706 | 79aceca5 | bellard | /* multiply low immediate */
|
707 | 79aceca5 | bellard | PPC_OP(mulli) |
708 | 79aceca5 | bellard | { |
709 | 3cc62370 | bellard | T0 = (Ts0 * SPARAM(1));
|
710 | 79aceca5 | bellard | RETURN(); |
711 | 79aceca5 | bellard | } |
712 | 79aceca5 | bellard | |
713 | 79aceca5 | bellard | /* multiply low word */
|
714 | 79aceca5 | bellard | PPC_OP(mullw) |
715 | 79aceca5 | bellard | { |
716 | 79aceca5 | bellard | T0 *= T1; |
717 | 79aceca5 | bellard | RETURN(); |
718 | 79aceca5 | bellard | } |
719 | 79aceca5 | bellard | |
720 | fdabc366 | bellard | void do_mullwo (void); |
721 | fdabc366 | bellard | void op_mullwo (void) |
722 | 79aceca5 | bellard | { |
723 | fdabc366 | bellard | do_mullwo(); |
724 | 79aceca5 | bellard | RETURN(); |
725 | 79aceca5 | bellard | } |
726 | 79aceca5 | bellard | |
727 | 79aceca5 | bellard | /* negate */
|
728 | 79aceca5 | bellard | PPC_OP(neg) |
729 | 79aceca5 | bellard | { |
730 | 79aceca5 | bellard | if (T0 != 0x80000000) { |
731 | 3cc62370 | bellard | T0 = -Ts0; |
732 | 79aceca5 | bellard | } |
733 | 79aceca5 | bellard | RETURN(); |
734 | 79aceca5 | bellard | } |
735 | 79aceca5 | bellard | |
736 | fdabc366 | bellard | void do_nego (void); |
737 | fdabc366 | bellard | void op_nego (void) |
738 | 79aceca5 | bellard | { |
739 | fdabc366 | bellard | do_nego(); |
740 | 79aceca5 | bellard | RETURN(); |
741 | 79aceca5 | bellard | } |
742 | 79aceca5 | bellard | |
743 | 79aceca5 | bellard | /* substract from */
|
744 | 79aceca5 | bellard | PPC_OP(subf) |
745 | 79aceca5 | bellard | { |
746 | 79aceca5 | bellard | T0 = T1 - T0; |
747 | 79aceca5 | bellard | RETURN(); |
748 | 79aceca5 | bellard | } |
749 | 79aceca5 | bellard | |
750 | fdabc366 | bellard | void do_subfo (void); |
751 | fdabc366 | bellard | void op_subfo (void) |
752 | 79aceca5 | bellard | { |
753 | fdabc366 | bellard | do_subfo(); |
754 | 79aceca5 | bellard | RETURN(); |
755 | 79aceca5 | bellard | } |
756 | 79aceca5 | bellard | |
757 | 79aceca5 | bellard | /* substract from carrying */
|
758 | 79aceca5 | bellard | PPC_OP(subfc) |
759 | 79aceca5 | bellard | { |
760 | 79aceca5 | bellard | T0 = T1 - T0; |
761 | 79aceca5 | bellard | if (T0 <= T1) {
|
762 | 79aceca5 | bellard | xer_ca = 1;
|
763 | 79aceca5 | bellard | } else {
|
764 | 79aceca5 | bellard | xer_ca = 0;
|
765 | 79aceca5 | bellard | } |
766 | 79aceca5 | bellard | RETURN(); |
767 | 79aceca5 | bellard | } |
768 | 79aceca5 | bellard | |
769 | fdabc366 | bellard | void do_subfco (void); |
770 | fdabc366 | bellard | void op_subfco (void) |
771 | 79aceca5 | bellard | { |
772 | fdabc366 | bellard | do_subfco(); |
773 | 79aceca5 | bellard | RETURN(); |
774 | 79aceca5 | bellard | } |
775 | 79aceca5 | bellard | |
776 | 79aceca5 | bellard | /* substract from extended */
|
777 | fdabc366 | bellard | void do_subfe (void); |
778 | fdabc366 | bellard | void op_subfe (void) |
779 | 79aceca5 | bellard | { |
780 | fdabc366 | bellard | do_subfe(); |
781 | 79aceca5 | bellard | RETURN(); |
782 | 79aceca5 | bellard | } |
783 | 79aceca5 | bellard | |
784 | fdabc366 | bellard | void do_subfeo (void); |
785 | 79aceca5 | bellard | PPC_OP(subfeo) |
786 | 79aceca5 | bellard | { |
787 | fdabc366 | bellard | do_subfeo(); |
788 | 79aceca5 | bellard | RETURN(); |
789 | 79aceca5 | bellard | } |
790 | 79aceca5 | bellard | |
791 | 79aceca5 | bellard | /* substract from immediate carrying */
|
792 | 79aceca5 | bellard | PPC_OP(subfic) |
793 | 79aceca5 | bellard | { |
794 | 79aceca5 | bellard | T0 = PARAM(1) + ~T0 + 1; |
795 | 79aceca5 | bellard | if (T0 <= PARAM(1)) { |
796 | 79aceca5 | bellard | xer_ca = 1;
|
797 | 79aceca5 | bellard | } else {
|
798 | 79aceca5 | bellard | xer_ca = 0;
|
799 | 79aceca5 | bellard | } |
800 | 79aceca5 | bellard | RETURN(); |
801 | 79aceca5 | bellard | } |
802 | 79aceca5 | bellard | |
803 | 79aceca5 | bellard | /* substract from minus one extended */
|
804 | 79aceca5 | bellard | PPC_OP(subfme) |
805 | 79aceca5 | bellard | { |
806 | 79aceca5 | bellard | T0 = ~T0 + xer_ca - 1;
|
807 | 79aceca5 | bellard | |
808 | 79aceca5 | bellard | if (T0 != -1) |
809 | 79aceca5 | bellard | xer_ca = 1;
|
810 | 79aceca5 | bellard | RETURN(); |
811 | 79aceca5 | bellard | } |
812 | 79aceca5 | bellard | |
813 | fdabc366 | bellard | void do_subfmeo (void); |
814 | fdabc366 | bellard | void op_subfmeo (void) |
815 | 79aceca5 | bellard | { |
816 | fdabc366 | bellard | do_subfmeo(); |
817 | 79aceca5 | bellard | RETURN(); |
818 | 79aceca5 | bellard | } |
819 | 79aceca5 | bellard | |
820 | 79aceca5 | bellard | /* substract from zero extended */
|
821 | 79aceca5 | bellard | PPC_OP(subfze) |
822 | 79aceca5 | bellard | { |
823 | 79aceca5 | bellard | T1 = ~T0; |
824 | 79aceca5 | bellard | T0 = T1 + xer_ca; |
825 | 79aceca5 | bellard | if (T0 < T1) {
|
826 | 79aceca5 | bellard | xer_ca = 1;
|
827 | 79aceca5 | bellard | } else {
|
828 | 79aceca5 | bellard | xer_ca = 0;
|
829 | 79aceca5 | bellard | } |
830 | 79aceca5 | bellard | RETURN(); |
831 | 79aceca5 | bellard | } |
832 | 79aceca5 | bellard | |
833 | fdabc366 | bellard | void do_subfzeo (void); |
834 | fdabc366 | bellard | void op_subfzeo (void) |
835 | 79aceca5 | bellard | { |
836 | fdabc366 | bellard | do_subfzeo(); |
837 | 79aceca5 | bellard | RETURN(); |
838 | 79aceca5 | bellard | } |
839 | 79aceca5 | bellard | |
840 | 79aceca5 | bellard | /*** Integer comparison ***/
|
841 | 79aceca5 | bellard | /* compare */
|
842 | 79aceca5 | bellard | PPC_OP(cmp) |
843 | 79aceca5 | bellard | { |
844 | 79aceca5 | bellard | if (Ts0 < Ts1) {
|
845 | 79aceca5 | bellard | T0 = 0x08;
|
846 | 79aceca5 | bellard | } else if (Ts0 > Ts1) { |
847 | 79aceca5 | bellard | T0 = 0x04;
|
848 | 79aceca5 | bellard | } else {
|
849 | 79aceca5 | bellard | T0 = 0x02;
|
850 | 79aceca5 | bellard | } |
851 | 79aceca5 | bellard | RETURN(); |
852 | 79aceca5 | bellard | } |
853 | 79aceca5 | bellard | |
854 | 79aceca5 | bellard | /* compare immediate */
|
855 | 79aceca5 | bellard | PPC_OP(cmpi) |
856 | 79aceca5 | bellard | { |
857 | 79aceca5 | bellard | if (Ts0 < SPARAM(1)) { |
858 | 79aceca5 | bellard | T0 = 0x08;
|
859 | 79aceca5 | bellard | } else if (Ts0 > SPARAM(1)) { |
860 | 79aceca5 | bellard | T0 = 0x04;
|
861 | 79aceca5 | bellard | } else {
|
862 | 79aceca5 | bellard | T0 = 0x02;
|
863 | 79aceca5 | bellard | } |
864 | 79aceca5 | bellard | RETURN(); |
865 | 79aceca5 | bellard | } |
866 | 79aceca5 | bellard | |
867 | 79aceca5 | bellard | /* compare logical */
|
868 | 79aceca5 | bellard | PPC_OP(cmpl) |
869 | 79aceca5 | bellard | { |
870 | 79aceca5 | bellard | if (T0 < T1) {
|
871 | 79aceca5 | bellard | T0 = 0x08;
|
872 | 79aceca5 | bellard | } else if (T0 > T1) { |
873 | 79aceca5 | bellard | T0 = 0x04;
|
874 | 79aceca5 | bellard | } else {
|
875 | 79aceca5 | bellard | T0 = 0x02;
|
876 | 79aceca5 | bellard | } |
877 | 79aceca5 | bellard | RETURN(); |
878 | 79aceca5 | bellard | } |
879 | 79aceca5 | bellard | |
880 | 79aceca5 | bellard | /* compare logical immediate */
|
881 | 79aceca5 | bellard | PPC_OP(cmpli) |
882 | 79aceca5 | bellard | { |
883 | 79aceca5 | bellard | if (T0 < PARAM(1)) { |
884 | 79aceca5 | bellard | T0 = 0x08;
|
885 | 79aceca5 | bellard | } else if (T0 > PARAM(1)) { |
886 | 79aceca5 | bellard | T0 = 0x04;
|
887 | 79aceca5 | bellard | } else {
|
888 | 79aceca5 | bellard | T0 = 0x02;
|
889 | 79aceca5 | bellard | } |
890 | 79aceca5 | bellard | RETURN(); |
891 | 79aceca5 | bellard | } |
892 | 79aceca5 | bellard | |
893 | 79aceca5 | bellard | /*** Integer logical ***/
|
894 | 79aceca5 | bellard | /* and */
|
895 | 79aceca5 | bellard | PPC_OP(and) |
896 | 79aceca5 | bellard | { |
897 | 79aceca5 | bellard | T0 &= T1; |
898 | 79aceca5 | bellard | RETURN(); |
899 | 79aceca5 | bellard | } |
900 | 79aceca5 | bellard | |
901 | 79aceca5 | bellard | /* andc */
|
902 | 79aceca5 | bellard | PPC_OP(andc) |
903 | 79aceca5 | bellard | { |
904 | 79aceca5 | bellard | T0 &= ~T1; |
905 | 79aceca5 | bellard | RETURN(); |
906 | 79aceca5 | bellard | } |
907 | 79aceca5 | bellard | |
908 | 79aceca5 | bellard | /* andi. */
|
909 | 79aceca5 | bellard | PPC_OP(andi_) |
910 | 79aceca5 | bellard | { |
911 | 79aceca5 | bellard | T0 &= PARAM(1);
|
912 | 79aceca5 | bellard | RETURN(); |
913 | 79aceca5 | bellard | } |
914 | 79aceca5 | bellard | |
915 | 79aceca5 | bellard | /* count leading zero */
|
916 | 79aceca5 | bellard | PPC_OP(cntlzw) |
917 | 79aceca5 | bellard | { |
918 | 79aceca5 | bellard | T1 = T0; |
919 | 79aceca5 | bellard | for (T0 = 32; T1 > 0; T0--) |
920 | 79aceca5 | bellard | T1 = T1 >> 1;
|
921 | 79aceca5 | bellard | RETURN(); |
922 | 79aceca5 | bellard | } |
923 | 79aceca5 | bellard | |
924 | 79aceca5 | bellard | /* eqv */
|
925 | 79aceca5 | bellard | PPC_OP(eqv) |
926 | 79aceca5 | bellard | { |
927 | 79aceca5 | bellard | T0 = ~(T0 ^ T1); |
928 | 79aceca5 | bellard | RETURN(); |
929 | 79aceca5 | bellard | } |
930 | 79aceca5 | bellard | |
931 | 79aceca5 | bellard | /* extend sign byte */
|
932 | 79aceca5 | bellard | PPC_OP(extsb) |
933 | 79aceca5 | bellard | { |
934 | 3cc62370 | bellard | T0 = (int32_t)((int8_t)(Ts0)); |
935 | 79aceca5 | bellard | RETURN(); |
936 | 79aceca5 | bellard | } |
937 | 79aceca5 | bellard | |
938 | 79aceca5 | bellard | /* extend sign half word */
|
939 | 79aceca5 | bellard | PPC_OP(extsh) |
940 | 79aceca5 | bellard | { |
941 | 3cc62370 | bellard | T0 = (int32_t)((int16_t)(Ts0)); |
942 | 79aceca5 | bellard | RETURN(); |
943 | 79aceca5 | bellard | } |
944 | 79aceca5 | bellard | |
945 | 79aceca5 | bellard | /* nand */
|
946 | 79aceca5 | bellard | PPC_OP(nand) |
947 | 79aceca5 | bellard | { |
948 | 79aceca5 | bellard | T0 = ~(T0 & T1); |
949 | 79aceca5 | bellard | RETURN(); |
950 | 79aceca5 | bellard | } |
951 | 79aceca5 | bellard | |
952 | 79aceca5 | bellard | /* nor */
|
953 | 79aceca5 | bellard | PPC_OP(nor) |
954 | 79aceca5 | bellard | { |
955 | 79aceca5 | bellard | T0 = ~(T0 | T1); |
956 | 79aceca5 | bellard | RETURN(); |
957 | 79aceca5 | bellard | } |
958 | 79aceca5 | bellard | |
959 | 79aceca5 | bellard | /* or */
|
960 | 79aceca5 | bellard | PPC_OP(or) |
961 | 79aceca5 | bellard | { |
962 | 79aceca5 | bellard | T0 |= T1; |
963 | 79aceca5 | bellard | RETURN(); |
964 | 79aceca5 | bellard | } |
965 | 79aceca5 | bellard | |
966 | 79aceca5 | bellard | /* orc */
|
967 | 79aceca5 | bellard | PPC_OP(orc) |
968 | 79aceca5 | bellard | { |
969 | 79aceca5 | bellard | T0 |= ~T1; |
970 | 79aceca5 | bellard | RETURN(); |
971 | 79aceca5 | bellard | } |
972 | 79aceca5 | bellard | |
973 | 79aceca5 | bellard | /* ori */
|
974 | 79aceca5 | bellard | PPC_OP(ori) |
975 | 79aceca5 | bellard | { |
976 | 79aceca5 | bellard | T0 |= PARAM(1);
|
977 | 79aceca5 | bellard | RETURN(); |
978 | 79aceca5 | bellard | } |
979 | 79aceca5 | bellard | |
980 | 79aceca5 | bellard | /* xor */
|
981 | 79aceca5 | bellard | PPC_OP(xor) |
982 | 79aceca5 | bellard | { |
983 | 79aceca5 | bellard | T0 ^= T1; |
984 | 79aceca5 | bellard | RETURN(); |
985 | 79aceca5 | bellard | } |
986 | 79aceca5 | bellard | |
987 | 79aceca5 | bellard | /* xori */
|
988 | 79aceca5 | bellard | PPC_OP(xori) |
989 | 79aceca5 | bellard | { |
990 | 79aceca5 | bellard | T0 ^= PARAM(1);
|
991 | 79aceca5 | bellard | RETURN(); |
992 | 79aceca5 | bellard | } |
993 | 79aceca5 | bellard | |
994 | 79aceca5 | bellard | /*** Integer rotate ***/
|
995 | 79aceca5 | bellard | /* rotate left word immediate then mask insert */
|
996 | 79aceca5 | bellard | PPC_OP(rlwimi) |
997 | 79aceca5 | bellard | { |
998 | fb0eaffc | bellard | T0 = (rotl(T0, PARAM(1)) & PARAM(2)) | (T1 & PARAM(3)); |
999 | 79aceca5 | bellard | RETURN(); |
1000 | 79aceca5 | bellard | } |
1001 | 79aceca5 | bellard | |
1002 | 79aceca5 | bellard | /* rotate left immediate then and with mask insert */
|
1003 | 79aceca5 | bellard | PPC_OP(rotlwi) |
1004 | 79aceca5 | bellard | { |
1005 | 79aceca5 | bellard | T0 = rotl(T0, PARAM(1));
|
1006 | 79aceca5 | bellard | RETURN(); |
1007 | 79aceca5 | bellard | } |
1008 | 79aceca5 | bellard | |
1009 | 79aceca5 | bellard | PPC_OP(slwi) |
1010 | 79aceca5 | bellard | { |
1011 | 79aceca5 | bellard | T0 = T0 << PARAM(1);
|
1012 | 79aceca5 | bellard | RETURN(); |
1013 | 79aceca5 | bellard | } |
1014 | 79aceca5 | bellard | |
1015 | 79aceca5 | bellard | PPC_OP(srwi) |
1016 | 79aceca5 | bellard | { |
1017 | 79aceca5 | bellard | T0 = T0 >> PARAM(1);
|
1018 | 79aceca5 | bellard | RETURN(); |
1019 | 79aceca5 | bellard | } |
1020 | 79aceca5 | bellard | |
1021 | 79aceca5 | bellard | /* rotate left word then and with mask insert */
|
1022 | 79aceca5 | bellard | PPC_OP(rlwinm) |
1023 | 79aceca5 | bellard | { |
1024 | 79aceca5 | bellard | T0 = rotl(T0, PARAM(1)) & PARAM(2); |
1025 | 79aceca5 | bellard | RETURN(); |
1026 | 79aceca5 | bellard | } |
1027 | 79aceca5 | bellard | |
1028 | 79aceca5 | bellard | PPC_OP(rotl) |
1029 | 79aceca5 | bellard | { |
1030 | 79aceca5 | bellard | T0 = rotl(T0, T1); |
1031 | 79aceca5 | bellard | RETURN(); |
1032 | 79aceca5 | bellard | } |
1033 | 79aceca5 | bellard | |
1034 | 79aceca5 | bellard | PPC_OP(rlwnm) |
1035 | 79aceca5 | bellard | { |
1036 | 79aceca5 | bellard | T0 = rotl(T0, T1) & PARAM(1);
|
1037 | 79aceca5 | bellard | RETURN(); |
1038 | 79aceca5 | bellard | } |
1039 | 79aceca5 | bellard | |
1040 | 79aceca5 | bellard | /*** Integer shift ***/
|
1041 | 79aceca5 | bellard | /* shift left word */
|
1042 | 79aceca5 | bellard | PPC_OP(slw) |
1043 | 79aceca5 | bellard | { |
1044 | 79aceca5 | bellard | if (T1 & 0x20) { |
1045 | 79aceca5 | bellard | T0 = 0;
|
1046 | 79aceca5 | bellard | } else {
|
1047 | 79aceca5 | bellard | T0 = T0 << T1; |
1048 | 79aceca5 | bellard | } |
1049 | 79aceca5 | bellard | RETURN(); |
1050 | 79aceca5 | bellard | } |
1051 | 79aceca5 | bellard | |
1052 | 79aceca5 | bellard | /* shift right algebraic word */
|
1053 | fdabc366 | bellard | void op_sraw (void) |
1054 | 79aceca5 | bellard | { |
1055 | 9a64fbe4 | bellard | do_sraw(); |
1056 | 79aceca5 | bellard | RETURN(); |
1057 | 79aceca5 | bellard | } |
1058 | 79aceca5 | bellard | |
1059 | 79aceca5 | bellard | /* shift right algebraic word immediate */
|
1060 | 79aceca5 | bellard | PPC_OP(srawi) |
1061 | 79aceca5 | bellard | { |
1062 | 3cc62370 | bellard | T1 = T0; |
1063 | 3cc62370 | bellard | T0 = (Ts0 >> PARAM(1));
|
1064 | 79aceca5 | bellard | if (Ts1 < 0 && (Ts1 & PARAM(2)) != 0) { |
1065 | 79aceca5 | bellard | xer_ca = 1;
|
1066 | 79aceca5 | bellard | } else {
|
1067 | 79aceca5 | bellard | xer_ca = 0;
|
1068 | 79aceca5 | bellard | } |
1069 | 79aceca5 | bellard | RETURN(); |
1070 | 79aceca5 | bellard | } |
1071 | 79aceca5 | bellard | |
1072 | 79aceca5 | bellard | /* shift right word */
|
1073 | 79aceca5 | bellard | PPC_OP(srw) |
1074 | 79aceca5 | bellard | { |
1075 | 79aceca5 | bellard | if (T1 & 0x20) { |
1076 | 79aceca5 | bellard | T0 = 0;
|
1077 | 79aceca5 | bellard | } else {
|
1078 | 79aceca5 | bellard | T0 = T0 >> T1; |
1079 | 79aceca5 | bellard | } |
1080 | 79aceca5 | bellard | RETURN(); |
1081 | 79aceca5 | bellard | } |
1082 | 79aceca5 | bellard | |
1083 | 79aceca5 | bellard | /*** Floating-Point arithmetic ***/
|
1084 | 9a64fbe4 | bellard | /* fadd - fadd. */
|
1085 | 9a64fbe4 | bellard | PPC_OP(fadd) |
1086 | 79aceca5 | bellard | { |
1087 | 9a64fbe4 | bellard | FT0 += FT1; |
1088 | 79aceca5 | bellard | RETURN(); |
1089 | 79aceca5 | bellard | } |
1090 | 79aceca5 | bellard | |
1091 | 9a64fbe4 | bellard | /* fsub - fsub. */
|
1092 | 9a64fbe4 | bellard | PPC_OP(fsub) |
1093 | 79aceca5 | bellard | { |
1094 | 9a64fbe4 | bellard | FT0 -= FT1; |
1095 | 79aceca5 | bellard | RETURN(); |
1096 | 79aceca5 | bellard | } |
1097 | 79aceca5 | bellard | |
1098 | 9a64fbe4 | bellard | /* fmul - fmul. */
|
1099 | 9a64fbe4 | bellard | PPC_OP(fmul) |
1100 | 79aceca5 | bellard | { |
1101 | 9a64fbe4 | bellard | FT0 *= FT1; |
1102 | 79aceca5 | bellard | RETURN(); |
1103 | 79aceca5 | bellard | } |
1104 | 79aceca5 | bellard | |
1105 | 9a64fbe4 | bellard | /* fdiv - fdiv. */
|
1106 | 9a64fbe4 | bellard | PPC_OP(fdiv) |
1107 | 79aceca5 | bellard | { |
1108 | fdabc366 | bellard | FT0 = float64_div(FT0, FT1, &env->fp_status); |
1109 | 79aceca5 | bellard | RETURN(); |
1110 | 79aceca5 | bellard | } |
1111 | 28b6751f | bellard | |
1112 | 9a64fbe4 | bellard | /* fsqrt - fsqrt. */
|
1113 | 9a64fbe4 | bellard | PPC_OP(fsqrt) |
1114 | 28b6751f | bellard | { |
1115 | 9a64fbe4 | bellard | do_fsqrt(); |
1116 | 9a64fbe4 | bellard | RETURN(); |
1117 | 28b6751f | bellard | } |
1118 | 28b6751f | bellard | |
1119 | 9a64fbe4 | bellard | /* fres - fres. */
|
1120 | 9a64fbe4 | bellard | PPC_OP(fres) |
1121 | 28b6751f | bellard | { |
1122 | 9a64fbe4 | bellard | do_fres(); |
1123 | 9a64fbe4 | bellard | RETURN(); |
1124 | 28b6751f | bellard | } |
1125 | 28b6751f | bellard | |
1126 | 9a64fbe4 | bellard | /* frsqrte - frsqrte. */
|
1127 | 9a64fbe4 | bellard | PPC_OP(frsqrte) |
1128 | 28b6751f | bellard | { |
1129 | 4ecc3190 | bellard | do_frsqrte(); |
1130 | 9a64fbe4 | bellard | RETURN(); |
1131 | 28b6751f | bellard | } |
1132 | 28b6751f | bellard | |
1133 | 9a64fbe4 | bellard | /* fsel - fsel. */
|
1134 | 9a64fbe4 | bellard | PPC_OP(fsel) |
1135 | 28b6751f | bellard | { |
1136 | 9a64fbe4 | bellard | do_fsel(); |
1137 | 9a64fbe4 | bellard | RETURN(); |
1138 | 28b6751f | bellard | } |
1139 | 28b6751f | bellard | |
1140 | 9a64fbe4 | bellard | /*** Floating-Point multiply-and-add ***/
|
1141 | 9a64fbe4 | bellard | /* fmadd - fmadd. */
|
1142 | 9a64fbe4 | bellard | PPC_OP(fmadd) |
1143 | 28b6751f | bellard | { |
1144 | 9a64fbe4 | bellard | FT0 = (FT0 * FT1) + FT2; |
1145 | 9a64fbe4 | bellard | RETURN(); |
1146 | 28b6751f | bellard | } |
1147 | 28b6751f | bellard | |
1148 | 9a64fbe4 | bellard | /* fmsub - fmsub. */
|
1149 | 9a64fbe4 | bellard | PPC_OP(fmsub) |
1150 | 28b6751f | bellard | { |
1151 | 9a64fbe4 | bellard | FT0 = (FT0 * FT1) - FT2; |
1152 | 9a64fbe4 | bellard | RETURN(); |
1153 | 28b6751f | bellard | } |
1154 | 28b6751f | bellard | |
1155 | 9a64fbe4 | bellard | /* fnmadd - fnmadd. - fnmadds - fnmadds. */
|
1156 | 9a64fbe4 | bellard | PPC_OP(fnmadd) |
1157 | 28b6751f | bellard | { |
1158 | 4b3686fa | bellard | do_fnmadd(); |
1159 | 9a64fbe4 | bellard | RETURN(); |
1160 | 28b6751f | bellard | } |
1161 | 28b6751f | bellard | |
1162 | 9a64fbe4 | bellard | /* fnmsub - fnmsub. */
|
1163 | 9a64fbe4 | bellard | PPC_OP(fnmsub) |
1164 | 28b6751f | bellard | { |
1165 | 4b3686fa | bellard | do_fnmsub(); |
1166 | 9a64fbe4 | bellard | RETURN(); |
1167 | 28b6751f | bellard | } |
1168 | 28b6751f | bellard | |
1169 | 9a64fbe4 | bellard | /*** Floating-Point round & convert ***/
|
1170 | 9a64fbe4 | bellard | /* frsp - frsp. */
|
1171 | 9a64fbe4 | bellard | PPC_OP(frsp) |
1172 | 28b6751f | bellard | { |
1173 | 3cc62370 | bellard | FT0 = (float)FT0;
|
1174 | 9a64fbe4 | bellard | RETURN(); |
1175 | 28b6751f | bellard | } |
1176 | 28b6751f | bellard | |
1177 | 9a64fbe4 | bellard | /* fctiw - fctiw. */
|
1178 | 9a64fbe4 | bellard | PPC_OP(fctiw) |
1179 | 28b6751f | bellard | { |
1180 | 9a64fbe4 | bellard | do_fctiw(); |
1181 | 9a64fbe4 | bellard | RETURN(); |
1182 | 28b6751f | bellard | } |
1183 | 28b6751f | bellard | |
1184 | 9a64fbe4 | bellard | /* fctiwz - fctiwz. */
|
1185 | 9a64fbe4 | bellard | PPC_OP(fctiwz) |
1186 | 28b6751f | bellard | { |
1187 | 9a64fbe4 | bellard | do_fctiwz(); |
1188 | 9a64fbe4 | bellard | RETURN(); |
1189 | 28b6751f | bellard | } |
1190 | 28b6751f | bellard | |
1191 | 9a64fbe4 | bellard | |
1192 | 9a64fbe4 | bellard | /*** Floating-Point compare ***/
|
1193 | 9a64fbe4 | bellard | /* fcmpu */
|
1194 | 9a64fbe4 | bellard | PPC_OP(fcmpu) |
1195 | 28b6751f | bellard | { |
1196 | 9a64fbe4 | bellard | do_fcmpu(); |
1197 | 9a64fbe4 | bellard | RETURN(); |
1198 | 28b6751f | bellard | } |
1199 | 28b6751f | bellard | |
1200 | 9a64fbe4 | bellard | /* fcmpo */
|
1201 | 9a64fbe4 | bellard | PPC_OP(fcmpo) |
1202 | 28b6751f | bellard | { |
1203 | 9a64fbe4 | bellard | do_fcmpo(); |
1204 | 9a64fbe4 | bellard | RETURN(); |
1205 | fb0eaffc | bellard | } |
1206 | fb0eaffc | bellard | |
1207 | 9a64fbe4 | bellard | /*** Floating-point move ***/
|
1208 | 9a64fbe4 | bellard | /* fabs */
|
1209 | 9a64fbe4 | bellard | PPC_OP(fabs) |
1210 | fb0eaffc | bellard | { |
1211 | fdabc366 | bellard | FT0 = float64_abs(FT0); |
1212 | fb0eaffc | bellard | RETURN(); |
1213 | fb0eaffc | bellard | } |
1214 | fb0eaffc | bellard | |
1215 | 9a64fbe4 | bellard | /* fnabs */
|
1216 | 9a64fbe4 | bellard | PPC_OP(fnabs) |
1217 | fb0eaffc | bellard | { |
1218 | fdabc366 | bellard | FT0 = float64_abs(FT0); |
1219 | fdabc366 | bellard | FT0 = float64_chs(FT0); |
1220 | fb0eaffc | bellard | RETURN(); |
1221 | fb0eaffc | bellard | } |
1222 | fb0eaffc | bellard | |
1223 | 9a64fbe4 | bellard | /* fneg */
|
1224 | 9a64fbe4 | bellard | PPC_OP(fneg) |
1225 | fb0eaffc | bellard | { |
1226 | fdabc366 | bellard | FT0 = float64_chs(FT0); |
1227 | fb0eaffc | bellard | RETURN(); |
1228 | fb0eaffc | bellard | } |
1229 | fb0eaffc | bellard | |
1230 | 9a64fbe4 | bellard | /* Load and store */
|
1231 | 9a64fbe4 | bellard | #define MEMSUFFIX _raw
|
1232 | 9a64fbe4 | bellard | #include "op_mem.h" |
1233 | a541f297 | bellard | #if !defined(CONFIG_USER_ONLY)
|
1234 | 9a64fbe4 | bellard | #define MEMSUFFIX _user
|
1235 | 9a64fbe4 | bellard | #include "op_mem.h" |
1236 | 9a64fbe4 | bellard | |
1237 | 9a64fbe4 | bellard | #define MEMSUFFIX _kernel
|
1238 | 9a64fbe4 | bellard | #include "op_mem.h" |
1239 | 9a64fbe4 | bellard | #endif
|
1240 | 9a64fbe4 | bellard | |
1241 | 4b3686fa | bellard | /* Special op to check and maybe clear reservation */
|
1242 | 4b3686fa | bellard | PPC_OP(check_reservation) |
1243 | 4b3686fa | bellard | { |
1244 | fdabc366 | bellard | if ((uint32_t)env->reserve == (uint32_t)(T0 & ~0x00000003)) |
1245 | fdabc366 | bellard | env->reserve = -1;
|
1246 | 4b3686fa | bellard | RETURN(); |
1247 | 4b3686fa | bellard | } |
1248 | 4b3686fa | bellard | |
1249 | 9a64fbe4 | bellard | /* Return from interrupt */
|
1250 | fdabc366 | bellard | void do_rfi (void); |
1251 | fdabc366 | bellard | void op_rfi (void) |
1252 | fb0eaffc | bellard | { |
1253 | fdabc366 | bellard | do_rfi(); |
1254 | fb0eaffc | bellard | RETURN(); |
1255 | fb0eaffc | bellard | } |
1256 | fb0eaffc | bellard | |
1257 | 9a64fbe4 | bellard | /* Trap word */
|
1258 | fdabc366 | bellard | void do_tw (uint32_t cmp, int flags); |
1259 | fdabc366 | bellard | void op_tw (void) |
1260 | fb0eaffc | bellard | { |
1261 | fdabc366 | bellard | do_tw(T1, PARAM(1));
|
1262 | fb0eaffc | bellard | RETURN(); |
1263 | fb0eaffc | bellard | } |
1264 | fb0eaffc | bellard | |
1265 | fdabc366 | bellard | void op_twi (void) |
1266 | fb0eaffc | bellard | { |
1267 | fdabc366 | bellard | do_tw(PARAM(1), PARAM(2)); |
1268 | fb0eaffc | bellard | RETURN(); |
1269 | fb0eaffc | bellard | } |
1270 | fb0eaffc | bellard | |
1271 | fb0eaffc | bellard | /* Instruction cache block invalidate */
|
1272 | 9a64fbe4 | bellard | PPC_OP(icbi) |
1273 | fb0eaffc | bellard | { |
1274 | fb0eaffc | bellard | do_icbi(); |
1275 | fb0eaffc | bellard | RETURN(); |
1276 | fb0eaffc | bellard | } |
1277 | fb0eaffc | bellard | |
1278 | 9a64fbe4 | bellard | /* tlbia */
|
1279 | 9a64fbe4 | bellard | PPC_OP(tlbia) |
1280 | fb0eaffc | bellard | { |
1281 | 9a64fbe4 | bellard | do_tlbia(); |
1282 | 9a64fbe4 | bellard | RETURN(); |
1283 | 9a64fbe4 | bellard | } |
1284 | 9a64fbe4 | bellard | |
1285 | 9a64fbe4 | bellard | /* tlbie */
|
1286 | 9a64fbe4 | bellard | PPC_OP(tlbie) |
1287 | 9a64fbe4 | bellard | { |
1288 | 9a64fbe4 | bellard | do_tlbie(); |
1289 | fb0eaffc | bellard | RETURN(); |
1290 | 28b6751f | bellard | } |
1291 | 3fc6c082 | bellard | |
1292 | 3fc6c082 | bellard | void op_store_pir (void) |
1293 | 3fc6c082 | bellard | { |
1294 | 3fc6c082 | bellard | env->spr[SPR_PIR] = T0 & 0x0000000FUL;
|
1295 | 3fc6c082 | bellard | RETURN(); |
1296 | 3fc6c082 | bellard | } |