root / hw / exynos4210_pmu.c @ 9077f01b
History | View | Annotate | Download (23.2 kB)
1 |
/*
|
---|---|
2 |
* Exynos4210 Power Management Unit (PMU) Emulation
|
3 |
*
|
4 |
* Copyright (C) 2011 Samsung Electronics Co Ltd.
|
5 |
* Maksim Kozlov <m.kozlov@samsung.com>
|
6 |
*
|
7 |
* This program is free software; you can redistribute it and/or modify it
|
8 |
* under the terms of the GNU General Public License as published by the
|
9 |
* Free Software Foundation; either version 2 of the License, or
|
10 |
* (at your option) any later version.
|
11 |
*
|
12 |
* This program is distributed in the hope that it will be useful, but WITHOUT
|
13 |
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
14 |
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
15 |
* for more details.
|
16 |
*
|
17 |
* You should have received a copy of the GNU General Public License along
|
18 |
* with this program; if not, see <http://www.gnu.org/licenses/>.
|
19 |
*/
|
20 |
|
21 |
/*
|
22 |
* This model implements PMU registers just as a bulk of memory. Currently,
|
23 |
* the only reason this device exists is that secondary CPU boot loader
|
24 |
* uses PMU INFORM5 register as a holding pen.
|
25 |
*/
|
26 |
|
27 |
#include "sysbus.h" |
28 |
|
29 |
#ifndef DEBUG_PMU
|
30 |
#define DEBUG_PMU 0 |
31 |
#endif
|
32 |
|
33 |
#ifndef DEBUG_PMU_EXTEND
|
34 |
#define DEBUG_PMU_EXTEND 0 |
35 |
#endif
|
36 |
|
37 |
#if DEBUG_PMU
|
38 |
#define PRINT_DEBUG(fmt, args...) \
|
39 |
do { \
|
40 |
fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ |
41 |
} while (0) |
42 |
|
43 |
#if DEBUG_PMU_EXTEND
|
44 |
#define PRINT_DEBUG_EXTEND(fmt, args...) \
|
45 |
do { \
|
46 |
fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ |
47 |
} while (0) |
48 |
#else
|
49 |
#define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0) |
50 |
#endif /* EXTEND */ |
51 |
|
52 |
#else
|
53 |
#define PRINT_DEBUG(fmt, args...) do {} while (0) |
54 |
#define PRINT_DEBUG_EXTEND(fmt, args...) do {} while (0) |
55 |
#endif
|
56 |
|
57 |
/*
|
58 |
* Offsets for PMU registers
|
59 |
*/
|
60 |
#define OM_STAT 0x0000 /* OM status register */ |
61 |
#define RTC_CLKO_SEL 0x000C /* Controls RTCCLKOUT */ |
62 |
#define GNSS_RTC_OUT_CTRL 0x0010 /* Controls GNSS_RTC_OUT */ |
63 |
/* Decides whether system-level low-power mode is used. */
|
64 |
#define SYSTEM_POWER_DOWN_CTRL 0x0200 |
65 |
/* Sets control options for CENTRAL_SEQ */
|
66 |
#define SYSTEM_POWER_DOWN_OPTION 0x0208 |
67 |
#define SWRESET 0x0400 /* Generate software reset */ |
68 |
#define RST_STAT 0x0404 /* Reset status register */ |
69 |
#define WAKEUP_STAT 0x0600 /* Wakeup status register */ |
70 |
#define EINT_WAKEUP_MASK 0x0604 /* Configure External INTerrupt mask */ |
71 |
#define WAKEUP_MASK 0x0608 /* Configure wakeup source mask */ |
72 |
#define HDMI_PHY_CONTROL 0x0700 /* HDMI PHY control register */ |
73 |
#define USBDEVICE_PHY_CONTROL 0x0704 /* USB Device PHY control register */ |
74 |
#define USBHOST_PHY_CONTROL 0x0708 /* USB HOST PHY control register */ |
75 |
#define DAC_PHY_CONTROL 0x070C /* DAC control register */ |
76 |
#define MIPI_PHY0_CONTROL 0x0710 /* MIPI PHY control register */ |
77 |
#define MIPI_PHY1_CONTROL 0x0714 /* MIPI PHY control register */ |
78 |
#define ADC_PHY_CONTROL 0x0718 /* TS-ADC control register */ |
79 |
#define PCIe_PHY_CONTROL 0x071C /* TS-PCIe control register */ |
80 |
#define SATA_PHY_CONTROL 0x0720 /* TS-SATA control register */ |
81 |
#define INFORM0 0x0800 /* Information register 0 */ |
82 |
#define INFORM1 0x0804 /* Information register 1 */ |
83 |
#define INFORM2 0x0808 /* Information register 2 */ |
84 |
#define INFORM3 0x080C /* Information register 3 */ |
85 |
#define INFORM4 0x0810 /* Information register 4 */ |
86 |
#define INFORM5 0x0814 /* Information register 5 */ |
87 |
#define INFORM6 0x0818 /* Information register 6 */ |
88 |
#define INFORM7 0x081C /* Information register 7 */ |
89 |
#define PMU_DEBUG 0x0A00 /* PMU debug register */ |
90 |
/* Registers to set system-level low-power option */
|
91 |
#define ARM_CORE0_SYS_PWR_REG 0x1000 |
92 |
#define ARM_CORE1_SYS_PWR_REG 0x1010 |
93 |
#define ARM_COMMON_SYS_PWR_REG 0x1080 |
94 |
#define ARM_CPU_L2_0_SYS_PWR_REG 0x10C0 |
95 |
#define ARM_CPU_L2_1_SYS_PWR_REG 0x10C4 |
96 |
#define CMU_ACLKSTOP_SYS_PWR_REG 0x1100 |
97 |
#define CMU_SCLKSTOP_SYS_PWR_REG 0x1104 |
98 |
#define CMU_RESET_SYS_PWR_REG 0x110C |
99 |
#define APLL_SYSCLK_SYS_PWR_REG 0x1120 |
100 |
#define MPLL_SYSCLK_SYS_PWR_REG 0x1124 |
101 |
#define VPLL_SYSCLK_SYS_PWR_REG 0x1128 |
102 |
#define EPLL_SYSCLK_SYS_PWR_REG 0x112C |
103 |
#define CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG 0x1138 |
104 |
#define CMU_RESET_GPS_ALIVE_SYS_PWR_REG 0x113C |
105 |
#define CMU_CLKSTOP_CAM_SYS_PWR_REG 0x1140 |
106 |
#define CMU_CLKSTOP_TV_SYS_PWR_REG 0x1144 |
107 |
#define CMU_CLKSTOP_MFC_SYS_PWR_REG 0x1148 |
108 |
#define CMU_CLKSTOP_G3D_SYS_PWR_REG 0x114C |
109 |
#define CMU_CLKSTOP_LCD0_SYS_PWR_REG 0x1150 |
110 |
#define CMU_CLKSTOP_LCD1_SYS_PWR_REG 0x1154 |
111 |
#define CMU_CLKSTOP_MAUDIO_SYS_PWR_REG 0x1158 |
112 |
#define CMU_CLKSTOP_GPS_SYS_PWR_REG 0x115C |
113 |
#define CMU_RESET_CAM_SYS_PWR_REG 0x1160 |
114 |
#define CMU_RESET_TV_SYS_PWR_REG 0x1164 |
115 |
#define CMU_RESET_MFC_SYS_PWR_REG 0x1168 |
116 |
#define CMU_RESET_G3D_SYS_PWR_REG 0x116C |
117 |
#define CMU_RESET_LCD0_SYS_PWR_REG 0x1170 |
118 |
#define CMU_RESET_LCD1_SYS_PWR_REG 0x1174 |
119 |
#define CMU_RESET_MAUDIO_SYS_PWR_REG 0x1178 |
120 |
#define CMU_RESET_GPS_SYS_PWR_REG 0x117C |
121 |
#define TOP_BUS_SYS_PWR_REG 0x1180 |
122 |
#define TOP_RETENTION_SYS_PWR_REG 0x1184 |
123 |
#define TOP_PWR_SYS_PWR_REG 0x1188 |
124 |
#define LOGIC_RESET_SYS_PWR_REG 0x11A0 |
125 |
#define OneNANDXL_MEM_SYS_PWR_REG 0x11C0 |
126 |
#define MODEMIF_MEM_SYS_PWR_REG 0x11C4 |
127 |
#define USBDEVICE_MEM_SYS_PWR_REG 0x11CC |
128 |
#define SDMMC_MEM_SYS_PWR_REG 0x11D0 |
129 |
#define CSSYS_MEM_SYS_PWR_REG 0x11D4 |
130 |
#define SECSS_MEM_SYS_PWR_REG 0x11D8 |
131 |
#define PCIe_MEM_SYS_PWR_REG 0x11E0 |
132 |
#define SATA_MEM_SYS_PWR_REG 0x11E4 |
133 |
#define PAD_RETENTION_DRAM_SYS_PWR_REG 0x1200 |
134 |
#define PAD_RETENTION_MAUDIO_SYS_PWR_REG 0x1204 |
135 |
#define PAD_RETENTION_GPIO_SYS_PWR_REG 0x1220 |
136 |
#define PAD_RETENTION_UART_SYS_PWR_REG 0x1224 |
137 |
#define PAD_RETENTION_MMCA_SYS_PWR_REG 0x1228 |
138 |
#define PAD_RETENTION_MMCB_SYS_PWR_REG 0x122C |
139 |
#define PAD_RETENTION_EBIA_SYS_PWR_REG 0x1230 |
140 |
#define PAD_RETENTION_EBIB_SYS_PWR_REG 0x1234 |
141 |
#define PAD_ISOLATION_SYS_PWR_REG 0x1240 |
142 |
#define PAD_ALV_SEL_SYS_PWR_REG 0x1260 |
143 |
#define XUSBXTI_SYS_PWR_REG 0x1280 |
144 |
#define XXTI_SYS_PWR_REG 0x1284 |
145 |
#define EXT_REGULATOR_SYS_PWR_REG 0x12C0 |
146 |
#define GPIO_MODE_SYS_PWR_REG 0x1300 |
147 |
#define GPIO_MODE_MAUDIO_SYS_PWR_REG 0x1340 |
148 |
#define CAM_SYS_PWR_REG 0x1380 |
149 |
#define TV_SYS_PWR_REG 0x1384 |
150 |
#define MFC_SYS_PWR_REG 0x1388 |
151 |
#define G3D_SYS_PWR_REG 0x138C |
152 |
#define LCD0_SYS_PWR_REG 0x1390 |
153 |
#define LCD1_SYS_PWR_REG 0x1394 |
154 |
#define MAUDIO_SYS_PWR_REG 0x1398 |
155 |
#define GPS_SYS_PWR_REG 0x139C |
156 |
#define GPS_ALIVE_SYS_PWR_REG 0x13A0 |
157 |
#define ARM_CORE0_CONFIGURATION 0x2000 /* Configure power mode of ARM_CORE0 */ |
158 |
#define ARM_CORE0_STATUS 0x2004 /* Check power mode of ARM_CORE0 */ |
159 |
#define ARM_CORE0_OPTION 0x2008 /* Sets control options for ARM_CORE0 */ |
160 |
#define ARM_CORE1_CONFIGURATION 0x2080 /* Configure power mode of ARM_CORE1 */ |
161 |
#define ARM_CORE1_STATUS 0x2084 /* Check power mode of ARM_CORE1 */ |
162 |
#define ARM_CORE1_OPTION 0x2088 /* Sets control options for ARM_CORE0 */ |
163 |
#define ARM_COMMON_OPTION 0x2408 /* Sets control options for ARM_COMMON */ |
164 |
/* Configure power mode of ARM_CPU_L2_0 */
|
165 |
#define ARM_CPU_L2_0_CONFIGURATION 0x2600 |
166 |
#define ARM_CPU_L2_0_STATUS 0x2604 /* Check power mode of ARM_CPU_L2_0 */ |
167 |
/* Configure power mode of ARM_CPU_L2_1 */
|
168 |
#define ARM_CPU_L2_1_CONFIGURATION 0x2620 |
169 |
#define ARM_CPU_L2_1_STATUS 0x2624 /* Check power mode of ARM_CPU_L2_1 */ |
170 |
/* Sets control options for PAD_RETENTION_MAUDIO */
|
171 |
#define PAD_RETENTION_MAUDIO_OPTION 0x3028 |
172 |
/* Sets control options for PAD_RETENTION_GPIO */
|
173 |
#define PAD_RETENTION_GPIO_OPTION 0x3108 |
174 |
/* Sets control options for PAD_RETENTION_UART */
|
175 |
#define PAD_RETENTION_UART_OPTION 0x3128 |
176 |
/* Sets control options for PAD_RETENTION_MMCA */
|
177 |
#define PAD_RETENTION_MMCA_OPTION 0x3148 |
178 |
/* Sets control options for PAD_RETENTION_MMCB */
|
179 |
#define PAD_RETENTION_MMCB_OPTION 0x3168 |
180 |
/* Sets control options for PAD_RETENTION_EBIA */
|
181 |
#define PAD_RETENTION_EBIA_OPTION 0x3188 |
182 |
/* Sets control options for PAD_RETENTION_EBIB */
|
183 |
#define PAD_RETENTION_EBIB_OPTION 0x31A8 |
184 |
#define PS_HOLD_CONTROL 0x330C /* PS_HOLD control register */ |
185 |
#define XUSBXTI_CONFIGURATION 0x3400 /* Configure the pad of XUSBXTI */ |
186 |
#define XUSBXTI_STATUS 0x3404 /* Check the pad of XUSBXTI */ |
187 |
/* Sets time required for XUSBXTI to be stabilized */
|
188 |
#define XUSBXTI_DURATION 0x341C |
189 |
#define XXTI_CONFIGURATION 0x3420 /* Configure the pad of XXTI */ |
190 |
#define XXTI_STATUS 0x3424 /* Check the pad of XXTI */ |
191 |
/* Sets time required for XXTI to be stabilized */
|
192 |
#define XXTI_DURATION 0x343C |
193 |
/* Sets time required for EXT_REGULATOR to be stabilized */
|
194 |
#define EXT_REGULATOR_DURATION 0x361C |
195 |
#define CAM_CONFIGURATION 0x3C00 /* Configure power mode of CAM */ |
196 |
#define CAM_STATUS 0x3C04 /* Check power mode of CAM */ |
197 |
#define CAM_OPTION 0x3C08 /* Sets control options for CAM */ |
198 |
#define TV_CONFIGURATION 0x3C20 /* Configure power mode of TV */ |
199 |
#define TV_STATUS 0x3C24 /* Check power mode of TV */ |
200 |
#define TV_OPTION 0x3C28 /* Sets control options for TV */ |
201 |
#define MFC_CONFIGURATION 0x3C40 /* Configure power mode of MFC */ |
202 |
#define MFC_STATUS 0x3C44 /* Check power mode of MFC */ |
203 |
#define MFC_OPTION 0x3C48 /* Sets control options for MFC */ |
204 |
#define G3D_CONFIGURATION 0x3C60 /* Configure power mode of G3D */ |
205 |
#define G3D_STATUS 0x3C64 /* Check power mode of G3D */ |
206 |
#define G3D_OPTION 0x3C68 /* Sets control options for G3D */ |
207 |
#define LCD0_CONFIGURATION 0x3C80 /* Configure power mode of LCD0 */ |
208 |
#define LCD0_STATUS 0x3C84 /* Check power mode of LCD0 */ |
209 |
#define LCD0_OPTION 0x3C88 /* Sets control options for LCD0 */ |
210 |
#define LCD1_CONFIGURATION 0x3CA0 /* Configure power mode of LCD1 */ |
211 |
#define LCD1_STATUS 0x3CA4 /* Check power mode of LCD1 */ |
212 |
#define LCD1_OPTION 0x3CA8 /* Sets control options for LCD1 */ |
213 |
#define GPS_CONFIGURATION 0x3CE0 /* Configure power mode of GPS */ |
214 |
#define GPS_STATUS 0x3CE4 /* Check power mode of GPS */ |
215 |
#define GPS_OPTION 0x3CE8 /* Sets control options for GPS */ |
216 |
#define GPS_ALIVE_CONFIGURATION 0x3D00 /* Configure power mode of GPS */ |
217 |
#define GPS_ALIVE_STATUS 0x3D04 /* Check power mode of GPS */ |
218 |
#define GPS_ALIVE_OPTION 0x3D08 /* Sets control options for GPS */ |
219 |
|
220 |
#define EXYNOS4210_PMU_REGS_MEM_SIZE 0x3d0c |
221 |
|
222 |
typedef struct Exynos4210PmuReg { |
223 |
const char *name; /* for debug only */ |
224 |
uint32_t offset; |
225 |
uint32_t reset_value; |
226 |
} Exynos4210PmuReg; |
227 |
|
228 |
static const Exynos4210PmuReg exynos4210_pmu_regs[] = { |
229 |
{"OM_STAT", OM_STAT, 0x00000000}, |
230 |
{"RTC_CLKO_SEL", RTC_CLKO_SEL, 0x00000000}, |
231 |
{"GNSS_RTC_OUT_CTRL", GNSS_RTC_OUT_CTRL, 0x00000001}, |
232 |
{"SYSTEM_POWER_DOWN_CTRL", SYSTEM_POWER_DOWN_CTRL, 0x00010000}, |
233 |
{"SYSTEM_POWER_DOWN_OPTION", SYSTEM_POWER_DOWN_OPTION, 0x03030000}, |
234 |
{"SWRESET", SWRESET, 0x00000000}, |
235 |
{"RST_STAT", RST_STAT, 0x00000000}, |
236 |
{"WAKEUP_STAT", WAKEUP_STAT, 0x00000000}, |
237 |
{"EINT_WAKEUP_MASK", EINT_WAKEUP_MASK, 0x00000000}, |
238 |
{"WAKEUP_MASK", WAKEUP_MASK, 0x00000000}, |
239 |
{"HDMI_PHY_CONTROL", HDMI_PHY_CONTROL, 0x00960000}, |
240 |
{"USBDEVICE_PHY_CONTROL", USBDEVICE_PHY_CONTROL, 0x00000000}, |
241 |
{"USBHOST_PHY_CONTROL", USBHOST_PHY_CONTROL, 0x00000000}, |
242 |
{"DAC_PHY_CONTROL", DAC_PHY_CONTROL, 0x00000000}, |
243 |
{"MIPI_PHY0_CONTROL", MIPI_PHY0_CONTROL, 0x00000000}, |
244 |
{"MIPI_PHY1_CONTROL", MIPI_PHY1_CONTROL, 0x00000000}, |
245 |
{"ADC_PHY_CONTROL", ADC_PHY_CONTROL, 0x00000001}, |
246 |
{"PCIe_PHY_CONTROL", PCIe_PHY_CONTROL, 0x00000000}, |
247 |
{"SATA_PHY_CONTROL", SATA_PHY_CONTROL, 0x00000000}, |
248 |
{"INFORM0", INFORM0, 0x00000000}, |
249 |
{"INFORM1", INFORM1, 0x00000000}, |
250 |
{"INFORM2", INFORM2, 0x00000000}, |
251 |
{"INFORM3", INFORM3, 0x00000000}, |
252 |
{"INFORM4", INFORM4, 0x00000000}, |
253 |
{"INFORM5", INFORM5, 0x00000000}, |
254 |
{"INFORM6", INFORM6, 0x00000000}, |
255 |
{"INFORM7", INFORM7, 0x00000000}, |
256 |
{"PMU_DEBUG", PMU_DEBUG, 0x00000000}, |
257 |
{"ARM_CORE0_SYS_PWR_REG", ARM_CORE0_SYS_PWR_REG, 0xFFFFFFFF}, |
258 |
{"ARM_CORE1_SYS_PWR_REG", ARM_CORE1_SYS_PWR_REG, 0xFFFFFFFF}, |
259 |
{"ARM_COMMON_SYS_PWR_REG", ARM_COMMON_SYS_PWR_REG, 0xFFFFFFFF}, |
260 |
{"ARM_CPU_L2_0_SYS_PWR_REG", ARM_CPU_L2_0_SYS_PWR_REG, 0xFFFFFFFF}, |
261 |
{"ARM_CPU_L2_1_SYS_PWR_REG", ARM_CPU_L2_1_SYS_PWR_REG, 0xFFFFFFFF}, |
262 |
{"CMU_ACLKSTOP_SYS_PWR_REG", CMU_ACLKSTOP_SYS_PWR_REG, 0xFFFFFFFF}, |
263 |
{"CMU_SCLKSTOP_SYS_PWR_REG", CMU_SCLKSTOP_SYS_PWR_REG, 0xFFFFFFFF}, |
264 |
{"CMU_RESET_SYS_PWR_REG", CMU_RESET_SYS_PWR_REG, 0xFFFFFFFF}, |
265 |
{"APLL_SYSCLK_SYS_PWR_REG", APLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, |
266 |
{"MPLL_SYSCLK_SYS_PWR_REG", MPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, |
267 |
{"VPLL_SYSCLK_SYS_PWR_REG", VPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, |
268 |
{"EPLL_SYSCLK_SYS_PWR_REG", EPLL_SYSCLK_SYS_PWR_REG, 0xFFFFFFFF}, |
269 |
{"CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG", CMU_CLKSTOP_GPS_ALIVE_SYS_PWR_REG,
|
270 |
0xFFFFFFFF},
|
271 |
{"CMU_RESET_GPS_ALIVE_SYS_PWR_REG", CMU_RESET_GPS_ALIVE_SYS_PWR_REG,
|
272 |
0xFFFFFFFF},
|
273 |
{"CMU_CLKSTOP_CAM_SYS_PWR_REG", CMU_CLKSTOP_CAM_SYS_PWR_REG, 0xFFFFFFFF}, |
274 |
{"CMU_CLKSTOP_TV_SYS_PWR_REG", CMU_CLKSTOP_TV_SYS_PWR_REG, 0xFFFFFFFF}, |
275 |
{"CMU_CLKSTOP_MFC_SYS_PWR_REG", CMU_CLKSTOP_MFC_SYS_PWR_REG, 0xFFFFFFFF}, |
276 |
{"CMU_CLKSTOP_G3D_SYS_PWR_REG", CMU_CLKSTOP_G3D_SYS_PWR_REG, 0xFFFFFFFF}, |
277 |
{"CMU_CLKSTOP_LCD0_SYS_PWR_REG", CMU_CLKSTOP_LCD0_SYS_PWR_REG, 0xFFFFFFFF}, |
278 |
{"CMU_CLKSTOP_LCD1_SYS_PWR_REG", CMU_CLKSTOP_LCD1_SYS_PWR_REG, 0xFFFFFFFF}, |
279 |
{"CMU_CLKSTOP_MAUDIO_SYS_PWR_REG", CMU_CLKSTOP_MAUDIO_SYS_PWR_REG,
|
280 |
0xFFFFFFFF},
|
281 |
{"CMU_CLKSTOP_GPS_SYS_PWR_REG", CMU_CLKSTOP_GPS_SYS_PWR_REG, 0xFFFFFFFF}, |
282 |
{"CMU_RESET_CAM_SYS_PWR_REG", CMU_RESET_CAM_SYS_PWR_REG, 0xFFFFFFFF}, |
283 |
{"CMU_RESET_TV_SYS_PWR_REG", CMU_RESET_TV_SYS_PWR_REG, 0xFFFFFFFF}, |
284 |
{"CMU_RESET_MFC_SYS_PWR_REG", CMU_RESET_MFC_SYS_PWR_REG, 0xFFFFFFFF}, |
285 |
{"CMU_RESET_G3D_SYS_PWR_REG", CMU_RESET_G3D_SYS_PWR_REG, 0xFFFFFFFF}, |
286 |
{"CMU_RESET_LCD0_SYS_PWR_REG", CMU_RESET_LCD0_SYS_PWR_REG, 0xFFFFFFFF}, |
287 |
{"CMU_RESET_LCD1_SYS_PWR_REG", CMU_RESET_LCD1_SYS_PWR_REG, 0xFFFFFFFF}, |
288 |
{"CMU_RESET_MAUDIO_SYS_PWR_REG", CMU_RESET_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, |
289 |
{"CMU_RESET_GPS_SYS_PWR_REG", CMU_RESET_GPS_SYS_PWR_REG, 0xFFFFFFFF}, |
290 |
{"TOP_BUS_SYS_PWR_REG", TOP_BUS_SYS_PWR_REG, 0xFFFFFFFF}, |
291 |
{"TOP_RETENTION_SYS_PWR_REG", TOP_RETENTION_SYS_PWR_REG, 0xFFFFFFFF}, |
292 |
{"TOP_PWR_SYS_PWR_REG", TOP_PWR_SYS_PWR_REG, 0xFFFFFFFF}, |
293 |
{"LOGIC_RESET_SYS_PWR_REG", LOGIC_RESET_SYS_PWR_REG, 0xFFFFFFFF}, |
294 |
{"OneNANDXL_MEM_SYS_PWR_REG", OneNANDXL_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
295 |
{"MODEMIF_MEM_SYS_PWR_REG", MODEMIF_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
296 |
{"USBDEVICE_MEM_SYS_PWR_REG", USBDEVICE_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
297 |
{"SDMMC_MEM_SYS_PWR_REG", SDMMC_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
298 |
{"CSSYS_MEM_SYS_PWR_REG", CSSYS_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
299 |
{"SECSS_MEM_SYS_PWR_REG", SECSS_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
300 |
{"PCIe_MEM_SYS_PWR_REG", PCIe_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
301 |
{"SATA_MEM_SYS_PWR_REG", SATA_MEM_SYS_PWR_REG, 0xFFFFFFFF}, |
302 |
{"PAD_RETENTION_DRAM_SYS_PWR_REG", PAD_RETENTION_DRAM_SYS_PWR_REG,
|
303 |
0xFFFFFFFF},
|
304 |
{"PAD_RETENTION_MAUDIO_SYS_PWR_REG", PAD_RETENTION_MAUDIO_SYS_PWR_REG,
|
305 |
0xFFFFFFFF},
|
306 |
{"PAD_RETENTION_GPIO_SYS_PWR_REG", PAD_RETENTION_GPIO_SYS_PWR_REG,
|
307 |
0xFFFFFFFF},
|
308 |
{"PAD_RETENTION_UART_SYS_PWR_REG", PAD_RETENTION_UART_SYS_PWR_REG,
|
309 |
0xFFFFFFFF},
|
310 |
{"PAD_RETENTION_MMCA_SYS_PWR_REG", PAD_RETENTION_MMCA_SYS_PWR_REG,
|
311 |
0xFFFFFFFF},
|
312 |
{"PAD_RETENTION_MMCB_SYS_PWR_REG", PAD_RETENTION_MMCB_SYS_PWR_REG,
|
313 |
0xFFFFFFFF},
|
314 |
{"PAD_RETENTION_EBIA_SYS_PWR_REG", PAD_RETENTION_EBIA_SYS_PWR_REG,
|
315 |
0xFFFFFFFF},
|
316 |
{"PAD_RETENTION_EBIB_SYS_PWR_REG", PAD_RETENTION_EBIB_SYS_PWR_REG,
|
317 |
0xFFFFFFFF},
|
318 |
{"PAD_ISOLATION_SYS_PWR_REG", PAD_ISOLATION_SYS_PWR_REG, 0xFFFFFFFF}, |
319 |
{"PAD_ALV_SEL_SYS_PWR_REG", PAD_ALV_SEL_SYS_PWR_REG, 0xFFFFFFFF}, |
320 |
{"XUSBXTI_SYS_PWR_REG", XUSBXTI_SYS_PWR_REG, 0xFFFFFFFF}, |
321 |
{"XXTI_SYS_PWR_REG", XXTI_SYS_PWR_REG, 0xFFFFFFFF}, |
322 |
{"EXT_REGULATOR_SYS_PWR_REG", EXT_REGULATOR_SYS_PWR_REG, 0xFFFFFFFF}, |
323 |
{"GPIO_MODE_SYS_PWR_REG", GPIO_MODE_SYS_PWR_REG, 0xFFFFFFFF}, |
324 |
{"GPIO_MODE_MAUDIO_SYS_PWR_REG", GPIO_MODE_MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, |
325 |
{"CAM_SYS_PWR_REG", CAM_SYS_PWR_REG, 0xFFFFFFFF}, |
326 |
{"TV_SYS_PWR_REG", TV_SYS_PWR_REG, 0xFFFFFFFF}, |
327 |
{"MFC_SYS_PWR_REG", MFC_SYS_PWR_REG, 0xFFFFFFFF}, |
328 |
{"G3D_SYS_PWR_REG", G3D_SYS_PWR_REG, 0xFFFFFFFF}, |
329 |
{"LCD0_SYS_PWR_REG", LCD0_SYS_PWR_REG, 0xFFFFFFFF}, |
330 |
{"LCD1_SYS_PWR_REG", LCD1_SYS_PWR_REG, 0xFFFFFFFF}, |
331 |
{"MAUDIO_SYS_PWR_REG", MAUDIO_SYS_PWR_REG, 0xFFFFFFFF}, |
332 |
{"GPS_SYS_PWR_REG", GPS_SYS_PWR_REG, 0xFFFFFFFF}, |
333 |
{"GPS_ALIVE_SYS_PWR_REG", GPS_ALIVE_SYS_PWR_REG, 0xFFFFFFFF}, |
334 |
{"ARM_CORE0_CONFIGURATION", ARM_CORE0_CONFIGURATION, 0x00000003}, |
335 |
{"ARM_CORE0_STATUS", ARM_CORE0_STATUS, 0x00030003}, |
336 |
{"ARM_CORE0_OPTION", ARM_CORE0_OPTION, 0x01010001}, |
337 |
{"ARM_CORE1_CONFIGURATION", ARM_CORE1_CONFIGURATION, 0x00000003}, |
338 |
{"ARM_CORE1_STATUS", ARM_CORE1_STATUS, 0x00030003}, |
339 |
{"ARM_CORE1_OPTION", ARM_CORE1_OPTION, 0x01010001}, |
340 |
{"ARM_COMMON_OPTION", ARM_COMMON_OPTION, 0x00000001}, |
341 |
{"ARM_CPU_L2_0_CONFIGURATION", ARM_CPU_L2_0_CONFIGURATION, 0x00000003}, |
342 |
{"ARM_CPU_L2_0_STATUS", ARM_CPU_L2_0_STATUS, 0x00000003}, |
343 |
{"ARM_CPU_L2_1_CONFIGURATION", ARM_CPU_L2_1_CONFIGURATION, 0x00000003}, |
344 |
{"ARM_CPU_L2_1_STATUS", ARM_CPU_L2_1_STATUS, 0x00000003}, |
345 |
{"PAD_RETENTION_MAUDIO_OPTION", PAD_RETENTION_MAUDIO_OPTION, 0x00000000}, |
346 |
{"PAD_RETENTION_GPIO_OPTION", PAD_RETENTION_GPIO_OPTION, 0x00000000}, |
347 |
{"PAD_RETENTION_UART_OPTION", PAD_RETENTION_UART_OPTION, 0x00000000}, |
348 |
{"PAD_RETENTION_MMCA_OPTION", PAD_RETENTION_MMCA_OPTION, 0x00000000}, |
349 |
{"PAD_RETENTION_MMCB_OPTION", PAD_RETENTION_MMCB_OPTION, 0x00000000}, |
350 |
{"PAD_RETENTION_EBIA_OPTION", PAD_RETENTION_EBIA_OPTION, 0x00000000}, |
351 |
{"PAD_RETENTION_EBIB_OPTION", PAD_RETENTION_EBIB_OPTION, 0x00000000}, |
352 |
{"PS_HOLD_CONTROL", PS_HOLD_CONTROL, 0x00005200}, |
353 |
{"XUSBXTI_CONFIGURATION", XUSBXTI_CONFIGURATION, 0x00000001}, |
354 |
{"XUSBXTI_STATUS", XUSBXTI_STATUS, 0x00000001}, |
355 |
{"XUSBXTI_DURATION", XUSBXTI_DURATION, 0xFFF00000}, |
356 |
{"XXTI_CONFIGURATION", XXTI_CONFIGURATION, 0x00000001}, |
357 |
{"XXTI_STATUS", XXTI_STATUS, 0x00000001}, |
358 |
{"XXTI_DURATION", XXTI_DURATION, 0xFFF00000}, |
359 |
{"EXT_REGULATOR_DURATION", EXT_REGULATOR_DURATION, 0xFFF03FFF}, |
360 |
{"CAM_CONFIGURATION", CAM_CONFIGURATION, 0x00000007}, |
361 |
{"CAM_STATUS", CAM_STATUS, 0x00060007}, |
362 |
{"CAM_OPTION", CAM_OPTION, 0x00000001}, |
363 |
{"TV_CONFIGURATION", TV_CONFIGURATION, 0x00000007}, |
364 |
{"TV_STATUS", TV_STATUS, 0x00060007}, |
365 |
{"TV_OPTION", TV_OPTION, 0x00000001}, |
366 |
{"MFC_CONFIGURATION", MFC_CONFIGURATION, 0x00000007}, |
367 |
{"MFC_STATUS", MFC_STATUS, 0x00060007}, |
368 |
{"MFC_OPTION", MFC_OPTION, 0x00000001}, |
369 |
{"G3D_CONFIGURATION", G3D_CONFIGURATION, 0x00000007}, |
370 |
{"G3D_STATUS", G3D_STATUS, 0x00060007}, |
371 |
{"G3D_OPTION", G3D_OPTION, 0x00000001}, |
372 |
{"LCD0_CONFIGURATION", LCD0_CONFIGURATION, 0x00000007}, |
373 |
{"LCD0_STATUS", LCD0_STATUS, 0x00060007}, |
374 |
{"LCD0_OPTION", LCD0_OPTION, 0x00000001}, |
375 |
{"LCD1_CONFIGURATION", LCD1_CONFIGURATION, 0x00000007}, |
376 |
{"LCD1_STATUS", LCD1_STATUS, 0x00060007}, |
377 |
{"LCD1_OPTION", LCD1_OPTION, 0x00000001}, |
378 |
{"GPS_CONFIGURATION", GPS_CONFIGURATION, 0x00000007}, |
379 |
{"GPS_STATUS", GPS_STATUS, 0x00060007}, |
380 |
{"GPS_OPTION", GPS_OPTION, 0x00000001}, |
381 |
{"GPS_ALIVE_CONFIGURATION", GPS_ALIVE_CONFIGURATION, 0x00000007}, |
382 |
{"GPS_ALIVE_STATUS", GPS_ALIVE_STATUS, 0x00060007}, |
383 |
{"GPS_ALIVE_OPTION", GPS_ALIVE_OPTION, 0x00000001}, |
384 |
}; |
385 |
|
386 |
#define PMU_NUM_OF_REGISTERS \
|
387 |
(sizeof(exynos4210_pmu_regs) / sizeof(Exynos4210PmuReg)) |
388 |
|
389 |
typedef struct Exynos4210PmuState { |
390 |
SysBusDevice busdev; |
391 |
MemoryRegion iomem; |
392 |
uint32_t reg[PMU_NUM_OF_REGISTERS]; |
393 |
} Exynos4210PmuState; |
394 |
|
395 |
static uint64_t exynos4210_pmu_read(void *opaque, target_phys_addr_t offset, |
396 |
unsigned size)
|
397 |
{ |
398 |
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; |
399 |
unsigned i;
|
400 |
const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
|
401 |
|
402 |
for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { |
403 |
if (reg_p->offset == offset) {
|
404 |
PRINT_DEBUG_EXTEND("%s [0x%04x] -> 0x%04x\n", reg_p->name,
|
405 |
(uint32_t)offset, s->reg[i]); |
406 |
return s->reg[i];
|
407 |
} |
408 |
reg_p++; |
409 |
} |
410 |
PRINT_DEBUG("QEMU PMU ERROR: bad read offset 0x%04x\n", (uint32_t)offset);
|
411 |
return 0; |
412 |
} |
413 |
|
414 |
static void exynos4210_pmu_write(void *opaque, target_phys_addr_t offset, |
415 |
uint64_t val, unsigned size)
|
416 |
{ |
417 |
Exynos4210PmuState *s = (Exynos4210PmuState *)opaque; |
418 |
unsigned i;
|
419 |
const Exynos4210PmuReg *reg_p = exynos4210_pmu_regs;
|
420 |
|
421 |
for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { |
422 |
if (reg_p->offset == offset) {
|
423 |
PRINT_DEBUG_EXTEND("%s <0x%04x> <- 0x%04x\n", reg_p->name,
|
424 |
(uint32_t)offset, (uint32_t)val); |
425 |
s->reg[i] = val; |
426 |
return;
|
427 |
} |
428 |
reg_p++; |
429 |
} |
430 |
PRINT_DEBUG("QEMU PMU ERROR: bad write offset 0x%04x\n", (uint32_t)offset);
|
431 |
} |
432 |
|
433 |
static const MemoryRegionOps exynos4210_pmu_ops = { |
434 |
.read = exynos4210_pmu_read, |
435 |
.write = exynos4210_pmu_write, |
436 |
.endianness = DEVICE_NATIVE_ENDIAN, |
437 |
.valid = { |
438 |
.min_access_size = 4,
|
439 |
.max_access_size = 4,
|
440 |
.unaligned = false
|
441 |
} |
442 |
}; |
443 |
|
444 |
static void exynos4210_pmu_reset(DeviceState *dev) |
445 |
{ |
446 |
Exynos4210PmuState *s = |
447 |
container_of(dev, Exynos4210PmuState, busdev.qdev); |
448 |
unsigned i;
|
449 |
|
450 |
/* Set default values for registers */
|
451 |
for (i = 0; i < PMU_NUM_OF_REGISTERS; i++) { |
452 |
s->reg[i] = exynos4210_pmu_regs[i].reset_value; |
453 |
} |
454 |
} |
455 |
|
456 |
static int exynos4210_pmu_init(SysBusDevice *dev) |
457 |
{ |
458 |
Exynos4210PmuState *s = FROM_SYSBUS(Exynos4210PmuState, dev); |
459 |
|
460 |
/* memory mapping */
|
461 |
memory_region_init_io(&s->iomem, &exynos4210_pmu_ops, s, "exynos4210.pmu",
|
462 |
EXYNOS4210_PMU_REGS_MEM_SIZE); |
463 |
sysbus_init_mmio(dev, &s->iomem); |
464 |
return 0; |
465 |
} |
466 |
|
467 |
static const VMStateDescription exynos4210_pmu_vmstate = { |
468 |
.name = "exynos4210.pmu",
|
469 |
.version_id = 1,
|
470 |
.minimum_version_id = 1,
|
471 |
.fields = (VMStateField[]) { |
472 |
VMSTATE_UINT32_ARRAY(reg, Exynos4210PmuState, PMU_NUM_OF_REGISTERS), |
473 |
VMSTATE_END_OF_LIST() |
474 |
} |
475 |
}; |
476 |
|
477 |
static void exynos4210_pmu_class_init(ObjectClass *klass, void *data) |
478 |
{ |
479 |
DeviceClass *dc = DEVICE_CLASS(klass); |
480 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
481 |
|
482 |
k->init = exynos4210_pmu_init; |
483 |
dc->reset = exynos4210_pmu_reset; |
484 |
dc->vmsd = &exynos4210_pmu_vmstate; |
485 |
} |
486 |
|
487 |
static TypeInfo exynos4210_pmu_info = {
|
488 |
.name = "exynos4210.pmu",
|
489 |
.parent = TYPE_SYS_BUS_DEVICE, |
490 |
.instance_size = sizeof(Exynos4210PmuState),
|
491 |
.class_init = exynos4210_pmu_class_init, |
492 |
}; |
493 |
|
494 |
static void exynos4210_pmu_register(void) |
495 |
{ |
496 |
type_register_static(&exynos4210_pmu_info); |
497 |
} |
498 |
|
499 |
type_init(exynos4210_pmu_register) |