Revision 90cb786c

b/target-mips/translate.c
1902 1902

  
1903 1903
            tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[1], 0, l1);
1904 1904
            {
1905
                TCGv r_tmp1 = new_tmp();
1906
                TCGv r_tmp2 = new_tmp();
1907
                TCGv r_tmp3 = new_tmp();
1905
                TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_I64);
1906
                TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64);
1908 1907

  
1909
                tcg_gen_trunc_tl_i32(r_tmp1, cpu_T[0]);
1910
                tcg_gen_trunc_tl_i32(r_tmp2, cpu_T[1]);
1911
                tcg_gen_div_i32(r_tmp3, r_tmp1, r_tmp2);
1912
                tcg_gen_rem_i32(r_tmp1, r_tmp1, r_tmp2);
1913
                tcg_gen_ext_i32_tl(cpu_T[0], r_tmp3);
1914
                tcg_gen_ext_i32_tl(cpu_T[1], r_tmp1);
1915
                gen_store_LO(cpu_T[0], 0);
1916
                gen_store_HI(cpu_T[1], 0);
1917
                dead_tmp(r_tmp1);
1918
                dead_tmp(r_tmp2);
1919
                dead_tmp(r_tmp3);
1908
                tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
1909
                tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
1910
                tcg_gen_div_i64(r_tmp1, cpu_T[0], cpu_T[1]);
1911
                tcg_gen_rem_i64(r_tmp2, cpu_T[0], cpu_T[1]);
1912
                tcg_gen_ext32s_tl(r_tmp1, r_tmp1);
1913
                tcg_gen_ext32s_tl(r_tmp2, r_tmp2);
1914
                gen_store_LO(r_tmp1, 0);
1915
                gen_store_HI(r_tmp2, 0);
1920 1916
            }
1921 1917
            gen_set_label(l1);
1922 1918
        }

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