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/*
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 * QEMU Floppy disk emulator (Intel 82078)
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 *
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 * Copyright (c) 2003, 2007 Jocelyn Mayer
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 * Copyright (c) 2008 Herv? Poussineau
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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/*
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 * The controller is used in Sun4m systems in a slightly different
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 * way. There are changes in DOR register and DMA is not available.
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 */
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#include "hw.h"
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#include "fdc.h"
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#include "block.h"
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#include "qemu-timer.h"
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#include "isa.h"
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/********************************************************/
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/* debug Floppy devices */
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//#define DEBUG_FLOPPY
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#ifdef DEBUG_FLOPPY
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#define FLOPPY_DPRINTF(fmt, ...)                                \
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    do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define FLOPPY_DPRINTF(fmt, ...)
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#endif
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#define FLOPPY_ERROR(fmt, ...)                                          \
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    do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
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/********************************************************/
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/* Floppy drive emulation                               */
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#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
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#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
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/* Will always be a fixed parameter for us */
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#define FD_SECTOR_LEN          512
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#define FD_SECTOR_SC           2   /* Sector size code */
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#define FD_RESET_SENSEI_COUNT  4   /* Number of sense interrupts on RESET */
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/* Floppy disk drive emulation */
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typedef enum fdisk_type_t {
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    FDRIVE_DISK_288   = 0x01, /* 2.88 MB disk           */
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    FDRIVE_DISK_144   = 0x02, /* 1.44 MB disk           */
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    FDRIVE_DISK_720   = 0x03, /* 720 kB disk            */
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    FDRIVE_DISK_USER  = 0x04, /* User defined geometry  */
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    FDRIVE_DISK_NONE  = 0x05, /* No disk                */
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} fdisk_type_t;
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typedef enum fdrive_type_t {
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    FDRIVE_DRV_144  = 0x00,   /* 1.44 MB 3"5 drive      */
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    FDRIVE_DRV_288  = 0x01,   /* 2.88 MB 3"5 drive      */
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    FDRIVE_DRV_120  = 0x02,   /* 1.2  MB 5"25 drive     */
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    FDRIVE_DRV_NONE = 0x03,   /* No drive connected     */
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} fdrive_type_t;
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typedef enum fdisk_flags_t {
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    FDISK_DBL_SIDES  = 0x01,
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} fdisk_flags_t;
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typedef struct fdrive_t {
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    BlockDriverState *bs;
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    /* Drive status */
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    fdrive_type_t drive;
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    uint8_t perpendicular;    /* 2.88 MB access mode    */
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    /* Position */
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    uint8_t head;
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    uint8_t track;
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    uint8_t sect;
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    /* Media */
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    fdisk_flags_t flags;
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    uint8_t last_sect;        /* Nb sector per track    */
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    uint8_t max_track;        /* Nb of tracks           */
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    uint16_t bps;             /* Bytes per sector       */
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    uint8_t ro;               /* Is read-only           */
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} fdrive_t;
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static void fd_init (fdrive_t *drv, BlockDriverState *bs)
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{
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    /* Drive */
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    drv->bs = bs;
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    drv->drive = FDRIVE_DRV_NONE;
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    drv->perpendicular = 0;
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    /* Disk */
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    drv->last_sect = 0;
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    drv->max_track = 0;
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}
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static int _fd_sector (uint8_t head, uint8_t track,
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                       uint8_t sect, uint8_t last_sect)
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{
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    return (((track * 2) + head) * last_sect) + sect - 1;
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}
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/* Returns current position, in sectors, for given drive */
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static int fd_sector (fdrive_t *drv)
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{
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    return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
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}
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/* Seek to a new position:
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 * returns 0 if already on right track
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 * returns 1 if track changed
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 * returns 2 if track is invalid
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 * returns 3 if sector is invalid
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 * returns 4 if seek is disabled
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 */
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static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
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                    int enable_seek)
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{
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    uint32_t sector;
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    int ret;
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    if (track > drv->max_track ||
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        (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 2;
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    }
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    if (sect > drv->last_sect) {
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        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
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                       head, track, sect, 1,
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                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
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                       drv->max_track, drv->last_sect);
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        return 3;
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    }
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    sector = _fd_sector(head, track, sect, drv->last_sect);
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    ret = 0;
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    if (sector != fd_sector(drv)) {
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#if 0
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        if (!enable_seek) {
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            FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
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                         head, track, sect, 1, drv->max_track, drv->last_sect);
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            return 4;
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        }
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#endif
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        drv->head = head;
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        if (drv->track != track)
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            ret = 1;
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        drv->track = track;
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        drv->sect = sect;
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    }
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    return ret;
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}
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/* Set drive back to track 0 */
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static void fd_recalibrate (fdrive_t *drv)
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{
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    FLOPPY_DPRINTF("recalibrate\n");
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    drv->head = 0;
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    drv->track = 0;
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    drv->sect = 1;
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}
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/* Recognize floppy formats */
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typedef struct fd_format_t {
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    fdrive_type_t drive;
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    fdisk_type_t  disk;
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    uint8_t last_sect;
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    uint8_t max_track;
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    uint8_t max_head;
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    const char *str;
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} fd_format_t;
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static const fd_format_t fd_formats[] = {
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    /* First entry is default format */
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    /* 1.44 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1,  "1.6 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
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    /* 2.88 MB 3"1/2 floppy disks */
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1,  "3.2 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
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    { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
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    /* 720 kB 3"1/2 floppy disks */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 1,  "720 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1,  "800 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1,  "820 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1,  "830 kB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
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    { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
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    /* 1.2 MB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1,  "1.2 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1,  "1.6 MB 5\"1/4", },
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    /* 720 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 80, 1,  "720 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1,  "880 kB 5\"1/4", },
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    /* 360 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 1,  "360 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 0,  "180 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1,  "410 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1,  "420 kB 5\"1/4", },
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    /* 320 kB 5"1/4 floppy disks */
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 1,  "320 kB 5\"1/4", },
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    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 0,  "160 kB 5\"1/4", },
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    /* 360 kB must match 5"1/4 better than 3"1/2... */
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    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 0,  "360 kB 3\"1/2", },
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    /* end */
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    { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
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};
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/* Revalidate a disk drive after a disk change */
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static void fd_revalidate (fdrive_t *drv)
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{
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    const fd_format_t *parse;
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    uint64_t nb_sectors, size;
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    int i, first_match, match;
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    int nb_heads, max_track, last_sect, ro;
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    FLOPPY_DPRINTF("revalidate\n");
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    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
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        ro = bdrv_is_read_only(drv->bs);
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        bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
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        if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
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            FLOPPY_DPRINTF("User defined disk (%d %d %d)",
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                           nb_heads - 1, max_track, last_sect);
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        } else {
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            bdrv_get_geometry(drv->bs, &nb_sectors);
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            match = -1;
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            first_match = -1;
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            for (i = 0;; i++) {
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                parse = &fd_formats[i];
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                if (parse->drive == FDRIVE_DRV_NONE)
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                    break;
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                if (drv->drive == parse->drive ||
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                    drv->drive == FDRIVE_DRV_NONE) {
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                    size = (parse->max_head + 1) * parse->max_track *
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                        parse->last_sect;
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                    if (nb_sectors == size) {
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                        match = i;
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                        break;
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                    }
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                    if (first_match == -1)
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                        first_match = i;
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                }
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            }
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            if (match == -1) {
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                if (first_match == -1)
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                    match = 1;
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                else
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                    match = first_match;
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                parse = &fd_formats[match];
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            }
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            nb_heads = parse->max_head + 1;
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            max_track = parse->max_track;
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            last_sect = parse->last_sect;
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            drv->drive = parse->drive;
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            FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
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                           nb_heads, max_track, last_sect, ro ? "ro" : "rw");
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        }
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        if (nb_heads == 1) {
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            drv->flags &= ~FDISK_DBL_SIDES;
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        } else {
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            drv->flags |= FDISK_DBL_SIDES;
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        }
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        drv->max_track = max_track;
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        drv->last_sect = last_sect;
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        drv->ro = ro;
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    } else {
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        FLOPPY_DPRINTF("No disk in drive\n");
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        drv->last_sect = 0;
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        drv->max_track = 0;
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        drv->flags &= ~FDISK_DBL_SIDES;
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    }
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}
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/********************************************************/
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/* Intel 82078 floppy disk controller emulation          */
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static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
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static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
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static int fdctrl_transfer_handler (void *opaque, int nchan,
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                                    int dma_pos, int dma_len);
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static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
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static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
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static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
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static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
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static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
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static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
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static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
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static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
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320 8977f3c1 bellard
enum {
321 8977f3c1 bellard
    FD_DIR_WRITE   = 0,
322 8977f3c1 bellard
    FD_DIR_READ    = 1,
323 8977f3c1 bellard
    FD_DIR_SCANE   = 2,
324 8977f3c1 bellard
    FD_DIR_SCANL   = 3,
325 8977f3c1 bellard
    FD_DIR_SCANH   = 4,
326 8977f3c1 bellard
};
327 8977f3c1 bellard
328 8977f3c1 bellard
enum {
329 b9b3d225 blueswir1
    FD_STATE_MULTI  = 0x01,        /* multi track flag */
330 b9b3d225 blueswir1
    FD_STATE_FORMAT = 0x02,        /* format flag */
331 b9b3d225 blueswir1
    FD_STATE_SEEK   = 0x04,        /* seek flag */
332 8977f3c1 bellard
};
333 8977f3c1 bellard
334 9fea808a blueswir1
enum {
335 8c6a4d77 blueswir1
    FD_REG_SRA = 0x00,
336 8c6a4d77 blueswir1
    FD_REG_SRB = 0x01,
337 9fea808a blueswir1
    FD_REG_DOR = 0x02,
338 9fea808a blueswir1
    FD_REG_TDR = 0x03,
339 9fea808a blueswir1
    FD_REG_MSR = 0x04,
340 9fea808a blueswir1
    FD_REG_DSR = 0x04,
341 9fea808a blueswir1
    FD_REG_FIFO = 0x05,
342 9fea808a blueswir1
    FD_REG_DIR = 0x07,
343 9fea808a blueswir1
};
344 9fea808a blueswir1
345 9fea808a blueswir1
enum {
346 65cef780 blueswir1
    FD_CMD_READ_TRACK = 0x02,
347 9fea808a blueswir1
    FD_CMD_SPECIFY = 0x03,
348 9fea808a blueswir1
    FD_CMD_SENSE_DRIVE_STATUS = 0x04,
349 65cef780 blueswir1
    FD_CMD_WRITE = 0x05,
350 65cef780 blueswir1
    FD_CMD_READ = 0x06,
351 9fea808a blueswir1
    FD_CMD_RECALIBRATE = 0x07,
352 9fea808a blueswir1
    FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
353 65cef780 blueswir1
    FD_CMD_WRITE_DELETED = 0x09,
354 65cef780 blueswir1
    FD_CMD_READ_ID = 0x0a,
355 65cef780 blueswir1
    FD_CMD_READ_DELETED = 0x0c,
356 65cef780 blueswir1
    FD_CMD_FORMAT_TRACK = 0x0d,
357 9fea808a blueswir1
    FD_CMD_DUMPREG = 0x0e,
358 9fea808a blueswir1
    FD_CMD_SEEK = 0x0f,
359 9fea808a blueswir1
    FD_CMD_VERSION = 0x10,
360 65cef780 blueswir1
    FD_CMD_SCAN_EQUAL = 0x11,
361 9fea808a blueswir1
    FD_CMD_PERPENDICULAR_MODE = 0x12,
362 9fea808a blueswir1
    FD_CMD_CONFIGURE = 0x13,
363 65cef780 blueswir1
    FD_CMD_LOCK = 0x14,
364 65cef780 blueswir1
    FD_CMD_VERIFY = 0x16,
365 9fea808a blueswir1
    FD_CMD_POWERDOWN_MODE = 0x17,
366 9fea808a blueswir1
    FD_CMD_PART_ID = 0x18,
367 65cef780 blueswir1
    FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
368 65cef780 blueswir1
    FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
369 9fea808a blueswir1
    FD_CMD_SAVE = 0x2c,
370 9fea808a blueswir1
    FD_CMD_OPTION = 0x33,
371 9fea808a blueswir1
    FD_CMD_RESTORE = 0x4c,
372 9fea808a blueswir1
    FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
373 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
374 9fea808a blueswir1
    FD_CMD_FORMAT_AND_WRITE = 0xcd,
375 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_IN = 0xcf,
376 9fea808a blueswir1
};
377 9fea808a blueswir1
378 9fea808a blueswir1
enum {
379 9fea808a blueswir1
    FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
380 9fea808a blueswir1
    FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
381 9fea808a blueswir1
    FD_CONFIG_POLL  = 0x10, /* Poll enabled */
382 9fea808a blueswir1
    FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
383 9fea808a blueswir1
    FD_CONFIG_EIS   = 0x40, /* No implied seeks */
384 9fea808a blueswir1
};
385 9fea808a blueswir1
386 9fea808a blueswir1
enum {
387 9fea808a blueswir1
    FD_SR0_EQPMT    = 0x10,
388 9fea808a blueswir1
    FD_SR0_SEEK     = 0x20,
389 9fea808a blueswir1
    FD_SR0_ABNTERM  = 0x40,
390 9fea808a blueswir1
    FD_SR0_INVCMD   = 0x80,
391 9fea808a blueswir1
    FD_SR0_RDYCHG   = 0xc0,
392 9fea808a blueswir1
};
393 9fea808a blueswir1
394 9fea808a blueswir1
enum {
395 77370520 blueswir1
    FD_SR1_EC       = 0x80, /* End of cylinder */
396 77370520 blueswir1
};
397 77370520 blueswir1
398 77370520 blueswir1
enum {
399 77370520 blueswir1
    FD_SR2_SNS      = 0x04, /* Scan not satisfied */
400 77370520 blueswir1
    FD_SR2_SEH      = 0x08, /* Scan equal hit */
401 77370520 blueswir1
};
402 77370520 blueswir1
403 77370520 blueswir1
enum {
404 8c6a4d77 blueswir1
    FD_SRA_DIR      = 0x01,
405 8c6a4d77 blueswir1
    FD_SRA_nWP      = 0x02,
406 8c6a4d77 blueswir1
    FD_SRA_nINDX    = 0x04,
407 8c6a4d77 blueswir1
    FD_SRA_HDSEL    = 0x08,
408 8c6a4d77 blueswir1
    FD_SRA_nTRK0    = 0x10,
409 8c6a4d77 blueswir1
    FD_SRA_STEP     = 0x20,
410 8c6a4d77 blueswir1
    FD_SRA_nDRV2    = 0x40,
411 8c6a4d77 blueswir1
    FD_SRA_INTPEND  = 0x80,
412 8c6a4d77 blueswir1
};
413 8c6a4d77 blueswir1
414 8c6a4d77 blueswir1
enum {
415 8c6a4d77 blueswir1
    FD_SRB_MTR0     = 0x01,
416 8c6a4d77 blueswir1
    FD_SRB_MTR1     = 0x02,
417 8c6a4d77 blueswir1
    FD_SRB_WGATE    = 0x04,
418 8c6a4d77 blueswir1
    FD_SRB_RDATA    = 0x08,
419 8c6a4d77 blueswir1
    FD_SRB_WDATA    = 0x10,
420 8c6a4d77 blueswir1
    FD_SRB_DR0      = 0x20,
421 8c6a4d77 blueswir1
};
422 8c6a4d77 blueswir1
423 8c6a4d77 blueswir1
enum {
424 78ae820c blueswir1
#if MAX_FD == 4
425 78ae820c blueswir1
    FD_DOR_SELMASK  = 0x03,
426 78ae820c blueswir1
#else
427 9fea808a blueswir1
    FD_DOR_SELMASK  = 0x01,
428 78ae820c blueswir1
#endif
429 9fea808a blueswir1
    FD_DOR_nRESET   = 0x04,
430 9fea808a blueswir1
    FD_DOR_DMAEN    = 0x08,
431 9fea808a blueswir1
    FD_DOR_MOTEN0   = 0x10,
432 9fea808a blueswir1
    FD_DOR_MOTEN1   = 0x20,
433 9fea808a blueswir1
    FD_DOR_MOTEN2   = 0x40,
434 9fea808a blueswir1
    FD_DOR_MOTEN3   = 0x80,
435 9fea808a blueswir1
};
436 9fea808a blueswir1
437 9fea808a blueswir1
enum {
438 78ae820c blueswir1
#if MAX_FD == 4
439 9fea808a blueswir1
    FD_TDR_BOOTSEL  = 0x0c,
440 78ae820c blueswir1
#else
441 78ae820c blueswir1
    FD_TDR_BOOTSEL  = 0x04,
442 78ae820c blueswir1
#endif
443 9fea808a blueswir1
};
444 9fea808a blueswir1
445 9fea808a blueswir1
enum {
446 9fea808a blueswir1
    FD_DSR_DRATEMASK= 0x03,
447 9fea808a blueswir1
    FD_DSR_PWRDOWN  = 0x40,
448 9fea808a blueswir1
    FD_DSR_SWRESET  = 0x80,
449 9fea808a blueswir1
};
450 9fea808a blueswir1
451 9fea808a blueswir1
enum {
452 9fea808a blueswir1
    FD_MSR_DRV0BUSY = 0x01,
453 9fea808a blueswir1
    FD_MSR_DRV1BUSY = 0x02,
454 9fea808a blueswir1
    FD_MSR_DRV2BUSY = 0x04,
455 9fea808a blueswir1
    FD_MSR_DRV3BUSY = 0x08,
456 9fea808a blueswir1
    FD_MSR_CMDBUSY  = 0x10,
457 9fea808a blueswir1
    FD_MSR_NONDMA   = 0x20,
458 9fea808a blueswir1
    FD_MSR_DIO      = 0x40,
459 9fea808a blueswir1
    FD_MSR_RQM      = 0x80,
460 9fea808a blueswir1
};
461 9fea808a blueswir1
462 9fea808a blueswir1
enum {
463 9fea808a blueswir1
    FD_DIR_DSKCHG   = 0x80,
464 9fea808a blueswir1
};
465 9fea808a blueswir1
466 8977f3c1 bellard
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
467 8977f3c1 bellard
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
468 baca51fa bellard
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
469 8977f3c1 bellard
470 baca51fa bellard
struct fdctrl_t {
471 4b19ec0c bellard
    /* Controller's identification */
472 8977f3c1 bellard
    uint8_t version;
473 8977f3c1 bellard
    /* HW */
474 d537cf6c pbrook
    qemu_irq irq;
475 8977f3c1 bellard
    int dma_chann;
476 5dcb6b91 blueswir1
    target_phys_addr_t io_base;
477 4b19ec0c bellard
    /* Controller state */
478 ed5fd2cc bellard
    QEMUTimer *result_timer;
479 8c6a4d77 blueswir1
    uint8_t sra;
480 8c6a4d77 blueswir1
    uint8_t srb;
481 368df94d blueswir1
    uint8_t dor;
482 46d3233b blueswir1
    uint8_t tdr;
483 b9b3d225 blueswir1
    uint8_t dsr;
484 368df94d blueswir1
    uint8_t msr;
485 8977f3c1 bellard
    uint8_t cur_drv;
486 77370520 blueswir1
    uint8_t status0;
487 77370520 blueswir1
    uint8_t status1;
488 77370520 blueswir1
    uint8_t status2;
489 8977f3c1 bellard
    /* Command FIFO */
490 33f00271 balrog
    uint8_t *fifo;
491 8977f3c1 bellard
    uint32_t data_pos;
492 8977f3c1 bellard
    uint32_t data_len;
493 8977f3c1 bellard
    uint8_t data_state;
494 8977f3c1 bellard
    uint8_t data_dir;
495 890fa6be bellard
    uint8_t eot; /* last wanted sector */
496 8977f3c1 bellard
    /* States kept only to be returned back */
497 8977f3c1 bellard
    /* Timers state */
498 8977f3c1 bellard
    uint8_t timer0;
499 8977f3c1 bellard
    uint8_t timer1;
500 8977f3c1 bellard
    /* precompensation */
501 8977f3c1 bellard
    uint8_t precomp_trk;
502 8977f3c1 bellard
    uint8_t config;
503 8977f3c1 bellard
    uint8_t lock;
504 8977f3c1 bellard
    /* Power down config (also with status regB access mode */
505 8977f3c1 bellard
    uint8_t pwrd;
506 741402f9 blueswir1
    /* Sun4m quirks? */
507 a06e5a3c blueswir1
    int sun4m;
508 8977f3c1 bellard
    /* Floppy drives */
509 78ae820c blueswir1
    fdrive_t drives[MAX_FD];
510 f2d81b33 blueswir1
    int reset_sensei;
511 baca51fa bellard
};
512 baca51fa bellard
513 baca51fa bellard
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
514 baca51fa bellard
{
515 baca51fa bellard
    fdctrl_t *fdctrl = opaque;
516 baca51fa bellard
    uint32_t retval;
517 baca51fa bellard
518 e64d7d59 blueswir1
    switch (reg) {
519 8c6a4d77 blueswir1
    case FD_REG_SRA:
520 8c6a4d77 blueswir1
        retval = fdctrl_read_statusA(fdctrl);
521 4f431960 j_mayer
        break;
522 8c6a4d77 blueswir1
    case FD_REG_SRB:
523 4f431960 j_mayer
        retval = fdctrl_read_statusB(fdctrl);
524 4f431960 j_mayer
        break;
525 9fea808a blueswir1
    case FD_REG_DOR:
526 4f431960 j_mayer
        retval = fdctrl_read_dor(fdctrl);
527 4f431960 j_mayer
        break;
528 9fea808a blueswir1
    case FD_REG_TDR:
529 baca51fa bellard
        retval = fdctrl_read_tape(fdctrl);
530 4f431960 j_mayer
        break;
531 9fea808a blueswir1
    case FD_REG_MSR:
532 baca51fa bellard
        retval = fdctrl_read_main_status(fdctrl);
533 4f431960 j_mayer
        break;
534 9fea808a blueswir1
    case FD_REG_FIFO:
535 baca51fa bellard
        retval = fdctrl_read_data(fdctrl);
536 4f431960 j_mayer
        break;
537 9fea808a blueswir1
    case FD_REG_DIR:
538 baca51fa bellard
        retval = fdctrl_read_dir(fdctrl);
539 4f431960 j_mayer
        break;
540 a541f297 bellard
    default:
541 4f431960 j_mayer
        retval = (uint32_t)(-1);
542 4f431960 j_mayer
        break;
543 a541f297 bellard
    }
544 ed5fd2cc bellard
    FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
545 baca51fa bellard
546 baca51fa bellard
    return retval;
547 baca51fa bellard
}
548 baca51fa bellard
549 baca51fa bellard
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
550 baca51fa bellard
{
551 baca51fa bellard
    fdctrl_t *fdctrl = opaque;
552 baca51fa bellard
553 ed5fd2cc bellard
    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
554 ed5fd2cc bellard
555 e64d7d59 blueswir1
    switch (reg) {
556 9fea808a blueswir1
    case FD_REG_DOR:
557 4f431960 j_mayer
        fdctrl_write_dor(fdctrl, value);
558 4f431960 j_mayer
        break;
559 9fea808a blueswir1
    case FD_REG_TDR:
560 baca51fa bellard
        fdctrl_write_tape(fdctrl, value);
561 4f431960 j_mayer
        break;
562 9fea808a blueswir1
    case FD_REG_DSR:
563 baca51fa bellard
        fdctrl_write_rate(fdctrl, value);
564 4f431960 j_mayer
        break;
565 9fea808a blueswir1
    case FD_REG_FIFO:
566 baca51fa bellard
        fdctrl_write_data(fdctrl, value);
567 4f431960 j_mayer
        break;
568 a541f297 bellard
    default:
569 4f431960 j_mayer
        break;
570 a541f297 bellard
    }
571 baca51fa bellard
}
572 baca51fa bellard
573 e64d7d59 blueswir1
static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
574 e64d7d59 blueswir1
{
575 e64d7d59 blueswir1
    return fdctrl_read(opaque, reg & 7);
576 e64d7d59 blueswir1
}
577 e64d7d59 blueswir1
578 e64d7d59 blueswir1
static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
579 e64d7d59 blueswir1
{
580 e64d7d59 blueswir1
    fdctrl_write(opaque, reg & 7, value);
581 e64d7d59 blueswir1
}
582 e64d7d59 blueswir1
583 62a46c61 bellard
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
584 62a46c61 bellard
{
585 5dcb6b91 blueswir1
    return fdctrl_read(opaque, (uint32_t)reg);
586 62a46c61 bellard
}
587 62a46c61 bellard
588 5fafdf24 ths
static void fdctrl_write_mem (void *opaque,
589 62a46c61 bellard
                              target_phys_addr_t reg, uint32_t value)
590 62a46c61 bellard
{
591 5dcb6b91 blueswir1
    fdctrl_write(opaque, (uint32_t)reg, value);
592 62a46c61 bellard
}
593 62a46c61 bellard
594 e80cfcfc bellard
static CPUReadMemoryFunc *fdctrl_mem_read[3] = {
595 62a46c61 bellard
    fdctrl_read_mem,
596 62a46c61 bellard
    fdctrl_read_mem,
597 62a46c61 bellard
    fdctrl_read_mem,
598 e80cfcfc bellard
};
599 e80cfcfc bellard
600 e80cfcfc bellard
static CPUWriteMemoryFunc *fdctrl_mem_write[3] = {
601 62a46c61 bellard
    fdctrl_write_mem,
602 62a46c61 bellard
    fdctrl_write_mem,
603 62a46c61 bellard
    fdctrl_write_mem,
604 e80cfcfc bellard
};
605 e80cfcfc bellard
606 7c560456 blueswir1
static CPUReadMemoryFunc *fdctrl_mem_read_strict[3] = {
607 7c560456 blueswir1
    fdctrl_read_mem,
608 7c560456 blueswir1
    NULL,
609 7c560456 blueswir1
    NULL,
610 7c560456 blueswir1
};
611 7c560456 blueswir1
612 7c560456 blueswir1
static CPUWriteMemoryFunc *fdctrl_mem_write_strict[3] = {
613 7c560456 blueswir1
    fdctrl_write_mem,
614 7c560456 blueswir1
    NULL,
615 7c560456 blueswir1
    NULL,
616 7c560456 blueswir1
};
617 7c560456 blueswir1
618 3ccacc4a blueswir1
static void fd_save (QEMUFile *f, fdrive_t *fd)
619 3ccacc4a blueswir1
{
620 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->head);
621 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->track);
622 3ccacc4a blueswir1
    qemu_put_8s(f, &fd->sect);
623 3ccacc4a blueswir1
}
624 3ccacc4a blueswir1
625 3ccacc4a blueswir1
static void fdc_save (QEMUFile *f, void *opaque)
626 3ccacc4a blueswir1
{
627 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
628 78ae820c blueswir1
    uint8_t tmp;
629 78ae820c blueswir1
    int i;
630 cefec4f5 blueswir1
    uint8_t dor = s->dor | GET_CUR_DRV(s);
631 3ccacc4a blueswir1
632 8c6a4d77 blueswir1
    /* Controller state */
633 8c6a4d77 blueswir1
    qemu_put_8s(f, &s->sra);
634 8c6a4d77 blueswir1
    qemu_put_8s(f, &s->srb);
635 cefec4f5 blueswir1
    qemu_put_8s(f, &dor);
636 46d3233b blueswir1
    qemu_put_8s(f, &s->tdr);
637 77370520 blueswir1
    qemu_put_8s(f, &s->dsr);
638 77370520 blueswir1
    qemu_put_8s(f, &s->msr);
639 77370520 blueswir1
    qemu_put_8s(f, &s->status0);
640 77370520 blueswir1
    qemu_put_8s(f, &s->status1);
641 77370520 blueswir1
    qemu_put_8s(f, &s->status2);
642 77370520 blueswir1
    /* Command FIFO */
643 3ccacc4a blueswir1
    qemu_put_buffer(f, s->fifo, FD_SECTOR_LEN);
644 3ccacc4a blueswir1
    qemu_put_be32s(f, &s->data_pos);
645 3ccacc4a blueswir1
    qemu_put_be32s(f, &s->data_len);
646 3ccacc4a blueswir1
    qemu_put_8s(f, &s->data_state);
647 3ccacc4a blueswir1
    qemu_put_8s(f, &s->data_dir);
648 3ccacc4a blueswir1
    qemu_put_8s(f, &s->eot);
649 77370520 blueswir1
    /* States kept only to be returned back */
650 3ccacc4a blueswir1
    qemu_put_8s(f, &s->timer0);
651 3ccacc4a blueswir1
    qemu_put_8s(f, &s->timer1);
652 3ccacc4a blueswir1
    qemu_put_8s(f, &s->precomp_trk);
653 3ccacc4a blueswir1
    qemu_put_8s(f, &s->config);
654 3ccacc4a blueswir1
    qemu_put_8s(f, &s->lock);
655 3ccacc4a blueswir1
    qemu_put_8s(f, &s->pwrd);
656 78ae820c blueswir1
657 78ae820c blueswir1
    tmp = MAX_FD;
658 78ae820c blueswir1
    qemu_put_8s(f, &tmp);
659 78ae820c blueswir1
    for (i = 0; i < MAX_FD; i++)
660 78ae820c blueswir1
        fd_save(f, &s->drives[i]);
661 3ccacc4a blueswir1
}
662 3ccacc4a blueswir1
663 3ccacc4a blueswir1
static int fd_load (QEMUFile *f, fdrive_t *fd)
664 3ccacc4a blueswir1
{
665 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->head);
666 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->track);
667 3ccacc4a blueswir1
    qemu_get_8s(f, &fd->sect);
668 3ccacc4a blueswir1
669 3ccacc4a blueswir1
    return 0;
670 3ccacc4a blueswir1
}
671 3ccacc4a blueswir1
672 3ccacc4a blueswir1
static int fdc_load (QEMUFile *f, void *opaque, int version_id)
673 3ccacc4a blueswir1
{
674 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
675 78ae820c blueswir1
    int i, ret = 0;
676 78ae820c blueswir1
    uint8_t n;
677 3ccacc4a blueswir1
678 77370520 blueswir1
    if (version_id != 2)
679 3ccacc4a blueswir1
        return -EINVAL;
680 3ccacc4a blueswir1
681 8c6a4d77 blueswir1
    /* Controller state */
682 8c6a4d77 blueswir1
    qemu_get_8s(f, &s->sra);
683 8c6a4d77 blueswir1
    qemu_get_8s(f, &s->srb);
684 cefec4f5 blueswir1
    qemu_get_8s(f, &s->dor);
685 cefec4f5 blueswir1
    SET_CUR_DRV(s, s->dor & FD_DOR_SELMASK);
686 cefec4f5 blueswir1
    s->dor &= ~FD_DOR_SELMASK;
687 46d3233b blueswir1
    qemu_get_8s(f, &s->tdr);
688 77370520 blueswir1
    qemu_get_8s(f, &s->dsr);
689 77370520 blueswir1
    qemu_get_8s(f, &s->msr);
690 77370520 blueswir1
    qemu_get_8s(f, &s->status0);
691 77370520 blueswir1
    qemu_get_8s(f, &s->status1);
692 77370520 blueswir1
    qemu_get_8s(f, &s->status2);
693 77370520 blueswir1
    /* Command FIFO */
694 3ccacc4a blueswir1
    qemu_get_buffer(f, s->fifo, FD_SECTOR_LEN);
695 3ccacc4a blueswir1
    qemu_get_be32s(f, &s->data_pos);
696 3ccacc4a blueswir1
    qemu_get_be32s(f, &s->data_len);
697 3ccacc4a blueswir1
    qemu_get_8s(f, &s->data_state);
698 3ccacc4a blueswir1
    qemu_get_8s(f, &s->data_dir);
699 3ccacc4a blueswir1
    qemu_get_8s(f, &s->eot);
700 77370520 blueswir1
    /* States kept only to be returned back */
701 3ccacc4a blueswir1
    qemu_get_8s(f, &s->timer0);
702 3ccacc4a blueswir1
    qemu_get_8s(f, &s->timer1);
703 3ccacc4a blueswir1
    qemu_get_8s(f, &s->precomp_trk);
704 3ccacc4a blueswir1
    qemu_get_8s(f, &s->config);
705 3ccacc4a blueswir1
    qemu_get_8s(f, &s->lock);
706 3ccacc4a blueswir1
    qemu_get_8s(f, &s->pwrd);
707 78ae820c blueswir1
    qemu_get_8s(f, &n);
708 3ccacc4a blueswir1
709 78ae820c blueswir1
    if (n > MAX_FD)
710 78ae820c blueswir1
        return -EINVAL;
711 78ae820c blueswir1
712 78ae820c blueswir1
    for (i = 0; i < n; i++) {
713 78ae820c blueswir1
        ret = fd_load(f, &s->drives[i]);
714 78ae820c blueswir1
        if (ret != 0)
715 78ae820c blueswir1
            break;
716 78ae820c blueswir1
    }
717 3ccacc4a blueswir1
718 3ccacc4a blueswir1
    return ret;
719 3ccacc4a blueswir1
}
720 3ccacc4a blueswir1
721 3ccacc4a blueswir1
static void fdctrl_external_reset(void *opaque)
722 3ccacc4a blueswir1
{
723 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
724 3ccacc4a blueswir1
725 3ccacc4a blueswir1
    fdctrl_reset(s, 0);
726 3ccacc4a blueswir1
}
727 3ccacc4a blueswir1
728 2be17ebd blueswir1
static void fdctrl_handle_tc(void *opaque, int irq, int level)
729 2be17ebd blueswir1
{
730 2be17ebd blueswir1
    //fdctrl_t *s = opaque;
731 2be17ebd blueswir1
732 2be17ebd blueswir1
    if (level) {
733 2be17ebd blueswir1
        // XXX
734 2be17ebd blueswir1
        FLOPPY_DPRINTF("TC pulsed\n");
735 2be17ebd blueswir1
    }
736 2be17ebd blueswir1
}
737 2be17ebd blueswir1
738 baca51fa bellard
/* XXX: may change if moved to bdrv */
739 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
740 caed8802 bellard
{
741 baca51fa bellard
    return fdctrl->drives[drive_num].drive;
742 8977f3c1 bellard
}
743 8977f3c1 bellard
744 8977f3c1 bellard
/* Change IRQ state */
745 baca51fa bellard
static void fdctrl_reset_irq (fdctrl_t *fdctrl)
746 8977f3c1 bellard
{
747 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND))
748 8c6a4d77 blueswir1
        return;
749 ed5fd2cc bellard
    FLOPPY_DPRINTF("Reset interrupt\n");
750 d537cf6c pbrook
    qemu_set_irq(fdctrl->irq, 0);
751 8c6a4d77 blueswir1
    fdctrl->sra &= ~FD_SRA_INTPEND;
752 8977f3c1 bellard
}
753 8977f3c1 bellard
754 77370520 blueswir1
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
755 8977f3c1 bellard
{
756 b9b3d225 blueswir1
    /* Sparc mutation */
757 b9b3d225 blueswir1
    if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
758 b9b3d225 blueswir1
        /* XXX: not sure */
759 b9b3d225 blueswir1
        fdctrl->msr &= ~FD_MSR_CMDBUSY;
760 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
761 77370520 blueswir1
        fdctrl->status0 = status0;
762 4f431960 j_mayer
        return;
763 6f7e9aec bellard
    }
764 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND)) {
765 d537cf6c pbrook
        qemu_set_irq(fdctrl->irq, 1);
766 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_INTPEND;
767 8977f3c1 bellard
    }
768 f2d81b33 blueswir1
    fdctrl->reset_sensei = 0;
769 77370520 blueswir1
    fdctrl->status0 = status0;
770 77370520 blueswir1
    FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
771 8977f3c1 bellard
}
772 8977f3c1 bellard
773 4b19ec0c bellard
/* Reset controller */
774 baca51fa bellard
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
775 8977f3c1 bellard
{
776 8977f3c1 bellard
    int i;
777 8977f3c1 bellard
778 4b19ec0c bellard
    FLOPPY_DPRINTF("reset controller\n");
779 baca51fa bellard
    fdctrl_reset_irq(fdctrl);
780 4b19ec0c bellard
    /* Initialise controller */
781 8c6a4d77 blueswir1
    fdctrl->sra = 0;
782 8c6a4d77 blueswir1
    fdctrl->srb = 0xc0;
783 8c6a4d77 blueswir1
    if (!fdctrl->drives[1].bs)
784 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_nDRV2;
785 baca51fa bellard
    fdctrl->cur_drv = 0;
786 1c346df2 blueswir1
    fdctrl->dor = FD_DOR_nRESET;
787 368df94d blueswir1
    fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
788 b9b3d225 blueswir1
    fdctrl->msr = FD_MSR_RQM;
789 8977f3c1 bellard
    /* FIFO state */
790 baca51fa bellard
    fdctrl->data_pos = 0;
791 baca51fa bellard
    fdctrl->data_len = 0;
792 b9b3d225 blueswir1
    fdctrl->data_state = 0;
793 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
794 8977f3c1 bellard
    for (i = 0; i < MAX_FD; i++)
795 1c346df2 blueswir1
        fd_recalibrate(&fdctrl->drives[i]);
796 baca51fa bellard
    fdctrl_reset_fifo(fdctrl);
797 77370520 blueswir1
    if (do_irq) {
798 9fea808a blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
799 f2d81b33 blueswir1
        fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
800 77370520 blueswir1
    }
801 baca51fa bellard
}
802 baca51fa bellard
803 baca51fa bellard
static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
804 baca51fa bellard
{
805 46d3233b blueswir1
    return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
806 baca51fa bellard
}
807 baca51fa bellard
808 baca51fa bellard
static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
809 baca51fa bellard
{
810 46d3233b blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
811 46d3233b blueswir1
        return &fdctrl->drives[1];
812 46d3233b blueswir1
    else
813 46d3233b blueswir1
        return &fdctrl->drives[0];
814 baca51fa bellard
}
815 baca51fa bellard
816 78ae820c blueswir1
#if MAX_FD == 4
817 78ae820c blueswir1
static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
818 78ae820c blueswir1
{
819 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
820 78ae820c blueswir1
        return &fdctrl->drives[2];
821 78ae820c blueswir1
    else
822 78ae820c blueswir1
        return &fdctrl->drives[1];
823 78ae820c blueswir1
}
824 78ae820c blueswir1
825 78ae820c blueswir1
static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
826 78ae820c blueswir1
{
827 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
828 78ae820c blueswir1
        return &fdctrl->drives[3];
829 78ae820c blueswir1
    else
830 78ae820c blueswir1
        return &fdctrl->drives[2];
831 78ae820c blueswir1
}
832 78ae820c blueswir1
#endif
833 78ae820c blueswir1
834 baca51fa bellard
static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
835 baca51fa bellard
{
836 78ae820c blueswir1
    switch (fdctrl->cur_drv) {
837 78ae820c blueswir1
        case 0: return drv0(fdctrl);
838 78ae820c blueswir1
        case 1: return drv1(fdctrl);
839 78ae820c blueswir1
#if MAX_FD == 4
840 78ae820c blueswir1
        case 2: return drv2(fdctrl);
841 78ae820c blueswir1
        case 3: return drv3(fdctrl);
842 78ae820c blueswir1
#endif
843 78ae820c blueswir1
        default: return NULL;
844 78ae820c blueswir1
    }
845 8977f3c1 bellard
}
846 8977f3c1 bellard
847 8c6a4d77 blueswir1
/* Status A register : 0x00 (read-only) */
848 8c6a4d77 blueswir1
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
849 8c6a4d77 blueswir1
{
850 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->sra;
851 8c6a4d77 blueswir1
852 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
853 8c6a4d77 blueswir1
854 8c6a4d77 blueswir1
    return retval;
855 8c6a4d77 blueswir1
}
856 8c6a4d77 blueswir1
857 8977f3c1 bellard
/* Status B register : 0x01 (read-only) */
858 baca51fa bellard
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
859 8977f3c1 bellard
{
860 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->srb;
861 8c6a4d77 blueswir1
862 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
863 8c6a4d77 blueswir1
864 8c6a4d77 blueswir1
    return retval;
865 8977f3c1 bellard
}
866 8977f3c1 bellard
867 8977f3c1 bellard
/* Digital output register : 0x02 */
868 baca51fa bellard
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
869 8977f3c1 bellard
{
870 1c346df2 blueswir1
    uint32_t retval = fdctrl->dor;
871 8977f3c1 bellard
872 8977f3c1 bellard
    /* Selected drive */
873 baca51fa bellard
    retval |= fdctrl->cur_drv;
874 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
875 8977f3c1 bellard
876 8977f3c1 bellard
    return retval;
877 8977f3c1 bellard
}
878 8977f3c1 bellard
879 baca51fa bellard
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
880 8977f3c1 bellard
{
881 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
882 8c6a4d77 blueswir1
883 8c6a4d77 blueswir1
    /* Motors */
884 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN0)
885 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR0;
886 8c6a4d77 blueswir1
    else
887 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR0;
888 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN1)
889 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR1;
890 8c6a4d77 blueswir1
    else
891 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR1;
892 8c6a4d77 blueswir1
893 8c6a4d77 blueswir1
    /* Drive */
894 8c6a4d77 blueswir1
    if (value & 1)
895 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_DR0;
896 8c6a4d77 blueswir1
    else
897 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_DR0;
898 8c6a4d77 blueswir1
899 8977f3c1 bellard
    /* Reset */
900 9fea808a blueswir1
    if (!(value & FD_DOR_nRESET)) {
901 1c346df2 blueswir1
        if (fdctrl->dor & FD_DOR_nRESET) {
902 4b19ec0c bellard
            FLOPPY_DPRINTF("controller enter RESET state\n");
903 8977f3c1 bellard
        }
904 8977f3c1 bellard
    } else {
905 1c346df2 blueswir1
        if (!(fdctrl->dor & FD_DOR_nRESET)) {
906 4b19ec0c bellard
            FLOPPY_DPRINTF("controller out of RESET state\n");
907 fb6cf1d0 bellard
            fdctrl_reset(fdctrl, 1);
908 b9b3d225 blueswir1
            fdctrl->dsr &= ~FD_DSR_PWRDOWN;
909 8977f3c1 bellard
        }
910 8977f3c1 bellard
    }
911 8977f3c1 bellard
    /* Selected drive */
912 9fea808a blueswir1
    fdctrl->cur_drv = value & FD_DOR_SELMASK;
913 368df94d blueswir1
914 368df94d blueswir1
    fdctrl->dor = value;
915 8977f3c1 bellard
}
916 8977f3c1 bellard
917 8977f3c1 bellard
/* Tape drive register : 0x03 */
918 baca51fa bellard
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
919 8977f3c1 bellard
{
920 46d3233b blueswir1
    uint32_t retval = fdctrl->tdr;
921 8977f3c1 bellard
922 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
923 8977f3c1 bellard
924 8977f3c1 bellard
    return retval;
925 8977f3c1 bellard
}
926 8977f3c1 bellard
927 baca51fa bellard
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
928 8977f3c1 bellard
{
929 8977f3c1 bellard
    /* Reset mode */
930 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
931 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
932 8977f3c1 bellard
        return;
933 8977f3c1 bellard
    }
934 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
935 8977f3c1 bellard
    /* Disk boot selection indicator */
936 46d3233b blueswir1
    fdctrl->tdr = value & FD_TDR_BOOTSEL;
937 8977f3c1 bellard
    /* Tape indicators: never allow */
938 8977f3c1 bellard
}
939 8977f3c1 bellard
940 8977f3c1 bellard
/* Main status register : 0x04 (read) */
941 baca51fa bellard
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
942 8977f3c1 bellard
{
943 b9b3d225 blueswir1
    uint32_t retval = fdctrl->msr;
944 8977f3c1 bellard
945 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
946 1c346df2 blueswir1
    fdctrl->dor |= FD_DOR_nRESET;
947 b9b3d225 blueswir1
948 8977f3c1 bellard
    FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
949 8977f3c1 bellard
950 8977f3c1 bellard
    return retval;
951 8977f3c1 bellard
}
952 8977f3c1 bellard
953 8977f3c1 bellard
/* Data select rate register : 0x04 (write) */
954 baca51fa bellard
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
955 8977f3c1 bellard
{
956 8977f3c1 bellard
    /* Reset mode */
957 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
958 4f431960 j_mayer
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
959 4f431960 j_mayer
        return;
960 4f431960 j_mayer
    }
961 8977f3c1 bellard
    FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
962 8977f3c1 bellard
    /* Reset: autoclear */
963 9fea808a blueswir1
    if (value & FD_DSR_SWRESET) {
964 1c346df2 blueswir1
        fdctrl->dor &= ~FD_DOR_nRESET;
965 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
966 1c346df2 blueswir1
        fdctrl->dor |= FD_DOR_nRESET;
967 8977f3c1 bellard
    }
968 9fea808a blueswir1
    if (value & FD_DSR_PWRDOWN) {
969 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
970 8977f3c1 bellard
    }
971 b9b3d225 blueswir1
    fdctrl->dsr = value;
972 8977f3c1 bellard
}
973 8977f3c1 bellard
974 ea185bbd bellard
static int fdctrl_media_changed(fdrive_t *drv)
975 ea185bbd bellard
{
976 ea185bbd bellard
    int ret;
977 4f431960 j_mayer
978 5fafdf24 ths
    if (!drv->bs)
979 ea185bbd bellard
        return 0;
980 ea185bbd bellard
    ret = bdrv_media_changed(drv->bs);
981 ea185bbd bellard
    if (ret) {
982 ea185bbd bellard
        fd_revalidate(drv);
983 ea185bbd bellard
    }
984 ea185bbd bellard
    return ret;
985 ea185bbd bellard
}
986 ea185bbd bellard
987 8977f3c1 bellard
/* Digital input register : 0x07 (read-only) */
988 baca51fa bellard
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
989 8977f3c1 bellard
{
990 8977f3c1 bellard
    uint32_t retval = 0;
991 8977f3c1 bellard
992 78ae820c blueswir1
    if (fdctrl_media_changed(drv0(fdctrl))
993 78ae820c blueswir1
     || fdctrl_media_changed(drv1(fdctrl))
994 78ae820c blueswir1
#if MAX_FD == 4
995 78ae820c blueswir1
     || fdctrl_media_changed(drv2(fdctrl))
996 78ae820c blueswir1
     || fdctrl_media_changed(drv3(fdctrl))
997 78ae820c blueswir1
#endif
998 78ae820c blueswir1
        )
999 9fea808a blueswir1
        retval |= FD_DIR_DSKCHG;
1000 8977f3c1 bellard
    if (retval != 0)
1001 baca51fa bellard
        FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1002 8977f3c1 bellard
1003 8977f3c1 bellard
    return retval;
1004 8977f3c1 bellard
}
1005 8977f3c1 bellard
1006 8977f3c1 bellard
/* FIFO state control */
1007 baca51fa bellard
static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
1008 8977f3c1 bellard
{
1009 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
1010 baca51fa bellard
    fdctrl->data_pos = 0;
1011 b9b3d225 blueswir1
    fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1012 8977f3c1 bellard
}
1013 8977f3c1 bellard
1014 8977f3c1 bellard
/* Set FIFO status for the host to read */
1015 baca51fa bellard
static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1016 8977f3c1 bellard
{
1017 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1018 baca51fa bellard
    fdctrl->data_len = fifo_len;
1019 baca51fa bellard
    fdctrl->data_pos = 0;
1020 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1021 8977f3c1 bellard
    if (do_irq)
1022 baca51fa bellard
        fdctrl_raise_irq(fdctrl, 0x00);
1023 8977f3c1 bellard
}
1024 8977f3c1 bellard
1025 8977f3c1 bellard
/* Set an error: unimplemented/unknown command */
1026 65cef780 blueswir1
static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1027 8977f3c1 bellard
{
1028 77370520 blueswir1
    FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1029 9fea808a blueswir1
    fdctrl->fifo[0] = FD_SR0_INVCMD;
1030 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 1, 0);
1031 8977f3c1 bellard
}
1032 8977f3c1 bellard
1033 746d6de7 blueswir1
/* Seek to next sector */
1034 746d6de7 blueswir1
static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1035 746d6de7 blueswir1
{
1036 746d6de7 blueswir1
    FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1037 746d6de7 blueswir1
                   cur_drv->head, cur_drv->track, cur_drv->sect,
1038 746d6de7 blueswir1
                   fd_sector(cur_drv));
1039 746d6de7 blueswir1
    /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1040 746d6de7 blueswir1
       error in fact */
1041 746d6de7 blueswir1
    if (cur_drv->sect >= cur_drv->last_sect ||
1042 746d6de7 blueswir1
        cur_drv->sect == fdctrl->eot) {
1043 746d6de7 blueswir1
        cur_drv->sect = 1;
1044 746d6de7 blueswir1
        if (FD_MULTI_TRACK(fdctrl->data_state)) {
1045 746d6de7 blueswir1
            if (cur_drv->head == 0 &&
1046 746d6de7 blueswir1
                (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1047 746d6de7 blueswir1
                cur_drv->head = 1;
1048 746d6de7 blueswir1
            } else {
1049 746d6de7 blueswir1
                cur_drv->head = 0;
1050 746d6de7 blueswir1
                cur_drv->track++;
1051 746d6de7 blueswir1
                if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1052 746d6de7 blueswir1
                    return 0;
1053 746d6de7 blueswir1
            }
1054 746d6de7 blueswir1
        } else {
1055 746d6de7 blueswir1
            cur_drv->track++;
1056 746d6de7 blueswir1
            return 0;
1057 746d6de7 blueswir1
        }
1058 746d6de7 blueswir1
        FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1059 746d6de7 blueswir1
                       cur_drv->head, cur_drv->track,
1060 746d6de7 blueswir1
                       cur_drv->sect, fd_sector(cur_drv));
1061 746d6de7 blueswir1
    } else {
1062 746d6de7 blueswir1
        cur_drv->sect++;
1063 746d6de7 blueswir1
    }
1064 746d6de7 blueswir1
    return 1;
1065 746d6de7 blueswir1
}
1066 746d6de7 blueswir1
1067 8977f3c1 bellard
/* Callback for transfer end (stop or abort) */
1068 baca51fa bellard
static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1069 4f431960 j_mayer
                                  uint8_t status1, uint8_t status2)
1070 8977f3c1 bellard
{
1071 baca51fa bellard
    fdrive_t *cur_drv;
1072 8977f3c1 bellard
1073 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1074 8977f3c1 bellard
    FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1075 8977f3c1 bellard
                   status0, status1, status2,
1076 cefec4f5 blueswir1
                   status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1077 cefec4f5 blueswir1
    fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1078 baca51fa bellard
    fdctrl->fifo[1] = status1;
1079 baca51fa bellard
    fdctrl->fifo[2] = status2;
1080 baca51fa bellard
    fdctrl->fifo[3] = cur_drv->track;
1081 baca51fa bellard
    fdctrl->fifo[4] = cur_drv->head;
1082 baca51fa bellard
    fdctrl->fifo[5] = cur_drv->sect;
1083 baca51fa bellard
    fdctrl->fifo[6] = FD_SECTOR_SC;
1084 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1085 368df94d blueswir1
    if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1086 baca51fa bellard
        DMA_release_DREQ(fdctrl->dma_chann);
1087 ed5fd2cc bellard
    }
1088 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1089 368df94d blueswir1
    fdctrl->msr &= ~FD_MSR_NONDMA;
1090 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 7, 1);
1091 8977f3c1 bellard
}
1092 8977f3c1 bellard
1093 8977f3c1 bellard
/* Prepare a data transfer (either DMA or FIFO) */
1094 baca51fa bellard
static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1095 8977f3c1 bellard
{
1096 baca51fa bellard
    fdrive_t *cur_drv;
1097 8977f3c1 bellard
    uint8_t kh, kt, ks;
1098 77370520 blueswir1
    int did_seek = 0;
1099 8977f3c1 bellard
1100 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1101 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1102 baca51fa bellard
    kt = fdctrl->fifo[2];
1103 baca51fa bellard
    kh = fdctrl->fifo[3];
1104 baca51fa bellard
    ks = fdctrl->fifo[4];
1105 4b19ec0c bellard
    FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1106 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1107 8977f3c1 bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1108 77370520 blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1109 8977f3c1 bellard
    case 2:
1110 8977f3c1 bellard
        /* sect too big */
1111 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1112 baca51fa bellard
        fdctrl->fifo[3] = kt;
1113 baca51fa bellard
        fdctrl->fifo[4] = kh;
1114 baca51fa bellard
        fdctrl->fifo[5] = ks;
1115 8977f3c1 bellard
        return;
1116 8977f3c1 bellard
    case 3:
1117 8977f3c1 bellard
        /* track too big */
1118 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1119 baca51fa bellard
        fdctrl->fifo[3] = kt;
1120 baca51fa bellard
        fdctrl->fifo[4] = kh;
1121 baca51fa bellard
        fdctrl->fifo[5] = ks;
1122 8977f3c1 bellard
        return;
1123 8977f3c1 bellard
    case 4:
1124 8977f3c1 bellard
        /* No seek enabled */
1125 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1126 baca51fa bellard
        fdctrl->fifo[3] = kt;
1127 baca51fa bellard
        fdctrl->fifo[4] = kh;
1128 baca51fa bellard
        fdctrl->fifo[5] = ks;
1129 8977f3c1 bellard
        return;
1130 8977f3c1 bellard
    case 1:
1131 8977f3c1 bellard
        did_seek = 1;
1132 8977f3c1 bellard
        break;
1133 8977f3c1 bellard
    default:
1134 8977f3c1 bellard
        break;
1135 8977f3c1 bellard
    }
1136 b9b3d225 blueswir1
1137 8977f3c1 bellard
    /* Set the FIFO state */
1138 baca51fa bellard
    fdctrl->data_dir = direction;
1139 baca51fa bellard
    fdctrl->data_pos = 0;
1140 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY;
1141 baca51fa bellard
    if (fdctrl->fifo[0] & 0x80)
1142 baca51fa bellard
        fdctrl->data_state |= FD_STATE_MULTI;
1143 baca51fa bellard
    else
1144 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_MULTI;
1145 8977f3c1 bellard
    if (did_seek)
1146 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1147 baca51fa bellard
    else
1148 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_SEEK;
1149 baca51fa bellard
    if (fdctrl->fifo[5] == 00) {
1150 baca51fa bellard
        fdctrl->data_len = fdctrl->fifo[8];
1151 baca51fa bellard
    } else {
1152 4f431960 j_mayer
        int tmp;
1153 3bcb80f1 ths
        fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1154 771effeb blueswir1
        tmp = (fdctrl->fifo[6] - ks + 1);
1155 baca51fa bellard
        if (fdctrl->fifo[0] & 0x80)
1156 771effeb blueswir1
            tmp += fdctrl->fifo[6];
1157 4f431960 j_mayer
        fdctrl->data_len *= tmp;
1158 baca51fa bellard
    }
1159 890fa6be bellard
    fdctrl->eot = fdctrl->fifo[6];
1160 368df94d blueswir1
    if (fdctrl->dor & FD_DOR_DMAEN) {
1161 8977f3c1 bellard
        int dma_mode;
1162 8977f3c1 bellard
        /* DMA transfer are enabled. Check if DMA channel is well programmed */
1163 baca51fa bellard
        dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1164 8977f3c1 bellard
        dma_mode = (dma_mode >> 2) & 3;
1165 baca51fa bellard
        FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1166 4f431960 j_mayer
                       dma_mode, direction,
1167 baca51fa bellard
                       (128 << fdctrl->fifo[5]) *
1168 4f431960 j_mayer
                       (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1169 8977f3c1 bellard
        if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1170 8977f3c1 bellard
              direction == FD_DIR_SCANH) && dma_mode == 0) ||
1171 8977f3c1 bellard
            (direction == FD_DIR_WRITE && dma_mode == 2) ||
1172 8977f3c1 bellard
            (direction == FD_DIR_READ && dma_mode == 1)) {
1173 8977f3c1 bellard
            /* No access is allowed until DMA transfer has completed */
1174 b9b3d225 blueswir1
            fdctrl->msr &= ~FD_MSR_RQM;
1175 4b19ec0c bellard
            /* Now, we just have to wait for the DMA controller to
1176 8977f3c1 bellard
             * recall us...
1177 8977f3c1 bellard
             */
1178 baca51fa bellard
            DMA_hold_DREQ(fdctrl->dma_chann);
1179 baca51fa bellard
            DMA_schedule(fdctrl->dma_chann);
1180 8977f3c1 bellard
            return;
1181 baca51fa bellard
        } else {
1182 4f431960 j_mayer
            FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1183 8977f3c1 bellard
        }
1184 8977f3c1 bellard
    }
1185 8977f3c1 bellard
    FLOPPY_DPRINTF("start non-DMA transfer\n");
1186 368df94d blueswir1
    fdctrl->msr |= FD_MSR_NONDMA;
1187 b9b3d225 blueswir1
    if (direction != FD_DIR_WRITE)
1188 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_DIO;
1189 8977f3c1 bellard
    /* IO based transfer: calculate len */
1190 baca51fa bellard
    fdctrl_raise_irq(fdctrl, 0x00);
1191 8977f3c1 bellard
1192 8977f3c1 bellard
    return;
1193 8977f3c1 bellard
}
1194 8977f3c1 bellard
1195 8977f3c1 bellard
/* Prepare a transfer of deleted data */
1196 baca51fa bellard
static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1197 8977f3c1 bellard
{
1198 77370520 blueswir1
    FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1199 77370520 blueswir1
1200 8977f3c1 bellard
    /* We don't handle deleted data,
1201 8977f3c1 bellard
     * so we don't return *ANYTHING*
1202 8977f3c1 bellard
     */
1203 9fea808a blueswir1
    fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1204 8977f3c1 bellard
}
1205 8977f3c1 bellard
1206 8977f3c1 bellard
/* handlers for DMA transfers */
1207 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
1208 85571bc7 bellard
                                    int dma_pos, int dma_len)
1209 8977f3c1 bellard
{
1210 baca51fa bellard
    fdctrl_t *fdctrl;
1211 baca51fa bellard
    fdrive_t *cur_drv;
1212 baca51fa bellard
    int len, start_pos, rel_pos;
1213 8977f3c1 bellard
    uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1214 8977f3c1 bellard
1215 baca51fa bellard
    fdctrl = opaque;
1216 b9b3d225 blueswir1
    if (fdctrl->msr & FD_MSR_RQM) {
1217 8977f3c1 bellard
        FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1218 8977f3c1 bellard
        return 0;
1219 8977f3c1 bellard
    }
1220 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1221 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1222 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1223 77370520 blueswir1
        status2 = FD_SR2_SNS;
1224 85571bc7 bellard
    if (dma_len > fdctrl->data_len)
1225 85571bc7 bellard
        dma_len = fdctrl->data_len;
1226 890fa6be bellard
    if (cur_drv->bs == NULL) {
1227 4f431960 j_mayer
        if (fdctrl->data_dir == FD_DIR_WRITE)
1228 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1229 4f431960 j_mayer
        else
1230 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1231 4f431960 j_mayer
        len = 0;
1232 890fa6be bellard
        goto transfer_error;
1233 890fa6be bellard
    }
1234 baca51fa bellard
    rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1235 85571bc7 bellard
    for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1236 85571bc7 bellard
        len = dma_len - fdctrl->data_pos;
1237 baca51fa bellard
        if (len + rel_pos > FD_SECTOR_LEN)
1238 baca51fa bellard
            len = FD_SECTOR_LEN - rel_pos;
1239 6f7e9aec bellard
        FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1240 6f7e9aec bellard
                       "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1241 cefec4f5 blueswir1
                       fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1242 baca51fa bellard
                       cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1243 9fea808a blueswir1
                       fd_sector(cur_drv) * FD_SECTOR_LEN);
1244 baca51fa bellard
        if (fdctrl->data_dir != FD_DIR_WRITE ||
1245 4f431960 j_mayer
            len < FD_SECTOR_LEN || rel_pos != 0) {
1246 baca51fa bellard
            /* READ & SCAN commands and realign to a sector for WRITE */
1247 baca51fa bellard
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1248 4f431960 j_mayer
                          fdctrl->fifo, 1) < 0) {
1249 8977f3c1 bellard
                FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1250 8977f3c1 bellard
                               fd_sector(cur_drv));
1251 8977f3c1 bellard
                /* Sure, image size is too small... */
1252 baca51fa bellard
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1253 8977f3c1 bellard
            }
1254 890fa6be bellard
        }
1255 4f431960 j_mayer
        switch (fdctrl->data_dir) {
1256 4f431960 j_mayer
        case FD_DIR_READ:
1257 4f431960 j_mayer
            /* READ commands */
1258 85571bc7 bellard
            DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1259 85571bc7 bellard
                              fdctrl->data_pos, len);
1260 4f431960 j_mayer
            break;
1261 4f431960 j_mayer
        case FD_DIR_WRITE:
1262 baca51fa bellard
            /* WRITE commands */
1263 85571bc7 bellard
            DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1264 85571bc7 bellard
                             fdctrl->data_pos, len);
1265 baca51fa bellard
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1266 4f431960 j_mayer
                           fdctrl->fifo, 1) < 0) {
1267 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1268 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1269 baca51fa bellard
                goto transfer_error;
1270 890fa6be bellard
            }
1271 4f431960 j_mayer
            break;
1272 4f431960 j_mayer
        default:
1273 4f431960 j_mayer
            /* SCAN commands */
1274 baca51fa bellard
            {
1275 4f431960 j_mayer
                uint8_t tmpbuf[FD_SECTOR_LEN];
1276 baca51fa bellard
                int ret;
1277 85571bc7 bellard
                DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1278 baca51fa bellard
                ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1279 8977f3c1 bellard
                if (ret == 0) {
1280 77370520 blueswir1
                    status2 = FD_SR2_SEH;
1281 8977f3c1 bellard
                    goto end_transfer;
1282 8977f3c1 bellard
                }
1283 baca51fa bellard
                if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1284 baca51fa bellard
                    (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1285 8977f3c1 bellard
                    status2 = 0x00;
1286 8977f3c1 bellard
                    goto end_transfer;
1287 8977f3c1 bellard
                }
1288 8977f3c1 bellard
            }
1289 4f431960 j_mayer
            break;
1290 8977f3c1 bellard
        }
1291 4f431960 j_mayer
        fdctrl->data_pos += len;
1292 4f431960 j_mayer
        rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1293 baca51fa bellard
        if (rel_pos == 0) {
1294 8977f3c1 bellard
            /* Seek to next sector */
1295 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1296 746d6de7 blueswir1
                break;
1297 8977f3c1 bellard
        }
1298 8977f3c1 bellard
    }
1299 4f431960 j_mayer
 end_transfer:
1300 baca51fa bellard
    len = fdctrl->data_pos - start_pos;
1301 baca51fa bellard
    FLOPPY_DPRINTF("end transfer %d %d %d\n",
1302 4f431960 j_mayer
                   fdctrl->data_pos, len, fdctrl->data_len);
1303 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE ||
1304 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANL ||
1305 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1306 77370520 blueswir1
        status2 = FD_SR2_SEH;
1307 baca51fa bellard
    if (FD_DID_SEEK(fdctrl->data_state))
1308 9fea808a blueswir1
        status0 |= FD_SR0_SEEK;
1309 baca51fa bellard
    fdctrl->data_len -= len;
1310 890fa6be bellard
    fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1311 4f431960 j_mayer
 transfer_error:
1312 8977f3c1 bellard
1313 baca51fa bellard
    return len;
1314 8977f3c1 bellard
}
1315 8977f3c1 bellard
1316 8977f3c1 bellard
/* Data register : 0x05 */
1317 baca51fa bellard
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1318 8977f3c1 bellard
{
1319 baca51fa bellard
    fdrive_t *cur_drv;
1320 8977f3c1 bellard
    uint32_t retval = 0;
1321 746d6de7 blueswir1
    int pos;
1322 8977f3c1 bellard
1323 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1324 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1325 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1326 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for reading\n");
1327 8977f3c1 bellard
        return 0;
1328 8977f3c1 bellard
    }
1329 baca51fa bellard
    pos = fdctrl->data_pos;
1330 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1331 8977f3c1 bellard
        pos %= FD_SECTOR_LEN;
1332 8977f3c1 bellard
        if (pos == 0) {
1333 746d6de7 blueswir1
            if (fdctrl->data_pos != 0)
1334 746d6de7 blueswir1
                if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1335 746d6de7 blueswir1
                    FLOPPY_DPRINTF("error seeking to next sector %d\n",
1336 746d6de7 blueswir1
                                   fd_sector(cur_drv));
1337 746d6de7 blueswir1
                    return 0;
1338 746d6de7 blueswir1
                }
1339 77370520 blueswir1
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1340 77370520 blueswir1
                FLOPPY_DPRINTF("error getting sector %d\n",
1341 77370520 blueswir1
                               fd_sector(cur_drv));
1342 77370520 blueswir1
                /* Sure, image size is too small... */
1343 77370520 blueswir1
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1344 77370520 blueswir1
            }
1345 8977f3c1 bellard
        }
1346 8977f3c1 bellard
    }
1347 baca51fa bellard
    retval = fdctrl->fifo[pos];
1348 baca51fa bellard
    if (++fdctrl->data_pos == fdctrl->data_len) {
1349 baca51fa bellard
        fdctrl->data_pos = 0;
1350 890fa6be bellard
        /* Switch from transfer mode to status mode
1351 8977f3c1 bellard
         * then from status mode to command mode
1352 8977f3c1 bellard
         */
1353 368df94d blueswir1
        if (fdctrl->msr & FD_MSR_NONDMA) {
1354 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1355 ed5fd2cc bellard
        } else {
1356 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1357 ed5fd2cc bellard
            fdctrl_reset_irq(fdctrl);
1358 ed5fd2cc bellard
        }
1359 8977f3c1 bellard
    }
1360 8977f3c1 bellard
    FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1361 8977f3c1 bellard
1362 8977f3c1 bellard
    return retval;
1363 8977f3c1 bellard
}
1364 8977f3c1 bellard
1365 baca51fa bellard
static void fdctrl_format_sector (fdctrl_t *fdctrl)
1366 8977f3c1 bellard
{
1367 baca51fa bellard
    fdrive_t *cur_drv;
1368 baca51fa bellard
    uint8_t kh, kt, ks;
1369 8977f3c1 bellard
1370 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1371 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1372 baca51fa bellard
    kt = fdctrl->fifo[6];
1373 baca51fa bellard
    kh = fdctrl->fifo[7];
1374 baca51fa bellard
    ks = fdctrl->fifo[8];
1375 baca51fa bellard
    FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1376 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1377 baca51fa bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1378 9fea808a blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1379 baca51fa bellard
    case 2:
1380 baca51fa bellard
        /* sect too big */
1381 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1382 baca51fa bellard
        fdctrl->fifo[3] = kt;
1383 baca51fa bellard
        fdctrl->fifo[4] = kh;
1384 baca51fa bellard
        fdctrl->fifo[5] = ks;
1385 baca51fa bellard
        return;
1386 baca51fa bellard
    case 3:
1387 baca51fa bellard
        /* track too big */
1388 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1389 baca51fa bellard
        fdctrl->fifo[3] = kt;
1390 baca51fa bellard
        fdctrl->fifo[4] = kh;
1391 baca51fa bellard
        fdctrl->fifo[5] = ks;
1392 baca51fa bellard
        return;
1393 baca51fa bellard
    case 4:
1394 baca51fa bellard
        /* No seek enabled */
1395 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1396 baca51fa bellard
        fdctrl->fifo[3] = kt;
1397 baca51fa bellard
        fdctrl->fifo[4] = kh;
1398 baca51fa bellard
        fdctrl->fifo[5] = ks;
1399 baca51fa bellard
        return;
1400 baca51fa bellard
    case 1:
1401 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1402 baca51fa bellard
        break;
1403 baca51fa bellard
    default:
1404 baca51fa bellard
        break;
1405 baca51fa bellard
    }
1406 baca51fa bellard
    memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1407 baca51fa bellard
    if (cur_drv->bs == NULL ||
1408 baca51fa bellard
        bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1409 37a4c539 ths
        FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1410 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1411 baca51fa bellard
    } else {
1412 4f431960 j_mayer
        if (cur_drv->sect == cur_drv->last_sect) {
1413 4f431960 j_mayer
            fdctrl->data_state &= ~FD_STATE_FORMAT;
1414 4f431960 j_mayer
            /* Last sector done */
1415 4f431960 j_mayer
            if (FD_DID_SEEK(fdctrl->data_state))
1416 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1417 4f431960 j_mayer
            else
1418 4f431960 j_mayer
                fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1419 4f431960 j_mayer
        } else {
1420 4f431960 j_mayer
            /* More to do */
1421 4f431960 j_mayer
            fdctrl->data_pos = 0;
1422 4f431960 j_mayer
            fdctrl->data_len = 4;
1423 4f431960 j_mayer
        }
1424 baca51fa bellard
    }
1425 baca51fa bellard
}
1426 baca51fa bellard
1427 65cef780 blueswir1
static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1428 65cef780 blueswir1
{
1429 65cef780 blueswir1
    fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1430 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->lock << 4;
1431 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1432 65cef780 blueswir1
}
1433 65cef780 blueswir1
1434 65cef780 blueswir1
static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1435 65cef780 blueswir1
{
1436 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1437 65cef780 blueswir1
1438 65cef780 blueswir1
    /* Drives position */
1439 65cef780 blueswir1
    fdctrl->fifo[0] = drv0(fdctrl)->track;
1440 65cef780 blueswir1
    fdctrl->fifo[1] = drv1(fdctrl)->track;
1441 78ae820c blueswir1
#if MAX_FD == 4
1442 78ae820c blueswir1
    fdctrl->fifo[2] = drv2(fdctrl)->track;
1443 78ae820c blueswir1
    fdctrl->fifo[3] = drv3(fdctrl)->track;
1444 78ae820c blueswir1
#else
1445 65cef780 blueswir1
    fdctrl->fifo[2] = 0;
1446 65cef780 blueswir1
    fdctrl->fifo[3] = 0;
1447 78ae820c blueswir1
#endif
1448 65cef780 blueswir1
    /* timers */
1449 65cef780 blueswir1
    fdctrl->fifo[4] = fdctrl->timer0;
1450 368df94d blueswir1
    fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1451 65cef780 blueswir1
    fdctrl->fifo[6] = cur_drv->last_sect;
1452 65cef780 blueswir1
    fdctrl->fifo[7] = (fdctrl->lock << 7) |
1453 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1454 65cef780 blueswir1
    fdctrl->fifo[8] = fdctrl->config;
1455 65cef780 blueswir1
    fdctrl->fifo[9] = fdctrl->precomp_trk;
1456 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 10, 0);
1457 65cef780 blueswir1
}
1458 65cef780 blueswir1
1459 65cef780 blueswir1
static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1460 65cef780 blueswir1
{
1461 65cef780 blueswir1
    /* Controller's version */
1462 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->version;
1463 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1464 65cef780 blueswir1
}
1465 65cef780 blueswir1
1466 65cef780 blueswir1
static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1467 65cef780 blueswir1
{
1468 65cef780 blueswir1
    fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1469 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1470 65cef780 blueswir1
}
1471 65cef780 blueswir1
1472 65cef780 blueswir1
static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1473 65cef780 blueswir1
{
1474 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1475 65cef780 blueswir1
1476 65cef780 blueswir1
    /* Drives position */
1477 65cef780 blueswir1
    drv0(fdctrl)->track = fdctrl->fifo[3];
1478 65cef780 blueswir1
    drv1(fdctrl)->track = fdctrl->fifo[4];
1479 78ae820c blueswir1
#if MAX_FD == 4
1480 78ae820c blueswir1
    drv2(fdctrl)->track = fdctrl->fifo[5];
1481 78ae820c blueswir1
    drv3(fdctrl)->track = fdctrl->fifo[6];
1482 78ae820c blueswir1
#endif
1483 65cef780 blueswir1
    /* timers */
1484 65cef780 blueswir1
    fdctrl->timer0 = fdctrl->fifo[7];
1485 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[8];
1486 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[9];
1487 65cef780 blueswir1
    fdctrl->lock = fdctrl->fifo[10] >> 7;
1488 65cef780 blueswir1
    cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1489 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[11];
1490 65cef780 blueswir1
    fdctrl->precomp_trk = fdctrl->fifo[12];
1491 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[13];
1492 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1493 65cef780 blueswir1
}
1494 65cef780 blueswir1
1495 65cef780 blueswir1
static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1496 65cef780 blueswir1
{
1497 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1498 65cef780 blueswir1
1499 65cef780 blueswir1
    fdctrl->fifo[0] = 0;
1500 65cef780 blueswir1
    fdctrl->fifo[1] = 0;
1501 65cef780 blueswir1
    /* Drives position */
1502 65cef780 blueswir1
    fdctrl->fifo[2] = drv0(fdctrl)->track;
1503 65cef780 blueswir1
    fdctrl->fifo[3] = drv1(fdctrl)->track;
1504 78ae820c blueswir1
#if MAX_FD == 4
1505 78ae820c blueswir1
    fdctrl->fifo[4] = drv2(fdctrl)->track;
1506 78ae820c blueswir1
    fdctrl->fifo[5] = drv3(fdctrl)->track;
1507 78ae820c blueswir1
#else
1508 65cef780 blueswir1
    fdctrl->fifo[4] = 0;
1509 65cef780 blueswir1
    fdctrl->fifo[5] = 0;
1510 78ae820c blueswir1
#endif
1511 65cef780 blueswir1
    /* timers */
1512 65cef780 blueswir1
    fdctrl->fifo[6] = fdctrl->timer0;
1513 65cef780 blueswir1
    fdctrl->fifo[7] = fdctrl->timer1;
1514 65cef780 blueswir1
    fdctrl->fifo[8] = cur_drv->last_sect;
1515 65cef780 blueswir1
    fdctrl->fifo[9] = (fdctrl->lock << 7) |
1516 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1517 65cef780 blueswir1
    fdctrl->fifo[10] = fdctrl->config;
1518 65cef780 blueswir1
    fdctrl->fifo[11] = fdctrl->precomp_trk;
1519 65cef780 blueswir1
    fdctrl->fifo[12] = fdctrl->pwrd;
1520 65cef780 blueswir1
    fdctrl->fifo[13] = 0;
1521 65cef780 blueswir1
    fdctrl->fifo[14] = 0;
1522 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 15, 1);
1523 65cef780 blueswir1
}
1524 65cef780 blueswir1
1525 65cef780 blueswir1
static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1526 65cef780 blueswir1
{
1527 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1528 65cef780 blueswir1
1529 65cef780 blueswir1
    /* XXX: should set main status register to busy */
1530 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1531 65cef780 blueswir1
    qemu_mod_timer(fdctrl->result_timer,
1532 65cef780 blueswir1
                   qemu_get_clock(vm_clock) + (ticks_per_sec / 50));
1533 65cef780 blueswir1
}
1534 65cef780 blueswir1
1535 65cef780 blueswir1
static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1536 65cef780 blueswir1
{
1537 65cef780 blueswir1
    fdrive_t *cur_drv;
1538 65cef780 blueswir1
1539 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1540 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1541 65cef780 blueswir1
    fdctrl->data_state |= FD_STATE_FORMAT;
1542 65cef780 blueswir1
    if (fdctrl->fifo[0] & 0x80)
1543 65cef780 blueswir1
        fdctrl->data_state |= FD_STATE_MULTI;
1544 65cef780 blueswir1
    else
1545 65cef780 blueswir1
        fdctrl->data_state &= ~FD_STATE_MULTI;
1546 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_SEEK;
1547 65cef780 blueswir1
    cur_drv->bps =
1548 65cef780 blueswir1
        fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1549 65cef780 blueswir1
#if 0
1550 65cef780 blueswir1
    cur_drv->last_sect =
1551 65cef780 blueswir1
        cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1552 65cef780 blueswir1
        fdctrl->fifo[3] / 2;
1553 65cef780 blueswir1
#else
1554 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[3];
1555 65cef780 blueswir1
#endif
1556 65cef780 blueswir1
    /* TODO: implement format using DMA expected by the Bochs BIOS
1557 65cef780 blueswir1
     * and Linux fdformat (read 3 bytes per sector via DMA and fill
1558 65cef780 blueswir1
     * the sector with the specified fill byte
1559 65cef780 blueswir1
     */
1560 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_FORMAT;
1561 65cef780 blueswir1
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1562 65cef780 blueswir1
}
1563 65cef780 blueswir1
1564 65cef780 blueswir1
static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1565 65cef780 blueswir1
{
1566 65cef780 blueswir1
    fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1567 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1568 368df94d blueswir1
    if (fdctrl->fifo[2] & 1)
1569 368df94d blueswir1
        fdctrl->dor &= ~FD_DOR_DMAEN;
1570 368df94d blueswir1
    else
1571 368df94d blueswir1
        fdctrl->dor |= FD_DOR_DMAEN;
1572 65cef780 blueswir1
    /* No result back */
1573 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1574 65cef780 blueswir1
}
1575 65cef780 blueswir1
1576 65cef780 blueswir1
static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1577 65cef780 blueswir1
{
1578 65cef780 blueswir1
    fdrive_t *cur_drv;
1579 65cef780 blueswir1
1580 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1581 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1582 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1583 65cef780 blueswir1
    /* 1 Byte status back */
1584 65cef780 blueswir1
    fdctrl->fifo[0] = (cur_drv->ro << 6) |
1585 65cef780 blueswir1
        (cur_drv->track == 0 ? 0x10 : 0x00) |
1586 65cef780 blueswir1
        (cur_drv->head << 2) |
1587 cefec4f5 blueswir1
        GET_CUR_DRV(fdctrl) |
1588 65cef780 blueswir1
        0x28;
1589 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1590 65cef780 blueswir1
}
1591 65cef780 blueswir1
1592 65cef780 blueswir1
static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1593 65cef780 blueswir1
{
1594 65cef780 blueswir1
    fdrive_t *cur_drv;
1595 65cef780 blueswir1
1596 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1597 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1598 65cef780 blueswir1
    fd_recalibrate(cur_drv);
1599 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1600 65cef780 blueswir1
    /* Raise Interrupt */
1601 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1602 65cef780 blueswir1
}
1603 65cef780 blueswir1
1604 65cef780 blueswir1
static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1605 65cef780 blueswir1
{
1606 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1607 65cef780 blueswir1
1608 f2d81b33 blueswir1
    if(fdctrl->reset_sensei > 0) {
1609 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1610 f2d81b33 blueswir1
            FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1611 f2d81b33 blueswir1
        fdctrl->reset_sensei--;
1612 f2d81b33 blueswir1
    } else {
1613 f2d81b33 blueswir1
        /* XXX: status0 handling is broken for read/write
1614 f2d81b33 blueswir1
           commands, so we do this hack. It should be suppressed
1615 f2d81b33 blueswir1
           ASAP */
1616 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1617 f2d81b33 blueswir1
            FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1618 f2d81b33 blueswir1
    }
1619 f2d81b33 blueswir1
1620 65cef780 blueswir1
    fdctrl->fifo[1] = cur_drv->track;
1621 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 2, 0);
1622 65cef780 blueswir1
    fdctrl_reset_irq(fdctrl);
1623 77370520 blueswir1
    fdctrl->status0 = FD_SR0_RDYCHG;
1624 65cef780 blueswir1
}
1625 65cef780 blueswir1
1626 65cef780 blueswir1
static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1627 65cef780 blueswir1
{
1628 65cef780 blueswir1
    fdrive_t *cur_drv;
1629 65cef780 blueswir1
1630 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1631 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1632 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1633 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->max_track) {
1634 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1635 65cef780 blueswir1
    } else {
1636 65cef780 blueswir1
        cur_drv->track = fdctrl->fifo[2];
1637 65cef780 blueswir1
        /* Raise Interrupt */
1638 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1639 65cef780 blueswir1
    }
1640 65cef780 blueswir1
}
1641 65cef780 blueswir1
1642 65cef780 blueswir1
static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1643 65cef780 blueswir1
{
1644 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1645 65cef780 blueswir1
1646 65cef780 blueswir1
    if (fdctrl->fifo[1] & 0x80)
1647 65cef780 blueswir1
        cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1648 65cef780 blueswir1
    /* No result back */
1649 1c346df2 blueswir1
    fdctrl_reset_fifo(fdctrl);
1650 65cef780 blueswir1
}
1651 65cef780 blueswir1
1652 65cef780 blueswir1
static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1653 65cef780 blueswir1
{
1654 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[2];
1655 65cef780 blueswir1
    fdctrl->precomp_trk =  fdctrl->fifo[3];
1656 65cef780 blueswir1
    /* No result back */
1657 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1658 65cef780 blueswir1
}
1659 65cef780 blueswir1
1660 65cef780 blueswir1
static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1661 65cef780 blueswir1
{
1662 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[1];
1663 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->fifo[1];
1664 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1665 65cef780 blueswir1
}
1666 65cef780 blueswir1
1667 65cef780 blueswir1
static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1668 65cef780 blueswir1
{
1669 65cef780 blueswir1
    /* No result back */
1670 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1671 65cef780 blueswir1
}
1672 65cef780 blueswir1
1673 65cef780 blueswir1
static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1674 65cef780 blueswir1
{
1675 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1676 65cef780 blueswir1
1677 65cef780 blueswir1
    if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1678 65cef780 blueswir1
        /* Command parameters done */
1679 65cef780 blueswir1
        if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1680 65cef780 blueswir1
            fdctrl->fifo[0] = fdctrl->fifo[1];
1681 65cef780 blueswir1
            fdctrl->fifo[2] = 0;
1682 65cef780 blueswir1
            fdctrl->fifo[3] = 0;
1683 65cef780 blueswir1
            fdctrl_set_fifo(fdctrl, 4, 1);
1684 65cef780 blueswir1
        } else {
1685 65cef780 blueswir1
            fdctrl_reset_fifo(fdctrl);
1686 65cef780 blueswir1
        }
1687 65cef780 blueswir1
    } else if (fdctrl->data_len > 7) {
1688 65cef780 blueswir1
        /* ERROR */
1689 65cef780 blueswir1
        fdctrl->fifo[0] = 0x80 |
1690 cefec4f5 blueswir1
            (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1691 65cef780 blueswir1
        fdctrl_set_fifo(fdctrl, 1, 1);
1692 65cef780 blueswir1
    }
1693 65cef780 blueswir1
}
1694 65cef780 blueswir1
1695 65cef780 blueswir1
static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1696 65cef780 blueswir1
{
1697 77370520 blueswir1
    fdrive_t *cur_drv;
1698 65cef780 blueswir1
1699 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1700 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1701 65cef780 blueswir1
    if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1702 65cef780 blueswir1
        cur_drv->track = cur_drv->max_track - 1;
1703 65cef780 blueswir1
    } else {
1704 65cef780 blueswir1
        cur_drv->track += fdctrl->fifo[2];
1705 65cef780 blueswir1
    }
1706 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1707 77370520 blueswir1
    /* Raise Interrupt */
1708 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1709 65cef780 blueswir1
}
1710 65cef780 blueswir1
1711 65cef780 blueswir1
static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1712 65cef780 blueswir1
{
1713 77370520 blueswir1
    fdrive_t *cur_drv;
1714 65cef780 blueswir1
1715 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1716 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1717 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->track) {
1718 65cef780 blueswir1
        cur_drv->track = 0;
1719 65cef780 blueswir1
    } else {
1720 65cef780 blueswir1
        cur_drv->track -= fdctrl->fifo[2];
1721 65cef780 blueswir1
    }
1722 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1723 65cef780 blueswir1
    /* Raise Interrupt */
1724 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1725 65cef780 blueswir1
}
1726 65cef780 blueswir1
1727 678803ab blueswir1
static const struct {
1728 678803ab blueswir1
    uint8_t value;
1729 678803ab blueswir1
    uint8_t mask;
1730 678803ab blueswir1
    const char* name;
1731 678803ab blueswir1
    int parameters;
1732 678803ab blueswir1
    void (*handler)(fdctrl_t *fdctrl, int direction);
1733 678803ab blueswir1
    int direction;
1734 678803ab blueswir1
} handlers[] = {
1735 678803ab blueswir1
    { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1736 678803ab blueswir1
    { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1737 678803ab blueswir1
    { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1738 678803ab blueswir1
    { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1739 678803ab blueswir1
    { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1740 678803ab blueswir1
    { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1741 678803ab blueswir1
    { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1742 678803ab blueswir1
    { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1743 678803ab blueswir1
    { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1744 678803ab blueswir1
    { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1745 678803ab blueswir1
    { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1746 678803ab blueswir1
    { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1747 678803ab blueswir1
    { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1748 678803ab blueswir1
    { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1749 678803ab blueswir1
    { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1750 678803ab blueswir1
    { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1751 678803ab blueswir1
    { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1752 678803ab blueswir1
    { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1753 678803ab blueswir1
    { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1754 678803ab blueswir1
    { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1755 678803ab blueswir1
    { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1756 678803ab blueswir1
    { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1757 678803ab blueswir1
    { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1758 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1759 678803ab blueswir1
    { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1760 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1761 678803ab blueswir1
    { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1762 678803ab blueswir1
    { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1763 678803ab blueswir1
    { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1764 678803ab blueswir1
    { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1765 678803ab blueswir1
    { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1766 678803ab blueswir1
    { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1767 678803ab blueswir1
};
1768 678803ab blueswir1
/* Associate command to an index in the 'handlers' array */
1769 678803ab blueswir1
static uint8_t command_to_handler[256];
1770 678803ab blueswir1
1771 baca51fa bellard
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1772 baca51fa bellard
{
1773 baca51fa bellard
    fdrive_t *cur_drv;
1774 65cef780 blueswir1
    int pos;
1775 baca51fa bellard
1776 8977f3c1 bellard
    /* Reset mode */
1777 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
1778 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1779 8977f3c1 bellard
        return;
1780 8977f3c1 bellard
    }
1781 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1782 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for writing\n");
1783 8977f3c1 bellard
        return;
1784 8977f3c1 bellard
    }
1785 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1786 8977f3c1 bellard
    /* Is it write command time ? */
1787 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1788 8977f3c1 bellard
        /* FIFO data write */
1789 b3bc1540 blueswir1
        pos = fdctrl->data_pos++;
1790 b3bc1540 blueswir1
        pos %= FD_SECTOR_LEN;
1791 b3bc1540 blueswir1
        fdctrl->fifo[pos] = value;
1792 b3bc1540 blueswir1
        if (pos == FD_SECTOR_LEN - 1 ||
1793 baca51fa bellard
            fdctrl->data_pos == fdctrl->data_len) {
1794 77370520 blueswir1
            cur_drv = get_cur_drv(fdctrl);
1795 77370520 blueswir1
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1796 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1797 77370520 blueswir1
                return;
1798 77370520 blueswir1
            }
1799 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1800 746d6de7 blueswir1
                FLOPPY_DPRINTF("error seeking to next sector %d\n",
1801 746d6de7 blueswir1
                               fd_sector(cur_drv));
1802 746d6de7 blueswir1
                return;
1803 746d6de7 blueswir1
            }
1804 8977f3c1 bellard
        }
1805 890fa6be bellard
        /* Switch from transfer mode to status mode
1806 8977f3c1 bellard
         * then from status mode to command mode
1807 8977f3c1 bellard
         */
1808 b9b3d225 blueswir1
        if (fdctrl->data_pos == fdctrl->data_len)
1809 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1810 8977f3c1 bellard
        return;
1811 8977f3c1 bellard
    }
1812 baca51fa bellard
    if (fdctrl->data_pos == 0) {
1813 8977f3c1 bellard
        /* Command */
1814 678803ab blueswir1
        pos = command_to_handler[value & 0xff];
1815 678803ab blueswir1
        FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1816 678803ab blueswir1
        fdctrl->data_len = handlers[pos].parameters + 1;
1817 8977f3c1 bellard
    }
1818 678803ab blueswir1
1819 baca51fa bellard
    FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1820 77370520 blueswir1
    fdctrl->fifo[fdctrl->data_pos++] = value;
1821 77370520 blueswir1
    if (fdctrl->data_pos == fdctrl->data_len) {
1822 8977f3c1 bellard
        /* We now have all parameters
1823 8977f3c1 bellard
         * and will be able to treat the command
1824 8977f3c1 bellard
         */
1825 4f431960 j_mayer
        if (fdctrl->data_state & FD_STATE_FORMAT) {
1826 4f431960 j_mayer
            fdctrl_format_sector(fdctrl);
1827 8977f3c1 bellard
            return;
1828 8977f3c1 bellard
        }
1829 65cef780 blueswir1
1830 678803ab blueswir1
        pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1831 678803ab blueswir1
        FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1832 678803ab blueswir1
        (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1833 8977f3c1 bellard
    }
1834 8977f3c1 bellard
}
1835 ed5fd2cc bellard
1836 ed5fd2cc bellard
static void fdctrl_result_timer(void *opaque)
1837 ed5fd2cc bellard
{
1838 ed5fd2cc bellard
    fdctrl_t *fdctrl = opaque;
1839 b7ffa3b1 ths
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1840 4f431960 j_mayer
1841 b7ffa3b1 ths
    /* Pretend we are spinning.
1842 b7ffa3b1 ths
     * This is needed for Coherent, which uses READ ID to check for
1843 b7ffa3b1 ths
     * sector interleaving.
1844 b7ffa3b1 ths
     */
1845 b7ffa3b1 ths
    if (cur_drv->last_sect != 0) {
1846 b7ffa3b1 ths
        cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1847 b7ffa3b1 ths
    }
1848 ed5fd2cc bellard
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1849 ed5fd2cc bellard
}
1850 678803ab blueswir1
1851 678803ab blueswir1
/* Init functions */
1852 678803ab blueswir1
static fdctrl_t *fdctrl_init_common (qemu_irq irq, int dma_chann,
1853 678803ab blueswir1
                                     target_phys_addr_t io_base,
1854 678803ab blueswir1
                                     BlockDriverState **fds)
1855 678803ab blueswir1
{
1856 678803ab blueswir1
    fdctrl_t *fdctrl;
1857 678803ab blueswir1
    int i, j;
1858 678803ab blueswir1
1859 678803ab blueswir1
    /* Fill 'command_to_handler' lookup table */
1860 b1503cda malc
    for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1861 678803ab blueswir1
        for (j = 0; j < sizeof(command_to_handler); j++) {
1862 678803ab blueswir1
            if ((j & handlers[i].mask) == handlers[i].value)
1863 678803ab blueswir1
                command_to_handler[j] = i;
1864 678803ab blueswir1
        }
1865 678803ab blueswir1
    }
1866 678803ab blueswir1
1867 678803ab blueswir1
    FLOPPY_DPRINTF("init controller\n");
1868 678803ab blueswir1
    fdctrl = qemu_mallocz(sizeof(fdctrl_t));
1869 678803ab blueswir1
    fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1870 678803ab blueswir1
    fdctrl->result_timer = qemu_new_timer(vm_clock,
1871 678803ab blueswir1
                                          fdctrl_result_timer, fdctrl);
1872 678803ab blueswir1
1873 678803ab blueswir1
    fdctrl->version = 0x90; /* Intel 82078 controller */
1874 678803ab blueswir1
    fdctrl->irq = irq;
1875 678803ab blueswir1
    fdctrl->dma_chann = dma_chann;
1876 678803ab blueswir1
    fdctrl->io_base = io_base;
1877 678803ab blueswir1
    fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1878 678803ab blueswir1
    if (fdctrl->dma_chann != -1) {
1879 678803ab blueswir1
        DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1880 678803ab blueswir1
    }
1881 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1882 678803ab blueswir1
        fd_init(&fdctrl->drives[i], fds[i]);
1883 678803ab blueswir1
    }
1884 77370520 blueswir1
    fdctrl_external_reset(fdctrl);
1885 77370520 blueswir1
    register_savevm("fdc", io_base, 2, fdc_save, fdc_load, fdctrl);
1886 678803ab blueswir1
    qemu_register_reset(fdctrl_external_reset, fdctrl);
1887 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1888 678803ab blueswir1
        fd_revalidate(&fdctrl->drives[i]);
1889 678803ab blueswir1
    }
1890 678803ab blueswir1
1891 678803ab blueswir1
    return fdctrl;
1892 678803ab blueswir1
}
1893 678803ab blueswir1
1894 678803ab blueswir1
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1895 678803ab blueswir1
                       target_phys_addr_t io_base,
1896 678803ab blueswir1
                       BlockDriverState **fds)
1897 678803ab blueswir1
{
1898 678803ab blueswir1
    fdctrl_t *fdctrl;
1899 678803ab blueswir1
    int io_mem;
1900 678803ab blueswir1
1901 678803ab blueswir1
    fdctrl = fdctrl_init_common(irq, dma_chann, io_base, fds);
1902 678803ab blueswir1
1903 678803ab blueswir1
    fdctrl->sun4m = 0;
1904 678803ab blueswir1
    if (mem_mapped) {
1905 678803ab blueswir1
        io_mem = cpu_register_io_memory(0, fdctrl_mem_read, fdctrl_mem_write,
1906 678803ab blueswir1
                                        fdctrl);
1907 678803ab blueswir1
        cpu_register_physical_memory(io_base, 0x08, io_mem);
1908 678803ab blueswir1
    } else {
1909 e64d7d59 blueswir1
        register_ioport_read((uint32_t)io_base + 0x01, 5, 1,
1910 e64d7d59 blueswir1
                             &fdctrl_read_port, fdctrl);
1911 e64d7d59 blueswir1
        register_ioport_read((uint32_t)io_base + 0x07, 1, 1,
1912 e64d7d59 blueswir1
                             &fdctrl_read_port, fdctrl);
1913 e64d7d59 blueswir1
        register_ioport_write((uint32_t)io_base + 0x01, 5, 1,
1914 e64d7d59 blueswir1
                              &fdctrl_write_port, fdctrl);
1915 e64d7d59 blueswir1
        register_ioport_write((uint32_t)io_base + 0x07, 1, 1,
1916 e64d7d59 blueswir1
                              &fdctrl_write_port, fdctrl);
1917 678803ab blueswir1
    }
1918 678803ab blueswir1
1919 678803ab blueswir1
    return fdctrl;
1920 678803ab blueswir1
}
1921 678803ab blueswir1
1922 678803ab blueswir1
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1923 678803ab blueswir1
                             BlockDriverState **fds, qemu_irq *fdc_tc)
1924 678803ab blueswir1
{
1925 678803ab blueswir1
    fdctrl_t *fdctrl;
1926 678803ab blueswir1
    int io_mem;
1927 678803ab blueswir1
1928 368df94d blueswir1
    fdctrl = fdctrl_init_common(irq, -1, io_base, fds);
1929 678803ab blueswir1
    fdctrl->sun4m = 1;
1930 678803ab blueswir1
    io_mem = cpu_register_io_memory(0, fdctrl_mem_read_strict,
1931 678803ab blueswir1
                                    fdctrl_mem_write_strict,
1932 678803ab blueswir1
                                    fdctrl);
1933 678803ab blueswir1
    cpu_register_physical_memory(io_base, 0x08, io_mem);
1934 678803ab blueswir1
    *fdc_tc = *qemu_allocate_irqs(fdctrl_handle_tc, fdctrl, 1);
1935 678803ab blueswir1
1936 678803ab blueswir1
    return fdctrl;
1937 678803ab blueswir1
}