Revision 90f11f95 target-i386/translate.c

b/target-i386/translate.c
2074 2074
        gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
2075 2075
        gen_op_addl_A0_im(2 <<  s->dflag);
2076 2076
    }
2077
    gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
2077
    gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2078 2078
}
2079 2079

  
2080 2080
/* NOTE: wrap around in 16 bit not fully handled */
......
2096 2096
        }
2097 2097
        gen_op_addl_A0_im(2 <<  s->dflag);
2098 2098
    }
2099
    gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
2099
    gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2100 2100
}
2101 2101

  
2102 2102
static void gen_enter(DisasContext *s, int esp_addend, int level)
......
2122 2122
    }
2123 2123
    gen_op_mov_reg_T1[ot][R_EBP]();
2124 2124
    gen_op_addl_T1_im( -esp_addend + (-opsize * level) );
2125
    gen_op_mov_reg_T1[ot][R_ESP]();
2125
    gen_op_mov_reg_T1[OT_WORD + s->ss32][R_ESP]();
2126 2126
}
2127 2127

  
2128 2128
static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)

Also available in: Unified diff