root / hw / omap_spi.c @ 916452df
History | View | Annotate | Download (9.5 kB)
1 | 2d08cc7c | cmchao | /*
|
---|---|---|---|
2 | 2d08cc7c | cmchao | * TI OMAP processor's Multichannel SPI emulation.
|
3 | 2d08cc7c | cmchao | *
|
4 | 2d08cc7c | cmchao | * Copyright (C) 2007-2009 Nokia Corporation
|
5 | 2d08cc7c | cmchao | *
|
6 | 2d08cc7c | cmchao | * Original code for OMAP2 by Andrzej Zaborowski <andrew@openedhand.com>
|
7 | 2d08cc7c | cmchao | *
|
8 | 2d08cc7c | cmchao | * This program is free software; you can redistribute it and/or
|
9 | 2d08cc7c | cmchao | * modify it under the terms of the GNU General Public License as
|
10 | 2d08cc7c | cmchao | * published by the Free Software Foundation; either version 2 or
|
11 | 2d08cc7c | cmchao | * (at your option) any later version of the License.
|
12 | 2d08cc7c | cmchao | *
|
13 | 2d08cc7c | cmchao | * This program is distributed in the hope that it will be useful,
|
14 | 2d08cc7c | cmchao | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
15 | 2d08cc7c | cmchao | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
16 | 2d08cc7c | cmchao | * GNU General Public License for more details.
|
17 | 2d08cc7c | cmchao | *
|
18 | 2d08cc7c | cmchao | * You should have received a copy of the GNU General Public License along
|
19 | 2d08cc7c | cmchao | * with this program; if not, write to the Free Software Foundation, Inc.,
|
20 | 2d08cc7c | cmchao | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
|
21 | 2d08cc7c | cmchao | */
|
22 | 2d08cc7c | cmchao | #include "hw.h" |
23 | 2d08cc7c | cmchao | #include "omap.h" |
24 | 2d08cc7c | cmchao | |
25 | 2d08cc7c | cmchao | /* Multichannel SPI */
|
26 | 2d08cc7c | cmchao | struct omap_mcspi_s {
|
27 | 2d08cc7c | cmchao | qemu_irq irq; |
28 | 2d08cc7c | cmchao | int chnum;
|
29 | 2d08cc7c | cmchao | |
30 | 2d08cc7c | cmchao | uint32_t sysconfig; |
31 | 2d08cc7c | cmchao | uint32_t systest; |
32 | 2d08cc7c | cmchao | uint32_t irqst; |
33 | 2d08cc7c | cmchao | uint32_t irqen; |
34 | 2d08cc7c | cmchao | uint32_t wken; |
35 | 2d08cc7c | cmchao | uint32_t control; |
36 | 2d08cc7c | cmchao | |
37 | 2d08cc7c | cmchao | struct omap_mcspi_ch_s {
|
38 | 2d08cc7c | cmchao | qemu_irq txdrq; |
39 | 2d08cc7c | cmchao | qemu_irq rxdrq; |
40 | 2d08cc7c | cmchao | uint32_t (*txrx)(void *opaque, uint32_t, int); |
41 | 2d08cc7c | cmchao | void *opaque;
|
42 | 2d08cc7c | cmchao | |
43 | 2d08cc7c | cmchao | uint32_t tx; |
44 | 2d08cc7c | cmchao | uint32_t rx; |
45 | 2d08cc7c | cmchao | |
46 | 2d08cc7c | cmchao | uint32_t config; |
47 | 2d08cc7c | cmchao | uint32_t status; |
48 | 2d08cc7c | cmchao | uint32_t control; |
49 | 2d08cc7c | cmchao | } ch[4];
|
50 | 2d08cc7c | cmchao | }; |
51 | 2d08cc7c | cmchao | |
52 | 2d08cc7c | cmchao | static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s) |
53 | 2d08cc7c | cmchao | { |
54 | 2d08cc7c | cmchao | qemu_set_irq(s->irq, s->irqst & s->irqen); |
55 | 2d08cc7c | cmchao | } |
56 | 2d08cc7c | cmchao | |
57 | 2d08cc7c | cmchao | static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch) |
58 | 2d08cc7c | cmchao | { |
59 | 2d08cc7c | cmchao | qemu_set_irq(ch->txdrq, |
60 | 2d08cc7c | cmchao | (ch->control & 1) && /* EN */ |
61 | 2d08cc7c | cmchao | (ch->config & (1 << 14)) && /* DMAW */ |
62 | 2d08cc7c | cmchao | (ch->status & (1 << 1)) && /* TXS */ |
63 | 2d08cc7c | cmchao | ((ch->config >> 12) & 3) != 1); /* TRM */ |
64 | 2d08cc7c | cmchao | qemu_set_irq(ch->rxdrq, |
65 | 2d08cc7c | cmchao | (ch->control & 1) && /* EN */ |
66 | 2d08cc7c | cmchao | (ch->config & (1 << 15)) && /* DMAW */ |
67 | 2d08cc7c | cmchao | (ch->status & (1 << 0)) && /* RXS */ |
68 | 2d08cc7c | cmchao | ((ch->config >> 12) & 3) != 2); /* TRM */ |
69 | 2d08cc7c | cmchao | } |
70 | 2d08cc7c | cmchao | |
71 | 2d08cc7c | cmchao | static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum) |
72 | 2d08cc7c | cmchao | { |
73 | 2d08cc7c | cmchao | struct omap_mcspi_ch_s *ch = s->ch + chnum;
|
74 | 2d08cc7c | cmchao | |
75 | 2d08cc7c | cmchao | if (!(ch->control & 1)) /* EN */ |
76 | 2d08cc7c | cmchao | return;
|
77 | 2d08cc7c | cmchao | if ((ch->status & (1 << 0)) && /* RXS */ |
78 | 2d08cc7c | cmchao | ((ch->config >> 12) & 3) != 2 && /* TRM */ |
79 | 2d08cc7c | cmchao | !(ch->config & (1 << 19))) /* TURBO */ |
80 | 2d08cc7c | cmchao | goto intr_update;
|
81 | 2d08cc7c | cmchao | if ((ch->status & (1 << 1)) && /* TXS */ |
82 | 2d08cc7c | cmchao | ((ch->config >> 12) & 3) != 1) /* TRM */ |
83 | 2d08cc7c | cmchao | goto intr_update;
|
84 | 2d08cc7c | cmchao | |
85 | 2d08cc7c | cmchao | if (!(s->control & 1) || /* SINGLE */ |
86 | 2d08cc7c | cmchao | (ch->config & (1 << 20))) { /* FORCE */ |
87 | 2d08cc7c | cmchao | if (ch->txrx)
|
88 | 2d08cc7c | cmchao | ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
|
89 | 2d08cc7c | cmchao | 1 + (0x1f & (ch->config >> 7))); |
90 | 2d08cc7c | cmchao | } |
91 | 2d08cc7c | cmchao | |
92 | 2d08cc7c | cmchao | ch->tx = 0;
|
93 | 2d08cc7c | cmchao | ch->status |= 1 << 2; /* EOT */ |
94 | 2d08cc7c | cmchao | ch->status |= 1 << 1; /* TXS */ |
95 | 2d08cc7c | cmchao | if (((ch->config >> 12) & 3) != 2) /* TRM */ |
96 | 2d08cc7c | cmchao | ch->status |= 1 << 0; /* RXS */ |
97 | 2d08cc7c | cmchao | |
98 | 2d08cc7c | cmchao | intr_update:
|
99 | 2d08cc7c | cmchao | if ((ch->status & (1 << 0)) && /* RXS */ |
100 | 2d08cc7c | cmchao | ((ch->config >> 12) & 3) != 2 && /* TRM */ |
101 | 2d08cc7c | cmchao | !(ch->config & (1 << 19))) /* TURBO */ |
102 | 2d08cc7c | cmchao | s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */ |
103 | 2d08cc7c | cmchao | if ((ch->status & (1 << 1)) && /* TXS */ |
104 | 2d08cc7c | cmchao | ((ch->config >> 12) & 3) != 1) /* TRM */ |
105 | 2d08cc7c | cmchao | s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */ |
106 | 2d08cc7c | cmchao | omap_mcspi_interrupt_update(s); |
107 | 2d08cc7c | cmchao | omap_mcspi_dmarequest_update(ch); |
108 | 2d08cc7c | cmchao | } |
109 | 2d08cc7c | cmchao | |
110 | 2d08cc7c | cmchao | void omap_mcspi_reset(struct omap_mcspi_s *s) |
111 | 2d08cc7c | cmchao | { |
112 | 2d08cc7c | cmchao | int ch;
|
113 | 2d08cc7c | cmchao | |
114 | 2d08cc7c | cmchao | s->sysconfig = 0;
|
115 | 2d08cc7c | cmchao | s->systest = 0;
|
116 | 2d08cc7c | cmchao | s->irqst = 0;
|
117 | 2d08cc7c | cmchao | s->irqen = 0;
|
118 | 2d08cc7c | cmchao | s->wken = 0;
|
119 | 2d08cc7c | cmchao | s->control = 4;
|
120 | 2d08cc7c | cmchao | |
121 | 2d08cc7c | cmchao | for (ch = 0; ch < 4; ch ++) { |
122 | 2d08cc7c | cmchao | s->ch[ch].config = 0x060000;
|
123 | 2d08cc7c | cmchao | s->ch[ch].status = 2; /* TXS */ |
124 | 2d08cc7c | cmchao | s->ch[ch].control = 0;
|
125 | 2d08cc7c | cmchao | |
126 | 2d08cc7c | cmchao | omap_mcspi_dmarequest_update(s->ch + ch); |
127 | 2d08cc7c | cmchao | } |
128 | 2d08cc7c | cmchao | |
129 | 2d08cc7c | cmchao | omap_mcspi_interrupt_update(s); |
130 | 2d08cc7c | cmchao | } |
131 | 2d08cc7c | cmchao | |
132 | 2d08cc7c | cmchao | static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr) |
133 | 2d08cc7c | cmchao | { |
134 | 2d08cc7c | cmchao | struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
135 | 2d08cc7c | cmchao | int ch = 0; |
136 | 2d08cc7c | cmchao | uint32_t ret; |
137 | 2d08cc7c | cmchao | |
138 | 2d08cc7c | cmchao | switch (addr) {
|
139 | 2d08cc7c | cmchao | case 0x00: /* MCSPI_REVISION */ |
140 | 2d08cc7c | cmchao | return 0x91; |
141 | 2d08cc7c | cmchao | |
142 | 2d08cc7c | cmchao | case 0x10: /* MCSPI_SYSCONFIG */ |
143 | 2d08cc7c | cmchao | return s->sysconfig;
|
144 | 2d08cc7c | cmchao | |
145 | 2d08cc7c | cmchao | case 0x14: /* MCSPI_SYSSTATUS */ |
146 | 2d08cc7c | cmchao | return 1; /* RESETDONE */ |
147 | 2d08cc7c | cmchao | |
148 | 2d08cc7c | cmchao | case 0x18: /* MCSPI_IRQSTATUS */ |
149 | 2d08cc7c | cmchao | return s->irqst;
|
150 | 2d08cc7c | cmchao | |
151 | 2d08cc7c | cmchao | case 0x1c: /* MCSPI_IRQENABLE */ |
152 | 2d08cc7c | cmchao | return s->irqen;
|
153 | 2d08cc7c | cmchao | |
154 | 2d08cc7c | cmchao | case 0x20: /* MCSPI_WAKEUPENABLE */ |
155 | 2d08cc7c | cmchao | return s->wken;
|
156 | 2d08cc7c | cmchao | |
157 | 2d08cc7c | cmchao | case 0x24: /* MCSPI_SYST */ |
158 | 2d08cc7c | cmchao | return s->systest;
|
159 | 2d08cc7c | cmchao | |
160 | 2d08cc7c | cmchao | case 0x28: /* MCSPI_MODULCTRL */ |
161 | 2d08cc7c | cmchao | return s->control;
|
162 | 2d08cc7c | cmchao | |
163 | 2d08cc7c | cmchao | case 0x68: ch ++; |
164 | 2d08cc7c | cmchao | case 0x54: ch ++; |
165 | 2d08cc7c | cmchao | case 0x40: ch ++; |
166 | 2d08cc7c | cmchao | case 0x2c: /* MCSPI_CHCONF */ |
167 | 2d08cc7c | cmchao | return s->ch[ch].config;
|
168 | 2d08cc7c | cmchao | |
169 | 2d08cc7c | cmchao | case 0x6c: ch ++; |
170 | 2d08cc7c | cmchao | case 0x58: ch ++; |
171 | 2d08cc7c | cmchao | case 0x44: ch ++; |
172 | 2d08cc7c | cmchao | case 0x30: /* MCSPI_CHSTAT */ |
173 | 2d08cc7c | cmchao | return s->ch[ch].status;
|
174 | 2d08cc7c | cmchao | |
175 | 2d08cc7c | cmchao | case 0x70: ch ++; |
176 | 2d08cc7c | cmchao | case 0x5c: ch ++; |
177 | 2d08cc7c | cmchao | case 0x48: ch ++; |
178 | 2d08cc7c | cmchao | case 0x34: /* MCSPI_CHCTRL */ |
179 | 2d08cc7c | cmchao | return s->ch[ch].control;
|
180 | 2d08cc7c | cmchao | |
181 | 2d08cc7c | cmchao | case 0x74: ch ++; |
182 | 2d08cc7c | cmchao | case 0x60: ch ++; |
183 | 2d08cc7c | cmchao | case 0x4c: ch ++; |
184 | 2d08cc7c | cmchao | case 0x38: /* MCSPI_TX */ |
185 | 2d08cc7c | cmchao | return s->ch[ch].tx;
|
186 | 2d08cc7c | cmchao | |
187 | 2d08cc7c | cmchao | case 0x78: ch ++; |
188 | 2d08cc7c | cmchao | case 0x64: ch ++; |
189 | 2d08cc7c | cmchao | case 0x50: ch ++; |
190 | 2d08cc7c | cmchao | case 0x3c: /* MCSPI_RX */ |
191 | 2d08cc7c | cmchao | s->ch[ch].status &= ~(1 << 0); /* RXS */ |
192 | 2d08cc7c | cmchao | ret = s->ch[ch].rx; |
193 | 2d08cc7c | cmchao | omap_mcspi_transfer_run(s, ch); |
194 | 2d08cc7c | cmchao | return ret;
|
195 | 2d08cc7c | cmchao | } |
196 | 2d08cc7c | cmchao | |
197 | 2d08cc7c | cmchao | OMAP_BAD_REG(addr); |
198 | 2d08cc7c | cmchao | return 0; |
199 | 2d08cc7c | cmchao | } |
200 | 2d08cc7c | cmchao | |
201 | 2d08cc7c | cmchao | static void omap_mcspi_write(void *opaque, target_phys_addr_t addr, |
202 | 2d08cc7c | cmchao | uint32_t value) |
203 | 2d08cc7c | cmchao | { |
204 | 2d08cc7c | cmchao | struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque; |
205 | 2d08cc7c | cmchao | int ch = 0; |
206 | 2d08cc7c | cmchao | |
207 | 2d08cc7c | cmchao | switch (addr) {
|
208 | 2d08cc7c | cmchao | case 0x00: /* MCSPI_REVISION */ |
209 | 2d08cc7c | cmchao | case 0x14: /* MCSPI_SYSSTATUS */ |
210 | 2d08cc7c | cmchao | case 0x30: /* MCSPI_CHSTAT0 */ |
211 | 2d08cc7c | cmchao | case 0x3c: /* MCSPI_RX0 */ |
212 | 2d08cc7c | cmchao | case 0x44: /* MCSPI_CHSTAT1 */ |
213 | 2d08cc7c | cmchao | case 0x50: /* MCSPI_RX1 */ |
214 | 2d08cc7c | cmchao | case 0x58: /* MCSPI_CHSTAT2 */ |
215 | 2d08cc7c | cmchao | case 0x64: /* MCSPI_RX2 */ |
216 | 2d08cc7c | cmchao | case 0x6c: /* MCSPI_CHSTAT3 */ |
217 | 2d08cc7c | cmchao | case 0x78: /* MCSPI_RX3 */ |
218 | 2d08cc7c | cmchao | OMAP_RO_REG(addr); |
219 | 2d08cc7c | cmchao | return;
|
220 | 2d08cc7c | cmchao | |
221 | 2d08cc7c | cmchao | case 0x10: /* MCSPI_SYSCONFIG */ |
222 | 2d08cc7c | cmchao | if (value & (1 << 1)) /* SOFTRESET */ |
223 | 2d08cc7c | cmchao | omap_mcspi_reset(s); |
224 | 2d08cc7c | cmchao | s->sysconfig = value & 0x31d;
|
225 | 2d08cc7c | cmchao | break;
|
226 | 2d08cc7c | cmchao | |
227 | 2d08cc7c | cmchao | case 0x18: /* MCSPI_IRQSTATUS */ |
228 | 2d08cc7c | cmchao | if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) { |
229 | 2d08cc7c | cmchao | s->irqst &= ~value; |
230 | 2d08cc7c | cmchao | omap_mcspi_interrupt_update(s); |
231 | 2d08cc7c | cmchao | } |
232 | 2d08cc7c | cmchao | break;
|
233 | 2d08cc7c | cmchao | |
234 | 2d08cc7c | cmchao | case 0x1c: /* MCSPI_IRQENABLE */ |
235 | 2d08cc7c | cmchao | s->irqen = value & 0x1777f;
|
236 | 2d08cc7c | cmchao | omap_mcspi_interrupt_update(s); |
237 | 2d08cc7c | cmchao | break;
|
238 | 2d08cc7c | cmchao | |
239 | 2d08cc7c | cmchao | case 0x20: /* MCSPI_WAKEUPENABLE */ |
240 | 2d08cc7c | cmchao | s->wken = value & 1;
|
241 | 2d08cc7c | cmchao | break;
|
242 | 2d08cc7c | cmchao | |
243 | 2d08cc7c | cmchao | case 0x24: /* MCSPI_SYST */ |
244 | 2d08cc7c | cmchao | if (s->control & (1 << 3)) /* SYSTEM_TEST */ |
245 | 2d08cc7c | cmchao | if (value & (1 << 11)) { /* SSB */ |
246 | 2d08cc7c | cmchao | s->irqst |= 0x1777f;
|
247 | 2d08cc7c | cmchao | omap_mcspi_interrupt_update(s); |
248 | 2d08cc7c | cmchao | } |
249 | 2d08cc7c | cmchao | s->systest = value & 0xfff;
|
250 | 2d08cc7c | cmchao | break;
|
251 | 2d08cc7c | cmchao | |
252 | 2d08cc7c | cmchao | case 0x28: /* MCSPI_MODULCTRL */ |
253 | 2d08cc7c | cmchao | if (value & (1 << 3)) /* SYSTEM_TEST */ |
254 | 2d08cc7c | cmchao | if (s->systest & (1 << 11)) { /* SSB */ |
255 | 2d08cc7c | cmchao | s->irqst |= 0x1777f;
|
256 | 2d08cc7c | cmchao | omap_mcspi_interrupt_update(s); |
257 | 2d08cc7c | cmchao | } |
258 | 2d08cc7c | cmchao | s->control = value & 0xf;
|
259 | 2d08cc7c | cmchao | break;
|
260 | 2d08cc7c | cmchao | |
261 | 2d08cc7c | cmchao | case 0x68: ch ++; |
262 | 2d08cc7c | cmchao | case 0x54: ch ++; |
263 | 2d08cc7c | cmchao | case 0x40: ch ++; |
264 | 2d08cc7c | cmchao | case 0x2c: /* MCSPI_CHCONF */ |
265 | 2d08cc7c | cmchao | if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */ |
266 | 2d08cc7c | cmchao | omap_mcspi_dmarequest_update(s->ch + ch); |
267 | 2d08cc7c | cmchao | if (((value >> 12) & 3) == 3) /* TRM */ |
268 | 2d08cc7c | cmchao | fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
|
269 | 2d08cc7c | cmchao | if (((value >> 7) & 0x1f) < 3) /* WL */ |
270 | 2d08cc7c | cmchao | fprintf(stderr, "%s: invalid WL value (%i)\n",
|
271 | 2d08cc7c | cmchao | __FUNCTION__, (value >> 7) & 0x1f); |
272 | 2d08cc7c | cmchao | s->ch[ch].config = value & 0x7fffff;
|
273 | 2d08cc7c | cmchao | break;
|
274 | 2d08cc7c | cmchao | |
275 | 2d08cc7c | cmchao | case 0x70: ch ++; |
276 | 2d08cc7c | cmchao | case 0x5c: ch ++; |
277 | 2d08cc7c | cmchao | case 0x48: ch ++; |
278 | 2d08cc7c | cmchao | case 0x34: /* MCSPI_CHCTRL */ |
279 | 2d08cc7c | cmchao | if (value & ~s->ch[ch].control & 1) { /* EN */ |
280 | 2d08cc7c | cmchao | s->ch[ch].control |= 1;
|
281 | 2d08cc7c | cmchao | omap_mcspi_transfer_run(s, ch); |
282 | 2d08cc7c | cmchao | } else
|
283 | 2d08cc7c | cmchao | s->ch[ch].control = value & 1;
|
284 | 2d08cc7c | cmchao | break;
|
285 | 2d08cc7c | cmchao | |
286 | 2d08cc7c | cmchao | case 0x74: ch ++; |
287 | 2d08cc7c | cmchao | case 0x60: ch ++; |
288 | 2d08cc7c | cmchao | case 0x4c: ch ++; |
289 | 2d08cc7c | cmchao | case 0x38: /* MCSPI_TX */ |
290 | 2d08cc7c | cmchao | s->ch[ch].tx = value; |
291 | 2d08cc7c | cmchao | s->ch[ch].status &= ~(1 << 1); /* TXS */ |
292 | 2d08cc7c | cmchao | omap_mcspi_transfer_run(s, ch); |
293 | 2d08cc7c | cmchao | break;
|
294 | 2d08cc7c | cmchao | |
295 | 2d08cc7c | cmchao | default:
|
296 | 2d08cc7c | cmchao | OMAP_BAD_REG(addr); |
297 | 2d08cc7c | cmchao | return;
|
298 | 2d08cc7c | cmchao | } |
299 | 2d08cc7c | cmchao | } |
300 | 2d08cc7c | cmchao | |
301 | 2d08cc7c | cmchao | static CPUReadMemoryFunc * const omap_mcspi_readfn[] = { |
302 | 2d08cc7c | cmchao | omap_badwidth_read32, |
303 | 2d08cc7c | cmchao | omap_badwidth_read32, |
304 | 2d08cc7c | cmchao | omap_mcspi_read, |
305 | 2d08cc7c | cmchao | }; |
306 | 2d08cc7c | cmchao | |
307 | 2d08cc7c | cmchao | static CPUWriteMemoryFunc * const omap_mcspi_writefn[] = { |
308 | 2d08cc7c | cmchao | omap_badwidth_write32, |
309 | 2d08cc7c | cmchao | omap_badwidth_write32, |
310 | 2d08cc7c | cmchao | omap_mcspi_write, |
311 | 2d08cc7c | cmchao | }; |
312 | 2d08cc7c | cmchao | |
313 | 2d08cc7c | cmchao | struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum, |
314 | 2d08cc7c | cmchao | qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) |
315 | 2d08cc7c | cmchao | { |
316 | 2d08cc7c | cmchao | int iomemtype;
|
317 | 2d08cc7c | cmchao | struct omap_mcspi_s *s = (struct omap_mcspi_s *) |
318 | 2d08cc7c | cmchao | qemu_mallocz(sizeof(struct omap_mcspi_s)); |
319 | 2d08cc7c | cmchao | struct omap_mcspi_ch_s *ch = s->ch;
|
320 | 2d08cc7c | cmchao | |
321 | 2d08cc7c | cmchao | s->irq = irq; |
322 | 2d08cc7c | cmchao | s->chnum = chnum; |
323 | 2d08cc7c | cmchao | while (chnum --) {
|
324 | 2d08cc7c | cmchao | ch->txdrq = *drq ++; |
325 | 2d08cc7c | cmchao | ch->rxdrq = *drq ++; |
326 | 2d08cc7c | cmchao | ch ++; |
327 | 2d08cc7c | cmchao | } |
328 | 2d08cc7c | cmchao | omap_mcspi_reset(s); |
329 | 2d08cc7c | cmchao | |
330 | 2d08cc7c | cmchao | iomemtype = l4_register_io_memory(omap_mcspi_readfn, |
331 | 2d08cc7c | cmchao | omap_mcspi_writefn, s); |
332 | 2d08cc7c | cmchao | omap_l4_attach(ta, 0, iomemtype);
|
333 | 2d08cc7c | cmchao | |
334 | 2d08cc7c | cmchao | return s;
|
335 | 2d08cc7c | cmchao | } |
336 | 2d08cc7c | cmchao | |
337 | 2d08cc7c | cmchao | void omap_mcspi_attach(struct omap_mcspi_s *s, |
338 | 2d08cc7c | cmchao | uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque, |
339 | 2d08cc7c | cmchao | int chipselect)
|
340 | 2d08cc7c | cmchao | { |
341 | 2d08cc7c | cmchao | if (chipselect < 0 || chipselect >= s->chnum) |
342 | 2d08cc7c | cmchao | hw_error("%s: Bad chipselect %i\n", __FUNCTION__, chipselect);
|
343 | 2d08cc7c | cmchao | |
344 | 2d08cc7c | cmchao | s->ch[chipselect].txrx = txrx; |
345 | 2d08cc7c | cmchao | s->ch[chipselect].opaque = opaque; |
346 | 2d08cc7c | cmchao | } |