root / hw / flash.h @ 91834991
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1 | 87ecb68b | pbrook | /* NOR flash devices */
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2 | 87ecb68b | pbrook | typedef struct pflash_t pflash_t; |
3 | 87ecb68b | pbrook | |
4 | 88eeee0a | balrog | /* pflash_cfi01.c */
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5 | 88eeee0a | balrog | pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, |
6 | 88eeee0a | balrog | BlockDriverState *bs, |
7 | 88eeee0a | balrog | uint32_t sector_len, int nb_blocs, int width, |
8 | 88eeee0a | balrog | uint16_t id0, uint16_t id1, |
9 | 88eeee0a | balrog | uint16_t id2, uint16_t id3); |
10 | 88eeee0a | balrog | |
11 | 88eeee0a | balrog | /* pflash_cfi02.c */
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12 | 88eeee0a | balrog | pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, |
13 | cf6d9118 | balrog | BlockDriverState *bs, uint32_t sector_len, |
14 | 4fbd24ba | balrog | int nb_blocs, int nb_mappings, int width, |
15 | 88eeee0a | balrog | uint16_t id0, uint16_t id1, |
16 | 6725070d | balrog | uint16_t id2, uint16_t id3, |
17 | 6725070d | balrog | uint16_t unlock_addr0, uint16_t unlock_addr1); |
18 | 87ecb68b | pbrook | |
19 | 87ecb68b | pbrook | /* nand.c */
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20 | 87ecb68b | pbrook | struct nand_flash_s;
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21 | 87ecb68b | pbrook | struct nand_flash_s *nand_init(int manf_id, int chip_id); |
22 | 87ecb68b | pbrook | void nand_done(struct nand_flash_s *s); |
23 | 87ecb68b | pbrook | void nand_setpins(struct nand_flash_s *s, |
24 | 87ecb68b | pbrook | int cle, int ale, int ce, int wp, int gnd); |
25 | 87ecb68b | pbrook | void nand_getpins(struct nand_flash_s *s, int *rb); |
26 | 87ecb68b | pbrook | void nand_setio(struct nand_flash_s *s, uint8_t value); |
27 | 87ecb68b | pbrook | uint8_t nand_getio(struct nand_flash_s *s);
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28 | 87ecb68b | pbrook | |
29 | 87ecb68b | pbrook | #define NAND_MFR_TOSHIBA 0x98 |
30 | 87ecb68b | pbrook | #define NAND_MFR_SAMSUNG 0xec |
31 | 87ecb68b | pbrook | #define NAND_MFR_FUJITSU 0x04 |
32 | 87ecb68b | pbrook | #define NAND_MFR_NATIONAL 0x8f |
33 | 87ecb68b | pbrook | #define NAND_MFR_RENESAS 0x07 |
34 | 87ecb68b | pbrook | #define NAND_MFR_STMICRO 0x20 |
35 | 87ecb68b | pbrook | #define NAND_MFR_HYNIX 0xad |
36 | 87ecb68b | pbrook | #define NAND_MFR_MICRON 0x2c |
37 | 87ecb68b | pbrook | |
38 | 7e7c5e4c | balrog | /* onenand.c */
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39 | 7e7c5e4c | balrog | void onenand_base_update(void *opaque, target_phys_addr_t new); |
40 | 7e7c5e4c | balrog | void onenand_base_unmap(void *opaque); |
41 | 7e7c5e4c | balrog | void *onenand_init(uint32_t id, int regshift, qemu_irq irq); |
42 | 7e7c5e4c | balrog | |
43 | 87ecb68b | pbrook | /* ecc.c */
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44 | 87ecb68b | pbrook | struct ecc_state_s {
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45 | 87ecb68b | pbrook | uint8_t cp; /* Column parity */
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46 | 87ecb68b | pbrook | uint16_t lp[2]; /* Line parity */ |
47 | 87ecb68b | pbrook | uint16_t count; |
48 | 87ecb68b | pbrook | }; |
49 | 87ecb68b | pbrook | |
50 | 87ecb68b | pbrook | uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
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51 | 87ecb68b | pbrook | void ecc_reset(struct ecc_state_s *s); |
52 | 87ecb68b | pbrook | void ecc_put(QEMUFile *f, struct ecc_state_s *s); |
53 | 87ecb68b | pbrook | void ecc_get(QEMUFile *f, struct ecc_state_s *s); |