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/*
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* USB UHCI controller emulation
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*
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* Copyright (c) 2005 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "usb.h" |
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#include "pci.h" |
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#include "qemu-timer.h" |
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|
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//#define DEBUG
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//#define DEBUG_PACKET
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//#define DEBUG_ISOCH
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#define UHCI_CMD_FGR (1 << 4) |
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#define UHCI_CMD_EGSM (1 << 3) |
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#define UHCI_CMD_GRESET (1 << 2) |
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#define UHCI_CMD_HCRESET (1 << 1) |
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#define UHCI_CMD_RS (1 << 0) |
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|
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#define UHCI_STS_HCHALTED (1 << 5) |
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#define UHCI_STS_HCPERR (1 << 4) |
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#define UHCI_STS_HSERR (1 << 3) |
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#define UHCI_STS_RD (1 << 2) |
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#define UHCI_STS_USBERR (1 << 1) |
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#define UHCI_STS_USBINT (1 << 0) |
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|
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#define TD_CTRL_SPD (1 << 29) |
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#define TD_CTRL_ERROR_SHIFT 27 |
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#define TD_CTRL_IOS (1 << 25) |
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#define TD_CTRL_IOC (1 << 24) |
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#define TD_CTRL_ACTIVE (1 << 23) |
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#define TD_CTRL_STALL (1 << 22) |
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#define TD_CTRL_BABBLE (1 << 20) |
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#define TD_CTRL_NAK (1 << 19) |
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#define TD_CTRL_TIMEOUT (1 << 18) |
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|
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#define UHCI_PORT_RESET (1 << 9) |
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#define UHCI_PORT_LSDA (1 << 8) |
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#define UHCI_PORT_ENC (1 << 3) |
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#define UHCI_PORT_EN (1 << 2) |
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#define UHCI_PORT_CSC (1 << 1) |
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#define UHCI_PORT_CCS (1 << 0) |
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|
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#define FRAME_TIMER_FREQ 1000 |
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#define FRAME_MAX_LOOPS 100 |
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#define NB_PORTS 2 |
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typedef struct UHCIPort { |
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USBPort port; |
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uint16_t ctrl; |
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} UHCIPort; |
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typedef struct UHCIState { |
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PCIDevice dev; |
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uint16_t cmd; /* cmd register */
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uint16_t status; |
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uint16_t intr; /* interrupt enable register */
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uint16_t frnum; /* frame number */
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uint32_t fl_base_addr; /* frame list base address */
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uint8_t sof_timing; |
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uint8_t status2; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
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QEMUTimer *frame_timer; |
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UHCIPort ports[NB_PORTS]; |
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/* Interrupts that should be raised at the end of the current frame. */
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uint32_t pending_int_mask; |
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/* For simplicity of implementation we only allow a single pending USB
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request. This means all usb traffic on this controller is effectively
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suspended until that transfer completes. When the transfer completes
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the next transfer from that queue will be processed. However
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other queues will not be processed until the next frame. The solution
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is to allow multiple pending requests. */
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uint32_t async_qh; |
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uint32_t async_frame_addr; |
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USBPacket usb_packet; |
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uint8_t usb_buf[2048];
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} UHCIState; |
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typedef struct UHCI_TD { |
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uint32_t link; |
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uint32_t ctrl; /* see TD_CTRL_xxx */
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uint32_t token; |
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uint32_t buffer; |
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} UHCI_TD; |
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typedef struct UHCI_QH { |
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uint32_t link; |
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uint32_t el_link; |
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} UHCI_QH; |
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static void uhci_attach(USBPort *port1, USBDevice *dev); |
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static void uhci_update_irq(UHCIState *s) |
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{ |
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int level;
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if (((s->status2 & 1) && (s->intr & (1 << 2))) || |
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((s->status2 & 2) && (s->intr & (1 << 3))) || |
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((s->status & UHCI_STS_USBERR) && (s->intr & (1 << 0))) || |
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((s->status & UHCI_STS_RD) && (s->intr & (1 << 1))) || |
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(s->status & UHCI_STS_HSERR) || |
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(s->status & UHCI_STS_HCPERR)) { |
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level = 1;
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} else {
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level = 0;
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} |
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qemu_set_irq(s->dev.irq[3], level);
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} |
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static void uhci_reset(UHCIState *s) |
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{ |
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uint8_t *pci_conf; |
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int i;
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UHCIPort *port; |
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pci_conf = s->dev.config; |
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pci_conf[0x6a] = 0x01; /* usb clock */ |
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pci_conf[0x6b] = 0x00; |
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s->cmd = 0;
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s->status = 0;
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s->status2 = 0;
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s->intr = 0;
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s->fl_base_addr = 0;
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s->sof_timing = 64;
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for(i = 0; i < NB_PORTS; i++) { |
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port = &s->ports[i]; |
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port->ctrl = 0x0080;
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if (port->port.dev)
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uhci_attach(&port->port, port->port.dev); |
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} |
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} |
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#if 0
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static void uhci_save(QEMUFile *f, void *opaque)
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{
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UHCIState *s = opaque;
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uint8_t num_ports = NB_PORTS;
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int i;
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pci_device_save(&s->dev, f);
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qemu_put_8s(f, &num_ports);
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for (i = 0; i < num_ports; ++i)
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qemu_put_be16s(f, &s->ports[i].ctrl);
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qemu_put_be16s(f, &s->cmd);
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qemu_put_be16s(f, &s->status);
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qemu_put_be16s(f, &s->intr);
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qemu_put_be16s(f, &s->frnum);
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qemu_put_be32s(f, &s->fl_base_addr);
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qemu_put_8s(f, &s->sof_timing);
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qemu_put_8s(f, &s->status2);
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qemu_put_timer(f, s->frame_timer);
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}
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static int uhci_load(QEMUFile *f, void *opaque, int version_id)
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{
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UHCIState *s = opaque;
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uint8_t num_ports;
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int i, ret;
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if (version_id > 1)
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return -EINVAL;
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ret = pci_device_load(&s->dev, f);
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if (ret < 0)
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return ret;
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qemu_get_8s(f, &num_ports);
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if (num_ports != NB_PORTS)
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return -EINVAL;
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for (i = 0; i < num_ports; ++i)
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qemu_get_be16s(f, &s->ports[i].ctrl);
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qemu_get_be16s(f, &s->cmd);
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qemu_get_be16s(f, &s->status);
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qemu_get_be16s(f, &s->intr);
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qemu_get_be16s(f, &s->frnum);
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qemu_get_be32s(f, &s->fl_base_addr);
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qemu_get_8s(f, &s->sof_timing);
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qemu_get_8s(f, &s->status2);
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qemu_get_timer(f, s->frame_timer);
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return 0;
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}
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#endif
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static void uhci_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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UHCIState *s = opaque; |
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addr &= 0x1f;
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switch(addr) {
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case 0x0c: |
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s->sof_timing = val; |
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break;
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} |
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} |
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static uint32_t uhci_ioport_readb(void *opaque, uint32_t addr) |
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{ |
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UHCIState *s = opaque; |
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uint32_t val; |
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addr &= 0x1f;
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switch(addr) {
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case 0x0c: |
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val = s->sof_timing; |
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break;
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default:
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val = 0xff;
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break;
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} |
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return val;
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} |
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static void uhci_ioport_writew(void *opaque, uint32_t addr, uint32_t val) |
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{ |
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UHCIState *s = opaque; |
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addr &= 0x1f;
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#ifdef DEBUG
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printf("uhci writew port=0x%04x val=0x%04x\n", addr, val);
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#endif
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switch(addr) {
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case 0x00: |
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if ((val & UHCI_CMD_RS) && !(s->cmd & UHCI_CMD_RS)) {
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/* start frame processing */
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qemu_mod_timer(s->frame_timer, qemu_get_clock(vm_clock)); |
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s->status &= ~UHCI_STS_HCHALTED; |
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} else if (!(val & UHCI_CMD_RS)) { |
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s->status |= UHCI_STS_HCHALTED; |
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} |
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if (val & UHCI_CMD_GRESET) {
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UHCIPort *port; |
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USBDevice *dev; |
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int i;
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/* send reset on the USB bus */
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for(i = 0; i < NB_PORTS; i++) { |
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port = &s->ports[i]; |
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dev = port->port.dev; |
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if (dev) {
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usb_send_msg(dev, USB_MSG_RESET); |
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} |
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} |
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uhci_reset(s); |
268 |
return;
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} |
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if (val & UHCI_CMD_HCRESET) {
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uhci_reset(s); |
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return;
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} |
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s->cmd = val; |
275 |
break;
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case 0x02: |
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s->status &= ~val; |
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/* XXX: the chip spec is not coherent, so we add a hidden
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register to distinguish between IOC and SPD */
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if (val & UHCI_STS_USBINT)
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s->status2 = 0;
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uhci_update_irq(s); |
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break;
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case 0x04: |
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s->intr = val; |
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uhci_update_irq(s); |
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break;
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case 0x06: |
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if (s->status & UHCI_STS_HCHALTED)
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s->frnum = val & 0x7ff;
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break;
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case 0x10 ... 0x1f: |
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{ |
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UHCIPort *port; |
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USBDevice *dev; |
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int n;
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n = (addr >> 1) & 7; |
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if (n >= NB_PORTS)
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return;
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port = &s->ports[n]; |
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dev = port->port.dev; |
303 |
if (dev) {
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/* port reset */
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if ( (val & UHCI_PORT_RESET) &&
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!(port->ctrl & UHCI_PORT_RESET) ) { |
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usb_send_msg(dev, USB_MSG_RESET); |
308 |
} |
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} |
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port->ctrl = (port->ctrl & 0x01fb) | (val & ~0x01fb); |
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/* some bits are reset when a '1' is written to them */
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port->ctrl &= ~(val & 0x000a);
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} |
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break;
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} |
316 |
} |
317 |
|
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static uint32_t uhci_ioport_readw(void *opaque, uint32_t addr) |
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{ |
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UHCIState *s = opaque; |
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uint32_t val; |
322 |
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addr &= 0x1f;
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switch(addr) {
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case 0x00: |
326 |
val = s->cmd; |
327 |
break;
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case 0x02: |
329 |
val = s->status; |
330 |
break;
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case 0x04: |
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val = s->intr; |
333 |
break;
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case 0x06: |
335 |
val = s->frnum; |
336 |
break;
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case 0x10 ... 0x1f: |
338 |
{ |
339 |
UHCIPort *port; |
340 |
int n;
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n = (addr >> 1) & 7; |
342 |
if (n >= NB_PORTS)
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goto read_default;
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port = &s->ports[n]; |
345 |
val = port->ctrl; |
346 |
} |
347 |
break;
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default:
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read_default:
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val = 0xff7f; /* disabled port */ |
351 |
break;
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} |
353 |
#ifdef DEBUG
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printf("uhci readw port=0x%04x val=0x%04x\n", addr, val);
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#endif
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return val;
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} |
358 |
|
359 |
static void uhci_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
360 |
{ |
361 |
UHCIState *s = opaque; |
362 |
|
363 |
addr &= 0x1f;
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364 |
#ifdef DEBUG
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365 |
printf("uhci writel port=0x%04x val=0x%08x\n", addr, val);
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#endif
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367 |
switch(addr) {
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368 |
case 0x08: |
369 |
s->fl_base_addr = val & ~0xfff;
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break;
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} |
372 |
} |
373 |
|
374 |
static uint32_t uhci_ioport_readl(void *opaque, uint32_t addr) |
375 |
{ |
376 |
UHCIState *s = opaque; |
377 |
uint32_t val; |
378 |
|
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addr &= 0x1f;
|
380 |
switch(addr) {
|
381 |
case 0x08: |
382 |
val = s->fl_base_addr; |
383 |
break;
|
384 |
default:
|
385 |
val = 0xffffffff;
|
386 |
break;
|
387 |
} |
388 |
return val;
|
389 |
} |
390 |
|
391 |
/* signal resume if controller suspended */
|
392 |
static void uhci_resume (void *opaque) |
393 |
{ |
394 |
UHCIState *s = (UHCIState *)opaque; |
395 |
|
396 |
if (!s)
|
397 |
return;
|
398 |
|
399 |
if (s->cmd & UHCI_CMD_EGSM) {
|
400 |
s->cmd |= UHCI_CMD_FGR; |
401 |
s->status |= UHCI_STS_RD; |
402 |
uhci_update_irq(s); |
403 |
} |
404 |
} |
405 |
|
406 |
static void uhci_attach(USBPort *port1, USBDevice *dev) |
407 |
{ |
408 |
UHCIState *s = port1->opaque; |
409 |
UHCIPort *port = &s->ports[port1->index]; |
410 |
|
411 |
if (dev) {
|
412 |
if (port->port.dev) {
|
413 |
usb_attach(port1, NULL);
|
414 |
} |
415 |
/* set connect status */
|
416 |
port->ctrl |= UHCI_PORT_CCS | UHCI_PORT_CSC; |
417 |
|
418 |
/* update speed */
|
419 |
if (dev->speed == USB_SPEED_LOW)
|
420 |
port->ctrl |= UHCI_PORT_LSDA; |
421 |
else
|
422 |
port->ctrl &= ~UHCI_PORT_LSDA; |
423 |
|
424 |
uhci_resume(s); |
425 |
|
426 |
port->port.dev = dev; |
427 |
/* send the attach message */
|
428 |
usb_send_msg(dev, USB_MSG_ATTACH); |
429 |
} else {
|
430 |
/* set connect status */
|
431 |
if (port->ctrl & UHCI_PORT_CCS) {
|
432 |
port->ctrl &= ~UHCI_PORT_CCS; |
433 |
port->ctrl |= UHCI_PORT_CSC; |
434 |
} |
435 |
/* disable port */
|
436 |
if (port->ctrl & UHCI_PORT_EN) {
|
437 |
port->ctrl &= ~UHCI_PORT_EN; |
438 |
port->ctrl |= UHCI_PORT_ENC; |
439 |
} |
440 |
|
441 |
uhci_resume(s); |
442 |
|
443 |
dev = port->port.dev; |
444 |
if (dev) {
|
445 |
/* send the detach message */
|
446 |
usb_send_msg(dev, USB_MSG_DETACH); |
447 |
} |
448 |
port->port.dev = NULL;
|
449 |
} |
450 |
} |
451 |
|
452 |
static int uhci_broadcast_packet(UHCIState *s, USBPacket *p) |
453 |
{ |
454 |
UHCIPort *port; |
455 |
USBDevice *dev; |
456 |
int i, ret;
|
457 |
|
458 |
#ifdef DEBUG_PACKET
|
459 |
{ |
460 |
const char *pidstr; |
461 |
switch(p->pid) {
|
462 |
case USB_TOKEN_SETUP: pidstr = "SETUP"; break; |
463 |
case USB_TOKEN_IN: pidstr = "IN"; break; |
464 |
case USB_TOKEN_OUT: pidstr = "OUT"; break; |
465 |
default: pidstr = "?"; break; |
466 |
} |
467 |
printf("frame %d: pid=%s addr=0x%02x ep=%d len=%d\n",
|
468 |
s->frnum, pidstr, p->devaddr, p->devep, p->len); |
469 |
if (p->pid != USB_TOKEN_IN) {
|
470 |
printf(" data_out=");
|
471 |
for(i = 0; i < p->len; i++) { |
472 |
printf(" %02x", p->data[i]);
|
473 |
} |
474 |
printf("\n");
|
475 |
} |
476 |
} |
477 |
#endif
|
478 |
for(i = 0; i < NB_PORTS; i++) { |
479 |
port = &s->ports[i]; |
480 |
dev = port->port.dev; |
481 |
if (dev && (port->ctrl & UHCI_PORT_EN)) {
|
482 |
ret = dev->handle_packet(dev, p); |
483 |
if (ret != USB_RET_NODEV) {
|
484 |
#ifdef DEBUG_PACKET
|
485 |
if (ret == USB_RET_ASYNC) {
|
486 |
printf("usb-uhci: Async packet\n");
|
487 |
} else {
|
488 |
printf(" ret=%d ", ret);
|
489 |
if (p->pid == USB_TOKEN_IN && ret > 0) { |
490 |
printf("data_in=");
|
491 |
for(i = 0; i < ret; i++) { |
492 |
printf(" %02x", p->data[i]);
|
493 |
} |
494 |
} |
495 |
printf("\n");
|
496 |
} |
497 |
#endif
|
498 |
return ret;
|
499 |
} |
500 |
} |
501 |
} |
502 |
return USB_RET_NODEV;
|
503 |
} |
504 |
|
505 |
static void uhci_async_complete_packet(USBPacket * packet, void *opaque); |
506 |
|
507 |
/* return -1 if fatal error (frame must be stopped)
|
508 |
0 if TD successful
|
509 |
1 if TD unsuccessful or inactive
|
510 |
*/
|
511 |
static int uhci_handle_td(UHCIState *s, UHCI_TD *td, uint32_t *int_mask, |
512 |
int completion)
|
513 |
{ |
514 |
uint8_t pid; |
515 |
int len = 0, max_len, err, ret = 0; |
516 |
|
517 |
/* ??? This is wrong for async completion. */
|
518 |
if (td->ctrl & TD_CTRL_IOC) {
|
519 |
*int_mask |= 0x01;
|
520 |
} |
521 |
|
522 |
if (!(td->ctrl & TD_CTRL_ACTIVE))
|
523 |
return 1; |
524 |
|
525 |
/* TD is active */
|
526 |
max_len = ((td->token >> 21) + 1) & 0x7ff; |
527 |
pid = td->token & 0xff;
|
528 |
|
529 |
if (completion && (s->async_qh || s->async_frame_addr)) {
|
530 |
ret = s->usb_packet.len; |
531 |
if (ret >= 0) { |
532 |
len = ret; |
533 |
if (len > max_len) {
|
534 |
len = max_len; |
535 |
ret = USB_RET_BABBLE; |
536 |
} |
537 |
if (len > 0) { |
538 |
/* write the data back */
|
539 |
cpu_physical_memory_write(td->buffer, s->usb_buf, len); |
540 |
} |
541 |
} else {
|
542 |
len = 0;
|
543 |
} |
544 |
s->async_qh = 0;
|
545 |
s->async_frame_addr = 0;
|
546 |
} else if (!completion) { |
547 |
s->usb_packet.pid = pid; |
548 |
s->usb_packet.devaddr = (td->token >> 8) & 0x7f; |
549 |
s->usb_packet.devep = (td->token >> 15) & 0xf; |
550 |
s->usb_packet.data = s->usb_buf; |
551 |
s->usb_packet.len = max_len; |
552 |
s->usb_packet.complete_cb = uhci_async_complete_packet; |
553 |
s->usb_packet.complete_opaque = s; |
554 |
switch(pid) {
|
555 |
case USB_TOKEN_OUT:
|
556 |
case USB_TOKEN_SETUP:
|
557 |
cpu_physical_memory_read(td->buffer, s->usb_buf, max_len); |
558 |
ret = uhci_broadcast_packet(s, &s->usb_packet); |
559 |
len = max_len; |
560 |
break;
|
561 |
case USB_TOKEN_IN:
|
562 |
ret = uhci_broadcast_packet(s, &s->usb_packet); |
563 |
if (ret >= 0) { |
564 |
len = ret; |
565 |
if (len > max_len) {
|
566 |
len = max_len; |
567 |
ret = USB_RET_BABBLE; |
568 |
} |
569 |
if (len > 0) { |
570 |
/* write the data back */
|
571 |
cpu_physical_memory_write(td->buffer, s->usb_buf, len); |
572 |
} |
573 |
} else {
|
574 |
len = 0;
|
575 |
} |
576 |
break;
|
577 |
default:
|
578 |
/* invalid pid : frame interrupted */
|
579 |
s->status |= UHCI_STS_HCPERR; |
580 |
uhci_update_irq(s); |
581 |
return -1; |
582 |
} |
583 |
} |
584 |
|
585 |
if (ret == USB_RET_ASYNC) {
|
586 |
return 2; |
587 |
} |
588 |
if (td->ctrl & TD_CTRL_IOS)
|
589 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
590 |
if (ret >= 0) { |
591 |
td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); |
592 |
/* The NAK bit may have been set by a previous frame, so clear it
|
593 |
here. The docs are somewhat unclear, but win2k relies on this
|
594 |
behavior. */
|
595 |
td->ctrl &= ~(TD_CTRL_ACTIVE | TD_CTRL_NAK); |
596 |
if (pid == USB_TOKEN_IN &&
|
597 |
(td->ctrl & TD_CTRL_SPD) && |
598 |
len < max_len) { |
599 |
*int_mask |= 0x02;
|
600 |
/* short packet: do not update QH */
|
601 |
return 1; |
602 |
} else {
|
603 |
/* success */
|
604 |
return 0; |
605 |
} |
606 |
} else {
|
607 |
switch(ret) {
|
608 |
default:
|
609 |
case USB_RET_NODEV:
|
610 |
do_timeout:
|
611 |
td->ctrl |= TD_CTRL_TIMEOUT; |
612 |
err = (td->ctrl >> TD_CTRL_ERROR_SHIFT) & 3;
|
613 |
if (err != 0) { |
614 |
err--; |
615 |
if (err == 0) { |
616 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
617 |
s->status |= UHCI_STS_USBERR; |
618 |
uhci_update_irq(s); |
619 |
} |
620 |
} |
621 |
td->ctrl = (td->ctrl & ~(3 << TD_CTRL_ERROR_SHIFT)) |
|
622 |
(err << TD_CTRL_ERROR_SHIFT); |
623 |
return 1; |
624 |
case USB_RET_NAK:
|
625 |
td->ctrl |= TD_CTRL_NAK; |
626 |
if (pid == USB_TOKEN_SETUP)
|
627 |
goto do_timeout;
|
628 |
return 1; |
629 |
case USB_RET_STALL:
|
630 |
td->ctrl |= TD_CTRL_STALL; |
631 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
632 |
return 1; |
633 |
case USB_RET_BABBLE:
|
634 |
td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; |
635 |
td->ctrl &= ~TD_CTRL_ACTIVE; |
636 |
/* frame interrupted */
|
637 |
return -1; |
638 |
} |
639 |
} |
640 |
} |
641 |
|
642 |
static void uhci_async_complete_packet(USBPacket * packet, void *opaque) |
643 |
{ |
644 |
UHCIState *s = opaque; |
645 |
UHCI_QH qh; |
646 |
UHCI_TD td; |
647 |
uint32_t link; |
648 |
uint32_t old_td_ctrl; |
649 |
uint32_t val; |
650 |
uint32_t frame_addr; |
651 |
int ret;
|
652 |
|
653 |
/* Handle async isochronous packet completion */
|
654 |
frame_addr = s->async_frame_addr; |
655 |
if (frame_addr) {
|
656 |
cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
657 |
le32_to_cpus(&link); |
658 |
|
659 |
cpu_physical_memory_read(link & ~0xf, (uint8_t *)&td, sizeof(td)); |
660 |
le32_to_cpus(&td.link); |
661 |
le32_to_cpus(&td.ctrl); |
662 |
le32_to_cpus(&td.token); |
663 |
le32_to_cpus(&td.buffer); |
664 |
old_td_ctrl = td.ctrl; |
665 |
ret = uhci_handle_td(s, &td, &s->pending_int_mask, 1);
|
666 |
|
667 |
/* update the status bits of the TD */
|
668 |
if (old_td_ctrl != td.ctrl) {
|
669 |
val = cpu_to_le32(td.ctrl); |
670 |
cpu_physical_memory_write((link & ~0xf) + 4, |
671 |
(const uint8_t *)&val,
|
672 |
sizeof(val));
|
673 |
} |
674 |
if (ret == 2) { |
675 |
s->async_frame_addr = frame_addr; |
676 |
} else if (ret == 0) { |
677 |
/* update qh element link */
|
678 |
val = cpu_to_le32(td.link); |
679 |
cpu_physical_memory_write(frame_addr, |
680 |
(const uint8_t *)&val,
|
681 |
sizeof(val));
|
682 |
} |
683 |
return;
|
684 |
} |
685 |
|
686 |
link = s->async_qh; |
687 |
if (!link) {
|
688 |
/* This should never happen. It means a TD somehow got removed
|
689 |
without cancelling the associated async IO request. */
|
690 |
return;
|
691 |
} |
692 |
cpu_physical_memory_read(link & ~0xf, (uint8_t *)&qh, sizeof(qh)); |
693 |
le32_to_cpus(&qh.link); |
694 |
le32_to_cpus(&qh.el_link); |
695 |
/* Re-process the queue containing the async packet. */
|
696 |
while (1) { |
697 |
cpu_physical_memory_read(qh.el_link & ~0xf,
|
698 |
(uint8_t *)&td, sizeof(td));
|
699 |
le32_to_cpus(&td.link); |
700 |
le32_to_cpus(&td.ctrl); |
701 |
le32_to_cpus(&td.token); |
702 |
le32_to_cpus(&td.buffer); |
703 |
old_td_ctrl = td.ctrl; |
704 |
ret = uhci_handle_td(s, &td, &s->pending_int_mask, 1);
|
705 |
|
706 |
/* update the status bits of the TD */
|
707 |
if (old_td_ctrl != td.ctrl) {
|
708 |
val = cpu_to_le32(td.ctrl); |
709 |
cpu_physical_memory_write((qh.el_link & ~0xf) + 4, |
710 |
(const uint8_t *)&val,
|
711 |
sizeof(val));
|
712 |
} |
713 |
if (ret < 0) |
714 |
break; /* interrupted frame */ |
715 |
if (ret == 2) { |
716 |
s->async_qh = link; |
717 |
break;
|
718 |
} else if (ret == 0) { |
719 |
/* update qh element link */
|
720 |
qh.el_link = td.link; |
721 |
val = cpu_to_le32(qh.el_link); |
722 |
cpu_physical_memory_write((link & ~0xf) + 4, |
723 |
(const uint8_t *)&val,
|
724 |
sizeof(val));
|
725 |
if (!(qh.el_link & 4)) |
726 |
break;
|
727 |
} |
728 |
break;
|
729 |
} |
730 |
} |
731 |
|
732 |
static void uhci_frame_timer(void *opaque) |
733 |
{ |
734 |
UHCIState *s = opaque; |
735 |
int64_t expire_time; |
736 |
uint32_t frame_addr, link, old_td_ctrl, val, int_mask; |
737 |
int cnt, ret;
|
738 |
UHCI_TD td; |
739 |
UHCI_QH qh; |
740 |
uint32_t old_async_qh; |
741 |
|
742 |
if (!(s->cmd & UHCI_CMD_RS)) {
|
743 |
qemu_del_timer(s->frame_timer); |
744 |
/* set hchalted bit in status - UHCI11D 2.1.2 */
|
745 |
s->status |= UHCI_STS_HCHALTED; |
746 |
return;
|
747 |
} |
748 |
/* Complete the previous frame. */
|
749 |
s->frnum = (s->frnum + 1) & 0x7ff; |
750 |
if (s->pending_int_mask) {
|
751 |
s->status2 |= s->pending_int_mask; |
752 |
s->status |= UHCI_STS_USBINT; |
753 |
uhci_update_irq(s); |
754 |
} |
755 |
old_async_qh = s->async_qh; |
756 |
frame_addr = s->fl_base_addr + ((s->frnum & 0x3ff) << 2); |
757 |
cpu_physical_memory_read(frame_addr, (uint8_t *)&link, 4);
|
758 |
le32_to_cpus(&link); |
759 |
int_mask = 0;
|
760 |
cnt = FRAME_MAX_LOOPS; |
761 |
while ((link & 1) == 0) { |
762 |
if (--cnt == 0) |
763 |
break;
|
764 |
/* valid frame */
|
765 |
if (link & 2) { |
766 |
/* QH */
|
767 |
if (link == s->async_qh) {
|
768 |
/* We've found a previously issues packet.
|
769 |
Nothing else to do. */
|
770 |
old_async_qh = 0;
|
771 |
break;
|
772 |
} |
773 |
cpu_physical_memory_read(link & ~0xf, (uint8_t *)&qh, sizeof(qh)); |
774 |
le32_to_cpus(&qh.link); |
775 |
le32_to_cpus(&qh.el_link); |
776 |
depth_first:
|
777 |
if (qh.el_link & 1) { |
778 |
/* no element : go to next entry */
|
779 |
link = qh.link; |
780 |
} else if (qh.el_link & 2) { |
781 |
/* QH */
|
782 |
link = qh.el_link; |
783 |
} else if (s->async_qh) { |
784 |
/* We can only cope with one pending packet. Keep looking
|
785 |
for the previously issued packet. */
|
786 |
link = qh.link; |
787 |
} else {
|
788 |
/* TD */
|
789 |
if (--cnt == 0) |
790 |
break;
|
791 |
cpu_physical_memory_read(qh.el_link & ~0xf,
|
792 |
(uint8_t *)&td, sizeof(td));
|
793 |
le32_to_cpus(&td.link); |
794 |
le32_to_cpus(&td.ctrl); |
795 |
le32_to_cpus(&td.token); |
796 |
le32_to_cpus(&td.buffer); |
797 |
old_td_ctrl = td.ctrl; |
798 |
ret = uhci_handle_td(s, &td, &int_mask, 0);
|
799 |
|
800 |
/* update the status bits of the TD */
|
801 |
if (old_td_ctrl != td.ctrl) {
|
802 |
val = cpu_to_le32(td.ctrl); |
803 |
cpu_physical_memory_write((qh.el_link & ~0xf) + 4, |
804 |
(const uint8_t *)&val,
|
805 |
sizeof(val));
|
806 |
} |
807 |
if (ret < 0) |
808 |
break; /* interrupted frame */ |
809 |
if (ret == 2) { |
810 |
s->async_qh = link; |
811 |
} else if (ret == 0) { |
812 |
/* update qh element link */
|
813 |
qh.el_link = td.link; |
814 |
val = cpu_to_le32(qh.el_link); |
815 |
cpu_physical_memory_write((link & ~0xf) + 4, |
816 |
(const uint8_t *)&val,
|
817 |
sizeof(val));
|
818 |
if (qh.el_link & 4) { |
819 |
/* depth first */
|
820 |
goto depth_first;
|
821 |
} |
822 |
} |
823 |
/* go to next entry */
|
824 |
link = qh.link; |
825 |
} |
826 |
} else {
|
827 |
/* TD */
|
828 |
cpu_physical_memory_read(link & ~0xf, (uint8_t *)&td, sizeof(td)); |
829 |
le32_to_cpus(&td.link); |
830 |
le32_to_cpus(&td.ctrl); |
831 |
le32_to_cpus(&td.token); |
832 |
le32_to_cpus(&td.buffer); |
833 |
|
834 |
/* Handle isochonous transfer. */
|
835 |
/* FIXME: might be more than one isoc in frame */
|
836 |
old_td_ctrl = td.ctrl; |
837 |
ret = uhci_handle_td(s, &td, &int_mask, 0);
|
838 |
|
839 |
/* update the status bits of the TD */
|
840 |
if (old_td_ctrl != td.ctrl) {
|
841 |
val = cpu_to_le32(td.ctrl); |
842 |
cpu_physical_memory_write((link & ~0xf) + 4, |
843 |
(const uint8_t *)&val,
|
844 |
sizeof(val));
|
845 |
} |
846 |
if (ret < 0) |
847 |
break; /* interrupted frame */ |
848 |
if (ret == 2) { |
849 |
s->async_frame_addr = frame_addr; |
850 |
} |
851 |
link = td.link; |
852 |
} |
853 |
} |
854 |
s->pending_int_mask = int_mask; |
855 |
if (old_async_qh) {
|
856 |
/* A previously started transfer has disappeared from the transfer
|
857 |
list. There's nothing useful we can do with it now, so just
|
858 |
discard the packet and hope it wasn't too important. */
|
859 |
#ifdef DEBUG
|
860 |
printf("Discarding USB packet\n");
|
861 |
#endif
|
862 |
usb_cancel_packet(&s->usb_packet); |
863 |
s->async_qh = 0;
|
864 |
} |
865 |
|
866 |
/* prepare the timer for the next frame */
|
867 |
expire_time = qemu_get_clock(vm_clock) + |
868 |
(ticks_per_sec / FRAME_TIMER_FREQ); |
869 |
qemu_mod_timer(s->frame_timer, expire_time); |
870 |
} |
871 |
|
872 |
static void uhci_map(PCIDevice *pci_dev, int region_num, |
873 |
uint32_t addr, uint32_t size, int type)
|
874 |
{ |
875 |
UHCIState *s = (UHCIState *)pci_dev; |
876 |
|
877 |
register_ioport_write(addr, 32, 2, uhci_ioport_writew, s); |
878 |
register_ioport_read(addr, 32, 2, uhci_ioport_readw, s); |
879 |
register_ioport_write(addr, 32, 4, uhci_ioport_writel, s); |
880 |
register_ioport_read(addr, 32, 4, uhci_ioport_readl, s); |
881 |
register_ioport_write(addr, 32, 1, uhci_ioport_writeb, s); |
882 |
register_ioport_read(addr, 32, 1, uhci_ioport_readb, s); |
883 |
} |
884 |
|
885 |
void usb_uhci_piix3_init(PCIBus *bus, int devfn) |
886 |
{ |
887 |
UHCIState *s; |
888 |
uint8_t *pci_conf; |
889 |
int i;
|
890 |
|
891 |
s = (UHCIState *)pci_register_device(bus, |
892 |
"USB-UHCI", sizeof(UHCIState), |
893 |
devfn, NULL, NULL); |
894 |
pci_conf = s->dev.config; |
895 |
pci_conf[0x00] = 0x86; |
896 |
pci_conf[0x01] = 0x80; |
897 |
pci_conf[0x02] = 0x20; |
898 |
pci_conf[0x03] = 0x70; |
899 |
pci_conf[0x08] = 0x01; // revision number |
900 |
pci_conf[0x09] = 0x00; |
901 |
pci_conf[0x0a] = 0x03; |
902 |
pci_conf[0x0b] = 0x0c; |
903 |
pci_conf[0x0e] = 0x00; // header_type |
904 |
pci_conf[0x3d] = 4; // interrupt pin 3 |
905 |
pci_conf[0x60] = 0x10; // release number |
906 |
|
907 |
for(i = 0; i < NB_PORTS; i++) { |
908 |
qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
909 |
} |
910 |
s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
911 |
|
912 |
uhci_reset(s); |
913 |
|
914 |
/* Use region 4 for consistency with real hardware. BSD guests seem
|
915 |
to rely on this. */
|
916 |
pci_register_io_region(&s->dev, 4, 0x20, |
917 |
PCI_ADDRESS_SPACE_IO, uhci_map); |
918 |
} |
919 |
|
920 |
void usb_uhci_piix4_init(PCIBus *bus, int devfn) |
921 |
{ |
922 |
UHCIState *s; |
923 |
uint8_t *pci_conf; |
924 |
int i;
|
925 |
|
926 |
s = (UHCIState *)pci_register_device(bus, |
927 |
"USB-UHCI", sizeof(UHCIState), |
928 |
devfn, NULL, NULL); |
929 |
pci_conf = s->dev.config; |
930 |
pci_conf[0x00] = 0x86; |
931 |
pci_conf[0x01] = 0x80; |
932 |
pci_conf[0x02] = 0x12; |
933 |
pci_conf[0x03] = 0x71; |
934 |
pci_conf[0x08] = 0x01; // revision number |
935 |
pci_conf[0x09] = 0x00; |
936 |
pci_conf[0x0a] = 0x03; |
937 |
pci_conf[0x0b] = 0x0c; |
938 |
pci_conf[0x0e] = 0x00; // header_type |
939 |
pci_conf[0x3d] = 4; // interrupt pin 3 |
940 |
pci_conf[0x60] = 0x10; // release number |
941 |
|
942 |
for(i = 0; i < NB_PORTS; i++) { |
943 |
qemu_register_usb_port(&s->ports[i].port, s, i, uhci_attach); |
944 |
} |
945 |
s->frame_timer = qemu_new_timer(vm_clock, uhci_frame_timer, s); |
946 |
|
947 |
uhci_reset(s); |
948 |
|
949 |
/* Use region 4 for consistency with real hardware. BSD guests seem
|
950 |
to rely on this. */
|
951 |
pci_register_io_region(&s->dev, 4, 0x20, |
952 |
PCI_ADDRESS_SPACE_IO, uhci_map); |
953 |
} |