Revision 91a5bb76
| b/target-xtensa/translate.c | ||
|---|---|---|
| 267 | 267 |
} \ |
| 268 | 268 |
} while (0) |
| 269 | 269 |
|
| 270 |
#define TBD() qemu_log("TBD(pc = %08x): %s:%d\n", dc->pc, __FILE__, __LINE__)
|
|
| 271 |
#define RESERVED() do { \
|
|
| 272 |
qemu_log("RESERVED(pc = %08x, %02x%02x%02x): %s:%d\n", \
|
|
| 273 |
dc->pc, b0, b1, b2, __FILE__, __LINE__); \ |
|
| 274 |
goto invalid_opcode; \ |
|
| 275 |
} while (0) |
|
| 276 |
|
|
| 277 |
|
|
| 270 | 278 |
#ifdef TARGET_WORDS_BIGENDIAN |
| 271 | 279 |
#define OP0 (((b0) & 0xf0) >> 4) |
| 272 | 280 |
#define OP1 (((b2) & 0xf0) >> 4) |
| ... | ... | |
| 367 | 375 |
case 0: /*SNM0*/ |
| 368 | 376 |
switch (CALLX_M) {
|
| 369 | 377 |
case 0: /*ILL*/ |
| 378 |
TBD(); |
|
| 370 | 379 |
break; |
| 371 | 380 |
|
| 372 | 381 |
case 1: /*reserved*/ |
| 382 |
RESERVED(); |
|
| 373 | 383 |
break; |
| 374 | 384 |
|
| 375 | 385 |
case 2: /*JR*/ |
| ... | ... | |
| 381 | 391 |
|
| 382 | 392 |
case 1: /*RETWw*/ |
| 383 | 393 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
| 394 |
TBD(); |
|
| 384 | 395 |
break; |
| 385 | 396 |
|
| 386 | 397 |
case 3: /*reserved*/ |
| 398 |
RESERVED(); |
|
| 387 | 399 |
break; |
| 388 | 400 |
} |
| 389 | 401 |
break; |
| ... | ... | |
| 404 | 416 |
case 2: /*CALLX8w*/ |
| 405 | 417 |
case 3: /*CALLX12w*/ |
| 406 | 418 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
| 419 |
TBD(); |
|
| 407 | 420 |
break; |
| 408 | 421 |
} |
| 409 | 422 |
break; |
| ... | ... | |
| 412 | 425 |
|
| 413 | 426 |
case 1: /*MOVSPw*/ |
| 414 | 427 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
| 428 |
TBD(); |
|
| 415 | 429 |
break; |
| 416 | 430 |
|
| 417 | 431 |
case 2: /*SYNC*/ |
| 432 |
TBD(); |
|
| 433 |
break; |
|
| 434 |
|
|
| 435 |
case 3: /*RFEIx*/ |
|
| 436 |
TBD(); |
|
| 437 |
break; |
|
| 438 |
|
|
| 439 |
case 4: /*BREAKx*/ |
|
| 440 |
HAS_OPTION(XTENSA_OPTION_EXCEPTION); |
|
| 441 |
TBD(); |
|
| 442 |
break; |
|
| 443 |
|
|
| 444 |
case 5: /*SYSCALLx*/ |
|
| 445 |
HAS_OPTION(XTENSA_OPTION_EXCEPTION); |
|
| 446 |
TBD(); |
|
| 447 |
break; |
|
| 448 |
|
|
| 449 |
case 6: /*RSILx*/ |
|
| 450 |
HAS_OPTION(XTENSA_OPTION_INTERRUPT); |
|
| 451 |
TBD(); |
|
| 452 |
break; |
|
| 453 |
|
|
| 454 |
case 7: /*WAITIx*/ |
|
| 455 |
HAS_OPTION(XTENSA_OPTION_INTERRUPT); |
|
| 456 |
TBD(); |
|
| 457 |
break; |
|
| 458 |
|
|
| 459 |
case 8: /*ANY4p*/ |
|
| 460 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
|
| 461 |
TBD(); |
|
| 462 |
break; |
|
| 463 |
|
|
| 464 |
case 9: /*ALL4p*/ |
|
| 465 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
|
| 466 |
TBD(); |
|
| 418 | 467 |
break; |
| 419 | 468 |
|
| 420 |
case 3: |
|
| 469 |
case 10: /*ANY8p*/ |
|
| 470 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
|
| 471 |
TBD(); |
|
| 472 |
break; |
|
| 473 |
|
|
| 474 |
case 11: /*ALL8p*/ |
|
| 475 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
|
| 476 |
TBD(); |
|
| 477 |
break; |
|
| 478 |
|
|
| 479 |
default: /*reserved*/ |
|
| 480 |
RESERVED(); |
|
| 421 | 481 |
break; |
| 422 | 482 |
|
| 423 | 483 |
} |
| ... | ... | |
| 473 | 533 |
break; |
| 474 | 534 |
|
| 475 | 535 |
case 6: /*RER*/ |
| 536 |
TBD(); |
|
| 476 | 537 |
break; |
| 477 | 538 |
|
| 478 | 539 |
case 7: /*WER*/ |
| 540 |
TBD(); |
|
| 479 | 541 |
break; |
| 480 | 542 |
|
| 481 | 543 |
case 8: /*ROTWw*/ |
| 482 | 544 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
| 545 |
TBD(); |
|
| 483 | 546 |
break; |
| 484 | 547 |
|
| 485 | 548 |
case 14: /*NSAu*/ |
| ... | ... | |
| 493 | 556 |
break; |
| 494 | 557 |
|
| 495 | 558 |
default: /*reserved*/ |
| 559 |
RESERVED(); |
|
| 496 | 560 |
break; |
| 497 | 561 |
} |
| 498 | 562 |
break; |
| 499 | 563 |
|
| 500 | 564 |
case 5: /*TLB*/ |
| 565 |
TBD(); |
|
| 501 | 566 |
break; |
| 502 | 567 |
|
| 503 | 568 |
case 6: /*RT0*/ |
| ... | ... | |
| 518 | 583 |
break; |
| 519 | 584 |
|
| 520 | 585 |
default: /*reserved*/ |
| 586 |
RESERVED(); |
|
| 521 | 587 |
break; |
| 522 | 588 |
} |
| 523 | 589 |
break; |
| 524 | 590 |
|
| 525 | 591 |
case 7: /*reserved*/ |
| 592 |
RESERVED(); |
|
| 526 | 593 |
break; |
| 527 | 594 |
|
| 528 | 595 |
case 8: /*ADD*/ |
| ... | ... | |
| 582 | 649 |
gen_rsr(dc, cpu_R[RRR_T], RSR_SR); |
| 583 | 650 |
gen_wsr(dc, RSR_SR, tmp); |
| 584 | 651 |
tcg_temp_free(tmp); |
| 652 |
if (!sregnames[RSR_SR]) {
|
|
| 653 |
TBD(); |
|
| 654 |
} |
|
| 585 | 655 |
} |
| 586 | 656 |
break; |
| 587 | 657 |
|
| ... | ... | |
| 671 | 741 |
break; |
| 672 | 742 |
|
| 673 | 743 |
default: /*reserved*/ |
| 744 |
RESERVED(); |
|
| 674 | 745 |
break; |
| 675 | 746 |
} |
| 676 | 747 |
break; |
| 677 | 748 |
|
| 678 | 749 |
case 2: /*RST2*/ |
| 750 |
TBD(); |
|
| 679 | 751 |
break; |
| 680 | 752 |
|
| 681 | 753 |
case 3: /*RST3*/ |
| 682 | 754 |
switch (OP2) {
|
| 683 | 755 |
case 0: /*RSR*/ |
| 684 | 756 |
gen_rsr(dc, cpu_R[RRR_T], RSR_SR); |
| 757 |
if (!sregnames[RSR_SR]) {
|
|
| 758 |
TBD(); |
|
| 759 |
} |
|
| 685 | 760 |
break; |
| 686 | 761 |
|
| 687 | 762 |
case 1: /*WSR*/ |
| 688 | 763 |
gen_wsr(dc, RSR_SR, cpu_R[RRR_T]); |
| 764 |
if (!sregnames[RSR_SR]) {
|
|
| 765 |
TBD(); |
|
| 766 |
} |
|
| 689 | 767 |
break; |
| 690 | 768 |
|
| 691 | 769 |
case 2: /*SEXTu*/ |
| ... | ... | |
| 778 | 856 |
|
| 779 | 857 |
case 12: /*MOVFp*/ |
| 780 | 858 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
| 859 |
TBD(); |
|
| 781 | 860 |
break; |
| 782 | 861 |
|
| 783 | 862 |
case 13: /*MOVTp*/ |
| 784 | 863 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
| 864 |
TBD(); |
|
| 785 | 865 |
break; |
| 786 | 866 |
|
| 787 | 867 |
case 14: /*RUR*/ |
| ... | ... | |
| 791 | 871 |
tcg_gen_mov_i32(cpu_R[RRR_R], cpu_UR[st]); |
| 792 | 872 |
} else {
|
| 793 | 873 |
qemu_log("RUR %d not implemented, ", st);
|
| 874 |
TBD(); |
|
| 794 | 875 |
} |
| 795 | 876 |
} |
| 796 | 877 |
break; |
| ... | ... | |
| 801 | 882 |
tcg_gen_mov_i32(cpu_UR[RSR_SR], cpu_R[RRR_T]); |
| 802 | 883 |
} else {
|
| 803 | 884 |
qemu_log("WUR %d not implemented, ", RSR_SR);
|
| 885 |
TBD(); |
|
| 804 | 886 |
} |
| 805 | 887 |
} |
| 806 | 888 |
break; |
| ... | ... | |
| 822 | 904 |
break; |
| 823 | 905 |
|
| 824 | 906 |
case 6: /*CUST0*/ |
| 907 |
RESERVED(); |
|
| 825 | 908 |
break; |
| 826 | 909 |
|
| 827 | 910 |
case 7: /*CUST1*/ |
| 911 |
RESERVED(); |
|
| 828 | 912 |
break; |
| 829 | 913 |
|
| 830 | 914 |
case 8: /*LSCXp*/ |
| 831 | 915 |
HAS_OPTION(XTENSA_OPTION_COPROCESSOR); |
| 916 |
TBD(); |
|
| 832 | 917 |
break; |
| 833 | 918 |
|
| 834 | 919 |
case 9: /*LSC4*/ |
| 920 |
TBD(); |
|
| 835 | 921 |
break; |
| 836 | 922 |
|
| 837 | 923 |
case 10: /*FP0*/ |
| 838 | 924 |
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); |
| 925 |
TBD(); |
|
| 839 | 926 |
break; |
| 840 | 927 |
|
| 841 | 928 |
case 11: /*FP1*/ |
| 842 | 929 |
HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR); |
| 930 |
TBD(); |
|
| 843 | 931 |
break; |
| 844 | 932 |
|
| 845 | 933 |
default: /*reserved*/ |
| 934 |
RESERVED(); |
|
| 846 | 935 |
break; |
| 847 | 936 |
} |
| 848 | 937 |
break; |
| ... | ... | |
| 894 | 983 |
break; |
| 895 | 984 |
|
| 896 | 985 |
case 7: /*CACHEc*/ |
| 986 |
TBD(); |
|
| 897 | 987 |
break; |
| 898 | 988 |
|
| 899 | 989 |
case 9: /*L16SI*/ |
| ... | ... | |
| 946 | 1036 |
break; |
| 947 | 1037 |
|
| 948 | 1038 |
default: /*reserved*/ |
| 1039 |
RESERVED(); |
|
| 949 | 1040 |
break; |
| 950 | 1041 |
} |
| 951 | 1042 |
break; |
| ... | ... | |
| 953 | 1044 |
|
| 954 | 1045 |
case 3: /*LSCIp*/ |
| 955 | 1046 |
HAS_OPTION(XTENSA_OPTION_COPROCESSOR); |
| 1047 |
TBD(); |
|
| 956 | 1048 |
break; |
| 957 | 1049 |
|
| 958 | 1050 |
case 4: /*MAC16d*/ |
| 959 | 1051 |
HAS_OPTION(XTENSA_OPTION_MAC16); |
| 1052 |
TBD(); |
|
| 960 | 1053 |
break; |
| 961 | 1054 |
|
| 962 | 1055 |
case 5: /*CALLN*/ |
| ... | ... | |
| 970 | 1063 |
case 2: /*CALL8w*/ |
| 971 | 1064 |
case 3: /*CALL12w*/ |
| 972 | 1065 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
| 1066 |
TBD(); |
|
| 973 | 1067 |
break; |
| 974 | 1068 |
} |
| 975 | 1069 |
break; |
| ... | ... | |
| 1012 | 1106 |
switch (BRI8_M) {
|
| 1013 | 1107 |
case 0: /*ENTRYw*/ |
| 1014 | 1108 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
| 1109 |
TBD(); |
|
| 1015 | 1110 |
break; |
| 1016 | 1111 |
|
| 1017 | 1112 |
case 1: /*B1*/ |
| 1018 | 1113 |
switch (BRI8_R) {
|
| 1019 | 1114 |
case 0: /*BFp*/ |
| 1020 | 1115 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
| 1116 |
TBD(); |
|
| 1021 | 1117 |
break; |
| 1022 | 1118 |
|
| 1023 | 1119 |
case 1: /*BTp*/ |
| 1024 | 1120 |
HAS_OPTION(XTENSA_OPTION_BOOLEAN); |
| 1121 |
TBD(); |
|
| 1025 | 1122 |
break; |
| 1026 | 1123 |
|
| 1027 | 1124 |
case 8: /*LOOP*/ |
| 1125 |
TBD(); |
|
| 1028 | 1126 |
break; |
| 1029 | 1127 |
|
| 1030 | 1128 |
case 9: /*LOOPNEZ*/ |
| 1129 |
TBD(); |
|
| 1031 | 1130 |
break; |
| 1032 | 1131 |
|
| 1033 | 1132 |
case 10: /*LOOPGTZ*/ |
| 1133 |
TBD(); |
|
| 1034 | 1134 |
break; |
| 1035 | 1135 |
|
| 1036 | 1136 |
default: /*reserved*/ |
| 1137 |
RESERVED(); |
|
| 1037 | 1138 |
break; |
| 1038 | 1139 |
|
| 1039 | 1140 |
} |
| ... | ... | |
| 1169 | 1270 |
break; |
| 1170 | 1271 |
|
| 1171 | 1272 |
case 1: /*RETW.Nn*/ |
| 1273 |
HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER); |
|
| 1274 |
TBD(); |
|
| 1172 | 1275 |
break; |
| 1173 | 1276 |
|
| 1174 | 1277 |
case 2: /*BREAK.Nn*/ |
| 1278 |
TBD(); |
|
| 1175 | 1279 |
break; |
| 1176 | 1280 |
|
| 1177 | 1281 |
case 3: /*NOP.Nn*/ |
| 1178 | 1282 |
break; |
| 1179 | 1283 |
|
| 1180 | 1284 |
case 6: /*ILL.Nn*/ |
| 1285 |
TBD(); |
|
| 1181 | 1286 |
break; |
| 1182 | 1287 |
|
| 1183 | 1288 |
default: /*reserved*/ |
| 1289 |
RESERVED(); |
|
| 1184 | 1290 |
break; |
| 1185 | 1291 |
} |
| 1186 | 1292 |
break; |
| 1187 | 1293 |
|
| 1188 | 1294 |
default: /*reserved*/ |
| 1295 |
RESERVED(); |
|
| 1189 | 1296 |
break; |
| 1190 | 1297 |
} |
| 1191 | 1298 |
break; |
| 1192 | 1299 |
|
| 1193 | 1300 |
default: /*reserved*/ |
| 1301 |
RESERVED(); |
|
| 1194 | 1302 |
break; |
| 1195 | 1303 |
} |
| 1196 | 1304 |
|
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