Revision 925fd0f2
| b/target-mips/helper.c | ||
|---|---|---|
| 41 | 41 |
static int map_address (CPUState *env, target_ulong *physical, int *prot, |
| 42 | 42 |
target_ulong address, int rw, int access_type) |
| 43 | 43 |
{
|
| 44 |
uint8_t ASID = env->CP0_EntryHi & 0xFF; |
|
| 44 | 45 |
int i; |
| 45 | 46 |
|
| 46 | 47 |
for (i = 0; i < env->tlb_in_use; i++) {
|
| 47 | 48 |
tlb_t *tlb = &env->tlb[i]; |
| 48 | 49 |
/* 1k pages are not supported. */ |
| 49 |
uint8_t ASID = env->CP0_EntryHi & 0xFF; |
|
| 50 | 50 |
target_ulong mask = tlb->PageMask | 0x1FFF; |
| 51 | 51 |
target_ulong tag = address & ~mask; |
| 52 | 52 |
int n; |
| b/target-mips/op.c | ||
|---|---|---|
| 1340 | 1340 |
|
| 1341 | 1341 |
/* 1k pages not implemented */ |
| 1342 | 1342 |
/* Ignore MIPS64 TLB for now */ |
| 1343 |
val = (int32_t)T0 & 0xFFFFE0FF;
|
|
| 1343 |
val = (target_ulong)(int32_t)T0 & ~(target_ulong)0x1F00;
|
|
| 1344 | 1344 |
old = env->CP0_EntryHi; |
| 1345 | 1345 |
env->CP0_EntryHi = val; |
| 1346 | 1346 |
/* If the ASID changes, flush qemu's TLB. */ |
| b/target-mips/op_helper.c | ||
|---|---|---|
| 395 | 395 |
|
| 396 | 396 |
/* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ |
| 397 | 397 |
tlb = &env->tlb[idx]; |
| 398 |
tlb->VPN = env->CP0_EntryHi & (int32_t)0xFFFFE000;
|
|
| 398 |
tlb->VPN = env->CP0_EntryHi & ~(target_ulong)0x1FFF;
|
|
| 399 | 399 |
tlb->ASID = env->CP0_EntryHi & 0xFF; |
| 400 | 400 |
tlb->PageMask = env->CP0_PageMask; |
| 401 | 401 |
tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; |
Also available in: Unified diff