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1 | 7d85892b | blueswir1 | /*
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2 | 7d85892b | blueswir1 | * QEMU Sparc SBI interrupt controller emulation
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3 | 7d85892b | blueswir1 | *
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4 | 7d85892b | blueswir1 | * Based on slavio_intctl, copyright (c) 2003-2005 Fabrice Bellard
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5 | 7d85892b | blueswir1 | *
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6 | 7d85892b | blueswir1 | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 7d85892b | blueswir1 | * of this software and associated documentation files (the "Software"), to deal
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8 | 7d85892b | blueswir1 | * in the Software without restriction, including without limitation the rights
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9 | 7d85892b | blueswir1 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 7d85892b | blueswir1 | * copies of the Software, and to permit persons to whom the Software is
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11 | 7d85892b | blueswir1 | * furnished to do so, subject to the following conditions:
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12 | 7d85892b | blueswir1 | *
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13 | 7d85892b | blueswir1 | * The above copyright notice and this permission notice shall be included in
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14 | 7d85892b | blueswir1 | * all copies or substantial portions of the Software.
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15 | 7d85892b | blueswir1 | *
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16 | 7d85892b | blueswir1 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 7d85892b | blueswir1 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 7d85892b | blueswir1 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 7d85892b | blueswir1 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 7d85892b | blueswir1 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 7d85892b | blueswir1 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 7d85892b | blueswir1 | * THE SOFTWARE.
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23 | 7d85892b | blueswir1 | */
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24 | 7d85892b | blueswir1 | #include "hw.h" |
25 | 7d85892b | blueswir1 | #include "sun4m.h" |
26 | 7d85892b | blueswir1 | #include "console.h" |
27 | 7d85892b | blueswir1 | |
28 | 7d85892b | blueswir1 | //#define DEBUG_IRQ
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29 | 7d85892b | blueswir1 | |
30 | 7d85892b | blueswir1 | #ifdef DEBUG_IRQ
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31 | 7d85892b | blueswir1 | #define DPRINTF(fmt, args...) \
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32 | 7d85892b | blueswir1 | do { printf("IRQ: " fmt , ##args); } while (0) |
33 | 7d85892b | blueswir1 | #else
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34 | 7d85892b | blueswir1 | #define DPRINTF(fmt, args...)
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35 | 7d85892b | blueswir1 | #endif
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36 | 7d85892b | blueswir1 | |
37 | 7d85892b | blueswir1 | #define MAX_CPUS 16 |
38 | 7d85892b | blueswir1 | |
39 | 7d85892b | blueswir1 | #define SBI_NREGS 16 |
40 | 7d85892b | blueswir1 | |
41 | 7d85892b | blueswir1 | typedef struct SBIState { |
42 | 7d85892b | blueswir1 | uint32_t regs[SBI_NREGS]; |
43 | 7d85892b | blueswir1 | uint32_t intreg_pending[MAX_CPUS]; |
44 | 7d85892b | blueswir1 | qemu_irq *cpu_irqs[MAX_CPUS]; |
45 | 7d85892b | blueswir1 | uint32_t pil_out[MAX_CPUS]; |
46 | 7d85892b | blueswir1 | } SBIState; |
47 | 7d85892b | blueswir1 | |
48 | 7d85892b | blueswir1 | #define SBI_SIZE (SBI_NREGS * 4) |
49 | 7d85892b | blueswir1 | #define SBI_MASK (SBI_SIZE - 1) |
50 | 7d85892b | blueswir1 | |
51 | 7d85892b | blueswir1 | static void sbi_check_interrupts(void *opaque) |
52 | 7d85892b | blueswir1 | { |
53 | 7d85892b | blueswir1 | } |
54 | 7d85892b | blueswir1 | |
55 | 7d85892b | blueswir1 | static void sbi_set_irq(void *opaque, int irq, int level) |
56 | 7d85892b | blueswir1 | { |
57 | 7d85892b | blueswir1 | } |
58 | 7d85892b | blueswir1 | |
59 | 7d85892b | blueswir1 | static void sbi_set_timer_irq_cpu(void *opaque, int cpu, int level) |
60 | 7d85892b | blueswir1 | { |
61 | 7d85892b | blueswir1 | } |
62 | 7d85892b | blueswir1 | |
63 | 7d85892b | blueswir1 | static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) |
64 | 7d85892b | blueswir1 | { |
65 | 7d85892b | blueswir1 | SBIState *s = opaque; |
66 | 7d85892b | blueswir1 | uint32_t saddr, ret; |
67 | 7d85892b | blueswir1 | |
68 | 7d85892b | blueswir1 | saddr = (addr & SBI_MASK) >> 2;
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69 | 7d85892b | blueswir1 | switch (saddr) {
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70 | 7d85892b | blueswir1 | default:
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71 | 7d85892b | blueswir1 | ret = s->regs[saddr]; |
72 | 7d85892b | blueswir1 | break;
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73 | 7d85892b | blueswir1 | } |
74 | 7d85892b | blueswir1 | DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret); |
75 | 7d85892b | blueswir1 | |
76 | 7d85892b | blueswir1 | return ret;
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77 | 7d85892b | blueswir1 | } |
78 | 7d85892b | blueswir1 | |
79 | 7d85892b | blueswir1 | static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
80 | 7d85892b | blueswir1 | { |
81 | 7d85892b | blueswir1 | SBIState *s = opaque; |
82 | 7d85892b | blueswir1 | uint32_t saddr; |
83 | 7d85892b | blueswir1 | |
84 | 7d85892b | blueswir1 | saddr = (addr & SBI_MASK) >> 2;
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85 | 7d85892b | blueswir1 | DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); |
86 | 7d85892b | blueswir1 | switch (saddr) {
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87 | 7d85892b | blueswir1 | default:
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88 | 7d85892b | blueswir1 | s->regs[saddr] = val; |
89 | 7d85892b | blueswir1 | break;
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90 | 7d85892b | blueswir1 | } |
91 | 7d85892b | blueswir1 | } |
92 | 7d85892b | blueswir1 | |
93 | 7d85892b | blueswir1 | static CPUReadMemoryFunc *sbi_mem_read[3] = { |
94 | 7c560456 | blueswir1 | NULL,
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95 | 7c560456 | blueswir1 | NULL,
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96 | 7d85892b | blueswir1 | sbi_mem_readl, |
97 | 7d85892b | blueswir1 | }; |
98 | 7d85892b | blueswir1 | |
99 | 7d85892b | blueswir1 | static CPUWriteMemoryFunc *sbi_mem_write[3] = { |
100 | 7c560456 | blueswir1 | NULL,
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101 | 7c560456 | blueswir1 | NULL,
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102 | 7d85892b | blueswir1 | sbi_mem_writel, |
103 | 7d85892b | blueswir1 | }; |
104 | 7d85892b | blueswir1 | |
105 | 7d85892b | blueswir1 | static void sbi_save(QEMUFile *f, void *opaque) |
106 | 7d85892b | blueswir1 | { |
107 | 7d85892b | blueswir1 | SBIState *s = opaque; |
108 | 7d85892b | blueswir1 | unsigned int i; |
109 | 7d85892b | blueswir1 | |
110 | 7d85892b | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
111 | 7d85892b | blueswir1 | qemu_put_be32s(f, &s->intreg_pending[i]); |
112 | 7d85892b | blueswir1 | } |
113 | 7d85892b | blueswir1 | } |
114 | 7d85892b | blueswir1 | |
115 | 7d85892b | blueswir1 | static int sbi_load(QEMUFile *f, void *opaque, int version_id) |
116 | 7d85892b | blueswir1 | { |
117 | 7d85892b | blueswir1 | SBIState *s = opaque; |
118 | 7d85892b | blueswir1 | unsigned int i; |
119 | 7d85892b | blueswir1 | |
120 | 7d85892b | blueswir1 | if (version_id != 1) |
121 | 7d85892b | blueswir1 | return -EINVAL;
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122 | 7d85892b | blueswir1 | |
123 | 7d85892b | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
124 | 7d85892b | blueswir1 | qemu_get_be32s(f, &s->intreg_pending[i]); |
125 | 7d85892b | blueswir1 | } |
126 | 7d85892b | blueswir1 | sbi_check_interrupts(s); |
127 | 7d85892b | blueswir1 | |
128 | 7d85892b | blueswir1 | return 0; |
129 | 7d85892b | blueswir1 | } |
130 | 7d85892b | blueswir1 | |
131 | 7d85892b | blueswir1 | static void sbi_reset(void *opaque) |
132 | 7d85892b | blueswir1 | { |
133 | 7d85892b | blueswir1 | SBIState *s = opaque; |
134 | 7d85892b | blueswir1 | unsigned int i; |
135 | 7d85892b | blueswir1 | |
136 | 7d85892b | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
137 | 7d85892b | blueswir1 | s->intreg_pending[i] = 0;
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138 | 7d85892b | blueswir1 | } |
139 | 7d85892b | blueswir1 | sbi_check_interrupts(s); |
140 | 7d85892b | blueswir1 | } |
141 | 7d85892b | blueswir1 | |
142 | 7d85892b | blueswir1 | void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
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143 | 7d85892b | blueswir1 | qemu_irq **parent_irq) |
144 | 7d85892b | blueswir1 | { |
145 | 7d85892b | blueswir1 | unsigned int i; |
146 | 7d85892b | blueswir1 | int sbi_io_memory;
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147 | 7d85892b | blueswir1 | SBIState *s; |
148 | 7d85892b | blueswir1 | |
149 | 7d85892b | blueswir1 | s = qemu_mallocz(sizeof(SBIState));
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150 | 7d85892b | blueswir1 | if (!s)
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151 | 7d85892b | blueswir1 | return NULL; |
152 | 7d85892b | blueswir1 | |
153 | 7d85892b | blueswir1 | for (i = 0; i < MAX_CPUS; i++) { |
154 | 7d85892b | blueswir1 | s->cpu_irqs[i] = parent_irq[i]; |
155 | 7d85892b | blueswir1 | } |
156 | 7d85892b | blueswir1 | |
157 | 7d85892b | blueswir1 | sbi_io_memory = cpu_register_io_memory(0, sbi_mem_read, sbi_mem_write, s);
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158 | 7d85892b | blueswir1 | cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory); |
159 | 7d85892b | blueswir1 | |
160 | 7d85892b | blueswir1 | register_savevm("sbi", addr, 1, sbi_save, sbi_load, s); |
161 | 7d85892b | blueswir1 | qemu_register_reset(sbi_reset, s); |
162 | 7d85892b | blueswir1 | *irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
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163 | 7d85892b | blueswir1 | *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS); |
164 | 7d85892b | blueswir1 | sbi_reset(s); |
165 | 7d85892b | blueswir1 | |
166 | 7d85892b | blueswir1 | return s;
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167 | 7d85892b | blueswir1 | } |