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1 | aa0aa4fa | bellard | /* Instruction printing code for the ARM
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2 | 4b0f1a8b | pbrook | Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
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3 | 4b0f1a8b | pbrook | 2007, Free Software Foundation, Inc.
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4 | aa0aa4fa | bellard | Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org)
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5 | aa0aa4fa | bellard | Modification by James G. Smith (jsmith@cygnus.co.uk)
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6 | aa0aa4fa | bellard | |
7 | 4b0f1a8b | pbrook | This file is part of libopcodes.
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8 | aa0aa4fa | bellard | |
9 | 4b0f1a8b | pbrook | This program is free software; you can redistribute it and/or modify it under
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10 | 4b0f1a8b | pbrook | the terms of the GNU General Public License as published by the Free
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11 | 4b0f1a8b | pbrook | Software Foundation; either version 2 of the License, or (at your option)
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12 | 4b0f1a8b | pbrook | any later version.
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13 | aa0aa4fa | bellard | |
14 | 4b0f1a8b | pbrook | This program is distributed in the hope that it will be useful, but WITHOUT
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15 | 4b0f1a8b | pbrook | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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16 | 4b0f1a8b | pbrook | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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17 | 4b0f1a8b | pbrook | more details.
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18 | aa0aa4fa | bellard | |
19 | 4b0f1a8b | pbrook | You should have received a copy of the GNU General Public License
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20 | 4b0f1a8b | pbrook | along with this program; if not, write to the Free Software
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21 | 4b0f1a8b | pbrook | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
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22 | 4b0f1a8b | pbrook | |
23 | 4b0f1a8b | pbrook | /* Start of qemu specific additions. Mostly this is stub definitions
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24 | 4b0f1a8b | pbrook | for things we don't care about. */
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25 | aa0aa4fa | bellard | |
26 | aa0aa4fa | bellard | #include "dis-asm.h" |
27 | 4b0f1a8b | pbrook | #define FALSE 0 |
28 | 4b0f1a8b | pbrook | #define TRUE (!FALSE)
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29 | 4b0f1a8b | pbrook | #define ATTRIBUTE_UNUSED __attribute__((unused))
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30 | 4b0f1a8b | pbrook | #define ISSPACE(x) ((x) == ' ' || (x) == '\t' || (x) == '\n') |
31 | 4b0f1a8b | pbrook | |
32 | 4b0f1a8b | pbrook | #define ARM_EXT_V1 0 |
33 | 4b0f1a8b | pbrook | #define ARM_EXT_V2 0 |
34 | 4b0f1a8b | pbrook | #define ARM_EXT_V2S 0 |
35 | 4b0f1a8b | pbrook | #define ARM_EXT_V3 0 |
36 | 4b0f1a8b | pbrook | #define ARM_EXT_V3M 0 |
37 | 4b0f1a8b | pbrook | #define ARM_EXT_V4 0 |
38 | 4b0f1a8b | pbrook | #define ARM_EXT_V4T 0 |
39 | 4b0f1a8b | pbrook | #define ARM_EXT_V5 0 |
40 | 4b0f1a8b | pbrook | #define ARM_EXT_V5T 0 |
41 | 4b0f1a8b | pbrook | #define ARM_EXT_V5ExP 0 |
42 | 4b0f1a8b | pbrook | #define ARM_EXT_V5E 0 |
43 | 4b0f1a8b | pbrook | #define ARM_EXT_V5J 0 |
44 | 4b0f1a8b | pbrook | #define ARM_EXT_V6 0 |
45 | 4b0f1a8b | pbrook | #define ARM_EXT_V6K 0 |
46 | 4b0f1a8b | pbrook | #define ARM_EXT_V6Z 0 |
47 | 4b0f1a8b | pbrook | #define ARM_EXT_V6T2 0 |
48 | 4b0f1a8b | pbrook | #define ARM_EXT_V7 0 |
49 | 4b0f1a8b | pbrook | #define ARM_EXT_DIV 0 |
50 | 4b0f1a8b | pbrook | |
51 | 4b0f1a8b | pbrook | /* Co-processor space extensions. */
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52 | 4b0f1a8b | pbrook | #define ARM_CEXT_XSCALE 0 |
53 | 4b0f1a8b | pbrook | #define ARM_CEXT_MAVERICK 0 |
54 | 4b0f1a8b | pbrook | #define ARM_CEXT_IWMMXT 0 |
55 | 4b0f1a8b | pbrook | |
56 | 4b0f1a8b | pbrook | #define FPU_FPA_EXT_V1 0 |
57 | 4b0f1a8b | pbrook | #define FPU_FPA_EXT_V2 0 |
58 | 4b0f1a8b | pbrook | #define FPU_VFP_EXT_NONE 0 |
59 | 4b0f1a8b | pbrook | #define FPU_VFP_EXT_V1xD 0 |
60 | 4b0f1a8b | pbrook | #define FPU_VFP_EXT_V1 0 |
61 | 4b0f1a8b | pbrook | #define FPU_VFP_EXT_V2 0 |
62 | 4b0f1a8b | pbrook | #define FPU_MAVERICK 0 |
63 | 4b0f1a8b | pbrook | #define FPU_VFP_EXT_V3 0 |
64 | 4b0f1a8b | pbrook | #define FPU_NEON_EXT_V1 0 |
65 | 4b0f1a8b | pbrook | |
66 | 4b0f1a8b | pbrook | int floatformat_ieee_single_little;
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67 | 4b0f1a8b | pbrook | /* Assume host uses ieee float. */
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68 | 4b0f1a8b | pbrook | static void floatformat_to_double (int *ignored, unsigned char *data, |
69 | 4b0f1a8b | pbrook | double *dest)
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70 | 4b0f1a8b | pbrook | { |
71 | 4b0f1a8b | pbrook | union {
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72 | 4b0f1a8b | pbrook | uint32_t i; |
73 | 4b0f1a8b | pbrook | float f;
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74 | 4b0f1a8b | pbrook | } u; |
75 | 4b0f1a8b | pbrook | u.i = data[0] | (data[1] << 8) | (data[2] << 16) | (data[3] << 24); |
76 | 4b0f1a8b | pbrook | *dest = u.f; |
77 | 4b0f1a8b | pbrook | } |
78 | 4b0f1a8b | pbrook | |
79 | 4b0f1a8b | pbrook | /* End of qemu specific additions. */
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80 | 4b0f1a8b | pbrook | |
81 | 4b0f1a8b | pbrook | /* FIXME: Belongs in global header. */
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82 | 4b0f1a8b | pbrook | #ifndef strneq
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83 | 4b0f1a8b | pbrook | #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0) |
84 | 4b0f1a8b | pbrook | #endif
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85 | aa0aa4fa | bellard | |
86 | 4b0f1a8b | pbrook | #ifndef NUM_ELEM
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87 | 4b0f1a8b | pbrook | #define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0]) |
88 | 4b0f1a8b | pbrook | #endif
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89 | 4b0f1a8b | pbrook | |
90 | 4b0f1a8b | pbrook | struct opcode32
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91 | 4b0f1a8b | pbrook | { |
92 | 4b0f1a8b | pbrook | unsigned long arch; /* Architecture defining this insn. */ |
93 | 4b0f1a8b | pbrook | unsigned long value, mask; /* Recognise insn if (op&mask)==value. */ |
94 | 4b0f1a8b | pbrook | const char *assembler; /* How to disassemble this insn. */ |
95 | aa0aa4fa | bellard | }; |
96 | aa0aa4fa | bellard | |
97 | 4b0f1a8b | pbrook | struct opcode16
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98 | aa0aa4fa | bellard | { |
99 | 4b0f1a8b | pbrook | unsigned long arch; /* Architecture defining this insn. */ |
100 | 4b0f1a8b | pbrook | unsigned short value, mask; /* Recognise insn if (op&mask)==value. */ |
101 | 4b0f1a8b | pbrook | const char *assembler; /* How to disassemble this insn. */ |
102 | aa0aa4fa | bellard | }; |
103 | aa0aa4fa | bellard | |
104 | 4b0f1a8b | pbrook | /* print_insn_coprocessor recognizes the following format control codes:
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105 | 3b46e624 | ths | |
106 | aa0aa4fa | bellard | %% %
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107 | 4b0f1a8b | pbrook | |
108 | 4b0f1a8b | pbrook | %c print condition code (always bits 28-31 in ARM mode)
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109 | 4b0f1a8b | pbrook | %q print shifter argument
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110 | 4b0f1a8b | pbrook | %u print condition code (unconditional in ARM mode)
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111 | 4b0f1a8b | pbrook | %A print address for ldc/stc/ldf/stf instruction
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112 | 4b0f1a8b | pbrook | %B print vstm/vldm register list
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113 | 4b0f1a8b | pbrook | %C print vstr/vldr address operand
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114 | 4b0f1a8b | pbrook | %I print cirrus signed shift immediate: bits 0..3|4..6
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115 | 4b0f1a8b | pbrook | %F print the COUNT field of a LFM/SFM instruction.
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116 | 4b0f1a8b | pbrook | %P print floating point precision in arithmetic insn
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117 | 4b0f1a8b | pbrook | %Q print floating point precision in ldf/stf insn
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118 | 4b0f1a8b | pbrook | %R print floating point rounding mode
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119 | 4b0f1a8b | pbrook | |
120 | 4b0f1a8b | pbrook | %<bitfield>r print as an ARM register
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121 | aa0aa4fa | bellard | %<bitfield>d print the bitfield in decimal
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122 | 4b0f1a8b | pbrook | %<bitfield>k print immediate for VFPv3 conversion instruction
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123 | aa0aa4fa | bellard | %<bitfield>x print the bitfield in hex
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124 | aa0aa4fa | bellard | %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
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125 | aa0aa4fa | bellard | %<bitfield>f print a floating point constant if >7 else a
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126 | aa0aa4fa | bellard | floating point register
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127 | 4b0f1a8b | pbrook | %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us
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128 | 4b0f1a8b | pbrook | %<bitfield>g print as an iWMMXt 64-bit register
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129 | 4b0f1a8b | pbrook | %<bitfield>G print as an iWMMXt general purpose or control register
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130 | 4b0f1a8b | pbrook | %<bitfield>D print as a NEON D register
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131 | 4b0f1a8b | pbrook | %<bitfield>Q print as a NEON Q register
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132 | 4b0f1a8b | pbrook | |
133 | 4b0f1a8b | pbrook | %y<code> print a single precision VFP reg.
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134 | aa0aa4fa | bellard | Codes: 0=>Sm, 1=>Sd, 2=>Sn, 3=>multi-list, 4=>Sm pair
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135 | 4b0f1a8b | pbrook | %z<code> print a double precision VFP reg
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136 | aa0aa4fa | bellard | Codes: 0=>Dm, 1=>Dd, 2=>Dn, 3=>multi-list
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137 | 4b0f1a8b | pbrook | |
138 | 4b0f1a8b | pbrook | %<bitfield>'c print specified char iff bitfield is all ones
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139 | 4b0f1a8b | pbrook | %<bitfield>`c print specified char iff bitfield is all zeroes
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140 | 4b0f1a8b | pbrook | %<bitfield>?ab... select from array of values in big endian order
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141 | 4b0f1a8b | pbrook | |
142 | 4b0f1a8b | pbrook | %L print as an iWMMXt N/M width field.
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143 | 4b0f1a8b | pbrook | %Z print the Immediate of a WSHUFH instruction.
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144 | 4b0f1a8b | pbrook | %l like 'A' except use byte offsets for 'B' & 'H'
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145 | 4b0f1a8b | pbrook | versions.
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146 | 4b0f1a8b | pbrook | %i print 5-bit immediate in bits 8,3..0
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147 | 4b0f1a8b | pbrook | (print "32" when 0)
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148 | 4b0f1a8b | pbrook | %r print register offset address for wldt/wstr instruction
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149 | 4b0f1a8b | pbrook | */
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150 | 4b0f1a8b | pbrook | |
151 | 4b0f1a8b | pbrook | /* Common coprocessor opcodes shared between Arm and Thumb-2. */
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152 | 4b0f1a8b | pbrook | |
153 | 4b0f1a8b | pbrook | static const struct opcode32 coprocessor_opcodes[] = |
154 | 4b0f1a8b | pbrook | { |
155 | 4b0f1a8b | pbrook | /* XScale instructions. */
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156 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0ff0, "mia%c\tacc0, %0-3r, %12-15r"}, |
157 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0ff0, "miaph%c\tacc0, %0-3r, %12-15r"}, |
158 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0ff0, "mia%17'T%17`B%16'T%16`B%c\tacc0, %0-3r, %12-15r"}, |
159 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00fff, "mar%c\tacc0, %12-15r, %16-19r"}, |
160 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, |
161 | 4b0f1a8b | pbrook | |
162 | 4b0f1a8b | pbrook | /* Intel Wireless MMX technology instructions. */
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163 | 4b0f1a8b | pbrook | #define FIRST_IWMMXT_INSN 0x0e130130 |
164 | 4b0f1a8b | pbrook | #define IWMMXT_INSN_COUNT 73 |
165 | 4b0f1a8b | pbrook | {ARM_CEXT_IWMMXT, 0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, |
166 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, |
167 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, |
168 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, |
169 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, |
170 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, |
171 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, |
172 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, |
173 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, |
174 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, |
175 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, |
176 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, |
177 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, |
178 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, |
179 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e130190, 0x0f3f0fff, "torvsc%22-23w%c\t%12-15r"}, |
180 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e2001c0, 0x0f300fff, "wabs%22-23w%c\t%12-15g, %16-19g"}, |
181 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, |
182 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, |
183 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e2001a0, 0x0f300ff0, "waddbhus%22?ml%c\t%12-15g, %16-19g, %0-3g"}, |
184 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0ea001a0, 0x0ff00ff0, "waddsubhx%c\t%12-15g, %16-19g, %0-3g"}, |
185 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, |
186 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, |
187 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, |
188 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, |
189 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e400000, 0x0fe00ff0, "wavg4%20'r%c\t%12-15g, %16-19g, %0-3g"}, |
190 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
191 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
192 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0xfc500100, 0xfe500f00, "wldrd\t%12-15g, %r"}, |
193 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, |
194 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, |
195 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, |
196 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e800100, 0x0fc00ff0, "wmadd%21?su%20'x%c\t%12-15g, %16-19g, %0-3g"}, |
197 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0ec00100, 0x0fd00ff0, "wmadd%21?sun%c\t%12-15g, %16-19g, %0-3g"}, |
198 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
199 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000080, 0x0f100fe0, "wmerge%c\t%12-15g, %16-19g, %0-3g, #%21-23d"}, |
200 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e0000a0, 0x0f800ff0, "wmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, |
201 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e800120, 0x0f800ff0, "wmiaw%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, |
202 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
203 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%23'r%c\t%12-15g, %16-19g, %0-3g"}, |
204 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0ed00100, 0x0fd00ff0, "wmul%21?sumr%c\t%12-15g, %16-19g, %0-3g"}, |
205 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0ee000c0, 0x0fe00ff0, "wmulwsm%20`r%c\t%12-15g, %16-19g, %0-3g"}, |
206 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0ec000c0, 0x0fe00ff0, "wmulwum%20`r%c\t%12-15g, %16-19g, %0-3g"}, |
207 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0eb000c0, 0x0ff00ff0, "wmulwl%c\t%12-15g, %16-19g, %0-3g"}, |
208 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e8000a0, 0x0f800ff0, "wqmia%21?tb%20?tb%22'n%c\t%12-15g, %16-19g, %0-3g"}, |
209 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e100080, 0x0fd00ff0, "wqmulm%21'r%c\t%12-15g, %16-19g, %0-3g"}, |
210 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0ec000e0, 0x0fd00ff0, "wqmulwm%21'r%c\t%12-15g, %16-19g, %0-3g"}, |
211 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, |
212 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, |
213 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0xfe300040, 0xff300ef0, "wror%22-23w\t%12-15g, %16-19g, #%i"}, |
214 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e300040, 0x0f300ff0, "wror%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
215 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e300140, 0x0f300ff0, "wror%22-23wg%c\t%12-15g, %16-19g, %0-3G"}, |
216 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, |
217 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, |
218 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0xfe100040, 0xff300ef0, "wsll%22-23w\t%12-15g, %16-19g, #%i"}, |
219 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, |
220 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, |
221 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0xfe000040, 0xff300ef0, "wsra%22-23w\t%12-15g, %16-19g, #%i"}, |
222 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, |
223 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, |
224 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0xfe200040, 0xff300ef0, "wsrl%22-23w\t%12-15g, %16-19g, #%i"}, |
225 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, |
226 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, |
227 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0xfc400100, 0xfe500f00, "wstrd\t%12-15g, %r"}, |
228 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, |
229 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, |
230 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, |
231 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0ed001c0, 0x0ff00ff0, "wsubaddhx%c\t%12-15g, %16-19g, %0-3g"}, |
232 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e1001c0, 0x0f300ff0, "wabsdiff%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
233 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e0000c0, 0x0fd00fff, "wunpckeh%21?sub%c\t%12-15g, %16-19g"}, |
234 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e4000c0, 0x0fd00fff, "wunpckeh%21?suh%c\t%12-15g, %16-19g"}, |
235 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e8000c0, 0x0fd00fff, "wunpckeh%21?suw%c\t%12-15g, %16-19g"}, |
236 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, |
237 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
238 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, |
239 | 4b0f1a8b | pbrook | {ARM_CEXT_XSCALE, 0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, |
240 | 4b0f1a8b | pbrook | |
241 | 4b0f1a8b | pbrook | /* Floating point coprocessor (FPA) instructions */
|
242 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e000100, 0x0ff08f10, "adf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
243 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e100100, 0x0ff08f10, "muf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
244 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e200100, 0x0ff08f10, "suf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
245 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e300100, 0x0ff08f10, "rsf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
246 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e400100, 0x0ff08f10, "dvf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
247 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e500100, 0x0ff08f10, "rdf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
248 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e600100, 0x0ff08f10, "pow%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
249 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e700100, 0x0ff08f10, "rpw%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
250 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e800100, 0x0ff08f10, "rmf%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
251 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e900100, 0x0ff08f10, "fml%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
252 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0ea00100, 0x0ff08f10, "fdv%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
253 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0eb00100, 0x0ff08f10, "frd%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
254 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0ec00100, 0x0ff08f10, "pol%c%P%R\t%12-14f, %16-18f, %0-3f"}, |
255 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e008100, 0x0ff08f10, "mvf%c%P%R\t%12-14f, %0-3f"}, |
256 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e108100, 0x0ff08f10, "mnf%c%P%R\t%12-14f, %0-3f"}, |
257 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e208100, 0x0ff08f10, "abs%c%P%R\t%12-14f, %0-3f"}, |
258 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e308100, 0x0ff08f10, "rnd%c%P%R\t%12-14f, %0-3f"}, |
259 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e408100, 0x0ff08f10, "sqt%c%P%R\t%12-14f, %0-3f"}, |
260 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e508100, 0x0ff08f10, "log%c%P%R\t%12-14f, %0-3f"}, |
261 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e608100, 0x0ff08f10, "lgn%c%P%R\t%12-14f, %0-3f"}, |
262 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e708100, 0x0ff08f10, "exp%c%P%R\t%12-14f, %0-3f"}, |
263 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e808100, 0x0ff08f10, "sin%c%P%R\t%12-14f, %0-3f"}, |
264 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e908100, 0x0ff08f10, "cos%c%P%R\t%12-14f, %0-3f"}, |
265 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0ea08100, 0x0ff08f10, "tan%c%P%R\t%12-14f, %0-3f"}, |
266 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0eb08100, 0x0ff08f10, "asn%c%P%R\t%12-14f, %0-3f"}, |
267 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0ec08100, 0x0ff08f10, "acs%c%P%R\t%12-14f, %0-3f"}, |
268 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0ed08100, 0x0ff08f10, "atn%c%P%R\t%12-14f, %0-3f"}, |
269 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0ee08100, 0x0ff08f10, "urd%c%P%R\t%12-14f, %0-3f"}, |
270 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0ef08100, 0x0ff08f10, "nrm%c%P%R\t%12-14f, %0-3f"}, |
271 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e000110, 0x0ff00f1f, "flt%c%P%R\t%16-18f, %12-15r"}, |
272 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e100110, 0x0fff0f98, "fix%c%R\t%12-15r, %0-2f"}, |
273 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e200110, 0x0fff0fff, "wfs%c\t%12-15r"}, |
274 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e300110, 0x0fff0fff, "rfs%c\t%12-15r"}, |
275 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e400110, 0x0fff0fff, "wfc%c\t%12-15r"}, |
276 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e500110, 0x0fff0fff, "rfc%c\t%12-15r"}, |
277 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0e90f110, 0x0ff8fff0, "cmf%c\t%16-18f, %0-3f"}, |
278 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0eb0f110, 0x0ff8fff0, "cnf%c\t%16-18f, %0-3f"}, |
279 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0ed0f110, 0x0ff8fff0, "cmfe%c\t%16-18f, %0-3f"}, |
280 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0ef0f110, 0x0ff8fff0, "cnfe%c\t%16-18f, %0-3f"}, |
281 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0c000100, 0x0e100f00, "stf%c%Q\t%12-14f, %A"}, |
282 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V1, 0x0c100100, 0x0e100f00, "ldf%c%Q\t%12-14f, %A"}, |
283 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V2, 0x0c000200, 0x0e100f00, "sfm%c\t%12-14f, %F, %A"}, |
284 | 4b0f1a8b | pbrook | {FPU_FPA_EXT_V2, 0x0c100200, 0x0e100f00, "lfm%c\t%12-14f, %F, %A"}, |
285 | 4b0f1a8b | pbrook | |
286 | 4b0f1a8b | pbrook | /* Register load/store */
|
287 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0d200b00, 0x0fb00f01, "vstmdb%c\t%16-19r%21'!, %B"}, |
288 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0d300b00, 0x0fb00f01, "vldmdb%c\t%16-19r%21'!, %B"}, |
289 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0c800b00, 0x0f900f01, "vstmia%c\t%16-19r%21'!, %B"}, |
290 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0c900b00, 0x0f900f01, "vldmia%c\t%16-19r%21'!, %B"}, |
291 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0d000b00, 0x0f300f00, "vstr%c\t%12-15,22D, %C"}, |
292 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0d100b00, 0x0f300f00, "vldr%c\t%12-15,22D, %C"}, |
293 | 4b0f1a8b | pbrook | |
294 | 4b0f1a8b | pbrook | /* Data transfer between ARM and NEON registers */
|
295 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, |
296 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, |
297 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, |
298 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, |
299 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, |
300 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, |
301 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0c400b10, 0x0ff00fd0, "vmov%c\t%0-3,5D, %12-15r, %16-19r"}, |
302 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0c500b10, 0x0ff00fd0, "vmov%c\t%12-15r, %16-19r, %0-3,5D"}, |
303 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0e000b10, 0x0fd00f70, "vmov%c.32\t%16-19,7D[%21d], %12-15r"}, |
304 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0e100b10, 0x0f500f70, "vmov%c.32\t%12-15r, %16-19,7D[%21d]"}, |
305 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0e000b30, 0x0fd00f30, "vmov%c.16\t%16-19,7D[%6,21d], %12-15r"}, |
306 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0e100b30, 0x0f500f30, "vmov%c.%23?us16\t%12-15r, %16-19,7D[%6,21d]"}, |
307 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0e400b10, 0x0fd00f10, "vmov%c.8\t%16-19,7D[%5,6,21d], %12-15r"}, |
308 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0x0e500b10, 0x0f500f10, "vmov%c.%23?us8\t%12-15r, %16-19,7D[%5,6,21d]"}, |
309 | 4b0f1a8b | pbrook | |
310 | 4b0f1a8b | pbrook | /* Floating point coprocessor (VFP) instructions */
|
311 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ef1fa10, 0x0fffffff, "fmstat%c"}, |
312 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0fff0fff, "fmxr%c\tfpsid, %12-15r"}, |
313 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ee10a10, 0x0fff0fff, "fmxr%c\tfpscr, %12-15r"}, |
314 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ee60a10, 0x0fff0fff, "fmxr%c\tmvfr1, %12-15r"}, |
315 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ee70a10, 0x0fff0fff, "fmxr%c\tmvfr0, %12-15r"}, |
316 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ee80a10, 0x0fff0fff, "fmxr%c\tfpexc, %12-15r"}, |
317 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ee90a10, 0x0fff0fff, "fmxr%c\tfpinst, %12-15r\t@ Impl def"}, |
318 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0eea0a10, 0x0fff0fff, "fmxr%c\tfpinst2, %12-15r\t@ Impl def"}, |
319 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpsid"}, |
320 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ef10a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpscr"}, |
321 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ef60a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr1"}, |
322 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ef70a10, 0x0fff0fff, "fmrx%c\t%12-15r, mvfr0"}, |
323 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ef80a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpexc"}, |
324 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ef90a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst\t@ Impl def"}, |
325 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0efa0a10, 0x0fff0fff, "fmrx%c\t%12-15r, fpinst2\t@ Impl def"}, |
326 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e000b10, 0x0ff00fff, "fmdlr%c\t%z2, %12-15r"}, |
327 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e100b10, 0x0ff00fff, "fmrdl%c\t%12-15r, %z2"}, |
328 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e200b10, 0x0ff00fff, "fmdhr%c\t%z2, %12-15r"}, |
329 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e300b10, 0x0ff00fff, "fmrdh%c\t%12-15r, %z2"}, |
330 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ee00a10, 0x0ff00fff, "fmxr%c\t<impl def %16-19x>, %12-15r"}, |
331 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ef00a10, 0x0ff00fff, "fmrx%c\t%12-15r, <impl def %16-19x>"}, |
332 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e000a10, 0x0ff00f7f, "fmsr%c\t%y2, %12-15r"}, |
333 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e100a10, 0x0ff00f7f, "fmrs%c\t%12-15r, %y2"}, |
334 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0eb50a40, 0x0fbf0f70, "fcmp%7'ezs%c\t%y1"}, |
335 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0eb50b40, 0x0fbf0f70, "fcmp%7'ezd%c\t%z1"}, |
336 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0eb00a40, 0x0fbf0fd0, "fcpys%c\t%y1, %y0"}, |
337 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0eb00ac0, 0x0fbf0fd0, "fabss%c\t%y1, %y0"}, |
338 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0eb00b40, 0x0fbf0fd0, "fcpyd%c\t%z1, %z0"}, |
339 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0eb00bc0, 0x0fbf0fd0, "fabsd%c\t%z1, %z0"}, |
340 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0eb10a40, 0x0fbf0fd0, "fnegs%c\t%y1, %y0"}, |
341 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0eb10ac0, 0x0fbf0fd0, "fsqrts%c\t%y1, %y0"}, |
342 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0eb10b40, 0x0fbf0fd0, "fnegd%c\t%z1, %z0"}, |
343 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0eb10bc0, 0x0fbf0fd0, "fsqrtd%c\t%z1, %z0"}, |
344 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0eb70ac0, 0x0fbf0fd0, "fcvtds%c\t%z1, %y0"}, |
345 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0eb70bc0, 0x0fbf0fd0, "fcvtsd%c\t%y1, %z0"}, |
346 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0eb80a40, 0x0fbf0fd0, "fuitos%c\t%y1, %y0"}, |
347 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0eb80ac0, 0x0fbf0fd0, "fsitos%c\t%y1, %y0"}, |
348 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0eb80b40, 0x0fbf0fd0, "fuitod%c\t%z1, %y0"}, |
349 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0eb80bc0, 0x0fbf0fd0, "fsitod%c\t%z1, %y0"}, |
350 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0eb40a40, 0x0fbf0f50, "fcmp%7'es%c\t%y1, %y0"}, |
351 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0eb40b40, 0x0fbf0f50, "fcmp%7'ed%c\t%z1, %z0"}, |
352 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V3, 0x0eba0a40, 0x0fbe0f50, "f%16?us%7?lhtos%c\t%y1, #%5,0-3k"}, |
353 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V3, 0x0eba0b40, 0x0fbe0f50, "f%16?us%7?lhtod%c\t%z1, #%5,0-3k"}, |
354 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0ebc0a40, 0x0fbe0f50, "fto%16?sui%7'zs%c\t%y1, %y0"}, |
355 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0ebc0b40, 0x0fbe0f50, "fto%16?sui%7'zd%c\t%y1, %z0"}, |
356 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V3, 0x0ebe0a40, 0x0fbe0f50, "fto%16?us%7?lhs%c\t%y1, #%5,0-3k"}, |
357 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V3, 0x0ebe0b40, 0x0fbe0f50, "fto%16?us%7?lhd%c\t%z1, #%5,0-3k"}, |
358 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0c500b10, 0x0fb00ff0, "fmrrd%c\t%12-15r, %16-19r, %z0"}, |
359 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V3, 0x0eb00a00, 0x0fb00ff0, "fconsts%c\t%y1, #%0-3,16-19d"}, |
360 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V3, 0x0eb00b00, 0x0fb00ff0, "fconstd%c\t%z1, #%0-3,16-19d"}, |
361 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V2, 0x0c400a10, 0x0ff00fd0, "fmsrr%c\t%y4, %12-15r, %16-19r"}, |
362 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V2, 0x0c400b10, 0x0ff00fd0, "fmdrr%c\t%z0, %12-15r, %16-19r"}, |
363 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V2, 0x0c500a10, 0x0ff00fd0, "fmrrs%c\t%12-15r, %16-19r, %y4"}, |
364 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e000a00, 0x0fb00f50, "fmacs%c\t%y1, %y2, %y0"}, |
365 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e000a40, 0x0fb00f50, "fnmacs%c\t%y1, %y2, %y0"}, |
366 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e000b00, 0x0fb00f50, "fmacd%c\t%z1, %z2, %z0"}, |
367 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e000b40, 0x0fb00f50, "fnmacd%c\t%z1, %z2, %z0"}, |
368 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e100a00, 0x0fb00f50, "fmscs%c\t%y1, %y2, %y0"}, |
369 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e100a40, 0x0fb00f50, "fnmscs%c\t%y1, %y2, %y0"}, |
370 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e100b00, 0x0fb00f50, "fmscd%c\t%z1, %z2, %z0"}, |
371 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e100b40, 0x0fb00f50, "fnmscd%c\t%z1, %z2, %z0"}, |
372 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e200a00, 0x0fb00f50, "fmuls%c\t%y1, %y2, %y0"}, |
373 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e200a40, 0x0fb00f50, "fnmuls%c\t%y1, %y2, %y0"}, |
374 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e200b00, 0x0fb00f50, "fmuld%c\t%z1, %z2, %z0"}, |
375 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e200b40, 0x0fb00f50, "fnmuld%c\t%z1, %z2, %z0"}, |
376 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e300a00, 0x0fb00f50, "fadds%c\t%y1, %y2, %y0"}, |
377 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e300a40, 0x0fb00f50, "fsubs%c\t%y1, %y2, %y0"}, |
378 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e300b00, 0x0fb00f50, "faddd%c\t%z1, %z2, %z0"}, |
379 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e300b40, 0x0fb00f50, "fsubd%c\t%z1, %z2, %z0"}, |
380 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0e800a00, 0x0fb00f50, "fdivs%c\t%y1, %y2, %y0"}, |
381 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0e800b00, 0x0fb00f50, "fdivd%c\t%z1, %z2, %z0"}, |
382 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0d200a00, 0x0fb00f00, "fstmdbs%c\t%16-19r!, %y3"}, |
383 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0d200b00, 0x0fb00f00, "fstmdb%0?xd%c\t%16-19r!, %z3"}, |
384 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0d300a00, 0x0fb00f00, "fldmdbs%c\t%16-19r!, %y3"}, |
385 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0d300b00, 0x0fb00f00, "fldmdb%0?xd%c\t%16-19r!, %z3"}, |
386 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0d000a00, 0x0f300f00, "fsts%c\t%y1, %A"}, |
387 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0d000b00, 0x0f300f00, "fstd%c\t%z1, %A"}, |
388 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0d100a00, 0x0f300f00, "flds%c\t%y1, %A"}, |
389 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1, 0x0d100b00, 0x0f300f00, "fldd%c\t%z1, %A"}, |
390 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0c800a00, 0x0f900f00, "fstmias%c\t%16-19r%21'!, %y3"}, |
391 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0c800b00, 0x0f900f00, "fstmia%0?xd%c\t%16-19r%21'!, %z3"}, |
392 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0c900a00, 0x0f900f00, "fldmias%c\t%16-19r%21'!, %y3"}, |
393 | 4b0f1a8b | pbrook | {FPU_VFP_EXT_V1xD, 0x0c900b00, 0x0f900f00, "fldmia%0?xd%c\t%16-19r%21'!, %z3"}, |
394 | 4b0f1a8b | pbrook | |
395 | 4b0f1a8b | pbrook | /* Cirrus coprocessor instructions. */
|
396 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0d100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, |
397 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0c100400, 0x0f500f00, "cfldrs%c\tmvf%12-15d, %A"}, |
398 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0d500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, |
399 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0c500400, 0x0f500f00, "cfldrd%c\tmvd%12-15d, %A"}, |
400 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0d100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, |
401 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0c100500, 0x0f500f00, "cfldr32%c\tmvfx%12-15d, %A"}, |
402 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0d500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, |
403 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0c500500, 0x0f500f00, "cfldr64%c\tmvdx%12-15d, %A"}, |
404 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0d000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, |
405 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0c000400, 0x0f500f00, "cfstrs%c\tmvf%12-15d, %A"}, |
406 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0d400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, |
407 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0c400400, 0x0f500f00, "cfstrd%c\tmvd%12-15d, %A"}, |
408 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0d000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, |
409 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0c000500, 0x0f500f00, "cfstr32%c\tmvfx%12-15d, %A"}, |
410 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0d400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, |
411 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0c400500, 0x0f500f00, "cfstr64%c\tmvdx%12-15d, %A"}, |
412 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000450, 0x0ff00ff0, "cfmvsr%c\tmvf%16-19d, %12-15r"}, |
413 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100450, 0x0ff00ff0, "cfmvrs%c\t%12-15r, mvf%16-19d"}, |
414 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000410, 0x0ff00ff0, "cfmvdlr%c\tmvd%16-19d, %12-15r"}, |
415 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100410, 0x0ff00ff0, "cfmvrdl%c\t%12-15r, mvd%16-19d"}, |
416 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000430, 0x0ff00ff0, "cfmvdhr%c\tmvd%16-19d, %12-15r"}, |
417 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100430, 0x0ff00fff, "cfmvrdh%c\t%12-15r, mvd%16-19d"}, |
418 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000510, 0x0ff00fff, "cfmv64lr%c\tmvdx%16-19d, %12-15r"}, |
419 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, |
420 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, |
421 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, |
422 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, |
423 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, |
424 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, |
425 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, |
426 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, |
427 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, |
428 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, |
429 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, |
430 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, |
431 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, |
432 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, |
433 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, |
434 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, |
435 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, |
436 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, |
437 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000440, 0x0ff00fff, "cfcvtds%c\tmvf%12-15d, mvd%16-19d"}, |
438 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000480, 0x0ff00fff, "cfcvt32s%c\tmvf%12-15d, mvfx%16-19d"}, |
439 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e0004a0, 0x0ff00fff, "cfcvt32d%c\tmvd%12-15d, mvfx%16-19d"}, |
440 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e0004c0, 0x0ff00fff, "cfcvt64s%c\tmvf%12-15d, mvdx%16-19d"}, |
441 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e0004e0, 0x0ff00fff, "cfcvt64d%c\tmvd%12-15d, mvdx%16-19d"}, |
442 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100580, 0x0ff00fff, "cfcvts32%c\tmvfx%12-15d, mvf%16-19d"}, |
443 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e1005a0, 0x0ff00fff, "cfcvtd32%c\tmvfx%12-15d, mvd%16-19d"}, |
444 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e1005c0, 0x0ff00fff, "cftruncs32%c\tmvfx%12-15d, mvf%16-19d"}, |
445 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e1005e0, 0x0ff00fff, "cftruncd32%c\tmvfx%12-15d, mvd%16-19d"}, |
446 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000550, 0x0ff00ff0, "cfrshl32%c\tmvfx%16-19d, mvfx%0-3d, %12-15r"}, |
447 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000570, 0x0ff00ff0, "cfrshl64%c\tmvdx%16-19d, mvdx%0-3d, %12-15r"}, |
448 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000500, 0x0ff00f10, "cfsh32%c\tmvfx%12-15d, mvfx%16-19d, #%I"}, |
449 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e200500, 0x0ff00f10, "cfsh64%c\tmvdx%12-15d, mvdx%16-19d, #%I"}, |
450 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100490, 0x0ff00ff0, "cfcmps%c\t%12-15r, mvf%16-19d, mvf%0-3d"}, |
451 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e1004b0, 0x0ff00ff0, "cfcmpd%c\t%12-15r, mvd%16-19d, mvd%0-3d"}, |
452 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100590, 0x0ff00ff0, "cfcmp32%c\t%12-15r, mvfx%16-19d, mvfx%0-3d"}, |
453 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e1005b0, 0x0ff00ff0, "cfcmp64%c\t%12-15r, mvdx%16-19d, mvdx%0-3d"}, |
454 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300400, 0x0ff00fff, "cfabss%c\tmvf%12-15d, mvf%16-19d"}, |
455 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300420, 0x0ff00fff, "cfabsd%c\tmvd%12-15d, mvd%16-19d"}, |
456 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300440, 0x0ff00fff, "cfnegs%c\tmvf%12-15d, mvf%16-19d"}, |
457 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300460, 0x0ff00fff, "cfnegd%c\tmvd%12-15d, mvd%16-19d"}, |
458 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300480, 0x0ff00ff0, "cfadds%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, |
459 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e3004a0, 0x0ff00ff0, "cfaddd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, |
460 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e3004c0, 0x0ff00ff0, "cfsubs%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, |
461 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e3004e0, 0x0ff00ff0, "cfsubd%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, |
462 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100400, 0x0ff00ff0, "cfmuls%c\tmvf%12-15d, mvf%16-19d, mvf%0-3d"}, |
463 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100420, 0x0ff00ff0, "cfmuld%c\tmvd%12-15d, mvd%16-19d, mvd%0-3d"}, |
464 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300500, 0x0ff00fff, "cfabs32%c\tmvfx%12-15d, mvfx%16-19d"}, |
465 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300520, 0x0ff00fff, "cfabs64%c\tmvdx%12-15d, mvdx%16-19d"}, |
466 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300540, 0x0ff00fff, "cfneg32%c\tmvfx%12-15d, mvfx%16-19d"}, |
467 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300560, 0x0ff00fff, "cfneg64%c\tmvdx%12-15d, mvdx%16-19d"}, |
468 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300580, 0x0ff00ff0, "cfadd32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
469 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e3005a0, 0x0ff00ff0, "cfadd64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, |
470 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e3005c0, 0x0ff00ff0, "cfsub32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
471 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e3005e0, 0x0ff00ff0, "cfsub64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, |
472 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100500, 0x0ff00ff0, "cfmul32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
473 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100520, 0x0ff00ff0, "cfmul64%c\tmvdx%12-15d, mvdx%16-19d, mvdx%0-3d"}, |
474 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100540, 0x0ff00ff0, "cfmac32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
475 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100560, 0x0ff00ff0, "cfmsc32%c\tmvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
476 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e000600, 0x0ff00f10, "cfmadd32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
477 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e100600, 0x0ff00f10, "cfmsub32%c\tmvax%5-7d, mvfx%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
478 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e200600, 0x0ff00f10, "cfmadda32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
479 | 4b0f1a8b | pbrook | {ARM_CEXT_MAVERICK, 0x0e300600, 0x0ff00f10, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, |
480 | 4b0f1a8b | pbrook | |
481 | 4b0f1a8b | pbrook | /* Generic coprocessor instructions */
|
482 | 4b0f1a8b | pbrook | {ARM_EXT_V2, 0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, |
483 | 4b0f1a8b | pbrook | {ARM_EXT_V2, 0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, |
484 | 4b0f1a8b | pbrook | {ARM_EXT_V2, 0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, |
485 | 4b0f1a8b | pbrook | {ARM_EXT_V2, 0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, |
486 | 4b0f1a8b | pbrook | {ARM_EXT_V2, 0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, |
487 | 4b0f1a8b | pbrook | {ARM_EXT_V2, 0x0c000000, 0x0e100000, "stc%22'l%c\t%8-11d, cr%12-15d, %A"}, |
488 | 4b0f1a8b | pbrook | {ARM_EXT_V2, 0x0c100000, 0x0e100000, "ldc%22'l%c\t%8-11d, cr%12-15d, %A"}, |
489 | 4b0f1a8b | pbrook | |
490 | 4b0f1a8b | pbrook | /* V6 coprocessor instructions */
|
491 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xfc500000, 0xfff00000, "mrrc2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, |
492 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xfc400000, 0xfff00000, "mcrr2%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, |
493 | 4b0f1a8b | pbrook | |
494 | 4b0f1a8b | pbrook | /* V5 coprocessor instructions */
|
495 | 4b0f1a8b | pbrook | {ARM_EXT_V5, 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"}, |
496 | 4b0f1a8b | pbrook | {ARM_EXT_V5, 0xfc000000, 0xfe100000, "stc2%22'l%c\t%8-11d, cr%12-15d, %A"}, |
497 | 4b0f1a8b | pbrook | {ARM_EXT_V5, 0xfe000000, 0xff000010, "cdp2%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, |
498 | 4b0f1a8b | pbrook | {ARM_EXT_V5, 0xfe000010, 0xff100010, "mcr2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, |
499 | 4b0f1a8b | pbrook | {ARM_EXT_V5, 0xfe100010, 0xff100010, "mrc2%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, |
500 | 4b0f1a8b | pbrook | |
501 | 4b0f1a8b | pbrook | {0, 0, 0, 0} |
502 | 4b0f1a8b | pbrook | }; |
503 | 4b0f1a8b | pbrook | |
504 | 4b0f1a8b | pbrook | /* Neon opcode table: This does not encode the top byte -- that is
|
505 | 4b0f1a8b | pbrook | checked by the print_insn_neon routine, as it depends on whether we are
|
506 | 4b0f1a8b | pbrook | doing thumb32 or arm32 disassembly. */
|
507 | 4b0f1a8b | pbrook | |
508 | 4b0f1a8b | pbrook | /* print_insn_neon recognizes the following format control codes:
|
509 | 4b0f1a8b | pbrook | |
510 | 4b0f1a8b | pbrook | %% %
|
511 | 4b0f1a8b | pbrook | |
512 | 4b0f1a8b | pbrook | %c print condition code
|
513 | 4b0f1a8b | pbrook | %A print v{st,ld}[1234] operands
|
514 | 4b0f1a8b | pbrook | %B print v{st,ld}[1234] any one operands
|
515 | 4b0f1a8b | pbrook | %C print v{st,ld}[1234] single->all operands
|
516 | 4b0f1a8b | pbrook | %D print scalar
|
517 | 4b0f1a8b | pbrook | %E print vmov, vmvn, vorr, vbic encoded constant
|
518 | 4b0f1a8b | pbrook | %F print vtbl,vtbx register list
|
519 | 4b0f1a8b | pbrook | |
520 | 4b0f1a8b | pbrook | %<bitfield>r print as an ARM register
|
521 | 4b0f1a8b | pbrook | %<bitfield>d print the bitfield in decimal
|
522 | 4b0f1a8b | pbrook | %<bitfield>e print the 2^N - bitfield in decimal
|
523 | 4b0f1a8b | pbrook | %<bitfield>D print as a NEON D register
|
524 | 4b0f1a8b | pbrook | %<bitfield>Q print as a NEON Q register
|
525 | 4b0f1a8b | pbrook | %<bitfield>R print as a NEON D or Q register
|
526 | 4b0f1a8b | pbrook | %<bitfield>Sn print byte scaled width limited by n
|
527 | 4b0f1a8b | pbrook | %<bitfield>Tn print short scaled width limited by n
|
528 | 4b0f1a8b | pbrook | %<bitfield>Un print long scaled width limited by n
|
529 | 4b0f1a8b | pbrook | |
530 | 4b0f1a8b | pbrook | %<bitfield>'c print specified char iff bitfield is all ones
|
531 | 4b0f1a8b | pbrook | %<bitfield>`c print specified char iff bitfield is all zeroes
|
532 | 4b0f1a8b | pbrook | %<bitfield>?ab... select from array of values in big endian order */
|
533 | 4b0f1a8b | pbrook | |
534 | 4b0f1a8b | pbrook | static const struct opcode32 neon_opcodes[] = |
535 | 4b0f1a8b | pbrook | { |
536 | 4b0f1a8b | pbrook | /* Extract */
|
537 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2b00840, 0xffb00850, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, |
538 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2b00000, 0xffb00810, "vext%c.8\t%12-15,22R, %16-19,7R, %0-3,5R, #%8-11d"}, |
539 | 4b0f1a8b | pbrook | |
540 | 4b0f1a8b | pbrook | /* Move data element to all lanes */
|
541 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b40c00, 0xffb70f90, "vdup%c.32\t%12-15,22R, %0-3,5D[%19d]"}, |
542 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b20c00, 0xffb30f90, "vdup%c.16\t%12-15,22R, %0-3,5D[%18-19d]"}, |
543 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b10c00, 0xffb10f90, "vdup%c.8\t%12-15,22R, %0-3,5D[%17-19d]"}, |
544 | 4b0f1a8b | pbrook | |
545 | 4b0f1a8b | pbrook | /* Table lookup */
|
546 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00800, 0xffb00c50, "vtbl%c.8\t%12-15,22D, %F, %0-3,5D"}, |
547 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00840, 0xffb00c50, "vtbx%c.8\t%12-15,22D, %F, %0-3,5D"}, |
548 | 4b0f1a8b | pbrook | |
549 | 4b0f1a8b | pbrook | /* Two registers, miscellaneous */
|
550 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880a10, 0xfebf0fd0, "vmovl%c.%24?us8\t%12-15,22Q, %0-3,5D"}, |
551 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900a10, 0xfebf0fd0, "vmovl%c.%24?us16\t%12-15,22Q, %0-3,5D"}, |
552 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfebf0fd0, "vmovl%c.%24?us32\t%12-15,22Q, %0-3,5D"}, |
553 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00500, 0xffbf0f90, "vcnt%c.8\t%12-15,22R, %0-3,5R"}, |
554 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00580, 0xffbf0f90, "vmvn%c\t%12-15,22R, %0-3,5R"}, |
555 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b20000, 0xffbf0f90, "vswp%c\t%12-15,22R, %0-3,5R"}, |
556 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b20200, 0xffb30fd0, "vmovn%c.i%18-19T2\t%12-15,22D, %0-3,5Q"}, |
557 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b20240, 0xffb30fd0, "vqmovun%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, |
558 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b20280, 0xffb30fd0, "vqmovn%c.s%18-19T2\t%12-15,22D, %0-3,5Q"}, |
559 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b202c0, 0xffb30fd0, "vqmovn%c.u%18-19T2\t%12-15,22D, %0-3,5Q"}, |
560 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b20300, 0xffb30fd0, "vshll%c.i%18-19S2\t%12-15,22Q, %0-3,5D, #%18-19S2"}, |
561 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3bb0400, 0xffbf0e90, "vrecpe%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, |
562 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3bb0480, 0xffbf0e90, "vrsqrte%c.%8?fu%18-19S2\t%12-15,22R, %0-3,5R"}, |
563 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00000, 0xffb30f90, "vrev64%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
564 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00080, 0xffb30f90, "vrev32%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
565 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00100, 0xffb30f90, "vrev16%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
566 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00400, 0xffb30f90, "vcls%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, |
567 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00480, 0xffb30f90, "vclz%c.i%18-19S2\t%12-15,22R, %0-3,5R"}, |
568 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00700, 0xffb30f90, "vqabs%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, |
569 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00780, 0xffb30f90, "vqneg%c.s%18-19S2\t%12-15,22R, %0-3,5R"}, |
570 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b20080, 0xffb30f90, "vtrn%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
571 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b20100, 0xffb30f90, "vuzp%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
572 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b20180, 0xffb30f90, "vzip%c.%18-19S2\t%12-15,22R, %0-3,5R"}, |
573 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b10000, 0xffb30b90, "vcgt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, |
574 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b10080, 0xffb30b90, "vcge%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, |
575 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b10100, 0xffb30b90, "vceq%c.%10?fi%18-19S2\t%12-15,22R, %0-3,5R, #0"}, |
576 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b10180, 0xffb30b90, "vcle%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, |
577 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b10200, 0xffb30b90, "vclt%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R, #0"}, |
578 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b10300, 0xffb30b90, "vabs%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, |
579 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b10380, 0xffb30b90, "vneg%c.%10?fs%18-19S2\t%12-15,22R, %0-3,5R"}, |
580 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00200, 0xffb30f10, "vpaddl%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, |
581 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b00600, 0xffb30f10, "vpadal%c.%7?us%18-19S2\t%12-15,22R, %0-3,5R"}, |
582 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"}, |
583 | 4b0f1a8b | pbrook | |
584 | 4b0f1a8b | pbrook | /* Three registers of the same length */
|
585 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
586 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
587 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
588 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2300110, 0xffb00f10, "vorn%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
589 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3000110, 0xffb00f10, "veor%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
590 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3100110, 0xffb00f10, "vbsl%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
591 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3200110, 0xffb00f10, "vbit%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
592 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3300110, 0xffb00f10, "vbif%c\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
593 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000d00, 0xffa00f10, "vadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
594 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000d10, 0xffa00f10, "vmla%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
595 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000e00, 0xffa00f10, "vceq%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
596 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000f00, 0xffa00f10, "vmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
597 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000f10, 0xffa00f10, "vrecps%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
598 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2200d00, 0xffa00f10, "vsub%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
599 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2200d10, 0xffa00f10, "vmls%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
600 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2200f00, 0xffa00f10, "vmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
601 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2200f10, 0xffa00f10, "vrsqrts%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
602 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3000d00, 0xffa00f10, "vpadd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
603 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3000d10, 0xffa00f10, "vmul%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
604 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3000e00, 0xffa00f10, "vcge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
605 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3000e10, 0xffa00f10, "vacge%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
606 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3000f00, 0xffa00f10, "vpmax%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
607 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3200d00, 0xffa00f10, "vabd%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
608 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3200e00, 0xffa00f10, "vcgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
609 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3200e10, 0xffa00f10, "vacgt%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
610 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3200f00, 0xffa00f10, "vpmin%c.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
611 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000800, 0xff800f10, "vadd%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
612 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000810, 0xff800f10, "vtst%c.%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
613 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000900, 0xff800f10, "vmla%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
614 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000b00, 0xff800f10, "vqdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
615 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000b10, 0xff800f10, "vpadd%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
616 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3000800, 0xff800f10, "vsub%c.i%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
617 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3000810, 0xff800f10, "vceq%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
618 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3000900, 0xff800f10, "vmls%c.i%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
619 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3000b00, 0xff800f10, "vqrdmulh%c.s%20-21S6\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
620 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000000, 0xfe800f10, "vhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
621 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000010, 0xfe800f10, "vqadd%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
622 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000100, 0xfe800f10, "vrhadd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
623 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000200, 0xfe800f10, "vhsub%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
624 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000210, 0xfe800f10, "vqsub%c.%24?us%20-21S3\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
625 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000300, 0xfe800f10, "vcgt%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
626 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000310, 0xfe800f10, "vcge%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
627 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000400, 0xfe800f10, "vshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, |
628 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000410, 0xfe800f10, "vqshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, |
629 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000500, 0xfe800f10, "vrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, |
630 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000510, 0xfe800f10, "vqrshl%c.%24?us%20-21S3\t%12-15,22R, %0-3,5R, %16-19,7R"}, |
631 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000600, 0xfe800f10, "vmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
632 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000610, 0xfe800f10, "vmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
633 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000700, 0xfe800f10, "vabd%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
634 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000710, 0xfe800f10, "vaba%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
635 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000910, 0xfe800f10, "vmul%c.%24?pi%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
636 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000a00, 0xfe800f10, "vpmax%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
637 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2000a10, 0xfe800f10, "vpmin%c.%24?us%20-21S2\t%12-15,22R, %16-19,7R, %0-3,5R"}, |
638 | 4b0f1a8b | pbrook | |
639 | 4b0f1a8b | pbrook | /* One register and an immediate value */
|
640 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800e10, 0xfeb80fb0, "vmov%c.i8\t%12-15,22R, %E"}, |
641 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800e30, 0xfeb80fb0, "vmov%c.i64\t%12-15,22R, %E"}, |
642 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800f10, 0xfeb80fb0, "vmov%c.f32\t%12-15,22R, %E"}, |
643 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800810, 0xfeb80db0, "vmov%c.i16\t%12-15,22R, %E"}, |
644 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800830, 0xfeb80db0, "vmvn%c.i16\t%12-15,22R, %E"}, |
645 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800910, 0xfeb80db0, "vorr%c.i16\t%12-15,22R, %E"}, |
646 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800930, 0xfeb80db0, "vbic%c.i16\t%12-15,22R, %E"}, |
647 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800c10, 0xfeb80eb0, "vmov%c.i32\t%12-15,22R, %E"}, |
648 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800c30, 0xfeb80eb0, "vmvn%c.i32\t%12-15,22R, %E"}, |
649 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800110, 0xfeb809b0, "vorr%c.i32\t%12-15,22R, %E"}, |
650 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800130, 0xfeb809b0, "vbic%c.i32\t%12-15,22R, %E"}, |
651 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800010, 0xfeb808b0, "vmov%c.i32\t%12-15,22R, %E"}, |
652 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800030, 0xfeb808b0, "vmvn%c.i32\t%12-15,22R, %E"}, |
653 | 4b0f1a8b | pbrook | |
654 | 4b0f1a8b | pbrook | /* Two registers and a shift amount */
|
655 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880810, 0xffb80fd0, "vshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, |
656 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880850, 0xffb80fd0, "vrshrn%c.i16\t%12-15,22D, %0-3,5Q, #%16-18e"}, |
657 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880810, 0xfeb80fd0, "vqshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, |
658 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880850, 0xfeb80fd0, "vqrshrun%c.s16\t%12-15,22D, %0-3,5Q, #%16-18e"}, |
659 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880910, 0xfeb80fd0, "vqshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, |
660 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880950, 0xfeb80fd0, "vqrshrn%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-18e"}, |
661 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880a10, 0xfeb80fd0, "vshll%c.%24?us8\t%12-15,22D, %0-3,5Q, #%16-18d"}, |
662 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900810, 0xffb00fd0, "vshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, |
663 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900850, 0xffb00fd0, "vrshrn%c.i32\t%12-15,22D, %0-3,5Q, #%16-19e"}, |
664 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880510, 0xffb80f90, "vshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, |
665 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3880410, 0xffb80f90, "vsri%c.8\t%12-15,22R, %0-3,5R, #%16-18e"}, |
666 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3880510, 0xffb80f90, "vsli%c.8\t%12-15,22R, %0-3,5R, #%16-18d"}, |
667 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3880610, 0xffb80f90, "vqshlu%c.s8\t%12-15,22R, %0-3,5R, #%16-18d"}, |
668 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900810, 0xfeb00fd0, "vqshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, |
669 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900850, 0xfeb00fd0, "vqrshrun%c.s32\t%12-15,22D, %0-3,5Q, #%16-19e"}, |
670 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900910, 0xfeb00fd0, "vqshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, |
671 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900950, 0xfeb00fd0, "vqrshrn%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-19e"}, |
672 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900a10, 0xfeb00fd0, "vshll%c.%24?us16\t%12-15,22D, %0-3,5Q, #%16-19d"}, |
673 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880010, 0xfeb80f90, "vshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, |
674 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880110, 0xfeb80f90, "vsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, |
675 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880210, 0xfeb80f90, "vrshr%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, |
676 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880310, 0xfeb80f90, "vrsra%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18e"}, |
677 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2880710, 0xfeb80f90, "vqshl%c.%24?us8\t%12-15,22R, %0-3,5R, #%16-18d"}, |
678 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00810, 0xffa00fd0, "vshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, |
679 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00850, 0xffa00fd0, "vrshrn%c.i64\t%12-15,22D, %0-3,5Q, #%16-20e"}, |
680 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900510, 0xffb00f90, "vshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, |
681 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3900410, 0xffb00f90, "vsri%c.16\t%12-15,22R, %0-3,5R, #%16-19e"}, |
682 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3900510, 0xffb00f90, "vsli%c.16\t%12-15,22R, %0-3,5R, #%16-19d"}, |
683 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3900610, 0xffb00f90, "vqshlu%c.s16\t%12-15,22R, %0-3,5R, #%16-19d"}, |
684 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00a10, 0xfea00fd0, "vshll%c.%24?us32\t%12-15,22D, %0-3,5Q, #%16-20d"}, |
685 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900010, 0xfeb00f90, "vshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, |
686 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900110, 0xfeb00f90, "vsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, |
687 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900210, 0xfeb00f90, "vrshr%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, |
688 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900310, 0xfeb00f90, "vrsra%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19e"}, |
689 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2900710, 0xfeb00f90, "vqshl%c.%24?us16\t%12-15,22R, %0-3,5R, #%16-19d"}, |
690 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800810, 0xfec00fd0, "vqshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, |
691 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800850, 0xfec00fd0, "vqrshrun%c.s64\t%12-15,22D, %0-3,5Q, #%16-20e"}, |
692 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800910, 0xfec00fd0, "vqshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, |
693 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800950, 0xfec00fd0, "vqrshrn%c.%24?us64\t%12-15,22D, %0-3,5Q, #%16-20e"}, |
694 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00510, 0xffa00f90, "vshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, |
695 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3a00410, 0xffa00f90, "vsri%c.32\t%12-15,22R, %0-3,5R, #%16-20e"}, |
696 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3a00510, 0xffa00f90, "vsli%c.32\t%12-15,22R, %0-3,5R, #%16-20d"}, |
697 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3a00610, 0xffa00f90, "vqshlu%c.s32\t%12-15,22R, %0-3,5R, #%16-20d"}, |
698 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00010, 0xfea00f90, "vshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, |
699 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00110, 0xfea00f90, "vsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, |
700 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00210, 0xfea00f90, "vrshr%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, |
701 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00310, 0xfea00f90, "vrsra%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20e"}, |
702 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00710, 0xfea00f90, "vqshl%c.%24?us32\t%12-15,22R, %0-3,5R, #%16-20d"}, |
703 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800590, 0xff800f90, "vshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, |
704 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800490, 0xff800f90, "vsri%c.64\t%12-15,22R, %0-3,5R, #%16-21e"}, |
705 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800590, 0xff800f90, "vsli%c.64\t%12-15,22R, %0-3,5R, #%16-21d"}, |
706 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800690, 0xff800f90, "vqshlu%c.s64\t%12-15,22R, %0-3,5R, #%16-21d"}, |
707 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800090, 0xfe800f90, "vshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, |
708 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800190, 0xfe800f90, "vsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, |
709 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800290, 0xfe800f90, "vrshr%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, |
710 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800390, 0xfe800f90, "vrsra%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21e"}, |
711 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800790, 0xfe800f90, "vqshl%c.%24?us64\t%12-15,22R, %0-3,5R, #%16-21d"}, |
712 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2a00e10, 0xfea00e90, "vcvt%c.%24,8?usff32.%24,8?ffus32\t%12-15,22R, %0-3,5R, #%16-20e"}, |
713 | 4b0f1a8b | pbrook | |
714 | 4b0f1a8b | pbrook | /* Three registers of different lengths */
|
715 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800e00, 0xfea00f50, "vmull%c.p%20S0\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
716 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800400, 0xff800f50, "vaddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, |
717 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800600, 0xff800f50, "vsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, |
718 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800900, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
719 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800b00, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
720 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800d00, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
721 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800400, 0xff800f50, "vraddhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, |
722 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800600, 0xff800f50, "vrsubhn%c.i%20-21T2\t%12-15,22D, %16-19,7Q, %0-3,5Q"}, |
723 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800000, 0xfe800f50, "vaddl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
724 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800100, 0xfe800f50, "vaddw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, |
725 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800200, 0xfe800f50, "vsubl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
726 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800300, 0xfe800f50, "vsubw%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7Q, %0-3,5D"}, |
727 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800500, 0xfe800f50, "vabal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
728 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800700, 0xfe800f50, "vabdl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
729 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800800, 0xfe800f50, "vmlal%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
730 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800a00, 0xfe800f50, "vmlsl%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
731 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800c00, 0xfe800f50, "vmull%c.%24?us%20-21S2\t%12-15,22Q, %16-19,7D, %0-3,5D"}, |
732 | 4b0f1a8b | pbrook | |
733 | 4b0f1a8b | pbrook | /* Two registers and a scalar */
|
734 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
735 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, |
736 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800340, 0xff800f50, "vqdmlal%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
737 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
738 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800540, 0xff800f50, "vmls%c.f%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
739 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800740, 0xff800f50, "vqdmlsl%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
740 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
741 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22D, %16-19,7D, %D"}, |
742 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800b40, 0xff800f50, "vqdmull%c.s%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
743 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
744 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22D, %16-19,7D, %D"}, |
745 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800040, 0xff800f50, "vmla%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
746 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800140, 0xff800f50, "vmla%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, |
747 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800440, 0xff800f50, "vmls%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
748 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800540, 0xff800f50, "vmls%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, |
749 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800840, 0xff800f50, "vmul%c.i%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
750 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800940, 0xff800f50, "vmul%c.f%20-21Sa\t%12-15,22Q, %16-19,7Q, %D"}, |
751 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800c40, 0xff800f50, "vqdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
752 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf3800d40, 0xff800f50, "vqrdmulh%c.s%20-21S6\t%12-15,22Q, %16-19,7Q, %D"}, |
753 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800240, 0xfe800f50, "vmlal%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
754 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800640, 0xfe800f50, "vmlsl%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
755 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf2800a40, 0xfe800f50, "vmull%c.%24?us%20-21S6\t%12-15,22Q, %16-19,7D, %D"}, |
756 | 4b0f1a8b | pbrook | |
757 | 4b0f1a8b | pbrook | /* Element and structure load/store */
|
758 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4a00fc0, 0xffb00fc0, "vld4%c.32\t%C"}, |
759 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4a00c00, 0xffb00f00, "vld1%c.%6-7S2\t%C"}, |
760 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4a00d00, 0xffb00f00, "vld2%c.%6-7S2\t%C"}, |
761 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4a00e00, 0xffb00f00, "vld3%c.%6-7S2\t%C"}, |
762 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4a00f00, 0xffb00f00, "vld4%c.%6-7S2\t%C"}, |
763 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4000200, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, |
764 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4000300, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, |
765 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4000400, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, |
766 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4000500, 0xff900f00, "v%21?ls%21?dt3%c.%6-7S2\t%A"}, |
767 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4000600, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, |
768 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4000700, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, |
769 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4000800, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, |
770 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4000900, 0xff900f00, "v%21?ls%21?dt2%c.%6-7S2\t%A"}, |
771 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4000a00, 0xff900f00, "v%21?ls%21?dt1%c.%6-7S3\t%A"}, |
772 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4000000, 0xff900e00, "v%21?ls%21?dt4%c.%6-7S2\t%A"}, |
773 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4800000, 0xff900300, "v%21?ls%21?dt1%c.%10-11S2\t%B"}, |
774 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4800100, 0xff900300, "v%21?ls%21?dt2%c.%10-11S2\t%B"}, |
775 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4800200, 0xff900300, "v%21?ls%21?dt3%c.%10-11S2\t%B"}, |
776 | 4b0f1a8b | pbrook | {FPU_NEON_EXT_V1, 0xf4800300, 0xff900300, "v%21?ls%21?dt4%c.%10-11S2\t%B"}, |
777 | 4b0f1a8b | pbrook | |
778 | 4b0f1a8b | pbrook | {0,0 ,0, 0} |
779 | 4b0f1a8b | pbrook | }; |
780 | 4b0f1a8b | pbrook | |
781 | 4b0f1a8b | pbrook | /* Opcode tables: ARM, 16-bit Thumb, 32-bit Thumb. All three are partially
|
782 | 4b0f1a8b | pbrook | ordered: they must be searched linearly from the top to obtain a correct
|
783 | 4b0f1a8b | pbrook | match. */
|
784 | 4b0f1a8b | pbrook | |
785 | 4b0f1a8b | pbrook | /* print_insn_arm recognizes the following format control codes:
|
786 | 4b0f1a8b | pbrook | |
787 | 4b0f1a8b | pbrook | %% %
|
788 | 4b0f1a8b | pbrook | |
789 | aa0aa4fa | bellard | %a print address for ldr/str instruction
|
790 | aa0aa4fa | bellard | %s print address for ldr/str halfword/signextend instruction
|
791 | aa0aa4fa | bellard | %b print branch destination
|
792 | 4b0f1a8b | pbrook | %c print condition code (always bits 28-31)
|
793 | aa0aa4fa | bellard | %m print register mask for ldm/stm instruction
|
794 | 4b0f1a8b | pbrook | %o print operand2 (immediate or register + shift)
|
795 | 4b0f1a8b | pbrook | %p print 'p' iff bits 12-15 are 15
|
796 | 4b0f1a8b | pbrook | %t print 't' iff bit 21 set and bit 24 clear
|
797 | 4b0f1a8b | pbrook | %B print arm BLX(1) destination
|
798 | aa0aa4fa | bellard | %C print the PSR sub type.
|
799 | 4b0f1a8b | pbrook | %U print barrier type.
|
800 | 4b0f1a8b | pbrook | %P print address for pli instruction.
|
801 | 4b0f1a8b | pbrook | |
802 | 4b0f1a8b | pbrook | %<bitfield>r print as an ARM register
|
803 | 4b0f1a8b | pbrook | %<bitfield>d print the bitfield in decimal
|
804 | 4b0f1a8b | pbrook | %<bitfield>W print the bitfield plus one in decimal
|
805 | 4b0f1a8b | pbrook | %<bitfield>x print the bitfield in hex
|
806 | 4b0f1a8b | pbrook | %<bitfield>X print the bitfield as 1 hex digit without leading "0x"
|
807 | 4b0f1a8b | pbrook | |
808 | 4b0f1a8b | pbrook | %<bitfield>'c print specified char iff bitfield is all ones
|
809 | 4b0f1a8b | pbrook | %<bitfield>`c print specified char iff bitfield is all zeroes
|
810 | 4b0f1a8b | pbrook | %<bitfield>?ab... select from array of values in big endian order
|
811 | 4b0f1a8b | pbrook | |
812 | 4b0f1a8b | pbrook | %e print arm SMI operand (bits 0..7,8..19).
|
813 | 4b0f1a8b | pbrook | %E print the LSB and WIDTH fields of a BFI or BFC instruction.
|
814 | 4b0f1a8b | pbrook | %V print the 16-bit immediate field of a MOVT or MOVW instruction. */
|
815 | 4b0f1a8b | pbrook | |
816 | 4b0f1a8b | pbrook | static const struct opcode32 arm_opcodes[] = |
817 | 4b0f1a8b | pbrook | { |
818 | 4b0f1a8b | pbrook | /* ARM instructions. */
|
819 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, |
820 | 4b0f1a8b | pbrook | {ARM_EXT_V4T | ARM_EXT_V5, 0x012FFF10, 0x0ffffff0, "bx%c\t%0-3r"}, |
821 | 4b0f1a8b | pbrook | {ARM_EXT_V2, 0x00000090, 0x0fe000f0, "mul%20's%c\t%16-19r, %0-3r, %8-11r"}, |
822 | 4b0f1a8b | pbrook | {ARM_EXT_V2, 0x00200090, 0x0fe000f0, "mla%20's%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
823 | 4b0f1a8b | pbrook | {ARM_EXT_V2S, 0x01000090, 0x0fb00ff0, "swp%22'b%c\t%12-15r, %0-3r, [%16-19r]"}, |
824 | 4b0f1a8b | pbrook | {ARM_EXT_V3M, 0x00800090, 0x0fa000f0, "%22?sumull%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
825 | 4b0f1a8b | pbrook | {ARM_EXT_V3M, 0x00a00090, 0x0fa000f0, "%22?sumlal%20's%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
826 | 4b0f1a8b | pbrook | |
827 | 4b0f1a8b | pbrook | /* V7 instructions. */
|
828 | 4b0f1a8b | pbrook | {ARM_EXT_V7, 0xf450f000, 0xfd70f000, "pli\t%P"}, |
829 | 4b0f1a8b | pbrook | {ARM_EXT_V7, 0x0320f0f0, 0x0ffffff0, "dbg%c\t#%0-3d"}, |
830 | 4b0f1a8b | pbrook | {ARM_EXT_V7, 0xf57ff050, 0xfffffff0, "dmb\t%U"}, |
831 | 4b0f1a8b | pbrook | {ARM_EXT_V7, 0xf57ff040, 0xfffffff0, "dsb\t%U"}, |
832 | 4b0f1a8b | pbrook | {ARM_EXT_V7, 0xf57ff060, 0xfffffff0, "isb\t%U"}, |
833 | 4b0f1a8b | pbrook | |
834 | 4b0f1a8b | pbrook | /* ARM V6T2 instructions. */
|
835 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0x07c0001f, 0x0fe0007f, "bfc%c\t%12-15r, %E"}, |
836 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0x07c00010, 0x0fe00070, "bfi%c\t%12-15r, %0-3r, %E"}, |
837 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0x00600090, 0x0ff000f0, "mls%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
838 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0x006000b0, 0x0f7000f0, "strht%c\t%12-15r, %s"}, |
839 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0x00300090, 0x0f300090, "ldr%6's%5?hbt%c\t%12-15r, %s"}, |
840 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0x03000000, 0x0ff00000, "movw%c\t%12-15r, %V"}, |
841 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0x03400000, 0x0ff00000, "movt%c\t%12-15r, %V"}, |
842 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0x06ff0f30, 0x0fff0ff0, "rbit%c\t%12-15r, %0-3r"}, |
843 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0x07a00050, 0x0fa00070, "%22?usbfx%c\t%12-15r, %0-3r, #%7-11d, #%16-20W"}, |
844 | 4b0f1a8b | pbrook | |
845 | 4b0f1a8b | pbrook | /* ARM V6Z instructions. */
|
846 | 4b0f1a8b | pbrook | {ARM_EXT_V6Z, 0x01600070, 0x0ff000f0, "smc%c\t%e"}, |
847 | 4b0f1a8b | pbrook | |
848 | 4b0f1a8b | pbrook | /* ARM V6K instructions. */
|
849 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0xf57ff01f, 0xffffffff, "clrex"}, |
850 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x01d00f9f, 0x0ff00fff, "ldrexb%c\t%12-15r, [%16-19r]"}, |
851 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x01b00f9f, 0x0ff00fff, "ldrexd%c\t%12-15r, [%16-19r]"}, |
852 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x01f00f9f, 0x0ff00fff, "ldrexh%c\t%12-15r, [%16-19r]"}, |
853 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x01c00f90, 0x0ff00ff0, "strexb%c\t%12-15r, %0-3r, [%16-19r]"}, |
854 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x01a00f90, 0x0ff00ff0, "strexd%c\t%12-15r, %0-3r, [%16-19r]"}, |
855 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x01e00f90, 0x0ff00ff0, "strexh%c\t%12-15r, %0-3r, [%16-19r]"}, |
856 | 4b0f1a8b | pbrook | |
857 | 4b0f1a8b | pbrook | /* ARM V6K NOP hints. */
|
858 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x0320f001, 0x0fffffff, "yield%c"}, |
859 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x0320f002, 0x0fffffff, "wfe%c"}, |
860 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x0320f003, 0x0fffffff, "wfi%c"}, |
861 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x0320f004, 0x0fffffff, "sev%c"}, |
862 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0x0320f000, 0x0fffff00, "nop%c\t{%0-7d}"}, |
863 | 4b0f1a8b | pbrook | |
864 | 4b0f1a8b | pbrook | /* ARM V6 instructions. */
|
865 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xf1080000, 0xfffffe3f, "cpsie\t%8'a%7'i%6'f"}, |
866 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xf10a0000, 0xfffffe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, |
867 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xf10C0000, 0xfffffe3f, "cpsid\t%8'a%7'i%6'f"}, |
868 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xf10e0000, 0xfffffe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, |
869 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, |
870 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"}, |
871 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, lsl #%7-11d"}, |
872 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #32"}, |
873 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, asr #%7-11d"}, |
874 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"}, |
875 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"}, |
876 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"}, |
877 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"}, |
878 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"}, |
879 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"}, |
880 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"}, |
881 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"}, |
882 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"}, |
883 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"}, |
884 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"}, |
885 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"}, |
886 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"}, |
887 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"}, |
888 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"}, |
889 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"}, |
890 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"}, |
891 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"}, |
892 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"}, |
893 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"}, |
894 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"}, |
895 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"}, |
896 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"}, |
897 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"}, |
898 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"}, |
899 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"}, |
900 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"}, |
901 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"}, |
902 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"}, |
903 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"}, |
904 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"}, |
905 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"}, |
906 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"}, |
907 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"}, |
908 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"}, |
909 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"}, |
910 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"}, |
911 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"}, |
912 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"}, |
913 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"}, |
914 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"}, |
915 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06bf0070, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r"}, |
916 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06bf0470, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #8"}, |
917 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06bf0870, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #16"}, |
918 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06bf0c70, 0x0fff0ff0, "sxth%c\t%12-15r, %0-3r, ror #24"}, |
919 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x068f0070, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r"}, |
920 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x068f0470, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #8"}, |
921 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x068f0870, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #16"}, |
922 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x068f0c70, 0x0fff0ff0, "sxtb16%c\t%12-15r, %0-3r, ror #24"}, |
923 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06af0070, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r"}, |
924 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06af0470, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #8"}, |
925 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06af0870, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #16"}, |
926 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06af0c70, 0x0fff0ff0, "sxtb%c\t%12-15r, %0-3r, ror #24"}, |
927 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06ff0070, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r"}, |
928 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06ff0470, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #8"}, |
929 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06ff0870, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #16"}, |
930 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06ff0c70, 0x0fff0ff0, "uxth%c\t%12-15r, %0-3r, ror #24"}, |
931 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06cf0070, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r"}, |
932 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06cf0470, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #8"}, |
933 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06cf0870, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #16"}, |
934 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06cf0c70, 0x0fff0ff0, "uxtb16%c\t%12-15r, %0-3r, ror #24"}, |
935 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06ef0070, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r"}, |
936 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06ef0470, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #8"}, |
937 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06ef0870, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #16"}, |
938 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06ef0c70, 0x0fff0ff0, "uxtb%c\t%12-15r, %0-3r, ror #24"}, |
939 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"}, |
940 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"}, |
941 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"}, |
942 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"}, |
943 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"}, |
944 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"}, |
945 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"}, |
946 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ror #24"}, |
947 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"}, |
948 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"}, |
949 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"}, |
950 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"}, |
951 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"}, |
952 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #8"}, |
953 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #16"}, |
954 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ror #24"}, |
955 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"}, |
956 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #8"}, |
957 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ror #16"}, |
958 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, |
959 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"}, |
960 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #8"}, |
961 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #16"}, |
962 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ror #24"}, |
963 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06800fb0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, |
964 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xf1010000, 0xfffffc00, "setend\t%9?ble"}, |
965 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, |
966 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"}, |
967 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
968 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
969 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
970 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
971 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"}, |
972 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
973 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
974 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t%16-19r%21'!, #%0-4d"}, |
975 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"}, |
976 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, lsl #%7-11d"}, |
977 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, asr #%7-11d"}, |
978 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, |
979 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"}, |
980 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
981 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"}, |
982 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
983 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"}, |
984 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, lsl #%7-11d"}, |
985 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, asr #%7-11d"}, |
986 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"}, |
987 | 4b0f1a8b | pbrook | |
988 | 4b0f1a8b | pbrook | /* V5J instruction. */
|
989 | 4b0f1a8b | pbrook | {ARM_EXT_V5J, 0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, |
990 | 4b0f1a8b | pbrook | |
991 | 4b0f1a8b | pbrook | /* V5 Instructions. */
|
992 | 4b0f1a8b | pbrook | {ARM_EXT_V5, 0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, |
993 | 4b0f1a8b | pbrook | {ARM_EXT_V5, 0xfa000000, 0xfe000000, "blx\t%B"}, |
994 | 4b0f1a8b | pbrook | {ARM_EXT_V5, 0x012fff30, 0x0ffffff0, "blx%c\t%0-3r"}, |
995 | 4b0f1a8b | pbrook | {ARM_EXT_V5, 0x016f0f10, 0x0fff0ff0, "clz%c\t%12-15r, %0-3r"}, |
996 | 4b0f1a8b | pbrook | |
997 | 4b0f1a8b | pbrook | /* V5E "El Segundo" Instructions. */
|
998 | 4b0f1a8b | pbrook | {ARM_EXT_V5E, 0x000000d0, 0x0e1000f0, "ldrd%c\t%12-15r, %s"}, |
999 | 4b0f1a8b | pbrook | {ARM_EXT_V5E, 0x000000f0, 0x0e1000f0, "strd%c\t%12-15r, %s"}, |
1000 | 4b0f1a8b | pbrook | {ARM_EXT_V5E, 0xf450f000, 0xfc70f000, "pld\t%a"}, |
1001 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x01000080, 0x0ff000f0, "smlabb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
1002 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x010000a0, 0x0ff000f0, "smlatb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
1003 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x010000c0, 0x0ff000f0, "smlabt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
1004 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x010000e0, 0x0ff000f0, "smlatt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
1005 | 4b0f1a8b | pbrook | |
1006 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x01200080, 0x0ff000f0, "smlawb%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
1007 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x012000c0, 0x0ff000f0, "smlawt%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, |
1008 | 4b0f1a8b | pbrook | |
1009 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x01400080, 0x0ff000f0, "smlalbb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
1010 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x014000a0, 0x0ff000f0, "smlaltb%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
1011 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x014000c0, 0x0ff000f0, "smlalbt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
1012 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x014000e0, 0x0ff000f0, "smlaltt%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, |
1013 | 4b0f1a8b | pbrook | |
1014 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x01600080, 0x0ff0f0f0, "smulbb%c\t%16-19r, %0-3r, %8-11r"}, |
1015 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x016000a0, 0x0ff0f0f0, "smultb%c\t%16-19r, %0-3r, %8-11r"}, |
1016 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x016000c0, 0x0ff0f0f0, "smulbt%c\t%16-19r, %0-3r, %8-11r"}, |
1017 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x016000e0, 0x0ff0f0f0, "smultt%c\t%16-19r, %0-3r, %8-11r"}, |
1018 | 4b0f1a8b | pbrook | |
1019 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x012000a0, 0x0ff0f0f0, "smulwb%c\t%16-19r, %0-3r, %8-11r"}, |
1020 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x012000e0, 0x0ff0f0f0, "smulwt%c\t%16-19r, %0-3r, %8-11r"}, |
1021 | 4b0f1a8b | pbrook | |
1022 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x01000050, 0x0ff00ff0, "qadd%c\t%12-15r, %0-3r, %16-19r"}, |
1023 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x01400050, 0x0ff00ff0, "qdadd%c\t%12-15r, %0-3r, %16-19r"}, |
1024 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, |
1025 | 4b0f1a8b | pbrook | {ARM_EXT_V5ExP, 0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, |
1026 | 4b0f1a8b | pbrook | |
1027 | 4b0f1a8b | pbrook | /* ARM Instructions. */
|
1028 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00000090, 0x0e100090, "str%6's%5?hb%c\t%12-15r, %s"}, |
1029 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00100090, 0x0e100090, "ldr%6's%5?hb%c\t%12-15r, %s"}, |
1030 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00000000, 0x0de00000, "and%20's%c\t%12-15r, %16-19r, %o"}, |
1031 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00200000, 0x0de00000, "eor%20's%c\t%12-15r, %16-19r, %o"}, |
1032 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00400000, 0x0de00000, "sub%20's%c\t%12-15r, %16-19r, %o"}, |
1033 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00600000, 0x0de00000, "rsb%20's%c\t%12-15r, %16-19r, %o"}, |
1034 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00800000, 0x0de00000, "add%20's%c\t%12-15r, %16-19r, %o"}, |
1035 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00a00000, 0x0de00000, "adc%20's%c\t%12-15r, %16-19r, %o"}, |
1036 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00c00000, 0x0de00000, "sbc%20's%c\t%12-15r, %16-19r, %o"}, |
1037 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00e00000, 0x0de00000, "rsc%20's%c\t%12-15r, %16-19r, %o"}, |
1038 | 4b0f1a8b | pbrook | {ARM_EXT_V3, 0x0120f000, 0x0db0f000, "msr%c\t%22?SCPSR%C, %o"}, |
1039 | 4b0f1a8b | pbrook | {ARM_EXT_V3, 0x010f0000, 0x0fbf0fff, "mrs%c\t%12-15r, %22?SCPSR"}, |
1040 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01000000, 0x0de00000, "tst%p%c\t%16-19r, %o"}, |
1041 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01200000, 0x0de00000, "teq%p%c\t%16-19r, %o"}, |
1042 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01400000, 0x0de00000, "cmp%p%c\t%16-19r, %o"}, |
1043 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01600000, 0x0de00000, "cmn%p%c\t%16-19r, %o"}, |
1044 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01800000, 0x0de00000, "orr%20's%c\t%12-15r, %16-19r, %o"}, |
1045 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x03a00000, 0x0fef0000, "mov%20's%c\t%12-15r, %o"}, |
1046 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01a00000, 0x0def0ff0, "mov%20's%c\t%12-15r, %0-3r"}, |
1047 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01a00000, 0x0def0060, "lsl%20's%c\t%12-15r, %q"}, |
1048 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01a00020, 0x0def0060, "lsr%20's%c\t%12-15r, %q"}, |
1049 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01a00040, 0x0def0060, "asr%20's%c\t%12-15r, %q"}, |
1050 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01a00060, 0x0def0ff0, "rrx%20's%c\t%12-15r, %0-3r"}, |
1051 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01a00060, 0x0def0060, "ror%20's%c\t%12-15r, %q"}, |
1052 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01c00000, 0x0de00000, "bic%20's%c\t%12-15r, %16-19r, %o"}, |
1053 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x01e00000, 0x0de00000, "mvn%20's%c\t%12-15r, %o"}, |
1054 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x052d0004, 0x0fff0fff, "push%c\t{%12-15r}\t\t; (str%c %12-15r, %a)"}, |
1055 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x04000000, 0x0e100000, "str%22'b%t%c\t%12-15r, %a"}, |
1056 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x06000000, 0x0e100ff0, "str%22'b%t%c\t%12-15r, %a"}, |
1057 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x04000000, 0x0c100010, "str%22'b%t%c\t%12-15r, %a"}, |
1058 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x06000010, 0x0e000010, "undefined"}, |
1059 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x049d0004, 0x0fff0fff, "pop%c\t{%12-15r}\t\t; (ldr%c %12-15r, %a)"}, |
1060 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x04100000, 0x0c100000, "ldr%22'b%t%c\t%12-15r, %a"}, |
1061 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x092d0000, 0x0fff0000, "push%c\t%m"}, |
1062 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x08800000, 0x0ff00000, "stm%c\t%16-19r%21'!, %m%22'^"}, |
1063 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x08000000, 0x0e100000, "stm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, |
1064 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x08bd0000, 0x0fff0000, "pop%c\t%m"}, |
1065 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x08900000, 0x0f900000, "ldm%c\t%16-19r%21'!, %m%22'^"}, |
1066 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x08100000, 0x0e100000, "ldm%23?id%24?ba%c\t%16-19r%21'!, %m%22'^"}, |
1067 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x0a000000, 0x0e000000, "b%24'l%c\t%b"}, |
1068 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x0f000000, 0x0f000000, "svc%c\t%0-23x"}, |
1069 | 4b0f1a8b | pbrook | |
1070 | 4b0f1a8b | pbrook | /* The rest. */
|
1071 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined instruction %0-31x"}, |
1072 | 4b0f1a8b | pbrook | {0, 0x00000000, 0x00000000, 0} |
1073 | 4b0f1a8b | pbrook | }; |
1074 | 4b0f1a8b | pbrook | |
1075 | 4b0f1a8b | pbrook | /* print_insn_thumb16 recognizes the following format control codes:
|
1076 | 4b0f1a8b | pbrook | |
1077 | aa0aa4fa | bellard | %S print Thumb register (bits 3..5 as high number if bit 6 set)
|
1078 | 4b0f1a8b | pbrook | %D print Thumb register (bits 0..2 as high number if bit 7 set)
|
1079 | aa0aa4fa | bellard | %<bitfield>I print bitfield as a signed decimal
|
1080 | aa0aa4fa | bellard | (top bit of range being the sign bit)
|
1081 | aa0aa4fa | bellard | %N print Thumb register mask (with LR)
|
1082 | aa0aa4fa | bellard | %O print Thumb register mask (with PC)
|
1083 | 4b0f1a8b | pbrook | %M print Thumb register mask
|
1084 | 4b0f1a8b | pbrook | %b print CZB's 6-bit unsigned branch destination
|
1085 | 4b0f1a8b | pbrook | %s print Thumb right-shift immediate (6..10; 0 == 32).
|
1086 | 4b0f1a8b | pbrook | %c print the condition code
|
1087 | 4b0f1a8b | pbrook | %C print the condition code, or "s" if not conditional
|
1088 | 4b0f1a8b | pbrook | %x print warning if conditional an not at end of IT block"
|
1089 | 4b0f1a8b | pbrook | %X print "\t; unpredictable <IT:code>" if conditional
|
1090 | 4b0f1a8b | pbrook | %I print IT instruction suffix and operands
|
1091 | 4b0f1a8b | pbrook | %<bitfield>r print bitfield as an ARM register
|
1092 | 4b0f1a8b | pbrook | %<bitfield>d print bitfield as a decimal
|
1093 | aa0aa4fa | bellard | %<bitfield>H print (bitfield * 2) as a decimal
|
1094 | 4b0f1a8b | pbrook | %<bitfield>W print (bitfield * 4) as a decimal
|
1095 | aa0aa4fa | bellard | %<bitfield>a print (bitfield * 4) as a pc-rel offset + decoded symbol
|
1096 | 4b0f1a8b | pbrook | %<bitfield>B print Thumb branch destination (signed displacement)
|
1097 | 4b0f1a8b | pbrook | %<bitfield>c print bitfield as a condition code
|
1098 | 4b0f1a8b | pbrook | %<bitnum>'c print specified char iff bit is one
|
1099 | 4b0f1a8b | pbrook | %<bitnum>?ab print a if bit is one else print b. */
|
1100 | aa0aa4fa | bellard | |
1101 | 4b0f1a8b | pbrook | static const struct opcode16 thumb_opcodes[] = |
1102 | aa0aa4fa | bellard | { |
1103 | aa0aa4fa | bellard | /* Thumb instructions. */
|
1104 | aa0aa4fa | bellard | |
1105 | 4b0f1a8b | pbrook | /* ARM V6K no-argument instructions. */
|
1106 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0xbf00, 0xffff, "nop%c"}, |
1107 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0xbf10, 0xffff, "yield%c"}, |
1108 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0xbf20, 0xffff, "wfe%c"}, |
1109 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0xbf30, 0xffff, "wfi%c"}, |
1110 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0xbf40, 0xffff, "sev%c"}, |
1111 | 4b0f1a8b | pbrook | {ARM_EXT_V6K, 0xbf00, 0xff0f, "nop%c\t{%4-7d}"}, |
1112 | 4b0f1a8b | pbrook | |
1113 | 4b0f1a8b | pbrook | /* ARM V6T2 instructions. */
|
1114 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xb900, 0xfd00, "cbnz\t%0-2r, %b%X"}, |
1115 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xb100, 0xfd00, "cbz\t%0-2r, %b%X"}, |
1116 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xbf00, 0xff00, "it%I%X"}, |
1117 | 4b0f1a8b | pbrook | |
1118 | 4b0f1a8b | pbrook | /* ARM V6. */
|
1119 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f%X"}, |
1120 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f%X"}, |
1121 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0x4600, 0xffc0, "mov%c\t%0-2r, %3-5r"}, |
1122 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xba00, 0xffc0, "rev%c\t%0-2r, %3-5r"}, |
1123 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xba40, 0xffc0, "rev16%c\t%0-2r, %3-5r"}, |
1124 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xbac0, 0xffc0, "revsh%c\t%0-2r, %3-5r"}, |
1125 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xb650, 0xfff7, "setend\t%3?ble%X"}, |
1126 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xb200, 0xffc0, "sxth%c\t%0-2r, %3-5r"}, |
1127 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xb240, 0xffc0, "sxtb%c\t%0-2r, %3-5r"}, |
1128 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xb280, 0xffc0, "uxth%c\t%0-2r, %3-5r"}, |
1129 | 4b0f1a8b | pbrook | {ARM_EXT_V6, 0xb2c0, 0xffc0, "uxtb%c\t%0-2r, %3-5r"}, |
1130 | 4b0f1a8b | pbrook | |
1131 | aa0aa4fa | bellard | /* ARM V5 ISA extends Thumb. */
|
1132 | 4b0f1a8b | pbrook | {ARM_EXT_V5T, 0xbe00, 0xff00, "bkpt\t%0-7x"}, /* Is always unconditional. */ |
1133 | 4b0f1a8b | pbrook | /* This is BLX(2). BLX(1) is a 32-bit instruction. */
|
1134 | 4b0f1a8b | pbrook | {ARM_EXT_V5T, 0x4780, 0xff87, "blx%c\t%3-6r%x"}, /* note: 4 bit register number. */ |
1135 | 4b0f1a8b | pbrook | /* ARM V4T ISA (Thumb v1). */
|
1136 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x46C0, 0xFFFF, "nop%c\t\t\t(mov r8, r8)"}, |
1137 | aa0aa4fa | bellard | /* Format 4. */
|
1138 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4000, 0xFFC0, "and%C\t%0-2r, %3-5r"}, |
1139 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4040, 0xFFC0, "eor%C\t%0-2r, %3-5r"}, |
1140 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4080, 0xFFC0, "lsl%C\t%0-2r, %3-5r"}, |
1141 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x40C0, 0xFFC0, "lsr%C\t%0-2r, %3-5r"}, |
1142 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4100, 0xFFC0, "asr%C\t%0-2r, %3-5r"}, |
1143 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4140, 0xFFC0, "adc%C\t%0-2r, %3-5r"}, |
1144 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4180, 0xFFC0, "sbc%C\t%0-2r, %3-5r"}, |
1145 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x41C0, 0xFFC0, "ror%C\t%0-2r, %3-5r"}, |
1146 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4200, 0xFFC0, "tst%c\t%0-2r, %3-5r"}, |
1147 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4240, 0xFFC0, "neg%C\t%0-2r, %3-5r"}, |
1148 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4280, 0xFFC0, "cmp%c\t%0-2r, %3-5r"}, |
1149 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x42C0, 0xFFC0, "cmn%c\t%0-2r, %3-5r"}, |
1150 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4300, 0xFFC0, "orr%C\t%0-2r, %3-5r"}, |
1151 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4340, 0xFFC0, "mul%C\t%0-2r, %3-5r"}, |
1152 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4380, 0xFFC0, "bic%C\t%0-2r, %3-5r"}, |
1153 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x43C0, 0xFFC0, "mvn%C\t%0-2r, %3-5r"}, |
1154 | aa0aa4fa | bellard | /* format 13 */
|
1155 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xB000, 0xFF80, "add%c\tsp, #%0-6W"}, |
1156 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xB080, 0xFF80, "sub%c\tsp, #%0-6W"}, |
1157 | aa0aa4fa | bellard | /* format 5 */
|
1158 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4700, 0xFF80, "bx%c\t%S%x"}, |
1159 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4400, 0xFF00, "add%c\t%D, %S"}, |
1160 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4500, 0xFF00, "cmp%c\t%D, %S"}, |
1161 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4600, 0xFF00, "mov%c\t%D, %S"}, |
1162 | aa0aa4fa | bellard | /* format 14 */
|
1163 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xB400, 0xFE00, "push%c\t%N"}, |
1164 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xBC00, 0xFE00, "pop%c\t%O"}, |
1165 | aa0aa4fa | bellard | /* format 2 */
|
1166 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x1800, 0xFE00, "add%C\t%0-2r, %3-5r, %6-8r"}, |
1167 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x1A00, 0xFE00, "sub%C\t%0-2r, %3-5r, %6-8r"}, |
1168 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x1C00, 0xFE00, "add%C\t%0-2r, %3-5r, #%6-8d"}, |
1169 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x1E00, 0xFE00, "sub%C\t%0-2r, %3-5r, #%6-8d"}, |
1170 | aa0aa4fa | bellard | /* format 8 */
|
1171 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x5200, 0xFE00, "strh%c\t%0-2r, [%3-5r, %6-8r]"}, |
1172 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x5A00, 0xFE00, "ldrh%c\t%0-2r, [%3-5r, %6-8r]"}, |
1173 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x5600, 0xF600, "ldrs%11?hb%c\t%0-2r, [%3-5r, %6-8r]"}, |
1174 | aa0aa4fa | bellard | /* format 7 */
|
1175 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x5000, 0xFA00, "str%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, |
1176 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x5800, 0xFA00, "ldr%10'b%c\t%0-2r, [%3-5r, %6-8r]"}, |
1177 | aa0aa4fa | bellard | /* format 1 */
|
1178 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x0000, 0xF800, "lsl%C\t%0-2r, %3-5r, #%6-10d"}, |
1179 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x0800, 0xF800, "lsr%C\t%0-2r, %3-5r, %s"}, |
1180 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x1000, 0xF800, "asr%C\t%0-2r, %3-5r, %s"}, |
1181 | aa0aa4fa | bellard | /* format 3 */
|
1182 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x2000, 0xF800, "mov%C\t%8-10r, #%0-7d"}, |
1183 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x2800, 0xF800, "cmp%c\t%8-10r, #%0-7d"}, |
1184 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x3000, 0xF800, "add%C\t%8-10r, #%0-7d"}, |
1185 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x3800, 0xF800, "sub%C\t%8-10r, #%0-7d"}, |
1186 | aa0aa4fa | bellard | /* format 6 */
|
1187 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x4800, 0xF800, "ldr%c\t%8-10r, [pc, #%0-7W]\t(%0-7a)"}, /* TODO: Disassemble PC relative "LDR rD,=<symbolic>" */ |
1188 | aa0aa4fa | bellard | /* format 9 */
|
1189 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x6000, 0xF800, "str%c\t%0-2r, [%3-5r, #%6-10W]"}, |
1190 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x6800, 0xF800, "ldr%c\t%0-2r, [%3-5r, #%6-10W]"}, |
1191 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x7000, 0xF800, "strb%c\t%0-2r, [%3-5r, #%6-10d]"}, |
1192 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x7800, 0xF800, "ldrb%c\t%0-2r, [%3-5r, #%6-10d]"}, |
1193 | aa0aa4fa | bellard | /* format 10 */
|
1194 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x8000, 0xF800, "strh%c\t%0-2r, [%3-5r, #%6-10H]"}, |
1195 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x8800, 0xF800, "ldrh%c\t%0-2r, [%3-5r, #%6-10H]"}, |
1196 | aa0aa4fa | bellard | /* format 11 */
|
1197 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x9000, 0xF800, "str%c\t%8-10r, [sp, #%0-7W]"}, |
1198 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0x9800, 0xF800, "ldr%c\t%8-10r, [sp, #%0-7W]"}, |
1199 | aa0aa4fa | bellard | /* format 12 */
|
1200 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xA000, 0xF800, "add%c\t%8-10r, pc, #%0-7W\t(adr %8-10r, %0-7a)"}, |
1201 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xA800, 0xF800, "add%c\t%8-10r, sp, #%0-7W"}, |
1202 | aa0aa4fa | bellard | /* format 15 */
|
1203 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xC000, 0xF800, "stmia%c\t%8-10r!, %M"}, |
1204 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xC800, 0xF800, "ldmia%c\t%8-10r!, %M"}, |
1205 | aa0aa4fa | bellard | /* format 17 */
|
1206 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xDF00, 0xFF00, "svc%c\t%0-7d"}, |
1207 | 4b0f1a8b | pbrook | /* format 16 */
|
1208 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xDE00, 0xFE00, "undefined"}, |
1209 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xD000, 0xF000, "b%8-11c.n\t%0-7B%X"}, |
1210 | 4b0f1a8b | pbrook | /* format 18 */
|
1211 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xE000, 0xF800, "b%c.n\t%0-10B%x"}, |
1212 | 4b0f1a8b | pbrook | |
1213 | 4b0f1a8b | pbrook | /* The E800 .. FFFF range is unconditionally redirected to the
|
1214 | 4b0f1a8b | pbrook | 32-bit table, because even in pre-V6T2 ISAs, BL and BLX(1) pairs
|
1215 | 4b0f1a8b | pbrook | are processed via that table. Thus, we can never encounter a
|
1216 | 4b0f1a8b | pbrook | bare "second half of BL/BLX(1)" instruction here. */
|
1217 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x0000, 0x0000, "undefined"}, |
1218 | 4b0f1a8b | pbrook | {0, 0, 0, 0} |
1219 | aa0aa4fa | bellard | }; |
1220 | aa0aa4fa | bellard | |
1221 | 4b0f1a8b | pbrook | /* Thumb32 opcodes use the same table structure as the ARM opcodes.
|
1222 | 4b0f1a8b | pbrook | We adopt the convention that hw1 is the high 16 bits of .value and
|
1223 | 4b0f1a8b | pbrook | .mask, hw2 the low 16 bits.
|
1224 | 4b0f1a8b | pbrook | |
1225 | 4b0f1a8b | pbrook | print_insn_thumb32 recognizes the following format control codes:
|
1226 | 4b0f1a8b | pbrook | |
1227 | 4b0f1a8b | pbrook | %% %
|
1228 | 4b0f1a8b | pbrook | |
1229 | 4b0f1a8b | pbrook | %I print a 12-bit immediate from hw1[10],hw2[14:12,7:0]
|
1230 | 4b0f1a8b | pbrook | %M print a modified 12-bit immediate (same location)
|
1231 | 4b0f1a8b | pbrook | %J print a 16-bit immediate from hw1[3:0,10],hw2[14:12,7:0]
|
1232 | 4b0f1a8b | pbrook | %K print a 16-bit immediate from hw2[3:0],hw1[3:0],hw2[11:4]
|
1233 | 4b0f1a8b | pbrook | %S print a possibly-shifted Rm
|
1234 | 4b0f1a8b | pbrook | |
1235 | 4b0f1a8b | pbrook | %a print the address of a plain load/store
|
1236 | 4b0f1a8b | pbrook | %w print the width and signedness of a core load/store
|
1237 | 4b0f1a8b | pbrook | %m print register mask for ldm/stm
|
1238 | 4b0f1a8b | pbrook | |
1239 | 4b0f1a8b | pbrook | %E print the lsb and width fields of a bfc/bfi instruction
|
1240 | 4b0f1a8b | pbrook | %F print the lsb and width fields of a sbfx/ubfx instruction
|
1241 | 4b0f1a8b | pbrook | %b print a conditional branch offset
|
1242 | 4b0f1a8b | pbrook | %B print an unconditional branch offset
|
1243 | 4b0f1a8b | pbrook | %s print the shift field of an SSAT instruction
|
1244 | 4b0f1a8b | pbrook | %R print the rotation field of an SXT instruction
|
1245 | 4b0f1a8b | pbrook | %U print barrier type.
|
1246 | 4b0f1a8b | pbrook | %P print address for pli instruction.
|
1247 | 4b0f1a8b | pbrook | %c print the condition code
|
1248 | 4b0f1a8b | pbrook | %x print warning if conditional an not at end of IT block"
|
1249 | 4b0f1a8b | pbrook | %X print "\t; unpredictable <IT:code>" if conditional
|
1250 | 4b0f1a8b | pbrook | |
1251 | 4b0f1a8b | pbrook | %<bitfield>d print bitfield in decimal
|
1252 | 4b0f1a8b | pbrook | %<bitfield>W print bitfield*4 in decimal
|
1253 | 4b0f1a8b | pbrook | %<bitfield>r print bitfield as an ARM register
|
1254 | 4b0f1a8b | pbrook | %<bitfield>c print bitfield as a condition code
|
1255 | 4b0f1a8b | pbrook | |
1256 | 4b0f1a8b | pbrook | %<bitfield>'c print specified char iff bitfield is all ones
|
1257 | 4b0f1a8b | pbrook | %<bitfield>`c print specified char iff bitfield is all zeroes
|
1258 | 4b0f1a8b | pbrook | %<bitfield>?ab... select from array of values in big endian order
|
1259 | 4b0f1a8b | pbrook | |
1260 | 4b0f1a8b | pbrook | With one exception at the bottom (done because BL and BLX(1) need
|
1261 | 4b0f1a8b | pbrook | to come dead last), this table was machine-sorted first in
|
1262 | 4b0f1a8b | pbrook | decreasing order of number of bits set in the mask, then in
|
1263 | 4b0f1a8b | pbrook | increasing numeric order of mask, then in increasing numeric order
|
1264 | 4b0f1a8b | pbrook | of opcode. This order is not the clearest for a human reader, but
|
1265 | 4b0f1a8b | pbrook | is guaranteed never to catch a special-case bit pattern with a more
|
1266 | 4b0f1a8b | pbrook | general mask, which is important, because this instruction encoding
|
1267 | 4b0f1a8b | pbrook | makes heavy use of special-case bit patterns. */
|
1268 | 4b0f1a8b | pbrook | static const struct opcode32 thumb32_opcodes[] = |
1269 | 4b0f1a8b | pbrook | { |
1270 | 4b0f1a8b | pbrook | /* V7 instructions. */
|
1271 | 4b0f1a8b | pbrook | {ARM_EXT_V7, 0xf910f000, 0xff70f000, "pli%c\t%a"}, |
1272 | 4b0f1a8b | pbrook | {ARM_EXT_V7, 0xf3af80f0, 0xfffffff0, "dbg%c\t#%0-3d"}, |
1273 | 4b0f1a8b | pbrook | {ARM_EXT_V7, 0xf3bf8f50, 0xfffffff0, "dmb%c\t%U"}, |
1274 | 4b0f1a8b | pbrook | {ARM_EXT_V7, 0xf3bf8f40, 0xfffffff0, "dsb%c\t%U"}, |
1275 | 4b0f1a8b | pbrook | {ARM_EXT_V7, 0xf3bf8f60, 0xfffffff0, "isb%c\t%U"}, |
1276 | 4b0f1a8b | pbrook | {ARM_EXT_DIV, 0xfb90f0f0, 0xfff0f0f0, "sdiv%c\t%8-11r, %16-19r, %0-3r"}, |
1277 | 4b0f1a8b | pbrook | {ARM_EXT_DIV, 0xfbb0f0f0, 0xfff0f0f0, "udiv%c\t%8-11r, %16-19r, %0-3r"}, |
1278 | 4b0f1a8b | pbrook | |
1279 | 4b0f1a8b | pbrook | /* Instructions defined in the basic V6T2 set. */
|
1280 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af8000, 0xffffffff, "nop%c.w"}, |
1281 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af8001, 0xffffffff, "yield%c.w"}, |
1282 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af8002, 0xffffffff, "wfe%c.w"}, |
1283 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af8003, 0xffffffff, "wfi%c.w"}, |
1284 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af9004, 0xffffffff, "sev%c.w"}, |
1285 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af8000, 0xffffff00, "nop%c.w\t{%0-7d}"}, |
1286 | 4b0f1a8b | pbrook | |
1287 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3bf8f2f, 0xffffffff, "clrex%c"}, |
1288 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af8400, 0xffffff1f, "cpsie.w\t%7'a%6'i%5'f%X"}, |
1289 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af8600, 0xffffff1f, "cpsid.w\t%7'a%6'i%5'f%X"}, |
1290 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3c08f00, 0xfff0ffff, "bxj%c\t%16-19r%x"}, |
1291 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe810c000, 0xffd0ffff, "rfedb%c\t%16-19r%21'!"}, |
1292 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe990c000, 0xffd0ffff, "rfeia%c\t%16-19r%21'!"}, |
1293 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3ef8000, 0xffeff000, "mrs%c\t%8-11r, %D"}, |
1294 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af8100, 0xffffffe0, "cps\t#%0-4d%X"}, |
1295 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8d0f000, 0xfff0fff0, "tbb%c\t[%16-19r, %0-3r]%x"}, |
1296 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8d0f010, 0xfff0fff0, "tbh%c\t[%16-19r, %0-3r, lsl #1]%x"}, |
1297 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af8500, 0xffffff00, "cpsie\t%7'a%6'i%5'f, #%0-4d%X"}, |
1298 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3af8700, 0xffffff00, "cpsid\t%7'a%6'i%5'f, #%0-4d%X"}, |
1299 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3de8f00, 0xffffff00, "subs%c\tpc, lr, #%0-7d"}, |
1300 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3808000, 0xffe0f000, "msr%c\t%C, %16-19r"}, |
1301 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8500f00, 0xfff00fff, "ldrex%c\t%12-15r, [%16-19r]"}, |
1302 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8d00f4f, 0xfff00fef, "ldrex%4?hb%c\t%12-15r, [%16-19r]"}, |
1303 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe800c000, 0xffd0ffe0, "srsdb%c\t%16-19r%21'!, #%0-4d"}, |
1304 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe980c000, 0xffd0ffe0, "srsia%c\t%16-19r%21'!, #%0-4d"}, |
1305 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa0ff080, 0xfffff0c0, "sxth%c.w\t%8-11r, %0-3r%R"}, |
1306 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa1ff080, 0xfffff0c0, "uxth%c.w\t%8-11r, %0-3r%R"}, |
1307 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa2ff080, 0xfffff0c0, "sxtb16%c\t%8-11r, %0-3r%R"}, |
1308 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa3ff080, 0xfffff0c0, "uxtb16%c\t%8-11r, %0-3r%R"}, |
1309 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa4ff080, 0xfffff0c0, "sxtb%c.w\t%8-11r, %0-3r%R"}, |
1310 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa5ff080, 0xfffff0c0, "uxtb%c.w\t%8-11r, %0-3r%R"}, |
1311 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8400000, 0xfff000ff, "strex%c\t%8-11r, %12-15r, [%16-19r]"}, |
1312 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8d0007f, 0xfff000ff, "ldrexd%c\t%12-15r, %8-11r, [%16-19r]"}, |
1313 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa80f000, 0xfff0f0f0, "sadd8%c\t%8-11r, %16-19r, %0-3r"}, |
1314 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa80f010, 0xfff0f0f0, "qadd8%c\t%8-11r, %16-19r, %0-3r"}, |
1315 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa80f020, 0xfff0f0f0, "shadd8%c\t%8-11r, %16-19r, %0-3r"}, |
1316 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa80f040, 0xfff0f0f0, "uadd8%c\t%8-11r, %16-19r, %0-3r"}, |
1317 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa80f050, 0xfff0f0f0, "uqadd8%c\t%8-11r, %16-19r, %0-3r"}, |
1318 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa80f060, 0xfff0f0f0, "uhadd8%c\t%8-11r, %16-19r, %0-3r"}, |
1319 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa80f080, 0xfff0f0f0, "qadd%c\t%8-11r, %0-3r, %16-19r"}, |
1320 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa80f090, 0xfff0f0f0, "qdadd%c\t%8-11r, %0-3r, %16-19r"}, |
1321 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa80f0a0, 0xfff0f0f0, "qsub%c\t%8-11r, %0-3r, %16-19r"}, |
1322 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa80f0b0, 0xfff0f0f0, "qdsub%c\t%8-11r, %0-3r, %16-19r"}, |
1323 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa90f000, 0xfff0f0f0, "sadd16%c\t%8-11r, %16-19r, %0-3r"}, |
1324 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa90f010, 0xfff0f0f0, "qadd16%c\t%8-11r, %16-19r, %0-3r"}, |
1325 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa90f020, 0xfff0f0f0, "shadd16%c\t%8-11r, %16-19r, %0-3r"}, |
1326 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa90f040, 0xfff0f0f0, "uadd16%c\t%8-11r, %16-19r, %0-3r"}, |
1327 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa90f050, 0xfff0f0f0, "uqadd16%c\t%8-11r, %16-19r, %0-3r"}, |
1328 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa90f060, 0xfff0f0f0, "uhadd16%c\t%8-11r, %16-19r, %0-3r"}, |
1329 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa90f080, 0xfff0f0f0, "rev%c.w\t%8-11r, %16-19r"}, |
1330 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa90f090, 0xfff0f0f0, "rev16%c.w\t%8-11r, %16-19r"}, |
1331 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa90f0a0, 0xfff0f0f0, "rbit%c\t%8-11r, %16-19r"}, |
1332 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa90f0b0, 0xfff0f0f0, "revsh%c.w\t%8-11r, %16-19r"}, |
1333 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfaa0f000, 0xfff0f0f0, "saddsubx%c\t%8-11r, %16-19r, %0-3r"}, |
1334 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfaa0f010, 0xfff0f0f0, "qaddsubx%c\t%8-11r, %16-19r, %0-3r"}, |
1335 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfaa0f020, 0xfff0f0f0, "shaddsubx%c\t%8-11r, %16-19r, %0-3r"}, |
1336 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfaa0f040, 0xfff0f0f0, "uaddsubx%c\t%8-11r, %16-19r, %0-3r"}, |
1337 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfaa0f050, 0xfff0f0f0, "uqaddsubx%c\t%8-11r, %16-19r, %0-3r"}, |
1338 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfaa0f060, 0xfff0f0f0, "uhaddsubx%c\t%8-11r, %16-19r, %0-3r"}, |
1339 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfaa0f080, 0xfff0f0f0, "sel%c\t%8-11r, %16-19r, %0-3r"}, |
1340 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfab0f080, 0xfff0f0f0, "clz%c\t%8-11r, %16-19r"}, |
1341 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfac0f000, 0xfff0f0f0, "ssub8%c\t%8-11r, %16-19r, %0-3r"}, |
1342 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfac0f010, 0xfff0f0f0, "qsub8%c\t%8-11r, %16-19r, %0-3r"}, |
1343 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfac0f020, 0xfff0f0f0, "shsub8%c\t%8-11r, %16-19r, %0-3r"}, |
1344 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfac0f040, 0xfff0f0f0, "usub8%c\t%8-11r, %16-19r, %0-3r"}, |
1345 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfac0f050, 0xfff0f0f0, "uqsub8%c\t%8-11r, %16-19r, %0-3r"}, |
1346 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfac0f060, 0xfff0f0f0, "uhsub8%c\t%8-11r, %16-19r, %0-3r"}, |
1347 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfad0f000, 0xfff0f0f0, "ssub16%c\t%8-11r, %16-19r, %0-3r"}, |
1348 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfad0f010, 0xfff0f0f0, "qsub16%c\t%8-11r, %16-19r, %0-3r"}, |
1349 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfad0f020, 0xfff0f0f0, "shsub16%c\t%8-11r, %16-19r, %0-3r"}, |
1350 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfad0f040, 0xfff0f0f0, "usub16%c\t%8-11r, %16-19r, %0-3r"}, |
1351 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfad0f050, 0xfff0f0f0, "uqsub16%c\t%8-11r, %16-19r, %0-3r"}, |
1352 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfad0f060, 0xfff0f0f0, "uhsub16%c\t%8-11r, %16-19r, %0-3r"}, |
1353 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfae0f000, 0xfff0f0f0, "ssubaddx%c\t%8-11r, %16-19r, %0-3r"}, |
1354 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfae0f010, 0xfff0f0f0, "qsubaddx%c\t%8-11r, %16-19r, %0-3r"}, |
1355 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfae0f020, 0xfff0f0f0, "shsubaddx%c\t%8-11r, %16-19r, %0-3r"}, |
1356 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfae0f040, 0xfff0f0f0, "usubaddx%c\t%8-11r, %16-19r, %0-3r"}, |
1357 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfae0f050, 0xfff0f0f0, "uqsubaddx%c\t%8-11r, %16-19r, %0-3r"}, |
1358 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfae0f060, 0xfff0f0f0, "uhsubaddx%c\t%8-11r, %16-19r, %0-3r"}, |
1359 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb00f000, 0xfff0f0f0, "mul%c.w\t%8-11r, %16-19r, %0-3r"}, |
1360 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb70f000, 0xfff0f0f0, "usad8%c\t%8-11r, %16-19r, %0-3r"}, |
1361 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa00f000, 0xffe0f0f0, "lsl%20's%c.w\t%8-11r, %16-19r, %0-3r"}, |
1362 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa20f000, 0xffe0f0f0, "lsr%20's%c.w\t%8-11r, %16-19r, %0-3r"}, |
1363 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa40f000, 0xffe0f0f0, "asr%20's%c.w\t%8-11r, %16-19r, %0-3r"}, |
1364 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa60f000, 0xffe0f0f0, "ror%20's%c.w\t%8-11r, %16-19r, %0-3r"}, |
1365 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8c00f40, 0xfff00fe0, "strex%4?hb%c\t%0-3r, %12-15r, [%16-19r]"}, |
1366 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3200000, 0xfff0f0e0, "ssat16%c\t%8-11r, #%0-4d, %16-19r"}, |
1367 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3a00000, 0xfff0f0e0, "usat16%c\t%8-11r, #%0-4d, %16-19r"}, |
1368 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb20f000, 0xfff0f0e0, "smuad%4'x%c\t%8-11r, %16-19r, %0-3r"}, |
1369 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb30f000, 0xfff0f0e0, "smulw%4?tb%c\t%8-11r, %16-19r, %0-3r"}, |
1370 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb40f000, 0xfff0f0e0, "smusd%4'x%c\t%8-11r, %16-19r, %0-3r"}, |
1371 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb50f000, 0xfff0f0e0, "smmul%4'r%c\t%8-11r, %16-19r, %0-3r"}, |
1372 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa00f080, 0xfff0f0c0, "sxtah%c\t%8-11r, %16-19r, %0-3r%R"}, |
1373 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa10f080, 0xfff0f0c0, "uxtah%c\t%8-11r, %16-19r, %0-3r%R"}, |
1374 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa20f080, 0xfff0f0c0, "sxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, |
1375 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa30f080, 0xfff0f0c0, "uxtab16%c\t%8-11r, %16-19r, %0-3r%R"}, |
1376 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa40f080, 0xfff0f0c0, "sxtab%c\t%8-11r, %16-19r, %0-3r%R"}, |
1377 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfa50f080, 0xfff0f0c0, "uxtab%c\t%8-11r, %16-19r, %0-3r%R"}, |
1378 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb10f000, 0xfff0f0c0, "smul%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r"}, |
1379 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf36f0000, 0xffff8020, "bfc%c\t%8-11r, %E"}, |
1380 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xea100f00, 0xfff08f00, "tst%c.w\t%16-19r, %S"}, |
1381 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xea900f00, 0xfff08f00, "teq%c\t%16-19r, %S"}, |
1382 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xeb100f00, 0xfff08f00, "cmn%c.w\t%16-19r, %S"}, |
1383 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xebb00f00, 0xfff08f00, "cmp%c.w\t%16-19r, %S"}, |
1384 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf0100f00, 0xfbf08f00, "tst%c.w\t%16-19r, %M"}, |
1385 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf0900f00, 0xfbf08f00, "teq%c\t%16-19r, %M"}, |
1386 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf1100f00, 0xfbf08f00, "cmn%c.w\t%16-19r, %M"}, |
1387 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf1b00f00, 0xfbf08f00, "cmp%c.w\t%16-19r, %M"}, |
1388 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xea4f0000, 0xffef8000, "mov%20's%c.w\t%8-11r, %S"}, |
1389 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xea6f0000, 0xffef8000, "mvn%20's%c.w\t%8-11r, %S"}, |
1390 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8c00070, 0xfff000f0, "strexd%c\t%0-3r, %12-15r, %8-11r, [%16-19r]"}, |
1391 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb000000, 0xfff000f0, "mla%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, |
1392 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb000010, 0xfff000f0, "mls%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, |
1393 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb700000, 0xfff000f0, "usada8%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, |
1394 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb800000, 0xfff000f0, "smull%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, |
1395 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfba00000, 0xfff000f0, "umull%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, |
1396 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfbc00000, 0xfff000f0, "smlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, |
1397 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfbe00000, 0xfff000f0, "umlal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, |
1398 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfbe00060, 0xfff000f0, "umaal%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, |
1399 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8500f00, 0xfff00f00, "ldrex%c\t%12-15r, [%16-19r, #%0-7W]"}, |
1400 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf7f08000, 0xfff0f000, "smc%c\t%K"}, |
1401 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf04f0000, 0xfbef8000, "mov%20's%c.w\t%8-11r, %M"}, |
1402 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf06f0000, 0xfbef8000, "mvn%20's%c.w\t%8-11r, %M"}, |
1403 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf810f000, 0xff70f000, "pld%c\t%a"}, |
1404 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb200000, 0xfff000e0, "smlad%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, |
1405 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb300000, 0xfff000e0, "smlaw%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, |
1406 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb400000, 0xfff000e0, "smlsd%4'x%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, |
1407 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb500000, 0xfff000e0, "smmla%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, |
1408 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb600000, 0xfff000e0, "smmls%4'r%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, |
1409 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfbc000c0, 0xfff000e0, "smlald%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, |
1410 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfbd000c0, 0xfff000e0, "smlsld%4'x%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, |
1411 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xeac00000, 0xfff08030, "pkhbt%c\t%8-11r, %16-19r, %S"}, |
1412 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xeac00020, 0xfff08030, "pkhtb%c\t%8-11r, %16-19r, %S"}, |
1413 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3400000, 0xfff08020, "sbfx%c\t%8-11r, %16-19r, %F"}, |
1414 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3c00000, 0xfff08020, "ubfx%c\t%8-11r, %16-19r, %F"}, |
1415 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf8000e00, 0xff900f00, "str%wt%c\t%12-15r, %a"}, |
1416 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfb100000, 0xfff000c0, "smla%5?tb%4?tb%c\t%8-11r, %16-19r, %0-3r, %12-15r"}, |
1417 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xfbc00080, 0xfff000c0, "smlal%5?tb%4?tb%c\t%12-15r, %8-11r, %16-19r, %0-3r"}, |
1418 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3600000, 0xfff08020, "bfi%c\t%8-11r, %16-19r, %E"}, |
1419 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf8100e00, 0xfe900f00, "ldr%wt%c\t%12-15r, %a"}, |
1420 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3000000, 0xffd08020, "ssat%c\t%8-11r, #%0-4d, %16-19r%s"}, |
1421 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3800000, 0xffd08020, "usat%c\t%8-11r, #%0-4d, %16-19r%s"}, |
1422 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf2000000, 0xfbf08000, "addw%c\t%8-11r, %16-19r, %I"}, |
1423 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf2400000, 0xfbf08000, "movw%c\t%8-11r, %J"}, |
1424 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf2a00000, 0xfbf08000, "subw%c\t%8-11r, %16-19r, %I"}, |
1425 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf2c00000, 0xfbf08000, "movt%c\t%8-11r, %J"}, |
1426 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xea000000, 0xffe08000, "and%20's%c.w\t%8-11r, %16-19r, %S"}, |
1427 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xea200000, 0xffe08000, "bic%20's%c.w\t%8-11r, %16-19r, %S"}, |
1428 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xea400000, 0xffe08000, "orr%20's%c.w\t%8-11r, %16-19r, %S"}, |
1429 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xea600000, 0xffe08000, "orn%20's%c\t%8-11r, %16-19r, %S"}, |
1430 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xea800000, 0xffe08000, "eor%20's%c.w\t%8-11r, %16-19r, %S"}, |
1431 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xeb000000, 0xffe08000, "add%20's%c.w\t%8-11r, %16-19r, %S"}, |
1432 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xeb400000, 0xffe08000, "adc%20's%c.w\t%8-11r, %16-19r, %S"}, |
1433 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xeb600000, 0xffe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %S"}, |
1434 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xeba00000, 0xffe08000, "sub%20's%c.w\t%8-11r, %16-19r, %S"}, |
1435 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xebc00000, 0xffe08000, "rsb%20's%c\t%8-11r, %16-19r, %S"}, |
1436 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8400000, 0xfff00000, "strex%c\t%8-11r, %12-15r, [%16-19r, #%0-7W]"}, |
1437 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf0000000, 0xfbe08000, "and%20's%c.w\t%8-11r, %16-19r, %M"}, |
1438 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf0200000, 0xfbe08000, "bic%20's%c.w\t%8-11r, %16-19r, %M"}, |
1439 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf0400000, 0xfbe08000, "orr%20's%c.w\t%8-11r, %16-19r, %M"}, |
1440 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf0600000, 0xfbe08000, "orn%20's%c\t%8-11r, %16-19r, %M"}, |
1441 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf0800000, 0xfbe08000, "eor%20's%c.w\t%8-11r, %16-19r, %M"}, |
1442 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf1000000, 0xfbe08000, "add%20's%c.w\t%8-11r, %16-19r, %M"}, |
1443 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf1400000, 0xfbe08000, "adc%20's%c.w\t%8-11r, %16-19r, %M"}, |
1444 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf1600000, 0xfbe08000, "sbc%20's%c.w\t%8-11r, %16-19r, %M"}, |
1445 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf1a00000, 0xfbe08000, "sub%20's%c.w\t%8-11r, %16-19r, %M"}, |
1446 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf1c00000, 0xfbe08000, "rsb%20's%c\t%8-11r, %16-19r, %M"}, |
1447 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8800000, 0xffd00000, "stmia%c.w\t%16-19r%21'!, %m"}, |
1448 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8900000, 0xffd00000, "ldmia%c.w\t%16-19r%21'!, %m"}, |
1449 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe9000000, 0xffd00000, "stmdb%c\t%16-19r%21'!, %m"}, |
1450 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe9100000, 0xffd00000, "ldmdb%c\t%16-19r%21'!, %m"}, |
1451 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe9c00000, 0xffd000ff, "strd%c\t%12-15r, %8-11r, [%16-19r]"}, |
1452 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe9d00000, 0xffd000ff, "ldrd%c\t%12-15r, %8-11r, [%16-19r]"}, |
1453 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe9400000, 0xff500000, "strd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, |
1454 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe9500000, 0xff500000, "ldrd%c\t%12-15r, %8-11r, [%16-19r, #%23`-%0-7W]%21'!"}, |
1455 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8600000, 0xff700000, "strd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, |
1456 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xe8700000, 0xff700000, "ldrd%c\t%12-15r, %8-11r, [%16-19r], #%23`-%0-7W"}, |
1457 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf8000000, 0xff100000, "str%w%c.w\t%12-15r, %a"}, |
1458 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf8100000, 0xfe100000, "ldr%w%c.w\t%12-15r, %a"}, |
1459 | 4b0f1a8b | pbrook | |
1460 | 4b0f1a8b | pbrook | /* Filter out Bcc with cond=E or F, which are used for other instructions. */
|
1461 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3c08000, 0xfbc0d000, "undefined (bcc, cond=0xF)"}, |
1462 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf3808000, 0xfbc0d000, "undefined (bcc, cond=0xE)"}, |
1463 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf0008000, 0xf800d000, "b%22-25c.w\t%b%X"}, |
1464 | 4b0f1a8b | pbrook | {ARM_EXT_V6T2, 0xf0009000, 0xf800d000, "b%c.w\t%B%x"}, |
1465 | 4b0f1a8b | pbrook | |
1466 | 4b0f1a8b | pbrook | /* These have been 32-bit since the invention of Thumb. */
|
1467 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xf000c000, 0xf800d000, "blx%c\t%B%x"}, |
1468 | 4b0f1a8b | pbrook | {ARM_EXT_V4T, 0xf000d000, 0xf800d000, "bl%c\t%B%x"}, |
1469 | 4b0f1a8b | pbrook | |
1470 | 4b0f1a8b | pbrook | /* Fallback. */
|
1471 | 4b0f1a8b | pbrook | {ARM_EXT_V1, 0x00000000, 0x00000000, "undefined"}, |
1472 | 4b0f1a8b | pbrook | {0, 0, 0, 0} |
1473 | 4b0f1a8b | pbrook | }; |
1474 | aa0aa4fa | bellard | |
1475 | 4b0f1a8b | pbrook | static const char *const arm_conditional[] = |
1476 | 4b0f1a8b | pbrook | {"eq", "ne", "cs", "cc", "mi", "pl", "vs", "vc", |
1477 | 4b0f1a8b | pbrook | "hi", "ls", "ge", "lt", "gt", "le", "al", "<und>", ""}; |
1478 | aa0aa4fa | bellard | |
1479 | 4b0f1a8b | pbrook | static const char *const arm_fp_const[] = |
1480 | 4b0f1a8b | pbrook | {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; |
1481 | aa0aa4fa | bellard | |
1482 | 4b0f1a8b | pbrook | static const char *const arm_shift[] = |
1483 | 4b0f1a8b | pbrook | {"lsl", "lsr", "asr", "ror"}; |
1484 | aa0aa4fa | bellard | |
1485 | aa0aa4fa | bellard | typedef struct |
1486 | aa0aa4fa | bellard | { |
1487 | 4b0f1a8b | pbrook | const char *name; |
1488 | 4b0f1a8b | pbrook | const char *description; |
1489 | 4b0f1a8b | pbrook | const char *reg_names[16]; |
1490 | aa0aa4fa | bellard | } |
1491 | aa0aa4fa | bellard | arm_regname; |
1492 | aa0aa4fa | bellard | |
1493 | 4b0f1a8b | pbrook | static const arm_regname regnames[] = |
1494 | aa0aa4fa | bellard | { |
1495 | aa0aa4fa | bellard | { "raw" , "Select raw register names", |
1496 | aa0aa4fa | bellard | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}}, |
1497 | aa0aa4fa | bellard | { "gcc", "Select register names used by GCC", |
1498 | aa0aa4fa | bellard | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }}, |
1499 | aa0aa4fa | bellard | { "std", "Select register names used in ARM's ISA documentation", |
1500 | aa0aa4fa | bellard | { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }}, |
1501 | aa0aa4fa | bellard | { "apcs", "Select register names used in the APCS", |
1502 | aa0aa4fa | bellard | { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }}, |
1503 | aa0aa4fa | bellard | { "atpcs", "Select register names used in the ATPCS", |
1504 | aa0aa4fa | bellard | { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, |
1505 | aa0aa4fa | bellard | { "special-atpcs", "Select special register names used in the ATPCS", |
1506 | 4b0f1a8b | pbrook | { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, |
1507 | 4b0f1a8b | pbrook | }; |
1508 | 4b0f1a8b | pbrook | |
1509 | 4b0f1a8b | pbrook | static const char *const iwmmxt_wwnames[] = |
1510 | 4b0f1a8b | pbrook | {"b", "h", "w", "d"}; |
1511 | 4b0f1a8b | pbrook | |
1512 | 4b0f1a8b | pbrook | static const char *const iwmmxt_wwssnames[] = |
1513 | 4b0f1a8b | pbrook | {"b", "bus", "bc", "bss", |
1514 | 4b0f1a8b | pbrook | "h", "hus", "hc", "hss", |
1515 | 4b0f1a8b | pbrook | "w", "wus", "wc", "wss", |
1516 | 4b0f1a8b | pbrook | "d", "dus", "dc", "dss" |
1517 | aa0aa4fa | bellard | }; |
1518 | aa0aa4fa | bellard | |
1519 | 4b0f1a8b | pbrook | static const char *const iwmmxt_regnames[] = |
1520 | 4b0f1a8b | pbrook | { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", |
1521 | 4b0f1a8b | pbrook | "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15" |
1522 | 4b0f1a8b | pbrook | }; |
1523 | 4b0f1a8b | pbrook | |
1524 | 4b0f1a8b | pbrook | static const char *const iwmmxt_cregnames[] = |
1525 | 4b0f1a8b | pbrook | { "wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", |
1526 | 4b0f1a8b | pbrook | "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved" |
1527 | 4b0f1a8b | pbrook | }; |
1528 | 4b0f1a8b | pbrook | |
1529 | 4b0f1a8b | pbrook | /* Default to GCC register name set. */
|
1530 | 4b0f1a8b | pbrook | static unsigned int regname_selected = 1; |
1531 | aa0aa4fa | bellard | |
1532 | aa0aa4fa | bellard | #define NUM_ARM_REGNAMES NUM_ELEM (regnames)
|
1533 | aa0aa4fa | bellard | #define arm_regnames regnames[regname_selected].reg_names
|
1534 | aa0aa4fa | bellard | |
1535 | 4b0f1a8b | pbrook | static bfd_boolean force_thumb = FALSE;
|
1536 | 4b0f1a8b | pbrook | |
1537 | 4b0f1a8b | pbrook | /* Current IT instruction state. This contains the same state as the IT
|
1538 | 4b0f1a8b | pbrook | bits in the CPSR. */
|
1539 | 4b0f1a8b | pbrook | static unsigned int ifthen_state; |
1540 | 4b0f1a8b | pbrook | /* IT state for the next instruction. */
|
1541 | 4b0f1a8b | pbrook | static unsigned int ifthen_next_state; |
1542 | 4b0f1a8b | pbrook | /* The address of the insn for which the IT state is valid. */
|
1543 | 4b0f1a8b | pbrook | static bfd_vma ifthen_address;
|
1544 | 4b0f1a8b | pbrook | #define IFTHEN_COND ((ifthen_state >> 4) & 0xf) |
1545 | 4b0f1a8b | pbrook | |
1546 | 4b0f1a8b | pbrook | /* Cached mapping symbol state. */
|
1547 | 4b0f1a8b | pbrook | enum map_type {
|
1548 | 4b0f1a8b | pbrook | MAP_ARM, |
1549 | 4b0f1a8b | pbrook | MAP_THUMB, |
1550 | 4b0f1a8b | pbrook | MAP_DATA |
1551 | 4b0f1a8b | pbrook | }; |
1552 | aa0aa4fa | bellard | |
1553 | 4b0f1a8b | pbrook | enum map_type last_type;
|
1554 | 4b0f1a8b | pbrook | int last_mapping_sym = -1; |
1555 | 4b0f1a8b | pbrook | bfd_vma last_mapping_addr = 0;
|
1556 | aa0aa4fa | bellard | |
1557 | aa0aa4fa | bellard | |
1558 | aa0aa4fa | bellard | /* Functions. */
|
1559 | aa0aa4fa | bellard | int
|
1560 | 4b0f1a8b | pbrook | get_arm_regname_num_options (void)
|
1561 | aa0aa4fa | bellard | { |
1562 | aa0aa4fa | bellard | return NUM_ARM_REGNAMES;
|
1563 | aa0aa4fa | bellard | } |
1564 | aa0aa4fa | bellard | |
1565 | aa0aa4fa | bellard | int
|
1566 | 4b0f1a8b | pbrook | set_arm_regname_option (int option)
|
1567 | aa0aa4fa | bellard | { |
1568 | aa0aa4fa | bellard | int old = regname_selected;
|
1569 | aa0aa4fa | bellard | regname_selected = option; |
1570 | aa0aa4fa | bellard | return old;
|
1571 | aa0aa4fa | bellard | } |
1572 | aa0aa4fa | bellard | |
1573 | aa0aa4fa | bellard | int
|
1574 | 4b0f1a8b | pbrook | get_arm_regnames (int option, const char **setname, const char **setdescription, |
1575 | 4b0f1a8b | pbrook | const char *const **register_names) |
1576 | aa0aa4fa | bellard | { |
1577 | aa0aa4fa | bellard | *setname = regnames[option].name; |
1578 | aa0aa4fa | bellard | *setdescription = regnames[option].description; |
1579 | aa0aa4fa | bellard | *register_names = regnames[option].reg_names; |
1580 | aa0aa4fa | bellard | return 16; |
1581 | aa0aa4fa | bellard | } |
1582 | aa0aa4fa | bellard | |
1583 | 4b0f1a8b | pbrook | /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
|
1584 | 4b0f1a8b | pbrook | Returns pointer to following character of the format string and
|
1585 | 4b0f1a8b | pbrook | fills in *VALUEP and *WIDTHP with the extracted value and number of
|
1586 | 4b0f1a8b | pbrook | bits extracted. WIDTHP can be NULL. */
|
1587 | 4b0f1a8b | pbrook | |
1588 | 4b0f1a8b | pbrook | static const char * |
1589 | 4b0f1a8b | pbrook | arm_decode_bitfield (const char *ptr, unsigned long insn, |
1590 | 4b0f1a8b | pbrook | unsigned long *valuep, int *widthp) |
1591 | 4b0f1a8b | pbrook | { |
1592 | 4b0f1a8b | pbrook | unsigned long value = 0; |
1593 | 4b0f1a8b | pbrook | int width = 0; |
1594 | 4b0f1a8b | pbrook | |
1595 | 4b0f1a8b | pbrook | do
|
1596 | 4b0f1a8b | pbrook | { |
1597 | 4b0f1a8b | pbrook | int start, end;
|
1598 | 4b0f1a8b | pbrook | int bits;
|
1599 | 4b0f1a8b | pbrook | |
1600 | 4b0f1a8b | pbrook | for (start = 0; *ptr >= '0' && *ptr <= '9'; ptr++) |
1601 | 4b0f1a8b | pbrook | start = start * 10 + *ptr - '0'; |
1602 | 4b0f1a8b | pbrook | if (*ptr == '-') |
1603 | 4b0f1a8b | pbrook | for (end = 0, ptr++; *ptr >= '0' && *ptr <= '9'; ptr++) |
1604 | 4b0f1a8b | pbrook | end = end * 10 + *ptr - '0'; |
1605 | 4b0f1a8b | pbrook | else
|
1606 | 4b0f1a8b | pbrook | end = start; |
1607 | 4b0f1a8b | pbrook | bits = end - start; |
1608 | 4b0f1a8b | pbrook | if (bits < 0) |
1609 | 4b0f1a8b | pbrook | abort (); |
1610 | 4b0f1a8b | pbrook | value |= ((insn >> start) & ((2ul << bits) - 1)) << width; |
1611 | 4b0f1a8b | pbrook | width += bits + 1;
|
1612 | 4b0f1a8b | pbrook | } |
1613 | 4b0f1a8b | pbrook | while (*ptr++ == ','); |
1614 | 4b0f1a8b | pbrook | *valuep = value; |
1615 | 4b0f1a8b | pbrook | if (widthp)
|
1616 | 4b0f1a8b | pbrook | *widthp = width; |
1617 | 4b0f1a8b | pbrook | return ptr - 1; |
1618 | 4b0f1a8b | pbrook | } |
1619 | 4b0f1a8b | pbrook | |
1620 | aa0aa4fa | bellard | static void |
1621 | 4b0f1a8b | pbrook | arm_decode_shift (long given, fprintf_ftype func, void *stream, |
1622 | 4b0f1a8b | pbrook | int print_shift)
|
1623 | aa0aa4fa | bellard | { |
1624 | aa0aa4fa | bellard | func (stream, "%s", arm_regnames[given & 0xf]); |
1625 | 3b46e624 | ths | |
1626 | aa0aa4fa | bellard | if ((given & 0xff0) != 0) |
1627 | aa0aa4fa | bellard | { |
1628 | aa0aa4fa | bellard | if ((given & 0x10) == 0) |
1629 | aa0aa4fa | bellard | { |
1630 | aa0aa4fa | bellard | int amount = (given & 0xf80) >> 7; |
1631 | aa0aa4fa | bellard | int shift = (given & 0x60) >> 5; |
1632 | 3b46e624 | ths | |
1633 | aa0aa4fa | bellard | if (amount == 0) |
1634 | aa0aa4fa | bellard | { |
1635 | aa0aa4fa | bellard | if (shift == 3) |
1636 | aa0aa4fa | bellard | { |
1637 | aa0aa4fa | bellard | func (stream, ", rrx");
|
1638 | aa0aa4fa | bellard | return;
|
1639 | aa0aa4fa | bellard | } |
1640 | 3b46e624 | ths | |
1641 | aa0aa4fa | bellard | amount = 32;
|
1642 | aa0aa4fa | bellard | } |
1643 | 3b46e624 | ths | |
1644 | 4b0f1a8b | pbrook | if (print_shift)
|
1645 | 4b0f1a8b | pbrook | func (stream, ", %s #%d", arm_shift[shift], amount);
|
1646 | 4b0f1a8b | pbrook | else
|
1647 | 4b0f1a8b | pbrook | func (stream, ", #%d", amount);
|
1648 | aa0aa4fa | bellard | } |
1649 | 4b0f1a8b | pbrook | else if (print_shift) |
1650 | aa0aa4fa | bellard | func (stream, ", %s %s", arm_shift[(given & 0x60) >> 5], |
1651 | aa0aa4fa | bellard | arm_regnames[(given & 0xf00) >> 8]); |
1652 | 4b0f1a8b | pbrook | else
|
1653 | 4b0f1a8b | pbrook | func (stream, ", %s", arm_regnames[(given & 0xf00) >> 8]); |
1654 | aa0aa4fa | bellard | } |
1655 | aa0aa4fa | bellard | } |
1656 | aa0aa4fa | bellard | |
1657 | 4b0f1a8b | pbrook | /* Print one coprocessor instruction on INFO->STREAM.
|
1658 | 4b0f1a8b | pbrook | Return TRUE if the instuction matched, FALSE if this is not a
|
1659 | 4b0f1a8b | pbrook | recognised coprocessor instruction. */
|
1660 | aa0aa4fa | bellard | |
1661 | 4b0f1a8b | pbrook | static bfd_boolean
|
1662 | 4b0f1a8b | pbrook | print_insn_coprocessor (bfd_vma pc, struct disassemble_info *info, long given, |
1663 | 4b0f1a8b | pbrook | bfd_boolean thumb) |
1664 | aa0aa4fa | bellard | { |
1665 | 4b0f1a8b | pbrook | const struct opcode32 *insn; |
1666 | 4b0f1a8b | pbrook | void *stream = info->stream;
|
1667 | 4b0f1a8b | pbrook | fprintf_ftype func = info->fprintf_func; |
1668 | 4b0f1a8b | pbrook | unsigned long mask; |
1669 | 4b0f1a8b | pbrook | unsigned long value; |
1670 | 4b0f1a8b | pbrook | int cond;
|
1671 | 4b0f1a8b | pbrook | |
1672 | 4b0f1a8b | pbrook | for (insn = coprocessor_opcodes; insn->assembler; insn++)
|
1673 | aa0aa4fa | bellard | { |
1674 | 4b0f1a8b | pbrook | if (insn->value == FIRST_IWMMXT_INSN
|
1675 | 4b0f1a8b | pbrook | && info->mach != bfd_mach_arm_XScale |
1676 | 4b0f1a8b | pbrook | && info->mach != bfd_mach_arm_iWMMXt |
1677 | 4b0f1a8b | pbrook | && info->mach != bfd_mach_arm_iWMMXt2) |
1678 | 4b0f1a8b | pbrook | insn = insn + IWMMXT_INSN_COUNT; |
1679 | 4b0f1a8b | pbrook | |
1680 | 4b0f1a8b | pbrook | mask = insn->mask; |
1681 | 4b0f1a8b | pbrook | value = insn->value; |
1682 | 4b0f1a8b | pbrook | if (thumb)
|
1683 | 4b0f1a8b | pbrook | { |
1684 | 4b0f1a8b | pbrook | /* The high 4 bits are 0xe for Arm conditional instructions, and
|
1685 | 4b0f1a8b | pbrook | 0xe for arm unconditional instructions. The rest of the
|
1686 | 4b0f1a8b | pbrook | encoding is the same. */
|
1687 | 4b0f1a8b | pbrook | mask |= 0xf0000000;
|
1688 | 4b0f1a8b | pbrook | value |= 0xe0000000;
|
1689 | 4b0f1a8b | pbrook | if (ifthen_state)
|
1690 | 4b0f1a8b | pbrook | cond = IFTHEN_COND; |
1691 | 4b0f1a8b | pbrook | else
|
1692 | 4b0f1a8b | pbrook | cond = 16;
|
1693 | 4b0f1a8b | pbrook | } |
1694 | 4b0f1a8b | pbrook | else
|
1695 | 4b0f1a8b | pbrook | { |
1696 | 4b0f1a8b | pbrook | /* Only match unconditional instuctions against unconditional
|
1697 | 4b0f1a8b | pbrook | patterns. */
|
1698 | 4b0f1a8b | pbrook | if ((given & 0xf0000000) == 0xf0000000) |
1699 | 4b0f1a8b | pbrook | { |
1700 | 4b0f1a8b | pbrook | mask |= 0xf0000000;
|
1701 | 4b0f1a8b | pbrook | cond = 16;
|
1702 | 4b0f1a8b | pbrook | } |
1703 | 4b0f1a8b | pbrook | else
|
1704 | 4b0f1a8b | pbrook | { |
1705 | 4b0f1a8b | pbrook | cond = (given >> 28) & 0xf; |
1706 | 4b0f1a8b | pbrook | if (cond == 0xe) |
1707 | 4b0f1a8b | pbrook | cond = 16;
|
1708 | 4b0f1a8b | pbrook | } |
1709 | 4b0f1a8b | pbrook | } |
1710 | 4b0f1a8b | pbrook | if ((given & mask) == value)
|
1711 | aa0aa4fa | bellard | { |
1712 | 4b0f1a8b | pbrook | const char *c; |
1713 | 3b46e624 | ths | |
1714 | aa0aa4fa | bellard | for (c = insn->assembler; *c; c++)
|
1715 | aa0aa4fa | bellard | { |
1716 | aa0aa4fa | bellard | if (*c == '%') |
1717 | aa0aa4fa | bellard | { |
1718 | aa0aa4fa | bellard | switch (*++c)
|
1719 | aa0aa4fa | bellard | { |
1720 | aa0aa4fa | bellard | case '%': |
1721 | aa0aa4fa | bellard | func (stream, "%%");
|
1722 | aa0aa4fa | bellard | break;
|
1723 | aa0aa4fa | bellard | |
1724 | 4b0f1a8b | pbrook | case 'A': |
1725 | 4b0f1a8b | pbrook | func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); |
1726 | aa0aa4fa | bellard | |
1727 | 4b0f1a8b | pbrook | if ((given & (1 << 24)) != 0) |
1728 | 4b0f1a8b | pbrook | { |
1729 | 4b0f1a8b | pbrook | int offset = given & 0xff; |
1730 | aa0aa4fa | bellard | |
1731 | 4b0f1a8b | pbrook | if (offset)
|
1732 | 4b0f1a8b | pbrook | func (stream, ", #%s%d]%s",
|
1733 | 4b0f1a8b | pbrook | ((given & 0x00800000) == 0 ? "-" : ""), |
1734 | 4b0f1a8b | pbrook | offset * 4,
|
1735 | 4b0f1a8b | pbrook | ((given & 0x00200000) != 0 ? "!" : "")); |
1736 | aa0aa4fa | bellard | else
|
1737 | 4b0f1a8b | pbrook | func (stream, "]");
|
1738 | aa0aa4fa | bellard | } |
1739 | aa0aa4fa | bellard | else
|
1740 | aa0aa4fa | bellard | { |
1741 | 4b0f1a8b | pbrook | int offset = given & 0xff; |
1742 | aa0aa4fa | bellard | |
1743 | 4b0f1a8b | pbrook | func (stream, "]");
|
1744 | 4b0f1a8b | pbrook | |
1745 | 4b0f1a8b | pbrook | if (given & (1 << 21)) |
1746 | aa0aa4fa | bellard | { |
1747 | 4b0f1a8b | pbrook | if (offset)
|
1748 | 4b0f1a8b | pbrook | func (stream, ", #%s%d",
|
1749 | 4b0f1a8b | pbrook | ((given & 0x00800000) == 0 ? "-" : ""), |
1750 | 4b0f1a8b | pbrook | offset * 4);
|
1751 | aa0aa4fa | bellard | } |
1752 | 4b0f1a8b | pbrook | else
|
1753 | 4b0f1a8b | pbrook | func (stream, ", {%d}", offset);
|
1754 | aa0aa4fa | bellard | } |
1755 | aa0aa4fa | bellard | break;
|
1756 | aa0aa4fa | bellard | |
1757 | 4b0f1a8b | pbrook | case 'B': |
1758 | 4b0f1a8b | pbrook | { |
1759 | 4b0f1a8b | pbrook | int regno = ((given >> 12) & 0xf) | ((given >> (22 - 4)) & 0x10); |
1760 | 4b0f1a8b | pbrook | int offset = (given >> 1) & 0x3f; |
1761 | 4b0f1a8b | pbrook | |
1762 | 4b0f1a8b | pbrook | if (offset == 1) |
1763 | 4b0f1a8b | pbrook | func (stream, "{d%d}", regno);
|
1764 | 4b0f1a8b | pbrook | else if (regno + offset > 32) |
1765 | 4b0f1a8b | pbrook | func (stream, "{d%d-<overflow reg d%d>}", regno, regno + offset - 1); |
1766 | 4b0f1a8b | pbrook | else
|
1767 | 4b0f1a8b | pbrook | func (stream, "{d%d-d%d}", regno, regno + offset - 1); |
1768 | 4b0f1a8b | pbrook | } |
1769 | 4b0f1a8b | pbrook | break;
|
1770 | 3b46e624 | ths | |
1771 | 4b0f1a8b | pbrook | case 'C': |
1772 | 4b0f1a8b | pbrook | { |
1773 | 4b0f1a8b | pbrook | int rn = (given >> 16) & 0xf; |
1774 | 4b0f1a8b | pbrook | int offset = (given & 0xff) * 4; |
1775 | 4b0f1a8b | pbrook | int add = (given >> 23) & 1; |
1776 | 3b46e624 | ths | |
1777 | 4b0f1a8b | pbrook | func (stream, "[%s", arm_regnames[rn]);
|
1778 | 3b46e624 | ths | |
1779 | 4b0f1a8b | pbrook | if (offset)
|
1780 | 4b0f1a8b | pbrook | { |
1781 | 4b0f1a8b | pbrook | if (!add)
|
1782 | 4b0f1a8b | pbrook | offset = -offset; |
1783 | 4b0f1a8b | pbrook | func (stream, ", #%d", offset);
|
1784 | 4b0f1a8b | pbrook | } |
1785 | 4b0f1a8b | pbrook | func (stream, "]");
|
1786 | 4b0f1a8b | pbrook | if (rn == 15) |
1787 | 4b0f1a8b | pbrook | { |
1788 | 4b0f1a8b | pbrook | func (stream, "\t; ");
|
1789 | 4b0f1a8b | pbrook | /* FIXME: Unsure if info->bytes_per_chunk is the
|
1790 | 4b0f1a8b | pbrook | right thing to use here. */
|
1791 | 4b0f1a8b | pbrook | info->print_address_func (offset + pc |
1792 | 4b0f1a8b | pbrook | + info->bytes_per_chunk * 2, info);
|
1793 | 4b0f1a8b | pbrook | } |
1794 | 4b0f1a8b | pbrook | } |
1795 | 4b0f1a8b | pbrook | break;
|
1796 | aa0aa4fa | bellard | |
1797 | aa0aa4fa | bellard | case 'c': |
1798 | 4b0f1a8b | pbrook | func (stream, "%s", arm_conditional[cond]);
|
1799 | aa0aa4fa | bellard | break;
|
1800 | aa0aa4fa | bellard | |
1801 | aa0aa4fa | bellard | case 'I': |
1802 | aa0aa4fa | bellard | /* Print a Cirrus/DSP shift immediate. */
|
1803 | aa0aa4fa | bellard | /* Immediates are 7bit signed ints with bits 0..3 in
|
1804 | aa0aa4fa | bellard | bits 0..3 of opcode and bits 4..6 in bits 5..7
|
1805 | aa0aa4fa | bellard | of opcode. */
|
1806 | aa0aa4fa | bellard | { |
1807 | aa0aa4fa | bellard | int imm;
|
1808 | aa0aa4fa | bellard | |
1809 | aa0aa4fa | bellard | imm = (given & 0xf) | ((given & 0xe0) >> 1); |
1810 | aa0aa4fa | bellard | |
1811 | aa0aa4fa | bellard | /* Is ``imm'' a negative number? */
|
1812 | aa0aa4fa | bellard | if (imm & 0x40) |
1813 | aa0aa4fa | bellard | imm |= (-1 << 7); |
1814 | aa0aa4fa | bellard | |
1815 | aa0aa4fa | bellard | func (stream, "%d", imm);
|
1816 | aa0aa4fa | bellard | } |
1817 | aa0aa4fa | bellard | |
1818 | aa0aa4fa | bellard | break;
|
1819 | aa0aa4fa | bellard | |
1820 | aa0aa4fa | bellard | case 'F': |
1821 | aa0aa4fa | bellard | switch (given & 0x00408000) |
1822 | aa0aa4fa | bellard | { |
1823 | aa0aa4fa | bellard | case 0: |
1824 | aa0aa4fa | bellard | func (stream, "4");
|
1825 | aa0aa4fa | bellard | break;
|
1826 | aa0aa4fa | bellard | case 0x8000: |
1827 | aa0aa4fa | bellard | func (stream, "1");
|
1828 | aa0aa4fa | bellard | break;
|
1829 | aa0aa4fa | bellard | case 0x00400000: |
1830 | aa0aa4fa | bellard | func (stream, "2");
|
1831 | aa0aa4fa | bellard | break;
|
1832 | aa0aa4fa | bellard | default:
|
1833 | aa0aa4fa | bellard | func (stream, "3");
|
1834 | aa0aa4fa | bellard | } |
1835 | aa0aa4fa | bellard | break;
|
1836 | 3b46e624 | ths | |
1837 | aa0aa4fa | bellard | case 'P': |
1838 | aa0aa4fa | bellard | switch (given & 0x00080080) |
1839 | aa0aa4fa | bellard | { |
1840 | aa0aa4fa | bellard | case 0: |
1841 | aa0aa4fa | bellard | func (stream, "s");
|
1842 | aa0aa4fa | bellard | break;
|
1843 | aa0aa4fa | bellard | case 0x80: |
1844 | aa0aa4fa | bellard | func (stream, "d");
|
1845 | aa0aa4fa | bellard | break;
|
1846 | aa0aa4fa | bellard | case 0x00080000: |
1847 | aa0aa4fa | bellard | func (stream, "e");
|
1848 | aa0aa4fa | bellard | break;
|
1849 | aa0aa4fa | bellard | default:
|
1850 | aa0aa4fa | bellard | func (stream, _("<illegal precision>"));
|
1851 | aa0aa4fa | bellard | break;
|
1852 | aa0aa4fa | bellard | } |
1853 | aa0aa4fa | bellard | break;
|
1854 | aa0aa4fa | bellard | case 'Q': |
1855 | aa0aa4fa | bellard | switch (given & 0x00408000) |
1856 | aa0aa4fa | bellard | { |
1857 | aa0aa4fa | bellard | case 0: |
1858 | aa0aa4fa | bellard | func (stream, "s");
|
1859 | aa0aa4fa | bellard | break;
|
1860 | aa0aa4fa | bellard | case 0x8000: |
1861 | aa0aa4fa | bellard | func (stream, "d");
|
1862 | aa0aa4fa | bellard | break;
|
1863 | aa0aa4fa | bellard | case 0x00400000: |
1864 | aa0aa4fa | bellard | func (stream, "e");
|
1865 | aa0aa4fa | bellard | break;
|
1866 | aa0aa4fa | bellard | default:
|
1867 | aa0aa4fa | bellard | func (stream, "p");
|
1868 | aa0aa4fa | bellard | break;
|
1869 | aa0aa4fa | bellard | } |
1870 | aa0aa4fa | bellard | break;
|
1871 | aa0aa4fa | bellard | case 'R': |
1872 | aa0aa4fa | bellard | switch (given & 0x60) |
1873 | aa0aa4fa | bellard | { |
1874 | aa0aa4fa | bellard | case 0: |
1875 | aa0aa4fa | bellard | break;
|
1876 | aa0aa4fa | bellard | case 0x20: |
1877 | aa0aa4fa | bellard | func (stream, "p");
|
1878 | aa0aa4fa | bellard | break;
|
1879 | aa0aa4fa | bellard | case 0x40: |
1880 | aa0aa4fa | bellard | func (stream, "m");
|
1881 | aa0aa4fa | bellard | break;
|
1882 | aa0aa4fa | bellard | default:
|
1883 | aa0aa4fa | bellard | func (stream, "z");
|
1884 | aa0aa4fa | bellard | break;
|
1885 | aa0aa4fa | bellard | } |
1886 | aa0aa4fa | bellard | break;
|
1887 | aa0aa4fa | bellard | |
1888 | 5fafdf24 | ths | case '0': case '1': case '2': case '3': case '4': |
1889 | aa0aa4fa | bellard | case '5': case '6': case '7': case '8': case '9': |
1890 | aa0aa4fa | bellard | { |
1891 | 4b0f1a8b | pbrook | int width;
|
1892 | 4b0f1a8b | pbrook | unsigned long value; |
1893 | 4b0f1a8b | pbrook | |
1894 | 4b0f1a8b | pbrook | c = arm_decode_bitfield (c, given, &value, &width); |
1895 | aa0aa4fa | bellard | |
1896 | aa0aa4fa | bellard | switch (*c)
|
1897 | aa0aa4fa | bellard | { |
1898 | 4b0f1a8b | pbrook | case 'r': |
1899 | 4b0f1a8b | pbrook | func (stream, "%s", arm_regnames[value]);
|
1900 | 4b0f1a8b | pbrook | break;
|
1901 | 4b0f1a8b | pbrook | case 'D': |
1902 | 4b0f1a8b | pbrook | func (stream, "d%ld", value);
|
1903 | 4b0f1a8b | pbrook | break;
|
1904 | 4b0f1a8b | pbrook | case 'Q': |
1905 | 4b0f1a8b | pbrook | if (value & 1) |
1906 | 4b0f1a8b | pbrook | func (stream, "<illegal reg q%ld.5>", value >> 1); |
1907 | 4b0f1a8b | pbrook | else
|
1908 | 4b0f1a8b | pbrook | func (stream, "q%ld", value >> 1); |
1909 | 4b0f1a8b | pbrook | break;
|
1910 | 4b0f1a8b | pbrook | case 'd': |
1911 | 4b0f1a8b | pbrook | func (stream, "%ld", value);
|
1912 | 4b0f1a8b | pbrook | break;
|
1913 | 4b0f1a8b | pbrook | case 'k': |
1914 | 4b0f1a8b | pbrook | { |
1915 | 4b0f1a8b | pbrook | int from = (given & (1 << 7)) ? 32 : 16; |
1916 | 4b0f1a8b | pbrook | func (stream, "%ld", from - value);
|
1917 | 4b0f1a8b | pbrook | } |
1918 | 4b0f1a8b | pbrook | break;
|
1919 | 4b0f1a8b | pbrook | |
1920 | 4b0f1a8b | pbrook | case 'f': |
1921 | 4b0f1a8b | pbrook | if (value > 7) |
1922 | 4b0f1a8b | pbrook | func (stream, "#%s", arm_fp_const[value & 7]); |
1923 | 4b0f1a8b | pbrook | else
|
1924 | 4b0f1a8b | pbrook | func (stream, "f%ld", value);
|
1925 | 4b0f1a8b | pbrook | break;
|
1926 | 3b46e624 | ths | |
1927 | 4b0f1a8b | pbrook | case 'w': |
1928 | 4b0f1a8b | pbrook | if (width == 2) |
1929 | 4b0f1a8b | pbrook | func (stream, "%s", iwmmxt_wwnames[value]);
|
1930 | 4b0f1a8b | pbrook | else
|
1931 | 4b0f1a8b | pbrook | func (stream, "%s", iwmmxt_wwssnames[value]);
|
1932 | 4b0f1a8b | pbrook | break;
|
1933 | 3b46e624 | ths | |
1934 | 4b0f1a8b | pbrook | case 'g': |
1935 | 4b0f1a8b | pbrook | func (stream, "%s", iwmmxt_regnames[value]);
|
1936 | 4b0f1a8b | pbrook | break;
|
1937 | 4b0f1a8b | pbrook | case 'G': |
1938 | 4b0f1a8b | pbrook | func (stream, "%s", iwmmxt_cregnames[value]);
|
1939 | 4b0f1a8b | pbrook | break;
|
1940 | 3b46e624 | ths | |
1941 | 4b0f1a8b | pbrook | case 'x': |
1942 | 4b0f1a8b | pbrook | func (stream, "0x%lx", value);
|
1943 | 4b0f1a8b | pbrook | break;
|
1944 | 4b0f1a8b | pbrook | |
1945 | 4b0f1a8b | pbrook | case '`': |
1946 | 4b0f1a8b | pbrook | c++; |
1947 | 4b0f1a8b | pbrook | if (value == 0) |
1948 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
1949 | 4b0f1a8b | pbrook | break;
|
1950 | 4b0f1a8b | pbrook | case '\'': |
1951 | 4b0f1a8b | pbrook | c++; |
1952 | 4b0f1a8b | pbrook | if (value == ((1ul << width) - 1)) |
1953 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
1954 | 4b0f1a8b | pbrook | break;
|
1955 | 4b0f1a8b | pbrook | case '?': |
1956 | 4b0f1a8b | pbrook | func (stream, "%c", c[(1 << width) - (int)value]); |
1957 | 4b0f1a8b | pbrook | c += 1 << width;
|
1958 | 4b0f1a8b | pbrook | break;
|
1959 | 4b0f1a8b | pbrook | default:
|
1960 | 4b0f1a8b | pbrook | abort (); |
1961 | 4b0f1a8b | pbrook | } |
1962 | 4b0f1a8b | pbrook | break;
|
1963 | 3b46e624 | ths | |
1964 | 4b0f1a8b | pbrook | case 'y': |
1965 | 4b0f1a8b | pbrook | case 'z': |
1966 | 4b0f1a8b | pbrook | { |
1967 | 4b0f1a8b | pbrook | int single = *c++ == 'y'; |
1968 | 4b0f1a8b | pbrook | int regno;
|
1969 | 3b46e624 | ths | |
1970 | 4b0f1a8b | pbrook | switch (*c)
|
1971 | 4b0f1a8b | pbrook | { |
1972 | 4b0f1a8b | pbrook | case '4': /* Sm pair */ |
1973 | 4b0f1a8b | pbrook | func (stream, "{");
|
1974 | 4b0f1a8b | pbrook | /* Fall through. */
|
1975 | 4b0f1a8b | pbrook | case '0': /* Sm, Dm */ |
1976 | 4b0f1a8b | pbrook | regno = given & 0x0000000f;
|
1977 | 4b0f1a8b | pbrook | if (single)
|
1978 | aa0aa4fa | bellard | { |
1979 | 4b0f1a8b | pbrook | regno <<= 1;
|
1980 | 4b0f1a8b | pbrook | regno += (given >> 5) & 1; |
1981 | 4b0f1a8b | pbrook | } |
1982 | 4b0f1a8b | pbrook | else
|
1983 | 4b0f1a8b | pbrook | regno += ((given >> 5) & 1) << 4; |
1984 | 4b0f1a8b | pbrook | break;
|
1985 | 3b46e624 | ths | |
1986 | 4b0f1a8b | pbrook | case '1': /* Sd, Dd */ |
1987 | 4b0f1a8b | pbrook | regno = (given >> 12) & 0x0000000f; |
1988 | 4b0f1a8b | pbrook | if (single)
|
1989 | 4b0f1a8b | pbrook | { |
1990 | 4b0f1a8b | pbrook | regno <<= 1;
|
1991 | 4b0f1a8b | pbrook | regno += (given >> 22) & 1; |
1992 | 4b0f1a8b | pbrook | } |
1993 | 4b0f1a8b | pbrook | else
|
1994 | 4b0f1a8b | pbrook | regno += ((given >> 22) & 1) << 4; |
1995 | 4b0f1a8b | pbrook | break;
|
1996 | 3b46e624 | ths | |
1997 | 4b0f1a8b | pbrook | case '2': /* Sn, Dn */ |
1998 | 4b0f1a8b | pbrook | regno = (given >> 16) & 0x0000000f; |
1999 | 4b0f1a8b | pbrook | if (single)
|
2000 | 4b0f1a8b | pbrook | { |
2001 | 4b0f1a8b | pbrook | regno <<= 1;
|
2002 | 4b0f1a8b | pbrook | regno += (given >> 7) & 1; |
2003 | aa0aa4fa | bellard | } |
2004 | 4b0f1a8b | pbrook | else
|
2005 | 4b0f1a8b | pbrook | regno += ((given >> 7) & 1) << 4; |
2006 | 4b0f1a8b | pbrook | break;
|
2007 | 4b0f1a8b | pbrook | |
2008 | 4b0f1a8b | pbrook | case '3': /* List */ |
2009 | 4b0f1a8b | pbrook | func (stream, "{");
|
2010 | 4b0f1a8b | pbrook | regno = (given >> 12) & 0x0000000f; |
2011 | 4b0f1a8b | pbrook | if (single)
|
2012 | aa0aa4fa | bellard | { |
2013 | 4b0f1a8b | pbrook | regno <<= 1;
|
2014 | 4b0f1a8b | pbrook | regno += (given >> 22) & 1; |
2015 | 4b0f1a8b | pbrook | } |
2016 | 4b0f1a8b | pbrook | else
|
2017 | 4b0f1a8b | pbrook | regno += ((given >> 22) & 1) << 4; |
2018 | 4b0f1a8b | pbrook | break;
|
2019 | 3b46e624 | ths | |
2020 | 4b0f1a8b | pbrook | default:
|
2021 | 4b0f1a8b | pbrook | abort (); |
2022 | 4b0f1a8b | pbrook | } |
2023 | 3b46e624 | ths | |
2024 | 4b0f1a8b | pbrook | func (stream, "%c%d", single ? 's' : 'd', regno); |
2025 | 3b46e624 | ths | |
2026 | 4b0f1a8b | pbrook | if (*c == '3') |
2027 | 4b0f1a8b | pbrook | { |
2028 | 4b0f1a8b | pbrook | int count = given & 0xff; |
2029 | 3b46e624 | ths | |
2030 | 4b0f1a8b | pbrook | if (single == 0) |
2031 | 4b0f1a8b | pbrook | count >>= 1;
|
2032 | 3b46e624 | ths | |
2033 | 4b0f1a8b | pbrook | if (--count)
|
2034 | aa0aa4fa | bellard | { |
2035 | 4b0f1a8b | pbrook | func (stream, "-%c%d",
|
2036 | 4b0f1a8b | pbrook | single ? 's' : 'd', |
2037 | 4b0f1a8b | pbrook | regno + count); |
2038 | 4b0f1a8b | pbrook | } |
2039 | 3b46e624 | ths | |
2040 | 4b0f1a8b | pbrook | func (stream, "}");
|
2041 | 4b0f1a8b | pbrook | } |
2042 | 4b0f1a8b | pbrook | else if (*c == '4') |
2043 | 4b0f1a8b | pbrook | func (stream, ", %c%d}", single ? 's' : 'd', |
2044 | 4b0f1a8b | pbrook | regno + 1);
|
2045 | 4b0f1a8b | pbrook | } |
2046 | 4b0f1a8b | pbrook | break;
|
2047 | 3b46e624 | ths | |
2048 | 4b0f1a8b | pbrook | case 'L': |
2049 | 4b0f1a8b | pbrook | switch (given & 0x00400100) |
2050 | 4b0f1a8b | pbrook | { |
2051 | 4b0f1a8b | pbrook | case 0x00000000: func (stream, "b"); break; |
2052 | 4b0f1a8b | pbrook | case 0x00400000: func (stream, "h"); break; |
2053 | 4b0f1a8b | pbrook | case 0x00000100: func (stream, "w"); break; |
2054 | 4b0f1a8b | pbrook | case 0x00400100: func (stream, "d"); break; |
2055 | 4b0f1a8b | pbrook | default:
|
2056 | aa0aa4fa | bellard | break;
|
2057 | 4b0f1a8b | pbrook | } |
2058 | 4b0f1a8b | pbrook | break;
|
2059 | aa0aa4fa | bellard | |
2060 | 4b0f1a8b | pbrook | case 'Z': |
2061 | 4b0f1a8b | pbrook | { |
2062 | 4b0f1a8b | pbrook | int value;
|
2063 | 4b0f1a8b | pbrook | /* given (20, 23) | given (0, 3) */
|
2064 | 4b0f1a8b | pbrook | value = ((given >> 16) & 0xf0) | (given & 0xf); |
2065 | 4b0f1a8b | pbrook | func (stream, "%d", value);
|
2066 | 4b0f1a8b | pbrook | } |
2067 | 4b0f1a8b | pbrook | break;
|
2068 | aa0aa4fa | bellard | |
2069 | 4b0f1a8b | pbrook | case 'l': |
2070 | 4b0f1a8b | pbrook | /* This is like the 'A' operator, except that if
|
2071 | 4b0f1a8b | pbrook | the width field "M" is zero, then the offset is
|
2072 | 4b0f1a8b | pbrook | *not* multiplied by four. */
|
2073 | 4b0f1a8b | pbrook | { |
2074 | 4b0f1a8b | pbrook | int offset = given & 0xff; |
2075 | 4b0f1a8b | pbrook | int multiplier = (given & 0x00000100) ? 4 : 1; |
2076 | aa0aa4fa | bellard | |
2077 | 4b0f1a8b | pbrook | func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); |
2078 | aa0aa4fa | bellard | |
2079 | 4b0f1a8b | pbrook | if (offset)
|
2080 | 4b0f1a8b | pbrook | { |
2081 | 4b0f1a8b | pbrook | if ((given & 0x01000000) != 0) |
2082 | 4b0f1a8b | pbrook | func (stream, ", #%s%d]%s",
|
2083 | 4b0f1a8b | pbrook | ((given & 0x00800000) == 0 ? "-" : ""), |
2084 | 4b0f1a8b | pbrook | offset * multiplier, |
2085 | 4b0f1a8b | pbrook | ((given & 0x00200000) != 0 ? "!" : "")); |
2086 | 4b0f1a8b | pbrook | else
|
2087 | 4b0f1a8b | pbrook | func (stream, "], #%s%d",
|
2088 | 4b0f1a8b | pbrook | ((given & 0x00800000) == 0 ? "-" : ""), |
2089 | 4b0f1a8b | pbrook | offset * multiplier); |
2090 | 4b0f1a8b | pbrook | } |
2091 | 4b0f1a8b | pbrook | else
|
2092 | 4b0f1a8b | pbrook | func (stream, "]");
|
2093 | 4b0f1a8b | pbrook | } |
2094 | 4b0f1a8b | pbrook | break;
|
2095 | aa0aa4fa | bellard | |
2096 | 4b0f1a8b | pbrook | case 'r': |
2097 | 4b0f1a8b | pbrook | { |
2098 | 4b0f1a8b | pbrook | int imm4 = (given >> 4) & 0xf; |
2099 | 4b0f1a8b | pbrook | int puw_bits = ((given >> 22) & 6) | ((given >> 21) & 1); |
2100 | 4b0f1a8b | pbrook | int ubit = (given >> 23) & 1; |
2101 | 4b0f1a8b | pbrook | const char *rm = arm_regnames [given & 0xf]; |
2102 | 4b0f1a8b | pbrook | const char *rn = arm_regnames [(given >> 16) & 0xf]; |
2103 | aa0aa4fa | bellard | |
2104 | 4b0f1a8b | pbrook | switch (puw_bits)
|
2105 | 4b0f1a8b | pbrook | { |
2106 | 4b0f1a8b | pbrook | case 1: |
2107 | 4b0f1a8b | pbrook | /* fall through */
|
2108 | 4b0f1a8b | pbrook | case 3: |
2109 | 4b0f1a8b | pbrook | func (stream, "[%s], %c%s", rn, ubit ? '+' : '-', rm); |
2110 | 4b0f1a8b | pbrook | if (imm4)
|
2111 | 4b0f1a8b | pbrook | func (stream, ", lsl #%d", imm4);
|
2112 | 4b0f1a8b | pbrook | break;
|
2113 | aa0aa4fa | bellard | |
2114 | 4b0f1a8b | pbrook | case 4: |
2115 | 4b0f1a8b | pbrook | /* fall through */
|
2116 | 4b0f1a8b | pbrook | case 5: |
2117 | 4b0f1a8b | pbrook | /* fall through */
|
2118 | 4b0f1a8b | pbrook | case 6: |
2119 | 4b0f1a8b | pbrook | /* fall through */
|
2120 | 4b0f1a8b | pbrook | case 7: |
2121 | 4b0f1a8b | pbrook | func (stream, "[%s, %c%s", rn, ubit ? '+' : '-', rm); |
2122 | 4b0f1a8b | pbrook | if (imm4 > 0) |
2123 | 4b0f1a8b | pbrook | func (stream, ", lsl #%d", imm4);
|
2124 | 4b0f1a8b | pbrook | func (stream, "]");
|
2125 | 4b0f1a8b | pbrook | if (puw_bits == 5 || puw_bits == 7) |
2126 | 4b0f1a8b | pbrook | func (stream, "!");
|
2127 | aa0aa4fa | bellard | break;
|
2128 | 4b0f1a8b | pbrook | |
2129 | 4b0f1a8b | pbrook | default:
|
2130 | 4b0f1a8b | pbrook | func (stream, "INVALID");
|
2131 | aa0aa4fa | bellard | } |
2132 | 4b0f1a8b | pbrook | } |
2133 | 4b0f1a8b | pbrook | break;
|
2134 | aa0aa4fa | bellard | |
2135 | 4b0f1a8b | pbrook | case 'i': |
2136 | 4b0f1a8b | pbrook | { |
2137 | 4b0f1a8b | pbrook | long imm5;
|
2138 | 4b0f1a8b | pbrook | imm5 = ((given & 0x100) >> 4) | (given & 0xf); |
2139 | 4b0f1a8b | pbrook | func (stream, "%ld", (imm5 == 0) ? 32 : imm5); |
2140 | 4b0f1a8b | pbrook | } |
2141 | aa0aa4fa | bellard | break;
|
2142 | aa0aa4fa | bellard | |
2143 | aa0aa4fa | bellard | default:
|
2144 | aa0aa4fa | bellard | abort (); |
2145 | aa0aa4fa | bellard | } |
2146 | aa0aa4fa | bellard | } |
2147 | aa0aa4fa | bellard | } |
2148 | aa0aa4fa | bellard | else
|
2149 | aa0aa4fa | bellard | func (stream, "%c", *c);
|
2150 | aa0aa4fa | bellard | } |
2151 | 4b0f1a8b | pbrook | return TRUE;
|
2152 | aa0aa4fa | bellard | } |
2153 | aa0aa4fa | bellard | } |
2154 | 4b0f1a8b | pbrook | return FALSE;
|
2155 | aa0aa4fa | bellard | } |
2156 | aa0aa4fa | bellard | |
2157 | 4b0f1a8b | pbrook | static void |
2158 | 4b0f1a8b | pbrook | print_arm_address (bfd_vma pc, struct disassemble_info *info, long given) |
2159 | aa0aa4fa | bellard | { |
2160 | 4b0f1a8b | pbrook | void *stream = info->stream;
|
2161 | 4b0f1a8b | pbrook | fprintf_ftype func = info->fprintf_func; |
2162 | aa0aa4fa | bellard | |
2163 | 4b0f1a8b | pbrook | if (((given & 0x000f0000) == 0x000f0000) |
2164 | 4b0f1a8b | pbrook | && ((given & 0x02000000) == 0)) |
2165 | aa0aa4fa | bellard | { |
2166 | 4b0f1a8b | pbrook | int offset = given & 0xfff; |
2167 | aa0aa4fa | bellard | |
2168 | 4b0f1a8b | pbrook | func (stream, "[pc");
|
2169 | 3b46e624 | ths | |
2170 | 4b0f1a8b | pbrook | if (given & 0x01000000) |
2171 | 4b0f1a8b | pbrook | { |
2172 | 4b0f1a8b | pbrook | if ((given & 0x00800000) == 0) |
2173 | 4b0f1a8b | pbrook | offset = - offset; |
2174 | aa0aa4fa | bellard | |
2175 | 4b0f1a8b | pbrook | /* Pre-indexed. */
|
2176 | 4b0f1a8b | pbrook | func (stream, ", #%d]", offset);
|
2177 | 3b46e624 | ths | |
2178 | 4b0f1a8b | pbrook | offset += pc + 8;
|
2179 | 3b46e624 | ths | |
2180 | 4b0f1a8b | pbrook | /* Cope with the possibility of write-back
|
2181 | 4b0f1a8b | pbrook | being used. Probably a very dangerous thing
|
2182 | 4b0f1a8b | pbrook | for the programmer to do, but who are we to
|
2183 | 4b0f1a8b | pbrook | argue ? */
|
2184 | 4b0f1a8b | pbrook | if (given & 0x00200000) |
2185 | 4b0f1a8b | pbrook | func (stream, "!");
|
2186 | 4b0f1a8b | pbrook | } |
2187 | 4b0f1a8b | pbrook | else
|
2188 | 4b0f1a8b | pbrook | { |
2189 | 4b0f1a8b | pbrook | /* Post indexed. */
|
2190 | 4b0f1a8b | pbrook | func (stream, "], #%d", offset);
|
2191 | 3b46e624 | ths | |
2192 | 4b0f1a8b | pbrook | /* ie ignore the offset. */
|
2193 | 4b0f1a8b | pbrook | offset = pc + 8;
|
2194 | 4b0f1a8b | pbrook | } |
2195 | 3b46e624 | ths | |
2196 | 4b0f1a8b | pbrook | func (stream, "\t; ");
|
2197 | 4b0f1a8b | pbrook | info->print_address_func (offset, info); |
2198 | 4b0f1a8b | pbrook | } |
2199 | 4b0f1a8b | pbrook | else
|
2200 | 4b0f1a8b | pbrook | { |
2201 | 4b0f1a8b | pbrook | func (stream, "[%s",
|
2202 | 4b0f1a8b | pbrook | arm_regnames[(given >> 16) & 0xf]); |
2203 | 4b0f1a8b | pbrook | if ((given & 0x01000000) != 0) |
2204 | 4b0f1a8b | pbrook | { |
2205 | 4b0f1a8b | pbrook | if ((given & 0x02000000) == 0) |
2206 | 4b0f1a8b | pbrook | { |
2207 | 4b0f1a8b | pbrook | int offset = given & 0xfff; |
2208 | 4b0f1a8b | pbrook | if (offset)
|
2209 | 4b0f1a8b | pbrook | func (stream, ", #%s%d",
|
2210 | 4b0f1a8b | pbrook | (((given & 0x00800000) == 0) |
2211 | 4b0f1a8b | pbrook | ? "-" : ""), offset); |
2212 | 4b0f1a8b | pbrook | } |
2213 | 4b0f1a8b | pbrook | else
|
2214 | 4b0f1a8b | pbrook | { |
2215 | 4b0f1a8b | pbrook | func (stream, ", %s",
|
2216 | 4b0f1a8b | pbrook | (((given & 0x00800000) == 0) |
2217 | 4b0f1a8b | pbrook | ? "-" : "")); |
2218 | 4b0f1a8b | pbrook | arm_decode_shift (given, func, stream, 1);
|
2219 | 4b0f1a8b | pbrook | } |
2220 | aa0aa4fa | bellard | |
2221 | 4b0f1a8b | pbrook | func (stream, "]%s",
|
2222 | 4b0f1a8b | pbrook | ((given & 0x00200000) != 0) ? "!" : ""); |
2223 | 4b0f1a8b | pbrook | } |
2224 | 4b0f1a8b | pbrook | else
|
2225 | 4b0f1a8b | pbrook | { |
2226 | 4b0f1a8b | pbrook | if ((given & 0x02000000) == 0) |
2227 | 4b0f1a8b | pbrook | { |
2228 | 4b0f1a8b | pbrook | int offset = given & 0xfff; |
2229 | 4b0f1a8b | pbrook | if (offset)
|
2230 | 4b0f1a8b | pbrook | func (stream, "], #%s%d",
|
2231 | 4b0f1a8b | pbrook | (((given & 0x00800000) == 0) |
2232 | 4b0f1a8b | pbrook | ? "-" : ""), offset); |
2233 | 4b0f1a8b | pbrook | else
|
2234 | 4b0f1a8b | pbrook | func (stream, "]");
|
2235 | 4b0f1a8b | pbrook | } |
2236 | 4b0f1a8b | pbrook | else
|
2237 | 4b0f1a8b | pbrook | { |
2238 | 4b0f1a8b | pbrook | func (stream, "], %s",
|
2239 | 4b0f1a8b | pbrook | (((given & 0x00800000) == 0) |
2240 | 4b0f1a8b | pbrook | ? "-" : "")); |
2241 | 4b0f1a8b | pbrook | arm_decode_shift (given, func, stream, 1);
|
2242 | 4b0f1a8b | pbrook | } |
2243 | 4b0f1a8b | pbrook | } |
2244 | 4b0f1a8b | pbrook | } |
2245 | 4b0f1a8b | pbrook | } |
2246 | 4b0f1a8b | pbrook | |
2247 | 4b0f1a8b | pbrook | /* Print one neon instruction on INFO->STREAM.
|
2248 | 4b0f1a8b | pbrook | Return TRUE if the instuction matched, FALSE if this is not a
|
2249 | 4b0f1a8b | pbrook | recognised neon instruction. */
|
2250 | 4b0f1a8b | pbrook | |
2251 | 4b0f1a8b | pbrook | static bfd_boolean
|
2252 | 4b0f1a8b | pbrook | print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) |
2253 | 4b0f1a8b | pbrook | { |
2254 | 4b0f1a8b | pbrook | const struct opcode32 *insn; |
2255 | 4b0f1a8b | pbrook | void *stream = info->stream;
|
2256 | 4b0f1a8b | pbrook | fprintf_ftype func = info->fprintf_func; |
2257 | 4b0f1a8b | pbrook | |
2258 | 4b0f1a8b | pbrook | if (thumb)
|
2259 | 4b0f1a8b | pbrook | { |
2260 | 4b0f1a8b | pbrook | if ((given & 0xef000000) == 0xef000000) |
2261 | 4b0f1a8b | pbrook | { |
2262 | 4b0f1a8b | pbrook | /* move bit 28 to bit 24 to translate Thumb2 to ARM encoding. */
|
2263 | 4b0f1a8b | pbrook | unsigned long bit28 = given & (1 << 28); |
2264 | 4b0f1a8b | pbrook | |
2265 | 4b0f1a8b | pbrook | given &= 0x00ffffff;
|
2266 | 4b0f1a8b | pbrook | if (bit28)
|
2267 | 4b0f1a8b | pbrook | given |= 0xf3000000;
|
2268 | 4b0f1a8b | pbrook | else
|
2269 | 4b0f1a8b | pbrook | given |= 0xf2000000;
|
2270 | 4b0f1a8b | pbrook | } |
2271 | 4b0f1a8b | pbrook | else if ((given & 0xff000000) == 0xf9000000) |
2272 | 4b0f1a8b | pbrook | given ^= 0xf9000000 ^ 0xf4000000; |
2273 | 4b0f1a8b | pbrook | else
|
2274 | 4b0f1a8b | pbrook | return FALSE;
|
2275 | 4b0f1a8b | pbrook | } |
2276 | 4b0f1a8b | pbrook | |
2277 | 4b0f1a8b | pbrook | for (insn = neon_opcodes; insn->assembler; insn++)
|
2278 | 4b0f1a8b | pbrook | { |
2279 | 4b0f1a8b | pbrook | if ((given & insn->mask) == insn->value)
|
2280 | 4b0f1a8b | pbrook | { |
2281 | 4b0f1a8b | pbrook | const char *c; |
2282 | 4b0f1a8b | pbrook | |
2283 | 4b0f1a8b | pbrook | for (c = insn->assembler; *c; c++)
|
2284 | 4b0f1a8b | pbrook | { |
2285 | 4b0f1a8b | pbrook | if (*c == '%') |
2286 | 4b0f1a8b | pbrook | { |
2287 | 4b0f1a8b | pbrook | switch (*++c)
|
2288 | 4b0f1a8b | pbrook | { |
2289 | 4b0f1a8b | pbrook | case '%': |
2290 | 4b0f1a8b | pbrook | func (stream, "%%");
|
2291 | 4b0f1a8b | pbrook | break;
|
2292 | 4b0f1a8b | pbrook | |
2293 | 4b0f1a8b | pbrook | case 'c': |
2294 | 4b0f1a8b | pbrook | if (thumb && ifthen_state)
|
2295 | 4b0f1a8b | pbrook | func (stream, "%s", arm_conditional[IFTHEN_COND]);
|
2296 | 4b0f1a8b | pbrook | break;
|
2297 | 4b0f1a8b | pbrook | |
2298 | 4b0f1a8b | pbrook | case 'A': |
2299 | 4b0f1a8b | pbrook | { |
2300 | 4b0f1a8b | pbrook | static const unsigned char enc[16] = |
2301 | 4b0f1a8b | pbrook | { |
2302 | 4b0f1a8b | pbrook | 0x4, 0x14, /* st4 0,1 */ |
2303 | 4b0f1a8b | pbrook | 0x4, /* st1 2 */ |
2304 | 4b0f1a8b | pbrook | 0x4, /* st2 3 */ |
2305 | 4b0f1a8b | pbrook | 0x3, /* st3 4 */ |
2306 | 4b0f1a8b | pbrook | 0x13, /* st3 5 */ |
2307 | 4b0f1a8b | pbrook | 0x3, /* st1 6 */ |
2308 | 4b0f1a8b | pbrook | 0x1, /* st1 7 */ |
2309 | 4b0f1a8b | pbrook | 0x2, /* st2 8 */ |
2310 | 4b0f1a8b | pbrook | 0x12, /* st2 9 */ |
2311 | 4b0f1a8b | pbrook | 0x2, /* st1 10 */ |
2312 | 4b0f1a8b | pbrook | 0, 0, 0, 0, 0 |
2313 | 4b0f1a8b | pbrook | }; |
2314 | 4b0f1a8b | pbrook | int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); |
2315 | 4b0f1a8b | pbrook | int rn = ((given >> 16) & 0xf); |
2316 | 4b0f1a8b | pbrook | int rm = ((given >> 0) & 0xf); |
2317 | 4b0f1a8b | pbrook | int align = ((given >> 4) & 0x3); |
2318 | 4b0f1a8b | pbrook | int type = ((given >> 8) & 0xf); |
2319 | 4b0f1a8b | pbrook | int n = enc[type] & 0xf; |
2320 | 4b0f1a8b | pbrook | int stride = (enc[type] >> 4) + 1; |
2321 | 4b0f1a8b | pbrook | int ix;
|
2322 | 4b0f1a8b | pbrook | |
2323 | 4b0f1a8b | pbrook | func (stream, "{");
|
2324 | 4b0f1a8b | pbrook | if (stride > 1) |
2325 | 4b0f1a8b | pbrook | for (ix = 0; ix != n; ix++) |
2326 | 4b0f1a8b | pbrook | func (stream, "%sd%d", ix ? "," : "", rd + ix * stride); |
2327 | 4b0f1a8b | pbrook | else if (n == 1) |
2328 | 4b0f1a8b | pbrook | func (stream, "d%d", rd);
|
2329 | 4b0f1a8b | pbrook | else
|
2330 | 4b0f1a8b | pbrook | func (stream, "d%d-d%d", rd, rd + n - 1); |
2331 | 4b0f1a8b | pbrook | func (stream, "}, [%s", arm_regnames[rn]);
|
2332 | 4b0f1a8b | pbrook | if (align)
|
2333 | 4b0f1a8b | pbrook | func (stream, ", :%d", 32 << align); |
2334 | 4b0f1a8b | pbrook | func (stream, "]");
|
2335 | 4b0f1a8b | pbrook | if (rm == 0xd) |
2336 | 4b0f1a8b | pbrook | func (stream, "!");
|
2337 | 4b0f1a8b | pbrook | else if (rm != 0xf) |
2338 | 4b0f1a8b | pbrook | func (stream, ", %s", arm_regnames[rm]);
|
2339 | 4b0f1a8b | pbrook | } |
2340 | 4b0f1a8b | pbrook | break;
|
2341 | 4b0f1a8b | pbrook | |
2342 | 4b0f1a8b | pbrook | case 'B': |
2343 | 4b0f1a8b | pbrook | { |
2344 | 4b0f1a8b | pbrook | int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); |
2345 | 4b0f1a8b | pbrook | int rn = ((given >> 16) & 0xf); |
2346 | 4b0f1a8b | pbrook | int rm = ((given >> 0) & 0xf); |
2347 | 4b0f1a8b | pbrook | int idx_align = ((given >> 4) & 0xf); |
2348 | 4b0f1a8b | pbrook | int align = 0; |
2349 | 4b0f1a8b | pbrook | int size = ((given >> 10) & 0x3); |
2350 | 4b0f1a8b | pbrook | int idx = idx_align >> (size + 1); |
2351 | 4b0f1a8b | pbrook | int length = ((given >> 8) & 3) + 1; |
2352 | 4b0f1a8b | pbrook | int stride = 1; |
2353 | 4b0f1a8b | pbrook | int i;
|
2354 | 4b0f1a8b | pbrook | |
2355 | 4b0f1a8b | pbrook | if (length > 1 && size > 0) |
2356 | 4b0f1a8b | pbrook | stride = (idx_align & (1 << size)) ? 2 : 1; |
2357 | 4b0f1a8b | pbrook | |
2358 | 4b0f1a8b | pbrook | switch (length)
|
2359 | 4b0f1a8b | pbrook | { |
2360 | 4b0f1a8b | pbrook | case 1: |
2361 | 4b0f1a8b | pbrook | { |
2362 | 4b0f1a8b | pbrook | int amask = (1 << size) - 1; |
2363 | 4b0f1a8b | pbrook | if ((idx_align & (1 << size)) != 0) |
2364 | 4b0f1a8b | pbrook | return FALSE;
|
2365 | 4b0f1a8b | pbrook | if (size > 0) |
2366 | 4b0f1a8b | pbrook | { |
2367 | 4b0f1a8b | pbrook | if ((idx_align & amask) == amask)
|
2368 | 4b0f1a8b | pbrook | align = 8 << size;
|
2369 | 4b0f1a8b | pbrook | else if ((idx_align & amask) != 0) |
2370 | 4b0f1a8b | pbrook | return FALSE;
|
2371 | 4b0f1a8b | pbrook | } |
2372 | 4b0f1a8b | pbrook | } |
2373 | 4b0f1a8b | pbrook | break;
|
2374 | 4b0f1a8b | pbrook | |
2375 | 4b0f1a8b | pbrook | case 2: |
2376 | 4b0f1a8b | pbrook | if (size == 2 && (idx_align & 2) != 0) |
2377 | 4b0f1a8b | pbrook | return FALSE;
|
2378 | 4b0f1a8b | pbrook | align = (idx_align & 1) ? 16 << size : 0; |
2379 | 4b0f1a8b | pbrook | break;
|
2380 | 4b0f1a8b | pbrook | |
2381 | 4b0f1a8b | pbrook | case 3: |
2382 | 4b0f1a8b | pbrook | if ((size == 2 && (idx_align & 3) != 0) |
2383 | 4b0f1a8b | pbrook | || (idx_align & 1) != 0) |
2384 | 4b0f1a8b | pbrook | return FALSE;
|
2385 | 4b0f1a8b | pbrook | break;
|
2386 | 4b0f1a8b | pbrook | |
2387 | 4b0f1a8b | pbrook | case 4: |
2388 | 4b0f1a8b | pbrook | if (size == 2) |
2389 | 4b0f1a8b | pbrook | { |
2390 | 4b0f1a8b | pbrook | if ((idx_align & 3) == 3) |
2391 | 4b0f1a8b | pbrook | return FALSE;
|
2392 | 4b0f1a8b | pbrook | align = (idx_align & 3) * 64; |
2393 | 4b0f1a8b | pbrook | } |
2394 | 4b0f1a8b | pbrook | else
|
2395 | 4b0f1a8b | pbrook | align = (idx_align & 1) ? 32 << size : 0; |
2396 | 4b0f1a8b | pbrook | break;
|
2397 | 4b0f1a8b | pbrook | |
2398 | 4b0f1a8b | pbrook | default:
|
2399 | 4b0f1a8b | pbrook | abort (); |
2400 | 4b0f1a8b | pbrook | } |
2401 | 4b0f1a8b | pbrook | |
2402 | 4b0f1a8b | pbrook | func (stream, "{");
|
2403 | 4b0f1a8b | pbrook | for (i = 0; i < length; i++) |
2404 | 4b0f1a8b | pbrook | func (stream, "%sd%d[%d]", (i == 0) ? "" : ",", |
2405 | 4b0f1a8b | pbrook | rd + i * stride, idx); |
2406 | 4b0f1a8b | pbrook | func (stream, "}, [%s", arm_regnames[rn]);
|
2407 | 4b0f1a8b | pbrook | if (align)
|
2408 | 4b0f1a8b | pbrook | func (stream, ", :%d", align);
|
2409 | 4b0f1a8b | pbrook | func (stream, "]");
|
2410 | 4b0f1a8b | pbrook | if (rm == 0xd) |
2411 | 4b0f1a8b | pbrook | func (stream, "!");
|
2412 | 4b0f1a8b | pbrook | else if (rm != 0xf) |
2413 | 4b0f1a8b | pbrook | func (stream, ", %s", arm_regnames[rm]);
|
2414 | 4b0f1a8b | pbrook | } |
2415 | 4b0f1a8b | pbrook | break;
|
2416 | 4b0f1a8b | pbrook | |
2417 | 4b0f1a8b | pbrook | case 'C': |
2418 | 4b0f1a8b | pbrook | { |
2419 | 4b0f1a8b | pbrook | int rd = ((given >> 12) & 0xf) | (((given >> 22) & 1) << 4); |
2420 | 4b0f1a8b | pbrook | int rn = ((given >> 16) & 0xf); |
2421 | 4b0f1a8b | pbrook | int rm = ((given >> 0) & 0xf); |
2422 | 4b0f1a8b | pbrook | int align = ((given >> 4) & 0x1); |
2423 | 4b0f1a8b | pbrook | int size = ((given >> 6) & 0x3); |
2424 | 4b0f1a8b | pbrook | int type = ((given >> 8) & 0x3); |
2425 | 4b0f1a8b | pbrook | int n = type + 1; |
2426 | 4b0f1a8b | pbrook | int stride = ((given >> 5) & 0x1); |
2427 | 4b0f1a8b | pbrook | int ix;
|
2428 | 4b0f1a8b | pbrook | |
2429 | 4b0f1a8b | pbrook | if (stride && (n == 1)) |
2430 | 4b0f1a8b | pbrook | n++; |
2431 | 4b0f1a8b | pbrook | else
|
2432 | 4b0f1a8b | pbrook | stride++; |
2433 | 4b0f1a8b | pbrook | |
2434 | 4b0f1a8b | pbrook | func (stream, "{");
|
2435 | 4b0f1a8b | pbrook | if (stride > 1) |
2436 | 4b0f1a8b | pbrook | for (ix = 0; ix != n; ix++) |
2437 | 4b0f1a8b | pbrook | func (stream, "%sd%d[]", ix ? "," : "", rd + ix * stride); |
2438 | 4b0f1a8b | pbrook | else if (n == 1) |
2439 | 4b0f1a8b | pbrook | func (stream, "d%d[]", rd);
|
2440 | 4b0f1a8b | pbrook | else
|
2441 | 4b0f1a8b | pbrook | func (stream, "d%d[]-d%d[]", rd, rd + n - 1); |
2442 | 4b0f1a8b | pbrook | func (stream, "}, [%s", arm_regnames[rn]);
|
2443 | 4b0f1a8b | pbrook | if (align)
|
2444 | 4b0f1a8b | pbrook | { |
2445 | 4b0f1a8b | pbrook | int align = (8 * (type + 1)) << size; |
2446 | 4b0f1a8b | pbrook | if (type == 3) |
2447 | 4b0f1a8b | pbrook | align = (size > 1) ? align >> 1 : align; |
2448 | 4b0f1a8b | pbrook | if (type == 2 || (type == 0 && !size)) |
2449 | 4b0f1a8b | pbrook | func (stream, ", :<bad align %d>", align);
|
2450 | 4b0f1a8b | pbrook | else
|
2451 | 4b0f1a8b | pbrook | func (stream, ", :%d", align);
|
2452 | 4b0f1a8b | pbrook | } |
2453 | 4b0f1a8b | pbrook | func (stream, "]");
|
2454 | 4b0f1a8b | pbrook | if (rm == 0xd) |
2455 | 4b0f1a8b | pbrook | func (stream, "!");
|
2456 | 4b0f1a8b | pbrook | else if (rm != 0xf) |
2457 | 4b0f1a8b | pbrook | func (stream, ", %s", arm_regnames[rm]);
|
2458 | 4b0f1a8b | pbrook | } |
2459 | 4b0f1a8b | pbrook | break;
|
2460 | 4b0f1a8b | pbrook | |
2461 | 4b0f1a8b | pbrook | case 'D': |
2462 | 4b0f1a8b | pbrook | { |
2463 | 4b0f1a8b | pbrook | int raw_reg = (given & 0xf) | ((given >> 1) & 0x10); |
2464 | 4b0f1a8b | pbrook | int size = (given >> 20) & 3; |
2465 | 4b0f1a8b | pbrook | int reg = raw_reg & ((4 << size) - 1); |
2466 | 4b0f1a8b | pbrook | int ix = raw_reg >> size >> 2; |
2467 | 4b0f1a8b | pbrook | |
2468 | 4b0f1a8b | pbrook | func (stream, "d%d[%d]", reg, ix);
|
2469 | 4b0f1a8b | pbrook | } |
2470 | 4b0f1a8b | pbrook | break;
|
2471 | 4b0f1a8b | pbrook | |
2472 | 4b0f1a8b | pbrook | case 'E': |
2473 | 4b0f1a8b | pbrook | /* Neon encoded constant for mov, mvn, vorr, vbic */
|
2474 | 4b0f1a8b | pbrook | { |
2475 | 4b0f1a8b | pbrook | int bits = 0; |
2476 | 4b0f1a8b | pbrook | int cmode = (given >> 8) & 0xf; |
2477 | 4b0f1a8b | pbrook | int op = (given >> 5) & 0x1; |
2478 | 4b0f1a8b | pbrook | unsigned long value = 0, hival = 0; |
2479 | 4b0f1a8b | pbrook | unsigned shift;
|
2480 | 4b0f1a8b | pbrook | int size = 0; |
2481 | 4b0f1a8b | pbrook | int isfloat = 0; |
2482 | 4b0f1a8b | pbrook | |
2483 | 4b0f1a8b | pbrook | bits |= ((given >> 24) & 1) << 7; |
2484 | 4b0f1a8b | pbrook | bits |= ((given >> 16) & 7) << 4; |
2485 | 4b0f1a8b | pbrook | bits |= ((given >> 0) & 15) << 0; |
2486 | 4b0f1a8b | pbrook | |
2487 | 4b0f1a8b | pbrook | if (cmode < 8) |
2488 | 4b0f1a8b | pbrook | { |
2489 | 4b0f1a8b | pbrook | shift = (cmode >> 1) & 3; |
2490 | 4b0f1a8b | pbrook | value = (unsigned long)bits << (8 * shift); |
2491 | 4b0f1a8b | pbrook | size = 32;
|
2492 | 4b0f1a8b | pbrook | } |
2493 | 4b0f1a8b | pbrook | else if (cmode < 12) |
2494 | 4b0f1a8b | pbrook | { |
2495 | 4b0f1a8b | pbrook | shift = (cmode >> 1) & 1; |
2496 | 4b0f1a8b | pbrook | value = (unsigned long)bits << (8 * shift); |
2497 | 4b0f1a8b | pbrook | size = 16;
|
2498 | 4b0f1a8b | pbrook | } |
2499 | 4b0f1a8b | pbrook | else if (cmode < 14) |
2500 | 4b0f1a8b | pbrook | { |
2501 | 4b0f1a8b | pbrook | shift = (cmode & 1) + 1; |
2502 | 4b0f1a8b | pbrook | value = (unsigned long)bits << (8 * shift); |
2503 | 4b0f1a8b | pbrook | value |= (1ul << (8 * shift)) - 1; |
2504 | 4b0f1a8b | pbrook | size = 32;
|
2505 | 4b0f1a8b | pbrook | } |
2506 | 4b0f1a8b | pbrook | else if (cmode == 14) |
2507 | 4b0f1a8b | pbrook | { |
2508 | 4b0f1a8b | pbrook | if (op)
|
2509 | 4b0f1a8b | pbrook | { |
2510 | 4b0f1a8b | pbrook | /* bit replication into bytes */
|
2511 | 4b0f1a8b | pbrook | int ix;
|
2512 | 4b0f1a8b | pbrook | unsigned long mask; |
2513 | 4b0f1a8b | pbrook | |
2514 | 4b0f1a8b | pbrook | value = 0;
|
2515 | 4b0f1a8b | pbrook | hival = 0;
|
2516 | 4b0f1a8b | pbrook | for (ix = 7; ix >= 0; ix--) |
2517 | 4b0f1a8b | pbrook | { |
2518 | 4b0f1a8b | pbrook | mask = ((bits >> ix) & 1) ? 0xff : 0; |
2519 | 4b0f1a8b | pbrook | if (ix <= 3) |
2520 | 4b0f1a8b | pbrook | value = (value << 8) | mask;
|
2521 | 4b0f1a8b | pbrook | else
|
2522 | 4b0f1a8b | pbrook | hival = (hival << 8) | mask;
|
2523 | 4b0f1a8b | pbrook | } |
2524 | 4b0f1a8b | pbrook | size = 64;
|
2525 | 4b0f1a8b | pbrook | } |
2526 | 4b0f1a8b | pbrook | else
|
2527 | 4b0f1a8b | pbrook | { |
2528 | 4b0f1a8b | pbrook | /* byte replication */
|
2529 | 4b0f1a8b | pbrook | value = (unsigned long)bits; |
2530 | 4b0f1a8b | pbrook | size = 8;
|
2531 | 4b0f1a8b | pbrook | } |
2532 | 4b0f1a8b | pbrook | } |
2533 | 4b0f1a8b | pbrook | else if (!op) |
2534 | 4b0f1a8b | pbrook | { |
2535 | 4b0f1a8b | pbrook | /* floating point encoding */
|
2536 | 4b0f1a8b | pbrook | int tmp;
|
2537 | 4b0f1a8b | pbrook | |
2538 | 4b0f1a8b | pbrook | value = (unsigned long)(bits & 0x7f) << 19; |
2539 | 4b0f1a8b | pbrook | value |= (unsigned long)(bits & 0x80) << 24; |
2540 | 4b0f1a8b | pbrook | tmp = bits & 0x40 ? 0x3c : 0x40; |
2541 | 4b0f1a8b | pbrook | value |= (unsigned long)tmp << 24; |
2542 | 4b0f1a8b | pbrook | size = 32;
|
2543 | 4b0f1a8b | pbrook | isfloat = 1;
|
2544 | 4b0f1a8b | pbrook | } |
2545 | 4b0f1a8b | pbrook | else
|
2546 | 4b0f1a8b | pbrook | { |
2547 | 4b0f1a8b | pbrook | func (stream, "<illegal constant %.8x:%x:%x>",
|
2548 | 4b0f1a8b | pbrook | bits, cmode, op); |
2549 | 4b0f1a8b | pbrook | size = 32;
|
2550 | 4b0f1a8b | pbrook | break;
|
2551 | 4b0f1a8b | pbrook | } |
2552 | 4b0f1a8b | pbrook | switch (size)
|
2553 | 4b0f1a8b | pbrook | { |
2554 | 4b0f1a8b | pbrook | case 8: |
2555 | 4b0f1a8b | pbrook | func (stream, "#%ld\t; 0x%.2lx", value, value);
|
2556 | 4b0f1a8b | pbrook | break;
|
2557 | 4b0f1a8b | pbrook | |
2558 | 4b0f1a8b | pbrook | case 16: |
2559 | 4b0f1a8b | pbrook | func (stream, "#%ld\t; 0x%.4lx", value, value);
|
2560 | 4b0f1a8b | pbrook | break;
|
2561 | 4b0f1a8b | pbrook | |
2562 | 4b0f1a8b | pbrook | case 32: |
2563 | 4b0f1a8b | pbrook | if (isfloat)
|
2564 | 4b0f1a8b | pbrook | { |
2565 | 4b0f1a8b | pbrook | unsigned char valbytes[4]; |
2566 | 4b0f1a8b | pbrook | double fvalue;
|
2567 | 4b0f1a8b | pbrook | |
2568 | 4b0f1a8b | pbrook | /* Do this a byte at a time so we don't have to
|
2569 | 4b0f1a8b | pbrook | worry about the host's endianness. */
|
2570 | 4b0f1a8b | pbrook | valbytes[0] = value & 0xff; |
2571 | 4b0f1a8b | pbrook | valbytes[1] = (value >> 8) & 0xff; |
2572 | 4b0f1a8b | pbrook | valbytes[2] = (value >> 16) & 0xff; |
2573 | 4b0f1a8b | pbrook | valbytes[3] = (value >> 24) & 0xff; |
2574 | 4b0f1a8b | pbrook | |
2575 | 4b0f1a8b | pbrook | floatformat_to_double |
2576 | 4b0f1a8b | pbrook | (&floatformat_ieee_single_little, valbytes, |
2577 | 4b0f1a8b | pbrook | &fvalue); |
2578 | 4b0f1a8b | pbrook | |
2579 | 4b0f1a8b | pbrook | func (stream, "#%.7g\t; 0x%.8lx", fvalue,
|
2580 | 4b0f1a8b | pbrook | value); |
2581 | 4b0f1a8b | pbrook | } |
2582 | 4b0f1a8b | pbrook | else
|
2583 | 4b0f1a8b | pbrook | func (stream, "#%ld\t; 0x%.8lx",
|
2584 | 4b0f1a8b | pbrook | (long) ((value & 0x80000000) |
2585 | 4b0f1a8b | pbrook | ? value | ~0xffffffffl : value), value);
|
2586 | 4b0f1a8b | pbrook | break;
|
2587 | 4b0f1a8b | pbrook | |
2588 | 4b0f1a8b | pbrook | case 64: |
2589 | 4b0f1a8b | pbrook | func (stream, "#0x%.8lx%.8lx", hival, value);
|
2590 | 4b0f1a8b | pbrook | break;
|
2591 | 4b0f1a8b | pbrook | |
2592 | 4b0f1a8b | pbrook | default:
|
2593 | 4b0f1a8b | pbrook | abort (); |
2594 | 4b0f1a8b | pbrook | } |
2595 | 4b0f1a8b | pbrook | } |
2596 | 4b0f1a8b | pbrook | break;
|
2597 | 4b0f1a8b | pbrook | |
2598 | 4b0f1a8b | pbrook | case 'F': |
2599 | 4b0f1a8b | pbrook | { |
2600 | 4b0f1a8b | pbrook | int regno = ((given >> 16) & 0xf) | ((given >> (7 - 4)) & 0x10); |
2601 | 4b0f1a8b | pbrook | int num = (given >> 8) & 0x3; |
2602 | 4b0f1a8b | pbrook | |
2603 | 4b0f1a8b | pbrook | if (!num)
|
2604 | 4b0f1a8b | pbrook | func (stream, "{d%d}", regno);
|
2605 | 4b0f1a8b | pbrook | else if (num + regno >= 32) |
2606 | 4b0f1a8b | pbrook | func (stream, "{d%d-<overflow reg d%d}", regno, regno + num);
|
2607 | 4b0f1a8b | pbrook | else
|
2608 | 4b0f1a8b | pbrook | func (stream, "{d%d-d%d}", regno, regno + num);
|
2609 | 4b0f1a8b | pbrook | } |
2610 | 4b0f1a8b | pbrook | break;
|
2611 | 4b0f1a8b | pbrook | |
2612 | 4b0f1a8b | pbrook | |
2613 | 4b0f1a8b | pbrook | case '0': case '1': case '2': case '3': case '4': |
2614 | 4b0f1a8b | pbrook | case '5': case '6': case '7': case '8': case '9': |
2615 | 4b0f1a8b | pbrook | { |
2616 | 4b0f1a8b | pbrook | int width;
|
2617 | 4b0f1a8b | pbrook | unsigned long value; |
2618 | 4b0f1a8b | pbrook | |
2619 | 4b0f1a8b | pbrook | c = arm_decode_bitfield (c, given, &value, &width); |
2620 | 4b0f1a8b | pbrook | |
2621 | 4b0f1a8b | pbrook | switch (*c)
|
2622 | 4b0f1a8b | pbrook | { |
2623 | 4b0f1a8b | pbrook | case 'r': |
2624 | 4b0f1a8b | pbrook | func (stream, "%s", arm_regnames[value]);
|
2625 | 4b0f1a8b | pbrook | break;
|
2626 | 4b0f1a8b | pbrook | case 'd': |
2627 | 4b0f1a8b | pbrook | func (stream, "%ld", value);
|
2628 | 4b0f1a8b | pbrook | break;
|
2629 | 4b0f1a8b | pbrook | case 'e': |
2630 | 4b0f1a8b | pbrook | func (stream, "%ld", (1ul << width) - value); |
2631 | 4b0f1a8b | pbrook | break;
|
2632 | 4b0f1a8b | pbrook | |
2633 | 4b0f1a8b | pbrook | case 'S': |
2634 | 4b0f1a8b | pbrook | case 'T': |
2635 | 4b0f1a8b | pbrook | case 'U': |
2636 | 4b0f1a8b | pbrook | /* various width encodings */
|
2637 | 4b0f1a8b | pbrook | { |
2638 | 4b0f1a8b | pbrook | int base = 8 << (*c - 'S'); /* 8,16 or 32 */ |
2639 | 4b0f1a8b | pbrook | int limit;
|
2640 | 4b0f1a8b | pbrook | unsigned low, high;
|
2641 | 4b0f1a8b | pbrook | |
2642 | 4b0f1a8b | pbrook | c++; |
2643 | 4b0f1a8b | pbrook | if (*c >= '0' && *c <= '9') |
2644 | 4b0f1a8b | pbrook | limit = *c - '0';
|
2645 | 4b0f1a8b | pbrook | else if (*c >= 'a' && *c <= 'f') |
2646 | 4b0f1a8b | pbrook | limit = *c - 'a' + 10; |
2647 | 4b0f1a8b | pbrook | else
|
2648 | 4b0f1a8b | pbrook | abort (); |
2649 | 4b0f1a8b | pbrook | low = limit >> 2;
|
2650 | 4b0f1a8b | pbrook | high = limit & 3;
|
2651 | 4b0f1a8b | pbrook | |
2652 | 4b0f1a8b | pbrook | if (value < low || value > high)
|
2653 | 4b0f1a8b | pbrook | func (stream, "<illegal width %d>", base << value);
|
2654 | 4b0f1a8b | pbrook | else
|
2655 | 4b0f1a8b | pbrook | func (stream, "%d", base << value);
|
2656 | 4b0f1a8b | pbrook | } |
2657 | 4b0f1a8b | pbrook | break;
|
2658 | 4b0f1a8b | pbrook | case 'R': |
2659 | 4b0f1a8b | pbrook | if (given & (1 << 6)) |
2660 | 4b0f1a8b | pbrook | goto Q;
|
2661 | 4b0f1a8b | pbrook | /* FALLTHROUGH */
|
2662 | 4b0f1a8b | pbrook | case 'D': |
2663 | 4b0f1a8b | pbrook | func (stream, "d%ld", value);
|
2664 | 4b0f1a8b | pbrook | break;
|
2665 | 4b0f1a8b | pbrook | case 'Q': |
2666 | 4b0f1a8b | pbrook | Q:
|
2667 | 4b0f1a8b | pbrook | if (value & 1) |
2668 | 4b0f1a8b | pbrook | func (stream, "<illegal reg q%ld.5>", value >> 1); |
2669 | 4b0f1a8b | pbrook | else
|
2670 | 4b0f1a8b | pbrook | func (stream, "q%ld", value >> 1); |
2671 | 4b0f1a8b | pbrook | break;
|
2672 | 4b0f1a8b | pbrook | |
2673 | 4b0f1a8b | pbrook | case '`': |
2674 | 4b0f1a8b | pbrook | c++; |
2675 | 4b0f1a8b | pbrook | if (value == 0) |
2676 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
2677 | 4b0f1a8b | pbrook | break;
|
2678 | 4b0f1a8b | pbrook | case '\'': |
2679 | 4b0f1a8b | pbrook | c++; |
2680 | 4b0f1a8b | pbrook | if (value == ((1ul << width) - 1)) |
2681 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
2682 | 4b0f1a8b | pbrook | break;
|
2683 | 4b0f1a8b | pbrook | case '?': |
2684 | 4b0f1a8b | pbrook | func (stream, "%c", c[(1 << width) - (int)value]); |
2685 | 4b0f1a8b | pbrook | c += 1 << width;
|
2686 | 4b0f1a8b | pbrook | break;
|
2687 | 4b0f1a8b | pbrook | default:
|
2688 | 4b0f1a8b | pbrook | abort (); |
2689 | 4b0f1a8b | pbrook | } |
2690 | 4b0f1a8b | pbrook | break;
|
2691 | 4b0f1a8b | pbrook | |
2692 | 4b0f1a8b | pbrook | default:
|
2693 | 4b0f1a8b | pbrook | abort (); |
2694 | 4b0f1a8b | pbrook | } |
2695 | 4b0f1a8b | pbrook | } |
2696 | 4b0f1a8b | pbrook | } |
2697 | 4b0f1a8b | pbrook | else
|
2698 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
2699 | 4b0f1a8b | pbrook | } |
2700 | 4b0f1a8b | pbrook | return TRUE;
|
2701 | 4b0f1a8b | pbrook | } |
2702 | 4b0f1a8b | pbrook | } |
2703 | 4b0f1a8b | pbrook | return FALSE;
|
2704 | 4b0f1a8b | pbrook | } |
2705 | 4b0f1a8b | pbrook | |
2706 | 4b0f1a8b | pbrook | /* Print one ARM instruction from PC on INFO->STREAM. */
|
2707 | 4b0f1a8b | pbrook | |
2708 | 4b0f1a8b | pbrook | static void |
2709 | 4b0f1a8b | pbrook | print_insn_arm_internal (bfd_vma pc, struct disassemble_info *info, long given) |
2710 | 4b0f1a8b | pbrook | { |
2711 | 4b0f1a8b | pbrook | const struct opcode32 *insn; |
2712 | 4b0f1a8b | pbrook | void *stream = info->stream;
|
2713 | 4b0f1a8b | pbrook | fprintf_ftype func = info->fprintf_func; |
2714 | 4b0f1a8b | pbrook | |
2715 | 4b0f1a8b | pbrook | if (print_insn_coprocessor (pc, info, given, FALSE))
|
2716 | 4b0f1a8b | pbrook | return;
|
2717 | 4b0f1a8b | pbrook | |
2718 | 4b0f1a8b | pbrook | if (print_insn_neon (info, given, FALSE))
|
2719 | 4b0f1a8b | pbrook | return;
|
2720 | 4b0f1a8b | pbrook | |
2721 | 4b0f1a8b | pbrook | for (insn = arm_opcodes; insn->assembler; insn++)
|
2722 | 4b0f1a8b | pbrook | { |
2723 | 4b0f1a8b | pbrook | if (insn->value == FIRST_IWMMXT_INSN
|
2724 | 4b0f1a8b | pbrook | && info->mach != bfd_mach_arm_XScale |
2725 | 4b0f1a8b | pbrook | && info->mach != bfd_mach_arm_iWMMXt) |
2726 | 4b0f1a8b | pbrook | insn = insn + IWMMXT_INSN_COUNT; |
2727 | 4b0f1a8b | pbrook | |
2728 | 4b0f1a8b | pbrook | if ((given & insn->mask) == insn->value
|
2729 | 4b0f1a8b | pbrook | /* Special case: an instruction with all bits set in the condition field
|
2730 | 4b0f1a8b | pbrook | (0xFnnn_nnnn) is only matched if all those bits are set in insn->mask,
|
2731 | 4b0f1a8b | pbrook | or by the catchall at the end of the table. */
|
2732 | 4b0f1a8b | pbrook | && ((given & 0xF0000000) != 0xF0000000 |
2733 | 4b0f1a8b | pbrook | || (insn->mask & 0xF0000000) == 0xF0000000 |
2734 | 4b0f1a8b | pbrook | || (insn->mask == 0 && insn->value == 0))) |
2735 | 4b0f1a8b | pbrook | { |
2736 | 4b0f1a8b | pbrook | const char *c; |
2737 | 4b0f1a8b | pbrook | |
2738 | 4b0f1a8b | pbrook | for (c = insn->assembler; *c; c++)
|
2739 | 4b0f1a8b | pbrook | { |
2740 | 4b0f1a8b | pbrook | if (*c == '%') |
2741 | 4b0f1a8b | pbrook | { |
2742 | 4b0f1a8b | pbrook | switch (*++c)
|
2743 | 4b0f1a8b | pbrook | { |
2744 | 4b0f1a8b | pbrook | case '%': |
2745 | 4b0f1a8b | pbrook | func (stream, "%%");
|
2746 | 4b0f1a8b | pbrook | break;
|
2747 | 4b0f1a8b | pbrook | |
2748 | 4b0f1a8b | pbrook | case 'a': |
2749 | 4b0f1a8b | pbrook | print_arm_address (pc, info, given); |
2750 | 4b0f1a8b | pbrook | break;
|
2751 | 4b0f1a8b | pbrook | |
2752 | 4b0f1a8b | pbrook | case 'P': |
2753 | 4b0f1a8b | pbrook | /* Set P address bit and use normal address
|
2754 | 4b0f1a8b | pbrook | printing routine. */
|
2755 | 4b0f1a8b | pbrook | print_arm_address (pc, info, given | (1 << 24)); |
2756 | 4b0f1a8b | pbrook | break;
|
2757 | 4b0f1a8b | pbrook | |
2758 | 4b0f1a8b | pbrook | case 's': |
2759 | 4b0f1a8b | pbrook | if ((given & 0x004f0000) == 0x004f0000) |
2760 | 4b0f1a8b | pbrook | { |
2761 | 4b0f1a8b | pbrook | /* PC relative with immediate offset. */
|
2762 | 4b0f1a8b | pbrook | int offset = ((given & 0xf00) >> 4) | (given & 0xf); |
2763 | 4b0f1a8b | pbrook | |
2764 | 4b0f1a8b | pbrook | if ((given & 0x00800000) == 0) |
2765 | 4b0f1a8b | pbrook | offset = -offset; |
2766 | 4b0f1a8b | pbrook | |
2767 | 4b0f1a8b | pbrook | func (stream, "[pc, #%d]\t; ", offset);
|
2768 | 4b0f1a8b | pbrook | info->print_address_func (offset + pc + 8, info);
|
2769 | 4b0f1a8b | pbrook | } |
2770 | 4b0f1a8b | pbrook | else
|
2771 | 4b0f1a8b | pbrook | { |
2772 | 4b0f1a8b | pbrook | func (stream, "[%s",
|
2773 | 4b0f1a8b | pbrook | arm_regnames[(given >> 16) & 0xf]); |
2774 | 4b0f1a8b | pbrook | if ((given & 0x01000000) != 0) |
2775 | 4b0f1a8b | pbrook | { |
2776 | 4b0f1a8b | pbrook | /* Pre-indexed. */
|
2777 | 4b0f1a8b | pbrook | if ((given & 0x00400000) == 0x00400000) |
2778 | 4b0f1a8b | pbrook | { |
2779 | 4b0f1a8b | pbrook | /* Immediate. */
|
2780 | 4b0f1a8b | pbrook | int offset = ((given & 0xf00) >> 4) | (given & 0xf); |
2781 | 4b0f1a8b | pbrook | if (offset)
|
2782 | 4b0f1a8b | pbrook | func (stream, ", #%s%d",
|
2783 | 4b0f1a8b | pbrook | (((given & 0x00800000) == 0) |
2784 | 4b0f1a8b | pbrook | ? "-" : ""), offset); |
2785 | 4b0f1a8b | pbrook | } |
2786 | 4b0f1a8b | pbrook | else
|
2787 | 4b0f1a8b | pbrook | { |
2788 | 4b0f1a8b | pbrook | /* Register. */
|
2789 | 4b0f1a8b | pbrook | func (stream, ", %s%s",
|
2790 | 4b0f1a8b | pbrook | (((given & 0x00800000) == 0) |
2791 | 4b0f1a8b | pbrook | ? "-" : ""), |
2792 | 4b0f1a8b | pbrook | arm_regnames[given & 0xf]);
|
2793 | 4b0f1a8b | pbrook | } |
2794 | 4b0f1a8b | pbrook | |
2795 | 4b0f1a8b | pbrook | func (stream, "]%s",
|
2796 | 4b0f1a8b | pbrook | ((given & 0x00200000) != 0) ? "!" : ""); |
2797 | 4b0f1a8b | pbrook | } |
2798 | 4b0f1a8b | pbrook | else
|
2799 | 4b0f1a8b | pbrook | { |
2800 | 4b0f1a8b | pbrook | /* Post-indexed. */
|
2801 | 4b0f1a8b | pbrook | if ((given & 0x00400000) == 0x00400000) |
2802 | 4b0f1a8b | pbrook | { |
2803 | 4b0f1a8b | pbrook | /* Immediate. */
|
2804 | 4b0f1a8b | pbrook | int offset = ((given & 0xf00) >> 4) | (given & 0xf); |
2805 | 4b0f1a8b | pbrook | if (offset)
|
2806 | 4b0f1a8b | pbrook | func (stream, "], #%s%d",
|
2807 | 4b0f1a8b | pbrook | (((given & 0x00800000) == 0) |
2808 | 4b0f1a8b | pbrook | ? "-" : ""), offset); |
2809 | 4b0f1a8b | pbrook | else
|
2810 | 4b0f1a8b | pbrook | func (stream, "]");
|
2811 | 4b0f1a8b | pbrook | } |
2812 | 4b0f1a8b | pbrook | else
|
2813 | 4b0f1a8b | pbrook | { |
2814 | 4b0f1a8b | pbrook | /* Register. */
|
2815 | 4b0f1a8b | pbrook | func (stream, "], %s%s",
|
2816 | 4b0f1a8b | pbrook | (((given & 0x00800000) == 0) |
2817 | 4b0f1a8b | pbrook | ? "-" : ""), |
2818 | 4b0f1a8b | pbrook | arm_regnames[given & 0xf]);
|
2819 | 4b0f1a8b | pbrook | } |
2820 | 4b0f1a8b | pbrook | } |
2821 | 4b0f1a8b | pbrook | } |
2822 | 4b0f1a8b | pbrook | break;
|
2823 | 4b0f1a8b | pbrook | |
2824 | 4b0f1a8b | pbrook | case 'b': |
2825 | 4b0f1a8b | pbrook | { |
2826 | 4b0f1a8b | pbrook | int disp = (((given & 0xffffff) ^ 0x800000) - 0x800000); |
2827 | 4b0f1a8b | pbrook | info->print_address_func (disp*4 + pc + 8, info); |
2828 | 4b0f1a8b | pbrook | } |
2829 | 4b0f1a8b | pbrook | break;
|
2830 | 4b0f1a8b | pbrook | |
2831 | 4b0f1a8b | pbrook | case 'c': |
2832 | 4b0f1a8b | pbrook | if (((given >> 28) & 0xf) != 0xe) |
2833 | 4b0f1a8b | pbrook | func (stream, "%s",
|
2834 | 4b0f1a8b | pbrook | arm_conditional [(given >> 28) & 0xf]); |
2835 | 4b0f1a8b | pbrook | break;
|
2836 | 4b0f1a8b | pbrook | |
2837 | 4b0f1a8b | pbrook | case 'm': |
2838 | 4b0f1a8b | pbrook | { |
2839 | 4b0f1a8b | pbrook | int started = 0; |
2840 | 4b0f1a8b | pbrook | int reg;
|
2841 | 4b0f1a8b | pbrook | |
2842 | 4b0f1a8b | pbrook | func (stream, "{");
|
2843 | 4b0f1a8b | pbrook | for (reg = 0; reg < 16; reg++) |
2844 | 4b0f1a8b | pbrook | if ((given & (1 << reg)) != 0) |
2845 | 4b0f1a8b | pbrook | { |
2846 | 4b0f1a8b | pbrook | if (started)
|
2847 | 4b0f1a8b | pbrook | func (stream, ", ");
|
2848 | 4b0f1a8b | pbrook | started = 1;
|
2849 | 4b0f1a8b | pbrook | func (stream, "%s", arm_regnames[reg]);
|
2850 | 4b0f1a8b | pbrook | } |
2851 | 4b0f1a8b | pbrook | func (stream, "}");
|
2852 | 4b0f1a8b | pbrook | } |
2853 | 4b0f1a8b | pbrook | break;
|
2854 | 4b0f1a8b | pbrook | |
2855 | 4b0f1a8b | pbrook | case 'q': |
2856 | 4b0f1a8b | pbrook | arm_decode_shift (given, func, stream, 0);
|
2857 | 4b0f1a8b | pbrook | break;
|
2858 | 4b0f1a8b | pbrook | |
2859 | 4b0f1a8b | pbrook | case 'o': |
2860 | 4b0f1a8b | pbrook | if ((given & 0x02000000) != 0) |
2861 | 4b0f1a8b | pbrook | { |
2862 | 4b0f1a8b | pbrook | int rotate = (given & 0xf00) >> 7; |
2863 | 4b0f1a8b | pbrook | int immed = (given & 0xff); |
2864 | 4b0f1a8b | pbrook | immed = (((immed << (32 - rotate))
|
2865 | 4b0f1a8b | pbrook | | (immed >> rotate)) & 0xffffffff);
|
2866 | 4b0f1a8b | pbrook | func (stream, "#%d\t; 0x%x", immed, immed);
|
2867 | 4b0f1a8b | pbrook | } |
2868 | 4b0f1a8b | pbrook | else
|
2869 | 4b0f1a8b | pbrook | arm_decode_shift (given, func, stream, 1);
|
2870 | 4b0f1a8b | pbrook | break;
|
2871 | 4b0f1a8b | pbrook | |
2872 | 4b0f1a8b | pbrook | case 'p': |
2873 | 4b0f1a8b | pbrook | if ((given & 0x0000f000) == 0x0000f000) |
2874 | 4b0f1a8b | pbrook | func (stream, "p");
|
2875 | 4b0f1a8b | pbrook | break;
|
2876 | 4b0f1a8b | pbrook | |
2877 | 4b0f1a8b | pbrook | case 't': |
2878 | 4b0f1a8b | pbrook | if ((given & 0x01200000) == 0x00200000) |
2879 | 4b0f1a8b | pbrook | func (stream, "t");
|
2880 | 4b0f1a8b | pbrook | break;
|
2881 | 4b0f1a8b | pbrook | |
2882 | 4b0f1a8b | pbrook | case 'A': |
2883 | 4b0f1a8b | pbrook | func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); |
2884 | 4b0f1a8b | pbrook | |
2885 | 4b0f1a8b | pbrook | if ((given & (1 << 24)) != 0) |
2886 | 4b0f1a8b | pbrook | { |
2887 | 4b0f1a8b | pbrook | int offset = given & 0xff; |
2888 | 4b0f1a8b | pbrook | |
2889 | 4b0f1a8b | pbrook | if (offset)
|
2890 | 4b0f1a8b | pbrook | func (stream, ", #%s%d]%s",
|
2891 | 4b0f1a8b | pbrook | ((given & 0x00800000) == 0 ? "-" : ""), |
2892 | 4b0f1a8b | pbrook | offset * 4,
|
2893 | 4b0f1a8b | pbrook | ((given & 0x00200000) != 0 ? "!" : "")); |
2894 | 4b0f1a8b | pbrook | else
|
2895 | 4b0f1a8b | pbrook | func (stream, "]");
|
2896 | 4b0f1a8b | pbrook | } |
2897 | 4b0f1a8b | pbrook | else
|
2898 | 4b0f1a8b | pbrook | { |
2899 | 4b0f1a8b | pbrook | int offset = given & 0xff; |
2900 | 4b0f1a8b | pbrook | |
2901 | 4b0f1a8b | pbrook | func (stream, "]");
|
2902 | 4b0f1a8b | pbrook | |
2903 | 4b0f1a8b | pbrook | if (given & (1 << 21)) |
2904 | 4b0f1a8b | pbrook | { |
2905 | 4b0f1a8b | pbrook | if (offset)
|
2906 | 4b0f1a8b | pbrook | func (stream, ", #%s%d",
|
2907 | 4b0f1a8b | pbrook | ((given & 0x00800000) == 0 ? "-" : ""), |
2908 | 4b0f1a8b | pbrook | offset * 4);
|
2909 | 4b0f1a8b | pbrook | } |
2910 | 4b0f1a8b | pbrook | else
|
2911 | 4b0f1a8b | pbrook | func (stream, ", {%d}", offset);
|
2912 | 4b0f1a8b | pbrook | } |
2913 | 4b0f1a8b | pbrook | break;
|
2914 | 4b0f1a8b | pbrook | |
2915 | 4b0f1a8b | pbrook | case 'B': |
2916 | 4b0f1a8b | pbrook | /* Print ARM V5 BLX(1) address: pc+25 bits. */
|
2917 | 4b0f1a8b | pbrook | { |
2918 | 4b0f1a8b | pbrook | bfd_vma address; |
2919 | 4b0f1a8b | pbrook | bfd_vma offset = 0;
|
2920 | 4b0f1a8b | pbrook | |
2921 | 4b0f1a8b | pbrook | if (given & 0x00800000) |
2922 | 4b0f1a8b | pbrook | /* Is signed, hi bits should be ones. */
|
2923 | 4b0f1a8b | pbrook | offset = (-1) ^ 0x00ffffff; |
2924 | 4b0f1a8b | pbrook | |
2925 | 4b0f1a8b | pbrook | /* Offset is (SignExtend(offset field)<<2). */
|
2926 | 4b0f1a8b | pbrook | offset += given & 0x00ffffff;
|
2927 | 4b0f1a8b | pbrook | offset <<= 2;
|
2928 | 4b0f1a8b | pbrook | address = offset + pc + 8;
|
2929 | 4b0f1a8b | pbrook | |
2930 | 4b0f1a8b | pbrook | if (given & 0x01000000) |
2931 | 4b0f1a8b | pbrook | /* H bit allows addressing to 2-byte boundaries. */
|
2932 | 4b0f1a8b | pbrook | address += 2;
|
2933 | 4b0f1a8b | pbrook | |
2934 | 4b0f1a8b | pbrook | info->print_address_func (address, info); |
2935 | 4b0f1a8b | pbrook | } |
2936 | 4b0f1a8b | pbrook | break;
|
2937 | 4b0f1a8b | pbrook | |
2938 | 4b0f1a8b | pbrook | case 'C': |
2939 | 4b0f1a8b | pbrook | func (stream, "_");
|
2940 | 4b0f1a8b | pbrook | if (given & 0x80000) |
2941 | 4b0f1a8b | pbrook | func (stream, "f");
|
2942 | 4b0f1a8b | pbrook | if (given & 0x40000) |
2943 | 4b0f1a8b | pbrook | func (stream, "s");
|
2944 | 4b0f1a8b | pbrook | if (given & 0x20000) |
2945 | 4b0f1a8b | pbrook | func (stream, "x");
|
2946 | 4b0f1a8b | pbrook | if (given & 0x10000) |
2947 | 4b0f1a8b | pbrook | func (stream, "c");
|
2948 | 4b0f1a8b | pbrook | break;
|
2949 | 4b0f1a8b | pbrook | |
2950 | 4b0f1a8b | pbrook | case 'U': |
2951 | 4b0f1a8b | pbrook | switch (given & 0xf) |
2952 | 4b0f1a8b | pbrook | { |
2953 | 4b0f1a8b | pbrook | case 0xf: func(stream, "sy"); break; |
2954 | 4b0f1a8b | pbrook | case 0x7: func(stream, "un"); break; |
2955 | 4b0f1a8b | pbrook | case 0xe: func(stream, "st"); break; |
2956 | 4b0f1a8b | pbrook | case 0x6: func(stream, "unst"); break; |
2957 | 4b0f1a8b | pbrook | default:
|
2958 | 4b0f1a8b | pbrook | func(stream, "#%d", (int)given & 0xf); |
2959 | 4b0f1a8b | pbrook | break;
|
2960 | 4b0f1a8b | pbrook | } |
2961 | 4b0f1a8b | pbrook | break;
|
2962 | 4b0f1a8b | pbrook | |
2963 | 4b0f1a8b | pbrook | case '0': case '1': case '2': case '3': case '4': |
2964 | 4b0f1a8b | pbrook | case '5': case '6': case '7': case '8': case '9': |
2965 | 4b0f1a8b | pbrook | { |
2966 | 4b0f1a8b | pbrook | int width;
|
2967 | 4b0f1a8b | pbrook | unsigned long value; |
2968 | 4b0f1a8b | pbrook | |
2969 | 4b0f1a8b | pbrook | c = arm_decode_bitfield (c, given, &value, &width); |
2970 | 4b0f1a8b | pbrook | |
2971 | 4b0f1a8b | pbrook | switch (*c)
|
2972 | 4b0f1a8b | pbrook | { |
2973 | 4b0f1a8b | pbrook | case 'r': |
2974 | 4b0f1a8b | pbrook | func (stream, "%s", arm_regnames[value]);
|
2975 | 4b0f1a8b | pbrook | break;
|
2976 | 4b0f1a8b | pbrook | case 'd': |
2977 | 4b0f1a8b | pbrook | func (stream, "%ld", value);
|
2978 | 4b0f1a8b | pbrook | break;
|
2979 | 4b0f1a8b | pbrook | case 'b': |
2980 | 4b0f1a8b | pbrook | func (stream, "%ld", value * 8); |
2981 | 4b0f1a8b | pbrook | break;
|
2982 | 4b0f1a8b | pbrook | case 'W': |
2983 | 4b0f1a8b | pbrook | func (stream, "%ld", value + 1); |
2984 | 4b0f1a8b | pbrook | break;
|
2985 | 4b0f1a8b | pbrook | case 'x': |
2986 | 4b0f1a8b | pbrook | func (stream, "0x%08lx", value);
|
2987 | 4b0f1a8b | pbrook | |
2988 | 4b0f1a8b | pbrook | /* Some SWI instructions have special
|
2989 | 4b0f1a8b | pbrook | meanings. */
|
2990 | 4b0f1a8b | pbrook | if ((given & 0x0fffffff) == 0x0FF00000) |
2991 | 4b0f1a8b | pbrook | func (stream, "\t; IMB");
|
2992 | 4b0f1a8b | pbrook | else if ((given & 0x0fffffff) == 0x0FF00001) |
2993 | 4b0f1a8b | pbrook | func (stream, "\t; IMBRange");
|
2994 | 4b0f1a8b | pbrook | break;
|
2995 | 4b0f1a8b | pbrook | case 'X': |
2996 | 4b0f1a8b | pbrook | func (stream, "%01lx", value & 0xf); |
2997 | 4b0f1a8b | pbrook | break;
|
2998 | 4b0f1a8b | pbrook | case '`': |
2999 | 4b0f1a8b | pbrook | c++; |
3000 | 4b0f1a8b | pbrook | if (value == 0) |
3001 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
3002 | 4b0f1a8b | pbrook | break;
|
3003 | 4b0f1a8b | pbrook | case '\'': |
3004 | 4b0f1a8b | pbrook | c++; |
3005 | 4b0f1a8b | pbrook | if (value == ((1ul << width) - 1)) |
3006 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
3007 | 4b0f1a8b | pbrook | break;
|
3008 | 4b0f1a8b | pbrook | case '?': |
3009 | 4b0f1a8b | pbrook | func (stream, "%c", c[(1 << width) - (int)value]); |
3010 | 4b0f1a8b | pbrook | c += 1 << width;
|
3011 | 4b0f1a8b | pbrook | break;
|
3012 | 4b0f1a8b | pbrook | default:
|
3013 | 4b0f1a8b | pbrook | abort (); |
3014 | 4b0f1a8b | pbrook | } |
3015 | 4b0f1a8b | pbrook | break;
|
3016 | 4b0f1a8b | pbrook | |
3017 | 4b0f1a8b | pbrook | case 'e': |
3018 | 4b0f1a8b | pbrook | { |
3019 | 4b0f1a8b | pbrook | int imm;
|
3020 | 4b0f1a8b | pbrook | |
3021 | 4b0f1a8b | pbrook | imm = (given & 0xf) | ((given & 0xfff00) >> 4); |
3022 | 4b0f1a8b | pbrook | func (stream, "%d", imm);
|
3023 | 4b0f1a8b | pbrook | } |
3024 | 4b0f1a8b | pbrook | break;
|
3025 | 4b0f1a8b | pbrook | |
3026 | 4b0f1a8b | pbrook | case 'E': |
3027 | 4b0f1a8b | pbrook | /* LSB and WIDTH fields of BFI or BFC. The machine-
|
3028 | 4b0f1a8b | pbrook | language instruction encodes LSB and MSB. */
|
3029 | 4b0f1a8b | pbrook | { |
3030 | 4b0f1a8b | pbrook | long msb = (given & 0x001f0000) >> 16; |
3031 | 4b0f1a8b | pbrook | long lsb = (given & 0x00000f80) >> 7; |
3032 | 4b0f1a8b | pbrook | |
3033 | 4b0f1a8b | pbrook | long width = msb - lsb + 1; |
3034 | 4b0f1a8b | pbrook | if (width > 0) |
3035 | 4b0f1a8b | pbrook | func (stream, "#%lu, #%lu", lsb, width);
|
3036 | 4b0f1a8b | pbrook | else
|
3037 | 4b0f1a8b | pbrook | func (stream, "(invalid: %lu:%lu)", lsb, msb);
|
3038 | 4b0f1a8b | pbrook | } |
3039 | 4b0f1a8b | pbrook | break;
|
3040 | 4b0f1a8b | pbrook | |
3041 | 4b0f1a8b | pbrook | case 'V': |
3042 | 4b0f1a8b | pbrook | /* 16-bit unsigned immediate from a MOVT or MOVW
|
3043 | 4b0f1a8b | pbrook | instruction, encoded in bits 0:11 and 15:19. */
|
3044 | 4b0f1a8b | pbrook | { |
3045 | 4b0f1a8b | pbrook | long hi = (given & 0x000f0000) >> 4; |
3046 | 4b0f1a8b | pbrook | long lo = (given & 0x00000fff); |
3047 | 4b0f1a8b | pbrook | long imm16 = hi | lo;
|
3048 | 4b0f1a8b | pbrook | func (stream, "#%lu\t; 0x%lx", imm16, imm16);
|
3049 | 4b0f1a8b | pbrook | } |
3050 | 4b0f1a8b | pbrook | break;
|
3051 | 4b0f1a8b | pbrook | |
3052 | 4b0f1a8b | pbrook | default:
|
3053 | 4b0f1a8b | pbrook | abort (); |
3054 | 4b0f1a8b | pbrook | } |
3055 | 4b0f1a8b | pbrook | } |
3056 | 4b0f1a8b | pbrook | } |
3057 | 4b0f1a8b | pbrook | else
|
3058 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
3059 | 4b0f1a8b | pbrook | } |
3060 | 4b0f1a8b | pbrook | return;
|
3061 | 4b0f1a8b | pbrook | } |
3062 | 4b0f1a8b | pbrook | } |
3063 | 4b0f1a8b | pbrook | abort (); |
3064 | 4b0f1a8b | pbrook | } |
3065 | 4b0f1a8b | pbrook | |
3066 | 4b0f1a8b | pbrook | /* Print one 16-bit Thumb instruction from PC on INFO->STREAM. */
|
3067 | 4b0f1a8b | pbrook | |
3068 | 4b0f1a8b | pbrook | static void |
3069 | 4b0f1a8b | pbrook | print_insn_thumb16 (bfd_vma pc, struct disassemble_info *info, long given) |
3070 | 4b0f1a8b | pbrook | { |
3071 | 4b0f1a8b | pbrook | const struct opcode16 *insn; |
3072 | 4b0f1a8b | pbrook | void *stream = info->stream;
|
3073 | 4b0f1a8b | pbrook | fprintf_ftype func = info->fprintf_func; |
3074 | 4b0f1a8b | pbrook | |
3075 | 4b0f1a8b | pbrook | for (insn = thumb_opcodes; insn->assembler; insn++)
|
3076 | 4b0f1a8b | pbrook | if ((given & insn->mask) == insn->value)
|
3077 | 4b0f1a8b | pbrook | { |
3078 | 4b0f1a8b | pbrook | const char *c = insn->assembler; |
3079 | 4b0f1a8b | pbrook | for (; *c; c++)
|
3080 | 4b0f1a8b | pbrook | { |
3081 | 4b0f1a8b | pbrook | int domaskpc = 0; |
3082 | 4b0f1a8b | pbrook | int domasklr = 0; |
3083 | 4b0f1a8b | pbrook | |
3084 | 4b0f1a8b | pbrook | if (*c != '%') |
3085 | 4b0f1a8b | pbrook | { |
3086 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
3087 | 4b0f1a8b | pbrook | continue;
|
3088 | 4b0f1a8b | pbrook | } |
3089 | 4b0f1a8b | pbrook | |
3090 | 4b0f1a8b | pbrook | switch (*++c)
|
3091 | 4b0f1a8b | pbrook | { |
3092 | 4b0f1a8b | pbrook | case '%': |
3093 | 4b0f1a8b | pbrook | func (stream, "%%");
|
3094 | 4b0f1a8b | pbrook | break;
|
3095 | 4b0f1a8b | pbrook | |
3096 | 4b0f1a8b | pbrook | case 'c': |
3097 | 4b0f1a8b | pbrook | if (ifthen_state)
|
3098 | 4b0f1a8b | pbrook | func (stream, "%s", arm_conditional[IFTHEN_COND]);
|
3099 | 4b0f1a8b | pbrook | break;
|
3100 | 4b0f1a8b | pbrook | |
3101 | 4b0f1a8b | pbrook | case 'C': |
3102 | 4b0f1a8b | pbrook | if (ifthen_state)
|
3103 | 4b0f1a8b | pbrook | func (stream, "%s", arm_conditional[IFTHEN_COND]);
|
3104 | 4b0f1a8b | pbrook | else
|
3105 | 4b0f1a8b | pbrook | func (stream, "s");
|
3106 | 4b0f1a8b | pbrook | break;
|
3107 | 4b0f1a8b | pbrook | |
3108 | 4b0f1a8b | pbrook | case 'I': |
3109 | 4b0f1a8b | pbrook | { |
3110 | 4b0f1a8b | pbrook | unsigned int tmp; |
3111 | 4b0f1a8b | pbrook | |
3112 | 4b0f1a8b | pbrook | ifthen_next_state = given & 0xff;
|
3113 | 4b0f1a8b | pbrook | for (tmp = given << 1; tmp & 0xf; tmp <<= 1) |
3114 | 4b0f1a8b | pbrook | func (stream, ((given ^ tmp) & 0x10) ? "e" : "t"); |
3115 | 4b0f1a8b | pbrook | func (stream, "\t%s", arm_conditional[(given >> 4) & 0xf]); |
3116 | 4b0f1a8b | pbrook | } |
3117 | 4b0f1a8b | pbrook | break;
|
3118 | 4b0f1a8b | pbrook | |
3119 | 4b0f1a8b | pbrook | case 'x': |
3120 | 4b0f1a8b | pbrook | if (ifthen_next_state)
|
3121 | 4b0f1a8b | pbrook | func (stream, "\t; unpredictable branch in IT block\n");
|
3122 | 4b0f1a8b | pbrook | break;
|
3123 | 4b0f1a8b | pbrook | |
3124 | 4b0f1a8b | pbrook | case 'X': |
3125 | 4b0f1a8b | pbrook | if (ifthen_state)
|
3126 | 4b0f1a8b | pbrook | func (stream, "\t; unpredictable <IT:%s>",
|
3127 | 4b0f1a8b | pbrook | arm_conditional[IFTHEN_COND]); |
3128 | 4b0f1a8b | pbrook | break;
|
3129 | 4b0f1a8b | pbrook | |
3130 | 4b0f1a8b | pbrook | case 'S': |
3131 | 4b0f1a8b | pbrook | { |
3132 | 4b0f1a8b | pbrook | long reg;
|
3133 | 4b0f1a8b | pbrook | |
3134 | 4b0f1a8b | pbrook | reg = (given >> 3) & 0x7; |
3135 | 4b0f1a8b | pbrook | if (given & (1 << 6)) |
3136 | 4b0f1a8b | pbrook | reg += 8;
|
3137 | 4b0f1a8b | pbrook | |
3138 | 4b0f1a8b | pbrook | func (stream, "%s", arm_regnames[reg]);
|
3139 | 4b0f1a8b | pbrook | } |
3140 | 4b0f1a8b | pbrook | break;
|
3141 | 4b0f1a8b | pbrook | |
3142 | 4b0f1a8b | pbrook | case 'D': |
3143 | 4b0f1a8b | pbrook | { |
3144 | 4b0f1a8b | pbrook | long reg;
|
3145 | 4b0f1a8b | pbrook | |
3146 | 4b0f1a8b | pbrook | reg = given & 0x7;
|
3147 | 4b0f1a8b | pbrook | if (given & (1 << 7)) |
3148 | 4b0f1a8b | pbrook | reg += 8;
|
3149 | 4b0f1a8b | pbrook | |
3150 | 4b0f1a8b | pbrook | func (stream, "%s", arm_regnames[reg]);
|
3151 | 4b0f1a8b | pbrook | } |
3152 | 4b0f1a8b | pbrook | break;
|
3153 | 4b0f1a8b | pbrook | |
3154 | 4b0f1a8b | pbrook | case 'N': |
3155 | 4b0f1a8b | pbrook | if (given & (1 << 8)) |
3156 | 4b0f1a8b | pbrook | domasklr = 1;
|
3157 | 4b0f1a8b | pbrook | /* Fall through. */
|
3158 | 4b0f1a8b | pbrook | case 'O': |
3159 | 4b0f1a8b | pbrook | if (*c == 'O' && (given & (1 << 8))) |
3160 | 4b0f1a8b | pbrook | domaskpc = 1;
|
3161 | 4b0f1a8b | pbrook | /* Fall through. */
|
3162 | 4b0f1a8b | pbrook | case 'M': |
3163 | 4b0f1a8b | pbrook | { |
3164 | 4b0f1a8b | pbrook | int started = 0; |
3165 | 4b0f1a8b | pbrook | int reg;
|
3166 | 4b0f1a8b | pbrook | |
3167 | 4b0f1a8b | pbrook | func (stream, "{");
|
3168 | 4b0f1a8b | pbrook | |
3169 | 4b0f1a8b | pbrook | /* It would be nice if we could spot
|
3170 | 4b0f1a8b | pbrook | ranges, and generate the rS-rE format: */
|
3171 | 4b0f1a8b | pbrook | for (reg = 0; (reg < 8); reg++) |
3172 | 4b0f1a8b | pbrook | if ((given & (1 << reg)) != 0) |
3173 | 4b0f1a8b | pbrook | { |
3174 | 4b0f1a8b | pbrook | if (started)
|
3175 | 4b0f1a8b | pbrook | func (stream, ", ");
|
3176 | 4b0f1a8b | pbrook | started = 1;
|
3177 | 4b0f1a8b | pbrook | func (stream, "%s", arm_regnames[reg]);
|
3178 | 4b0f1a8b | pbrook | } |
3179 | 4b0f1a8b | pbrook | |
3180 | 4b0f1a8b | pbrook | if (domasklr)
|
3181 | 4b0f1a8b | pbrook | { |
3182 | 4b0f1a8b | pbrook | if (started)
|
3183 | 4b0f1a8b | pbrook | func (stream, ", ");
|
3184 | 4b0f1a8b | pbrook | started = 1;
|
3185 | 4b0f1a8b | pbrook | func (stream, arm_regnames[14] /* "lr" */); |
3186 | 4b0f1a8b | pbrook | } |
3187 | 4b0f1a8b | pbrook | |
3188 | 4b0f1a8b | pbrook | if (domaskpc)
|
3189 | 4b0f1a8b | pbrook | { |
3190 | 4b0f1a8b | pbrook | if (started)
|
3191 | 4b0f1a8b | pbrook | func (stream, ", ");
|
3192 | 4b0f1a8b | pbrook | func (stream, arm_regnames[15] /* "pc" */); |
3193 | 4b0f1a8b | pbrook | } |
3194 | aa0aa4fa | bellard | |
3195 | 4b0f1a8b | pbrook | func (stream, "}");
|
3196 | 4b0f1a8b | pbrook | } |
3197 | 4b0f1a8b | pbrook | break;
|
3198 | aa0aa4fa | bellard | |
3199 | 4b0f1a8b | pbrook | case 'b': |
3200 | 4b0f1a8b | pbrook | /* Print ARM V6T2 CZB address: pc+4+6 bits. */
|
3201 | 4b0f1a8b | pbrook | { |
3202 | 4b0f1a8b | pbrook | bfd_vma address = (pc + 4
|
3203 | 4b0f1a8b | pbrook | + ((given & 0x00f8) >> 2) |
3204 | 4b0f1a8b | pbrook | + ((given & 0x0200) >> 3)); |
3205 | 4b0f1a8b | pbrook | info->print_address_func (address, info); |
3206 | 4b0f1a8b | pbrook | } |
3207 | 4b0f1a8b | pbrook | break;
|
3208 | aa0aa4fa | bellard | |
3209 | 4b0f1a8b | pbrook | case 's': |
3210 | 4b0f1a8b | pbrook | /* Right shift immediate -- bits 6..10; 1-31 print
|
3211 | 4b0f1a8b | pbrook | as themselves, 0 prints as 32. */
|
3212 | 4b0f1a8b | pbrook | { |
3213 | 4b0f1a8b | pbrook | long imm = (given & 0x07c0) >> 6; |
3214 | 4b0f1a8b | pbrook | if (imm == 0) |
3215 | 4b0f1a8b | pbrook | imm = 32;
|
3216 | 4b0f1a8b | pbrook | func (stream, "#%ld", imm);
|
3217 | 4b0f1a8b | pbrook | } |
3218 | 4b0f1a8b | pbrook | break;
|
3219 | aa0aa4fa | bellard | |
3220 | 4b0f1a8b | pbrook | case '0': case '1': case '2': case '3': case '4': |
3221 | 4b0f1a8b | pbrook | case '5': case '6': case '7': case '8': case '9': |
3222 | 4b0f1a8b | pbrook | { |
3223 | 4b0f1a8b | pbrook | int bitstart = *c++ - '0'; |
3224 | 4b0f1a8b | pbrook | int bitend = 0; |
3225 | 3b46e624 | ths | |
3226 | 4b0f1a8b | pbrook | while (*c >= '0' && *c <= '9') |
3227 | 4b0f1a8b | pbrook | bitstart = (bitstart * 10) + *c++ - '0'; |
3228 | aa0aa4fa | bellard | |
3229 | 4b0f1a8b | pbrook | switch (*c)
|
3230 | 4b0f1a8b | pbrook | { |
3231 | 4b0f1a8b | pbrook | case '-': |
3232 | 4b0f1a8b | pbrook | { |
3233 | 4b0f1a8b | pbrook | long reg;
|
3234 | 4b0f1a8b | pbrook | |
3235 | 4b0f1a8b | pbrook | c++; |
3236 | 4b0f1a8b | pbrook | while (*c >= '0' && *c <= '9') |
3237 | 4b0f1a8b | pbrook | bitend = (bitend * 10) + *c++ - '0'; |
3238 | 4b0f1a8b | pbrook | if (!bitend)
|
3239 | 4b0f1a8b | pbrook | abort (); |
3240 | 4b0f1a8b | pbrook | reg = given >> bitstart; |
3241 | 4b0f1a8b | pbrook | reg &= (2 << (bitend - bitstart)) - 1; |
3242 | 4b0f1a8b | pbrook | switch (*c)
|
3243 | 4b0f1a8b | pbrook | { |
3244 | 4b0f1a8b | pbrook | case 'r': |
3245 | 4b0f1a8b | pbrook | func (stream, "%s", arm_regnames[reg]);
|
3246 | 4b0f1a8b | pbrook | break;
|
3247 | 4b0f1a8b | pbrook | |
3248 | 4b0f1a8b | pbrook | case 'd': |
3249 | 4b0f1a8b | pbrook | func (stream, "%ld", reg);
|
3250 | 4b0f1a8b | pbrook | break;
|
3251 | 4b0f1a8b | pbrook | |
3252 | 4b0f1a8b | pbrook | case 'H': |
3253 | 4b0f1a8b | pbrook | func (stream, "%ld", reg << 1); |
3254 | 4b0f1a8b | pbrook | break;
|
3255 | 4b0f1a8b | pbrook | |
3256 | 4b0f1a8b | pbrook | case 'W': |
3257 | 4b0f1a8b | pbrook | func (stream, "%ld", reg << 2); |
3258 | 4b0f1a8b | pbrook | break;
|
3259 | 4b0f1a8b | pbrook | |
3260 | 4b0f1a8b | pbrook | case 'a': |
3261 | 4b0f1a8b | pbrook | /* PC-relative address -- the bottom two
|
3262 | 4b0f1a8b | pbrook | bits of the address are dropped
|
3263 | 4b0f1a8b | pbrook | before the calculation. */
|
3264 | 4b0f1a8b | pbrook | info->print_address_func |
3265 | 4b0f1a8b | pbrook | (((pc + 4) & ~3) + (reg << 2), info); |
3266 | 4b0f1a8b | pbrook | break;
|
3267 | 4b0f1a8b | pbrook | |
3268 | 4b0f1a8b | pbrook | case 'x': |
3269 | 4b0f1a8b | pbrook | func (stream, "0x%04lx", reg);
|
3270 | 4b0f1a8b | pbrook | break;
|
3271 | 4b0f1a8b | pbrook | |
3272 | 4b0f1a8b | pbrook | case 'B': |
3273 | 4b0f1a8b | pbrook | reg = ((reg ^ (1 << bitend)) - (1 << bitend)); |
3274 | 4b0f1a8b | pbrook | info->print_address_func (reg * 2 + pc + 4, info); |
3275 | 4b0f1a8b | pbrook | break;
|
3276 | 4b0f1a8b | pbrook | |
3277 | 4b0f1a8b | pbrook | case 'c': |
3278 | 4b0f1a8b | pbrook | func (stream, "%s", arm_conditional [reg]);
|
3279 | 4b0f1a8b | pbrook | break;
|
3280 | 4b0f1a8b | pbrook | |
3281 | 4b0f1a8b | pbrook | default:
|
3282 | 4b0f1a8b | pbrook | abort (); |
3283 | 4b0f1a8b | pbrook | } |
3284 | 4b0f1a8b | pbrook | } |
3285 | 4b0f1a8b | pbrook | break;
|
3286 | 4b0f1a8b | pbrook | |
3287 | 4b0f1a8b | pbrook | case '\'': |
3288 | 4b0f1a8b | pbrook | c++; |
3289 | 4b0f1a8b | pbrook | if ((given & (1 << bitstart)) != 0) |
3290 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
3291 | 4b0f1a8b | pbrook | break;
|
3292 | 4b0f1a8b | pbrook | |
3293 | 4b0f1a8b | pbrook | case '?': |
3294 | 4b0f1a8b | pbrook | ++c; |
3295 | 4b0f1a8b | pbrook | if ((given & (1 << bitstart)) != 0) |
3296 | 4b0f1a8b | pbrook | func (stream, "%c", *c++);
|
3297 | 4b0f1a8b | pbrook | else
|
3298 | 4b0f1a8b | pbrook | func (stream, "%c", *++c);
|
3299 | 4b0f1a8b | pbrook | break;
|
3300 | 4b0f1a8b | pbrook | |
3301 | 4b0f1a8b | pbrook | default:
|
3302 | 4b0f1a8b | pbrook | abort (); |
3303 | 4b0f1a8b | pbrook | } |
3304 | 4b0f1a8b | pbrook | } |
3305 | 4b0f1a8b | pbrook | break;
|
3306 | 4b0f1a8b | pbrook | |
3307 | 4b0f1a8b | pbrook | default:
|
3308 | 4b0f1a8b | pbrook | abort (); |
3309 | 4b0f1a8b | pbrook | } |
3310 | 4b0f1a8b | pbrook | } |
3311 | 4b0f1a8b | pbrook | return;
|
3312 | 4b0f1a8b | pbrook | } |
3313 | aa0aa4fa | bellard | |
3314 | aa0aa4fa | bellard | /* No match. */
|
3315 | aa0aa4fa | bellard | abort (); |
3316 | aa0aa4fa | bellard | } |
3317 | aa0aa4fa | bellard | |
3318 | 4b0f1a8b | pbrook | /* Return the name of an V7M special register. */
|
3319 | 4b0f1a8b | pbrook | static const char * |
3320 | 4b0f1a8b | pbrook | psr_name (int regno)
|
3321 | 4b0f1a8b | pbrook | { |
3322 | 4b0f1a8b | pbrook | switch (regno)
|
3323 | 4b0f1a8b | pbrook | { |
3324 | 4b0f1a8b | pbrook | case 0: return "APSR"; |
3325 | 4b0f1a8b | pbrook | case 1: return "IAPSR"; |
3326 | 4b0f1a8b | pbrook | case 2: return "EAPSR"; |
3327 | 4b0f1a8b | pbrook | case 3: return "PSR"; |
3328 | 4b0f1a8b | pbrook | case 5: return "IPSR"; |
3329 | 4b0f1a8b | pbrook | case 6: return "EPSR"; |
3330 | 4b0f1a8b | pbrook | case 7: return "IEPSR"; |
3331 | 4b0f1a8b | pbrook | case 8: return "MSP"; |
3332 | 4b0f1a8b | pbrook | case 9: return "PSP"; |
3333 | 4b0f1a8b | pbrook | case 16: return "PRIMASK"; |
3334 | 4b0f1a8b | pbrook | case 17: return "BASEPRI"; |
3335 | 4b0f1a8b | pbrook | case 18: return "BASEPRI_MASK"; |
3336 | 4b0f1a8b | pbrook | case 19: return "FAULTMASK"; |
3337 | 4b0f1a8b | pbrook | case 20: return "CONTROL"; |
3338 | 4b0f1a8b | pbrook | default: return "<unknown>"; |
3339 | 4b0f1a8b | pbrook | } |
3340 | 4b0f1a8b | pbrook | } |
3341 | 4b0f1a8b | pbrook | |
3342 | 4b0f1a8b | pbrook | /* Print one 32-bit Thumb instruction from PC on INFO->STREAM. */
|
3343 | aa0aa4fa | bellard | |
3344 | 4b0f1a8b | pbrook | static void |
3345 | 4b0f1a8b | pbrook | print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) |
3346 | aa0aa4fa | bellard | { |
3347 | 4b0f1a8b | pbrook | const struct opcode32 *insn; |
3348 | 4b0f1a8b | pbrook | void *stream = info->stream;
|
3349 | 4b0f1a8b | pbrook | fprintf_ftype func = info->fprintf_func; |
3350 | 3b46e624 | ths | |
3351 | 4b0f1a8b | pbrook | if (print_insn_coprocessor (pc, info, given, TRUE))
|
3352 | 4b0f1a8b | pbrook | return;
|
3353 | 5fafdf24 | ths | |
3354 | 4b0f1a8b | pbrook | if (print_insn_neon (info, given, TRUE))
|
3355 | 4b0f1a8b | pbrook | return;
|
3356 | aa0aa4fa | bellard | |
3357 | 4b0f1a8b | pbrook | for (insn = thumb32_opcodes; insn->assembler; insn++)
|
3358 | 4b0f1a8b | pbrook | if ((given & insn->mask) == insn->value)
|
3359 | 4b0f1a8b | pbrook | { |
3360 | 4b0f1a8b | pbrook | const char *c = insn->assembler; |
3361 | 4b0f1a8b | pbrook | for (; *c; c++)
|
3362 | aa0aa4fa | bellard | { |
3363 | 4b0f1a8b | pbrook | if (*c != '%') |
3364 | 4b0f1a8b | pbrook | { |
3365 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
3366 | 4b0f1a8b | pbrook | continue;
|
3367 | 4b0f1a8b | pbrook | } |
3368 | 4b0f1a8b | pbrook | |
3369 | 4b0f1a8b | pbrook | switch (*++c)
|
3370 | 4b0f1a8b | pbrook | { |
3371 | 4b0f1a8b | pbrook | case '%': |
3372 | 4b0f1a8b | pbrook | func (stream, "%%");
|
3373 | 4b0f1a8b | pbrook | break;
|
3374 | 4b0f1a8b | pbrook | |
3375 | 4b0f1a8b | pbrook | case 'c': |
3376 | 4b0f1a8b | pbrook | if (ifthen_state)
|
3377 | 4b0f1a8b | pbrook | func (stream, "%s", arm_conditional[IFTHEN_COND]);
|
3378 | 4b0f1a8b | pbrook | break;
|
3379 | 4b0f1a8b | pbrook | |
3380 | 4b0f1a8b | pbrook | case 'x': |
3381 | 4b0f1a8b | pbrook | if (ifthen_next_state)
|
3382 | 4b0f1a8b | pbrook | func (stream, "\t; unpredictable branch in IT block\n");
|
3383 | 4b0f1a8b | pbrook | break;
|
3384 | 4b0f1a8b | pbrook | |
3385 | 4b0f1a8b | pbrook | case 'X': |
3386 | 4b0f1a8b | pbrook | if (ifthen_state)
|
3387 | 4b0f1a8b | pbrook | func (stream, "\t; unpredictable <IT:%s>",
|
3388 | 4b0f1a8b | pbrook | arm_conditional[IFTHEN_COND]); |
3389 | 4b0f1a8b | pbrook | break;
|
3390 | 4b0f1a8b | pbrook | |
3391 | 4b0f1a8b | pbrook | case 'I': |
3392 | 4b0f1a8b | pbrook | { |
3393 | 4b0f1a8b | pbrook | unsigned int imm12 = 0; |
3394 | 4b0f1a8b | pbrook | imm12 |= (given & 0x000000ffu);
|
3395 | 4b0f1a8b | pbrook | imm12 |= (given & 0x00007000u) >> 4; |
3396 | 4b0f1a8b | pbrook | imm12 |= (given & 0x04000000u) >> 15; |
3397 | 4b0f1a8b | pbrook | func (stream, "#%u\t; 0x%x", imm12, imm12);
|
3398 | 4b0f1a8b | pbrook | } |
3399 | 4b0f1a8b | pbrook | break;
|
3400 | 3b46e624 | ths | |
3401 | 4b0f1a8b | pbrook | case 'M': |
3402 | 4b0f1a8b | pbrook | { |
3403 | 4b0f1a8b | pbrook | unsigned int bits = 0, imm, imm8, mod; |
3404 | 4b0f1a8b | pbrook | bits |= (given & 0x000000ffu);
|
3405 | 4b0f1a8b | pbrook | bits |= (given & 0x00007000u) >> 4; |
3406 | 4b0f1a8b | pbrook | bits |= (given & 0x04000000u) >> 15; |
3407 | 4b0f1a8b | pbrook | imm8 = (bits & 0x0ff);
|
3408 | 4b0f1a8b | pbrook | mod = (bits & 0xf00) >> 8; |
3409 | 4b0f1a8b | pbrook | switch (mod)
|
3410 | 4b0f1a8b | pbrook | { |
3411 | 4b0f1a8b | pbrook | case 0: imm = imm8; break; |
3412 | 4b0f1a8b | pbrook | case 1: imm = ((imm8<<16) | imm8); break; |
3413 | 4b0f1a8b | pbrook | case 2: imm = ((imm8<<24) | (imm8 << 8)); break; |
3414 | 4b0f1a8b | pbrook | case 3: imm = ((imm8<<24) | (imm8 << 16) | (imm8 << 8) | imm8); break; |
3415 | 4b0f1a8b | pbrook | default:
|
3416 | 4b0f1a8b | pbrook | mod = (bits & 0xf80) >> 7; |
3417 | 4b0f1a8b | pbrook | imm8 = (bits & 0x07f) | 0x80; |
3418 | 4b0f1a8b | pbrook | imm = (((imm8 << (32 - mod)) | (imm8 >> mod)) & 0xffffffff); |
3419 | 4b0f1a8b | pbrook | } |
3420 | 4b0f1a8b | pbrook | func (stream, "#%u\t; 0x%x", imm, imm);
|
3421 | 4b0f1a8b | pbrook | } |
3422 | 4b0f1a8b | pbrook | break;
|
3423 | 4b0f1a8b | pbrook | |
3424 | 4b0f1a8b | pbrook | case 'J': |
3425 | 4b0f1a8b | pbrook | { |
3426 | 4b0f1a8b | pbrook | unsigned int imm = 0; |
3427 | 4b0f1a8b | pbrook | imm |= (given & 0x000000ffu);
|
3428 | 4b0f1a8b | pbrook | imm |= (given & 0x00007000u) >> 4; |
3429 | 4b0f1a8b | pbrook | imm |= (given & 0x04000000u) >> 15; |
3430 | 4b0f1a8b | pbrook | imm |= (given & 0x000f0000u) >> 4; |
3431 | 4b0f1a8b | pbrook | func (stream, "#%u\t; 0x%x", imm, imm);
|
3432 | 4b0f1a8b | pbrook | } |
3433 | 4b0f1a8b | pbrook | break;
|
3434 | 4b0f1a8b | pbrook | |
3435 | 4b0f1a8b | pbrook | case 'K': |
3436 | 4b0f1a8b | pbrook | { |
3437 | 4b0f1a8b | pbrook | unsigned int imm = 0; |
3438 | 4b0f1a8b | pbrook | imm |= (given & 0x000f0000u) >> 16; |
3439 | 4b0f1a8b | pbrook | imm |= (given & 0x00000ff0u) >> 0; |
3440 | 4b0f1a8b | pbrook | imm |= (given & 0x0000000fu) << 12; |
3441 | 4b0f1a8b | pbrook | func (stream, "#%u\t; 0x%x", imm, imm);
|
3442 | 4b0f1a8b | pbrook | } |
3443 | 4b0f1a8b | pbrook | break;
|
3444 | 4b0f1a8b | pbrook | |
3445 | 4b0f1a8b | pbrook | case 'S': |
3446 | 4b0f1a8b | pbrook | { |
3447 | 4b0f1a8b | pbrook | unsigned int reg = (given & 0x0000000fu); |
3448 | 4b0f1a8b | pbrook | unsigned int stp = (given & 0x00000030u) >> 4; |
3449 | 4b0f1a8b | pbrook | unsigned int imm = 0; |
3450 | 4b0f1a8b | pbrook | imm |= (given & 0x000000c0u) >> 6; |
3451 | 4b0f1a8b | pbrook | imm |= (given & 0x00007000u) >> 10; |
3452 | 4b0f1a8b | pbrook | |
3453 | 4b0f1a8b | pbrook | func (stream, "%s", arm_regnames[reg]);
|
3454 | 4b0f1a8b | pbrook | switch (stp)
|
3455 | 4b0f1a8b | pbrook | { |
3456 | 4b0f1a8b | pbrook | case 0: |
3457 | 4b0f1a8b | pbrook | if (imm > 0) |
3458 | 4b0f1a8b | pbrook | func (stream, ", lsl #%u", imm);
|
3459 | 4b0f1a8b | pbrook | break;
|
3460 | 4b0f1a8b | pbrook | |
3461 | 4b0f1a8b | pbrook | case 1: |
3462 | 4b0f1a8b | pbrook | if (imm == 0) |
3463 | 4b0f1a8b | pbrook | imm = 32;
|
3464 | 4b0f1a8b | pbrook | func (stream, ", lsr #%u", imm);
|
3465 | 4b0f1a8b | pbrook | break;
|
3466 | 4b0f1a8b | pbrook | |
3467 | 4b0f1a8b | pbrook | case 2: |
3468 | 4b0f1a8b | pbrook | if (imm == 0) |
3469 | 4b0f1a8b | pbrook | imm = 32;
|
3470 | 4b0f1a8b | pbrook | func (stream, ", asr #%u", imm);
|
3471 | 4b0f1a8b | pbrook | break;
|
3472 | 4b0f1a8b | pbrook | |
3473 | 4b0f1a8b | pbrook | case 3: |
3474 | 4b0f1a8b | pbrook | if (imm == 0) |
3475 | 4b0f1a8b | pbrook | func (stream, ", rrx");
|
3476 | 4b0f1a8b | pbrook | else
|
3477 | 4b0f1a8b | pbrook | func (stream, ", ror #%u", imm);
|
3478 | 4b0f1a8b | pbrook | } |
3479 | 4b0f1a8b | pbrook | } |
3480 | 4b0f1a8b | pbrook | break;
|
3481 | 4b0f1a8b | pbrook | |
3482 | 4b0f1a8b | pbrook | case 'a': |
3483 | 4b0f1a8b | pbrook | { |
3484 | 4b0f1a8b | pbrook | unsigned int Rn = (given & 0x000f0000) >> 16; |
3485 | 4b0f1a8b | pbrook | unsigned int U = (given & 0x00800000) >> 23; |
3486 | 4b0f1a8b | pbrook | unsigned int op = (given & 0x00000f00) >> 8; |
3487 | 4b0f1a8b | pbrook | unsigned int i12 = (given & 0x00000fff); |
3488 | 4b0f1a8b | pbrook | unsigned int i8 = (given & 0x000000ff); |
3489 | 4b0f1a8b | pbrook | bfd_boolean writeback = FALSE, postind = FALSE; |
3490 | 4b0f1a8b | pbrook | int offset = 0; |
3491 | 4b0f1a8b | pbrook | |
3492 | 4b0f1a8b | pbrook | func (stream, "[%s", arm_regnames[Rn]);
|
3493 | 4b0f1a8b | pbrook | if (U) /* 12-bit positive immediate offset */ |
3494 | 4b0f1a8b | pbrook | offset = i12; |
3495 | 4b0f1a8b | pbrook | else if (Rn == 15) /* 12-bit negative immediate offset */ |
3496 | 4b0f1a8b | pbrook | offset = -(int)i12;
|
3497 | 4b0f1a8b | pbrook | else if (op == 0x0) /* shifted register offset */ |
3498 | 4b0f1a8b | pbrook | { |
3499 | 4b0f1a8b | pbrook | unsigned int Rm = (i8 & 0x0f); |
3500 | 4b0f1a8b | pbrook | unsigned int sh = (i8 & 0x30) >> 4; |
3501 | 4b0f1a8b | pbrook | func (stream, ", %s", arm_regnames[Rm]);
|
3502 | 4b0f1a8b | pbrook | if (sh)
|
3503 | 4b0f1a8b | pbrook | func (stream, ", lsl #%u", sh);
|
3504 | 4b0f1a8b | pbrook | func (stream, "]");
|
3505 | 4b0f1a8b | pbrook | break;
|
3506 | 4b0f1a8b | pbrook | } |
3507 | 4b0f1a8b | pbrook | else switch (op) |
3508 | 4b0f1a8b | pbrook | { |
3509 | 4b0f1a8b | pbrook | case 0xE: /* 8-bit positive immediate offset */ |
3510 | 4b0f1a8b | pbrook | offset = i8; |
3511 | 4b0f1a8b | pbrook | break;
|
3512 | 4b0f1a8b | pbrook | |
3513 | 4b0f1a8b | pbrook | case 0xC: /* 8-bit negative immediate offset */ |
3514 | 4b0f1a8b | pbrook | offset = -i8; |
3515 | 4b0f1a8b | pbrook | break;
|
3516 | 4b0f1a8b | pbrook | |
3517 | 4b0f1a8b | pbrook | case 0xF: /* 8-bit + preindex with wb */ |
3518 | 4b0f1a8b | pbrook | offset = i8; |
3519 | 4b0f1a8b | pbrook | writeback = TRUE; |
3520 | 4b0f1a8b | pbrook | break;
|
3521 | 4b0f1a8b | pbrook | |
3522 | 4b0f1a8b | pbrook | case 0xD: /* 8-bit - preindex with wb */ |
3523 | 4b0f1a8b | pbrook | offset = -i8; |
3524 | 4b0f1a8b | pbrook | writeback = TRUE; |
3525 | 4b0f1a8b | pbrook | break;
|
3526 | 4b0f1a8b | pbrook | |
3527 | 4b0f1a8b | pbrook | case 0xB: /* 8-bit + postindex */ |
3528 | 4b0f1a8b | pbrook | offset = i8; |
3529 | 4b0f1a8b | pbrook | postind = TRUE; |
3530 | 4b0f1a8b | pbrook | break;
|
3531 | 4b0f1a8b | pbrook | |
3532 | 4b0f1a8b | pbrook | case 0x9: /* 8-bit - postindex */ |
3533 | 4b0f1a8b | pbrook | offset = -i8; |
3534 | 4b0f1a8b | pbrook | postind = TRUE; |
3535 | 4b0f1a8b | pbrook | break;
|
3536 | 4b0f1a8b | pbrook | |
3537 | 4b0f1a8b | pbrook | default:
|
3538 | 4b0f1a8b | pbrook | func (stream, ", <undefined>]");
|
3539 | 4b0f1a8b | pbrook | goto skip;
|
3540 | 4b0f1a8b | pbrook | } |
3541 | 4b0f1a8b | pbrook | |
3542 | 4b0f1a8b | pbrook | if (postind)
|
3543 | 4b0f1a8b | pbrook | func (stream, "], #%d", offset);
|
3544 | 4b0f1a8b | pbrook | else
|
3545 | 4b0f1a8b | pbrook | { |
3546 | 4b0f1a8b | pbrook | if (offset)
|
3547 | 4b0f1a8b | pbrook | func (stream, ", #%d", offset);
|
3548 | 4b0f1a8b | pbrook | func (stream, writeback ? "]!" : "]"); |
3549 | 4b0f1a8b | pbrook | } |
3550 | 4b0f1a8b | pbrook | |
3551 | 4b0f1a8b | pbrook | if (Rn == 15) |
3552 | 4b0f1a8b | pbrook | { |
3553 | 4b0f1a8b | pbrook | func (stream, "\t; ");
|
3554 | 4b0f1a8b | pbrook | info->print_address_func (((pc + 4) & ~3) + offset, info); |
3555 | 4b0f1a8b | pbrook | } |
3556 | 4b0f1a8b | pbrook | } |
3557 | 4b0f1a8b | pbrook | skip:
|
3558 | 4b0f1a8b | pbrook | break;
|
3559 | 4b0f1a8b | pbrook | |
3560 | 4b0f1a8b | pbrook | case 'A': |
3561 | 4b0f1a8b | pbrook | { |
3562 | 4b0f1a8b | pbrook | unsigned int P = (given & 0x01000000) >> 24; |
3563 | 4b0f1a8b | pbrook | unsigned int U = (given & 0x00800000) >> 23; |
3564 | 4b0f1a8b | pbrook | unsigned int W = (given & 0x00400000) >> 21; |
3565 | 4b0f1a8b | pbrook | unsigned int Rn = (given & 0x000f0000) >> 16; |
3566 | 4b0f1a8b | pbrook | unsigned int off = (given & 0x000000ff); |
3567 | 4b0f1a8b | pbrook | |
3568 | 4b0f1a8b | pbrook | func (stream, "[%s", arm_regnames[Rn]);
|
3569 | 4b0f1a8b | pbrook | if (P)
|
3570 | 4b0f1a8b | pbrook | { |
3571 | 4b0f1a8b | pbrook | if (off || !U)
|
3572 | 4b0f1a8b | pbrook | func (stream, ", #%c%u", U ? '+' : '-', off * 4); |
3573 | 4b0f1a8b | pbrook | func (stream, "]");
|
3574 | 4b0f1a8b | pbrook | if (W)
|
3575 | 4b0f1a8b | pbrook | func (stream, "!");
|
3576 | 4b0f1a8b | pbrook | } |
3577 | 4b0f1a8b | pbrook | else
|
3578 | 4b0f1a8b | pbrook | { |
3579 | 4b0f1a8b | pbrook | func (stream, "], ");
|
3580 | 4b0f1a8b | pbrook | if (W)
|
3581 | 4b0f1a8b | pbrook | func (stream, "#%c%u", U ? '+' : '-', off * 4); |
3582 | 4b0f1a8b | pbrook | else
|
3583 | 4b0f1a8b | pbrook | func (stream, "{%u}", off);
|
3584 | 4b0f1a8b | pbrook | } |
3585 | 4b0f1a8b | pbrook | } |
3586 | 4b0f1a8b | pbrook | break;
|
3587 | 4b0f1a8b | pbrook | |
3588 | 4b0f1a8b | pbrook | case 'w': |
3589 | 4b0f1a8b | pbrook | { |
3590 | 4b0f1a8b | pbrook | unsigned int Sbit = (given & 0x01000000) >> 24; |
3591 | 4b0f1a8b | pbrook | unsigned int type = (given & 0x00600000) >> 21; |
3592 | 4b0f1a8b | pbrook | switch (type)
|
3593 | 4b0f1a8b | pbrook | { |
3594 | 4b0f1a8b | pbrook | case 0: func (stream, Sbit ? "sb" : "b"); break; |
3595 | 4b0f1a8b | pbrook | case 1: func (stream, Sbit ? "sh" : "h"); break; |
3596 | 4b0f1a8b | pbrook | case 2: |
3597 | 4b0f1a8b | pbrook | if (Sbit)
|
3598 | 4b0f1a8b | pbrook | func (stream, "??");
|
3599 | 4b0f1a8b | pbrook | break;
|
3600 | 4b0f1a8b | pbrook | case 3: |
3601 | 4b0f1a8b | pbrook | func (stream, "??");
|
3602 | 4b0f1a8b | pbrook | break;
|
3603 | 4b0f1a8b | pbrook | } |
3604 | 4b0f1a8b | pbrook | } |
3605 | 4b0f1a8b | pbrook | break;
|
3606 | 4b0f1a8b | pbrook | |
3607 | 4b0f1a8b | pbrook | case 'm': |
3608 | 4b0f1a8b | pbrook | { |
3609 | 4b0f1a8b | pbrook | int started = 0; |
3610 | 4b0f1a8b | pbrook | int reg;
|
3611 | 4b0f1a8b | pbrook | |
3612 | 4b0f1a8b | pbrook | func (stream, "{");
|
3613 | 4b0f1a8b | pbrook | for (reg = 0; reg < 16; reg++) |
3614 | 4b0f1a8b | pbrook | if ((given & (1 << reg)) != 0) |
3615 | 4b0f1a8b | pbrook | { |
3616 | 4b0f1a8b | pbrook | if (started)
|
3617 | 4b0f1a8b | pbrook | func (stream, ", ");
|
3618 | 4b0f1a8b | pbrook | started = 1;
|
3619 | 4b0f1a8b | pbrook | func (stream, "%s", arm_regnames[reg]);
|
3620 | 4b0f1a8b | pbrook | } |
3621 | 4b0f1a8b | pbrook | func (stream, "}");
|
3622 | 4b0f1a8b | pbrook | } |
3623 | 4b0f1a8b | pbrook | break;
|
3624 | 4b0f1a8b | pbrook | |
3625 | 4b0f1a8b | pbrook | case 'E': |
3626 | 4b0f1a8b | pbrook | { |
3627 | 4b0f1a8b | pbrook | unsigned int msb = (given & 0x0000001f); |
3628 | 4b0f1a8b | pbrook | unsigned int lsb = 0; |
3629 | 4b0f1a8b | pbrook | lsb |= (given & 0x000000c0u) >> 6; |
3630 | 4b0f1a8b | pbrook | lsb |= (given & 0x00007000u) >> 10; |
3631 | 4b0f1a8b | pbrook | func (stream, "#%u, #%u", lsb, msb - lsb + 1); |
3632 | 4b0f1a8b | pbrook | } |
3633 | 4b0f1a8b | pbrook | break;
|
3634 | 4b0f1a8b | pbrook | |
3635 | 4b0f1a8b | pbrook | case 'F': |
3636 | 4b0f1a8b | pbrook | { |
3637 | 4b0f1a8b | pbrook | unsigned int width = (given & 0x0000001f) + 1; |
3638 | 4b0f1a8b | pbrook | unsigned int lsb = 0; |
3639 | 4b0f1a8b | pbrook | lsb |= (given & 0x000000c0u) >> 6; |
3640 | 4b0f1a8b | pbrook | lsb |= (given & 0x00007000u) >> 10; |
3641 | 4b0f1a8b | pbrook | func (stream, "#%u, #%u", lsb, width);
|
3642 | 4b0f1a8b | pbrook | } |
3643 | 4b0f1a8b | pbrook | break;
|
3644 | 4b0f1a8b | pbrook | |
3645 | 4b0f1a8b | pbrook | case 'b': |
3646 | 4b0f1a8b | pbrook | { |
3647 | 4b0f1a8b | pbrook | unsigned int S = (given & 0x04000000u) >> 26; |
3648 | 4b0f1a8b | pbrook | unsigned int J1 = (given & 0x00002000u) >> 13; |
3649 | 4b0f1a8b | pbrook | unsigned int J2 = (given & 0x00000800u) >> 11; |
3650 | 4b0f1a8b | pbrook | int offset = 0; |
3651 | 4b0f1a8b | pbrook | |
3652 | 4b0f1a8b | pbrook | offset |= !S << 20;
|
3653 | 4b0f1a8b | pbrook | offset |= J2 << 19;
|
3654 | 4b0f1a8b | pbrook | offset |= J1 << 18;
|
3655 | 4b0f1a8b | pbrook | offset |= (given & 0x003f0000) >> 4; |
3656 | 4b0f1a8b | pbrook | offset |= (given & 0x000007ff) << 1; |
3657 | 4b0f1a8b | pbrook | offset -= (1 << 20); |
3658 | 4b0f1a8b | pbrook | |
3659 | 4b0f1a8b | pbrook | info->print_address_func (pc + 4 + offset, info);
|
3660 | 4b0f1a8b | pbrook | } |
3661 | 4b0f1a8b | pbrook | break;
|
3662 | 4b0f1a8b | pbrook | |
3663 | 4b0f1a8b | pbrook | case 'B': |
3664 | 4b0f1a8b | pbrook | { |
3665 | 4b0f1a8b | pbrook | unsigned int S = (given & 0x04000000u) >> 26; |
3666 | 4b0f1a8b | pbrook | unsigned int I1 = (given & 0x00002000u) >> 13; |
3667 | 4b0f1a8b | pbrook | unsigned int I2 = (given & 0x00000800u) >> 11; |
3668 | 4b0f1a8b | pbrook | int offset = 0; |
3669 | 4b0f1a8b | pbrook | |
3670 | 4b0f1a8b | pbrook | offset |= !S << 24;
|
3671 | 4b0f1a8b | pbrook | offset |= !(I1 ^ S) << 23;
|
3672 | 4b0f1a8b | pbrook | offset |= !(I2 ^ S) << 22;
|
3673 | 4b0f1a8b | pbrook | offset |= (given & 0x03ff0000u) >> 4; |
3674 | 4b0f1a8b | pbrook | offset |= (given & 0x000007ffu) << 1; |
3675 | 4b0f1a8b | pbrook | offset -= (1 << 24); |
3676 | 4b0f1a8b | pbrook | offset += pc + 4;
|
3677 | 4b0f1a8b | pbrook | |
3678 | 4b0f1a8b | pbrook | /* BLX target addresses are always word aligned. */
|
3679 | 4b0f1a8b | pbrook | if ((given & 0x00001000u) == 0) |
3680 | 4b0f1a8b | pbrook | offset &= ~2u;
|
3681 | 4b0f1a8b | pbrook | |
3682 | 4b0f1a8b | pbrook | info->print_address_func (offset, info); |
3683 | 4b0f1a8b | pbrook | } |
3684 | 4b0f1a8b | pbrook | break;
|
3685 | 4b0f1a8b | pbrook | |
3686 | 4b0f1a8b | pbrook | case 's': |
3687 | 4b0f1a8b | pbrook | { |
3688 | 4b0f1a8b | pbrook | unsigned int shift = 0; |
3689 | 4b0f1a8b | pbrook | shift |= (given & 0x000000c0u) >> 6; |
3690 | 4b0f1a8b | pbrook | shift |= (given & 0x00007000u) >> 10; |
3691 | 4b0f1a8b | pbrook | if (given & 0x00200000u) |
3692 | 4b0f1a8b | pbrook | func (stream, ", asr #%u", shift);
|
3693 | 4b0f1a8b | pbrook | else if (shift) |
3694 | 4b0f1a8b | pbrook | func (stream, ", lsl #%u", shift);
|
3695 | 4b0f1a8b | pbrook | /* else print nothing - lsl #0 */
|
3696 | 4b0f1a8b | pbrook | } |
3697 | 4b0f1a8b | pbrook | break;
|
3698 | 4b0f1a8b | pbrook | |
3699 | 4b0f1a8b | pbrook | case 'R': |
3700 | 4b0f1a8b | pbrook | { |
3701 | 4b0f1a8b | pbrook | unsigned int rot = (given & 0x00000030) >> 4; |
3702 | 4b0f1a8b | pbrook | if (rot)
|
3703 | 4b0f1a8b | pbrook | func (stream, ", ror #%u", rot * 8); |
3704 | 4b0f1a8b | pbrook | } |
3705 | 4b0f1a8b | pbrook | break;
|
3706 | 4b0f1a8b | pbrook | |
3707 | 4b0f1a8b | pbrook | case 'U': |
3708 | 4b0f1a8b | pbrook | switch (given & 0xf) |
3709 | 4b0f1a8b | pbrook | { |
3710 | 4b0f1a8b | pbrook | case 0xf: func(stream, "sy"); break; |
3711 | 4b0f1a8b | pbrook | case 0x7: func(stream, "un"); break; |
3712 | 4b0f1a8b | pbrook | case 0xe: func(stream, "st"); break; |
3713 | 4b0f1a8b | pbrook | case 0x6: func(stream, "unst"); break; |
3714 | 4b0f1a8b | pbrook | default:
|
3715 | 4b0f1a8b | pbrook | func(stream, "#%d", (int)given & 0xf); |
3716 | 4b0f1a8b | pbrook | break;
|
3717 | 4b0f1a8b | pbrook | } |
3718 | 4b0f1a8b | pbrook | break;
|
3719 | 4b0f1a8b | pbrook | |
3720 | 4b0f1a8b | pbrook | case 'C': |
3721 | 4b0f1a8b | pbrook | if ((given & 0xff) == 0) |
3722 | 4b0f1a8b | pbrook | { |
3723 | 4b0f1a8b | pbrook | func (stream, "%cPSR_", (given & 0x100000) ? 'S' : 'C'); |
3724 | 4b0f1a8b | pbrook | if (given & 0x800) |
3725 | 4b0f1a8b | pbrook | func (stream, "f");
|
3726 | 4b0f1a8b | pbrook | if (given & 0x400) |
3727 | 4b0f1a8b | pbrook | func (stream, "s");
|
3728 | 4b0f1a8b | pbrook | if (given & 0x200) |
3729 | 4b0f1a8b | pbrook | func (stream, "x");
|
3730 | 4b0f1a8b | pbrook | if (given & 0x100) |
3731 | 4b0f1a8b | pbrook | func (stream, "c");
|
3732 | 4b0f1a8b | pbrook | } |
3733 | 4b0f1a8b | pbrook | else
|
3734 | 4b0f1a8b | pbrook | { |
3735 | 4b0f1a8b | pbrook | func (stream, psr_name (given & 0xff));
|
3736 | 4b0f1a8b | pbrook | } |
3737 | 4b0f1a8b | pbrook | break;
|
3738 | 4b0f1a8b | pbrook | |
3739 | 4b0f1a8b | pbrook | case 'D': |
3740 | 4b0f1a8b | pbrook | if ((given & 0xff) == 0) |
3741 | 4b0f1a8b | pbrook | func (stream, "%cPSR", (given & 0x100000) ? 'S' : 'C'); |
3742 | 4b0f1a8b | pbrook | else
|
3743 | 4b0f1a8b | pbrook | func (stream, psr_name (given & 0xff));
|
3744 | 4b0f1a8b | pbrook | break;
|
3745 | 4b0f1a8b | pbrook | |
3746 | 4b0f1a8b | pbrook | case '0': case '1': case '2': case '3': case '4': |
3747 | 4b0f1a8b | pbrook | case '5': case '6': case '7': case '8': case '9': |
3748 | 4b0f1a8b | pbrook | { |
3749 | 4b0f1a8b | pbrook | int width;
|
3750 | 4b0f1a8b | pbrook | unsigned long val; |
3751 | 4b0f1a8b | pbrook | |
3752 | 4b0f1a8b | pbrook | c = arm_decode_bitfield (c, given, &val, &width); |
3753 | 4b0f1a8b | pbrook | |
3754 | 4b0f1a8b | pbrook | switch (*c)
|
3755 | 4b0f1a8b | pbrook | { |
3756 | 4b0f1a8b | pbrook | case 'd': func (stream, "%lu", val); break; |
3757 | 4b0f1a8b | pbrook | case 'W': func (stream, "%lu", val * 4); break; |
3758 | 4b0f1a8b | pbrook | case 'r': func (stream, "%s", arm_regnames[val]); break; |
3759 | 4b0f1a8b | pbrook | |
3760 | 4b0f1a8b | pbrook | case 'c': |
3761 | 4b0f1a8b | pbrook | func (stream, "%s", arm_conditional[val]);
|
3762 | 4b0f1a8b | pbrook | break;
|
3763 | 4b0f1a8b | pbrook | |
3764 | 4b0f1a8b | pbrook | case '\'': |
3765 | 4b0f1a8b | pbrook | c++; |
3766 | 4b0f1a8b | pbrook | if (val == ((1ul << width) - 1)) |
3767 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
3768 | 4b0f1a8b | pbrook | break;
|
3769 | 4b0f1a8b | pbrook | |
3770 | 4b0f1a8b | pbrook | case '`': |
3771 | 4b0f1a8b | pbrook | c++; |
3772 | 4b0f1a8b | pbrook | if (val == 0) |
3773 | 4b0f1a8b | pbrook | func (stream, "%c", *c);
|
3774 | 4b0f1a8b | pbrook | break;
|
3775 | 4b0f1a8b | pbrook | |
3776 | 4b0f1a8b | pbrook | case '?': |
3777 | 4b0f1a8b | pbrook | func (stream, "%c", c[(1 << width) - (int)val]); |
3778 | 4b0f1a8b | pbrook | c += 1 << width;
|
3779 | 4b0f1a8b | pbrook | break;
|
3780 | 4b0f1a8b | pbrook | |
3781 | 4b0f1a8b | pbrook | default:
|
3782 | 4b0f1a8b | pbrook | abort (); |
3783 | 4b0f1a8b | pbrook | } |
3784 | 4b0f1a8b | pbrook | } |
3785 | 4b0f1a8b | pbrook | break;
|
3786 | 3b46e624 | ths | |
3787 | 4b0f1a8b | pbrook | default:
|
3788 | 4b0f1a8b | pbrook | abort (); |
3789 | 4b0f1a8b | pbrook | } |
3790 | 4b0f1a8b | pbrook | } |
3791 | 4b0f1a8b | pbrook | return;
|
3792 | 4b0f1a8b | pbrook | } |
3793 | 4b0f1a8b | pbrook | |
3794 | 4b0f1a8b | pbrook | /* No match. */
|
3795 | 4b0f1a8b | pbrook | abort (); |
3796 | aa0aa4fa | bellard | } |
3797 | aa0aa4fa | bellard | |
3798 | 4b0f1a8b | pbrook | /* Print data bytes on INFO->STREAM. */
|
3799 | aa0aa4fa | bellard | |
3800 | aa0aa4fa | bellard | static void |
3801 | 4b0f1a8b | pbrook | print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED, struct disassemble_info *info,
|
3802 | 4b0f1a8b | pbrook | long given)
|
3803 | aa0aa4fa | bellard | { |
3804 | 4b0f1a8b | pbrook | switch (info->bytes_per_chunk)
|
3805 | 4b0f1a8b | pbrook | { |
3806 | 4b0f1a8b | pbrook | case 1: |
3807 | 4b0f1a8b | pbrook | info->fprintf_func (info->stream, ".byte\t0x%02lx", given);
|
3808 | 4b0f1a8b | pbrook | break;
|
3809 | 4b0f1a8b | pbrook | case 2: |
3810 | 4b0f1a8b | pbrook | info->fprintf_func (info->stream, ".short\t0x%04lx", given);
|
3811 | 4b0f1a8b | pbrook | break;
|
3812 | 4b0f1a8b | pbrook | case 4: |
3813 | 4b0f1a8b | pbrook | info->fprintf_func (info->stream, ".word\t0x%08lx", given);
|
3814 | 4b0f1a8b | pbrook | break;
|
3815 | 4b0f1a8b | pbrook | default:
|
3816 | 4b0f1a8b | pbrook | abort (); |
3817 | 4b0f1a8b | pbrook | } |
3818 | 4b0f1a8b | pbrook | } |
3819 | aa0aa4fa | bellard | |
3820 | 4b0f1a8b | pbrook | /* Search back through the insn stream to determine if this instruction is
|
3821 | 4b0f1a8b | pbrook | conditionally executed. */
|
3822 | 4b0f1a8b | pbrook | static void |
3823 | 4b0f1a8b | pbrook | find_ifthen_state (bfd_vma pc, struct disassemble_info *info,
|
3824 | 4b0f1a8b | pbrook | bfd_boolean little) |
3825 | 4b0f1a8b | pbrook | { |
3826 | 4b0f1a8b | pbrook | unsigned char b[2]; |
3827 | 4b0f1a8b | pbrook | unsigned int insn; |
3828 | 4b0f1a8b | pbrook | int status;
|
3829 | 4b0f1a8b | pbrook | /* COUNT is twice the number of instructions seen. It will be odd if we
|
3830 | 4b0f1a8b | pbrook | just crossed an instruction boundary. */
|
3831 | 4b0f1a8b | pbrook | int count;
|
3832 | 4b0f1a8b | pbrook | int it_count;
|
3833 | 4b0f1a8b | pbrook | unsigned int seen_it; |
3834 | 4b0f1a8b | pbrook | bfd_vma addr; |
3835 | 4b0f1a8b | pbrook | |
3836 | 4b0f1a8b | pbrook | ifthen_address = pc; |
3837 | 4b0f1a8b | pbrook | ifthen_state = 0;
|
3838 | 4b0f1a8b | pbrook | |
3839 | 4b0f1a8b | pbrook | addr = pc; |
3840 | 4b0f1a8b | pbrook | count = 1;
|
3841 | 4b0f1a8b | pbrook | it_count = 0;
|
3842 | 4b0f1a8b | pbrook | seen_it = 0;
|
3843 | 4b0f1a8b | pbrook | /* Scan backwards looking for IT instructions, keeping track of where
|
3844 | 4b0f1a8b | pbrook | instruction boundaries are. We don't know if something is actually an
|
3845 | 4b0f1a8b | pbrook | IT instruction until we find a definite instruction boundary. */
|
3846 | 4b0f1a8b | pbrook | for (;;)
|
3847 | aa0aa4fa | bellard | { |
3848 | 4b0f1a8b | pbrook | if (addr == 0 || info->symbol_at_address_func(addr, info)) |
3849 | 4b0f1a8b | pbrook | { |
3850 | 4b0f1a8b | pbrook | /* A symbol must be on an instruction boundary, and will not
|
3851 | 4b0f1a8b | pbrook | be within an IT block. */
|
3852 | 4b0f1a8b | pbrook | if (seen_it && (count & 1)) |
3853 | 4b0f1a8b | pbrook | break;
|
3854 | 4b0f1a8b | pbrook | |
3855 | 4b0f1a8b | pbrook | return;
|
3856 | 4b0f1a8b | pbrook | } |
3857 | 4b0f1a8b | pbrook | addr -= 2;
|
3858 | 4b0f1a8b | pbrook | status = info->read_memory_func (addr, (bfd_byte *)b, 2, info);
|
3859 | 4b0f1a8b | pbrook | if (status)
|
3860 | 4b0f1a8b | pbrook | return;
|
3861 | aa0aa4fa | bellard | |
3862 | 4b0f1a8b | pbrook | if (little)
|
3863 | 4b0f1a8b | pbrook | insn = (b[0]) | (b[1] << 8); |
3864 | 4b0f1a8b | pbrook | else
|
3865 | 4b0f1a8b | pbrook | insn = (b[1]) | (b[0] << 8); |
3866 | 4b0f1a8b | pbrook | if (seen_it)
|
3867 | 4b0f1a8b | pbrook | { |
3868 | 4b0f1a8b | pbrook | if ((insn & 0xf800) < 0xe800) |
3869 | 4b0f1a8b | pbrook | { |
3870 | 4b0f1a8b | pbrook | /* Addr + 2 is an instruction boundary. See if this matches
|
3871 | 4b0f1a8b | pbrook | the expected boundary based on the position of the last
|
3872 | 4b0f1a8b | pbrook | IT candidate. */
|
3873 | 4b0f1a8b | pbrook | if (count & 1) |
3874 | 4b0f1a8b | pbrook | break;
|
3875 | 4b0f1a8b | pbrook | seen_it = 0;
|
3876 | 4b0f1a8b | pbrook | } |
3877 | 4b0f1a8b | pbrook | } |
3878 | 4b0f1a8b | pbrook | if ((insn & 0xff00) == 0xbf00 && (insn & 0xf) != 0) |
3879 | aa0aa4fa | bellard | { |
3880 | 4b0f1a8b | pbrook | /* This could be an IT instruction. */
|
3881 | 4b0f1a8b | pbrook | seen_it = insn; |
3882 | 4b0f1a8b | pbrook | it_count = count >> 1;
|
3883 | aa0aa4fa | bellard | } |
3884 | 4b0f1a8b | pbrook | if ((insn & 0xf800) >= 0xe800) |
3885 | 4b0f1a8b | pbrook | count++; |
3886 | aa0aa4fa | bellard | else
|
3887 | 4b0f1a8b | pbrook | count = (count + 2) | 1; |
3888 | 4b0f1a8b | pbrook | /* IT blocks contain at most 4 instructions. */
|
3889 | 4b0f1a8b | pbrook | if (count >= 8 && !seen_it) |
3890 | 4b0f1a8b | pbrook | return;
|
3891 | aa0aa4fa | bellard | } |
3892 | 4b0f1a8b | pbrook | /* We found an IT instruction. */
|
3893 | 4b0f1a8b | pbrook | ifthen_state = (seen_it & 0xe0) | ((seen_it << it_count) & 0x1f); |
3894 | 4b0f1a8b | pbrook | if ((ifthen_state & 0xf) == 0) |
3895 | 4b0f1a8b | pbrook | ifthen_state = 0;
|
3896 | aa0aa4fa | bellard | } |
3897 | aa0aa4fa | bellard | |
3898 | aa0aa4fa | bellard | /* NOTE: There are no checks in these routines that
|
3899 | aa0aa4fa | bellard | the relevant number of data bytes exist. */
|
3900 | aa0aa4fa | bellard | |
3901 | aa0aa4fa | bellard | int
|
3902 | 4b0f1a8b | pbrook | print_insn_arm (bfd_vma pc, struct disassemble_info *info)
|
3903 | aa0aa4fa | bellard | { |
3904 | 4b0f1a8b | pbrook | unsigned char b[4]; |
3905 | 4b0f1a8b | pbrook | long given;
|
3906 | 4b0f1a8b | pbrook | int status;
|
3907 | 4b0f1a8b | pbrook | int is_thumb = FALSE;
|
3908 | 4b0f1a8b | pbrook | int is_data = FALSE;
|
3909 | 4b0f1a8b | pbrook | unsigned int size = 4; |
3910 | 4b0f1a8b | pbrook | void (*printer) (bfd_vma, struct disassemble_info *, long); |
3911 | 4b0f1a8b | pbrook | #if 0
|
3912 | 4b0f1a8b | pbrook | bfd_boolean found = FALSE;
|
3913 | aa0aa4fa | bellard | |
3914 | aa0aa4fa | bellard | if (info->disassembler_options)
|
3915 | aa0aa4fa | bellard | {
|
3916 | aa0aa4fa | bellard | parse_disassembler_options (info->disassembler_options);
|
3917 | 3b46e624 | ths | |
3918 | aa0aa4fa | bellard | /* To avoid repeated parsing of these options, we remove them here. */
|
3919 | aa0aa4fa | bellard | info->disassembler_options = NULL;
|
3920 | aa0aa4fa | bellard | }
|
3921 | 3b46e624 | ths | |
3922 | 4b0f1a8b | pbrook | /* First check the full symtab for a mapping symbol, even if there
|
3923 | 4b0f1a8b | pbrook | are no usable non-mapping symbols for this address. */
|
3924 | 4b0f1a8b | pbrook | if (info->symtab != NULL
|
3925 | 4b0f1a8b | pbrook | && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
|
3926 | c2d551ff | bellard | {
|
3927 | 4b0f1a8b | pbrook | bfd_vma addr;
|
3928 | 4b0f1a8b | pbrook | int n;
|
3929 | 4b0f1a8b | pbrook | int last_sym = -1;
|
3930 | 4b0f1a8b | pbrook | enum map_type type = MAP_ARM;
|
3931 | 4b0f1a8b | pbrook | |
3932 | 4b0f1a8b | pbrook | if (pc <= last_mapping_addr)
|
3933 | 4b0f1a8b | pbrook | last_mapping_sym = -1;
|
3934 | 4b0f1a8b | pbrook | is_thumb = (last_type == MAP_THUMB);
|
3935 | 4b0f1a8b | pbrook | found = FALSE;
|
3936 | 4b0f1a8b | pbrook | /* Start scanning at the start of the function, or wherever
|
3937 | 4b0f1a8b | pbrook | we finished last time. */
|
3938 | 4b0f1a8b | pbrook | n = info->symtab_pos + 1;
|
3939 | 4b0f1a8b | pbrook | if (n < last_mapping_sym)
|
3940 | 4b0f1a8b | pbrook | n = last_mapping_sym;
|
3941 | 4b0f1a8b | pbrook | |
3942 | 4b0f1a8b | pbrook | /* Scan up to the location being disassembled. */
|
3943 | 4b0f1a8b | pbrook | for (; n < info->symtab_size; n++)
|
3944 | 4b0f1a8b | pbrook | {
|
3945 | 4b0f1a8b | pbrook | addr = bfd_asymbol_value (info->symtab[n]);
|
3946 | 4b0f1a8b | pbrook | if (addr > pc)
|
3947 | 4b0f1a8b | pbrook | break;
|
3948 | 4b0f1a8b | pbrook | if ((info->section == NULL
|
3949 | 4b0f1a8b | pbrook | || info->section == info->symtab[n]->section)
|
3950 | 4b0f1a8b | pbrook | && get_sym_code_type (info, n, &type))
|
3951 | 4b0f1a8b | pbrook | {
|
3952 | 4b0f1a8b | pbrook | last_sym = n;
|
3953 | 4b0f1a8b | pbrook | found = TRUE;
|
3954 | 4b0f1a8b | pbrook | }
|
3955 | 4b0f1a8b | pbrook | }
|
3956 | 4b0f1a8b | pbrook | |
3957 | 4b0f1a8b | pbrook | if (!found)
|
3958 | 4b0f1a8b | pbrook | {
|
3959 | 4b0f1a8b | pbrook | n = info->symtab_pos;
|
3960 | 4b0f1a8b | pbrook | if (n < last_mapping_sym - 1)
|
3961 | 4b0f1a8b | pbrook | n = last_mapping_sym - 1;
|
3962 | 4b0f1a8b | pbrook | |
3963 | 4b0f1a8b | pbrook | /* No mapping symbol found at this address. Look backwards
|
3964 | 4b0f1a8b | pbrook | for a preceeding one. */
|
3965 | 4b0f1a8b | pbrook | for (; n >= 0; n--)
|
3966 | 4b0f1a8b | pbrook | {
|
3967 | 4b0f1a8b | pbrook | if (get_sym_code_type (info, n, &type))
|
3968 | 4b0f1a8b | pbrook | {
|
3969 | 4b0f1a8b | pbrook | last_sym = n;
|
3970 | 4b0f1a8b | pbrook | found = TRUE;
|
3971 | 4b0f1a8b | pbrook | break;
|
3972 | 4b0f1a8b | pbrook | }
|
3973 | 4b0f1a8b | pbrook | }
|
3974 | 4b0f1a8b | pbrook | }
|
3975 | 4b0f1a8b | pbrook | |
3976 | 4b0f1a8b | pbrook | last_mapping_sym = last_sym;
|
3977 | 4b0f1a8b | pbrook | last_type = type;
|
3978 | 4b0f1a8b | pbrook | is_thumb = (last_type == MAP_THUMB);
|
3979 | 4b0f1a8b | pbrook | is_data = (last_type == MAP_DATA);
|
3980 | 4b0f1a8b | pbrook | |
3981 | 4b0f1a8b | pbrook | /* Look a little bit ahead to see if we should print out
|
3982 | 4b0f1a8b | pbrook | two or four bytes of data. If there's a symbol,
|
3983 | 4b0f1a8b | pbrook | mapping or otherwise, after two bytes then don't
|
3984 | 4b0f1a8b | pbrook | print more. */
|
3985 | 4b0f1a8b | pbrook | if (is_data)
|
3986 | 4b0f1a8b | pbrook | {
|
3987 | 4b0f1a8b | pbrook | size = 4 - (pc & 3);
|
3988 | 4b0f1a8b | pbrook | for (n = last_sym + 1; n < info->symtab_size; n++)
|
3989 | 4b0f1a8b | pbrook | {
|
3990 | 4b0f1a8b | pbrook | addr = bfd_asymbol_value (info->symtab[n]);
|
3991 | 4b0f1a8b | pbrook | if (addr > pc)
|
3992 | 4b0f1a8b | pbrook | {
|
3993 | 4b0f1a8b | pbrook | if (addr - pc < size)
|
3994 | 4b0f1a8b | pbrook | size = addr - pc;
|
3995 | 4b0f1a8b | pbrook | break;
|
3996 | 4b0f1a8b | pbrook | }
|
3997 | 4b0f1a8b | pbrook | }
|
3998 | 4b0f1a8b | pbrook | /* If the next symbol is after three bytes, we need to
|
3999 | 4b0f1a8b | pbrook | print only part of the data, so that we can use either
|
4000 | 4b0f1a8b | pbrook | .byte or .short. */
|
4001 | 4b0f1a8b | pbrook | if (size == 3)
|
4002 | 4b0f1a8b | pbrook | size = (pc & 1) ? 1 : 2;
|
4003 | 4b0f1a8b | pbrook | }
|
4004 | c2d551ff | bellard | }
|
4005 | 3b46e624 | ths | |
4006 | 4b0f1a8b | pbrook | if (info->symbols != NULL)
|
4007 | aa0aa4fa | bellard | {
|
4008 | aa0aa4fa | bellard | if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour)
|
4009 | aa0aa4fa | bellard | {
|
4010 | aa0aa4fa | bellard | coff_symbol_type * cs;
|
4011 | 3b46e624 | ths | |
4012 | aa0aa4fa | bellard | cs = coffsymbol (*info->symbols);
|
4013 | aa0aa4fa | bellard | is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT
|
4014 | aa0aa4fa | bellard | || cs->native->u.syment.n_sclass == C_THUMBSTAT
|
4015 | aa0aa4fa | bellard | || cs->native->u.syment.n_sclass == C_THUMBLABEL
|
4016 | aa0aa4fa | bellard | || cs->native->u.syment.n_sclass == C_THUMBEXTFUNC
|
4017 | aa0aa4fa | bellard | || cs->native->u.syment.n_sclass == C_THUMBSTATFUNC);
|
4018 | aa0aa4fa | bellard | }
|
4019 | 4b0f1a8b | pbrook | else if (bfd_asymbol_flavour (*info->symbols) == bfd_target_elf_flavour
|
4020 | 4b0f1a8b | pbrook | && !found)
|
4021 | aa0aa4fa | bellard | {
|
4022 | 4b0f1a8b | pbrook | /* If no mapping symbol has been found then fall back to the type
|
4023 | 4b0f1a8b | pbrook | of the function symbol. */
|
4024 | aa0aa4fa | bellard | elf_symbol_type * es;
|
4025 | aa0aa4fa | bellard | unsigned int type;
|
4026 | 3b46e624 | ths | |
4027 | aa0aa4fa | bellard | es = *(elf_symbol_type **)(info->symbols);
|
4028 | aa0aa4fa | bellard | type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
|
4029 | 3b46e624 | ths | |
4030 | aa0aa4fa | bellard | is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT);
|
4031 | aa0aa4fa | bellard | }
|
4032 | aa0aa4fa | bellard | }
|
4033 | 4b0f1a8b | pbrook | #else
|
4034 | 4b0f1a8b | pbrook | int little;
|
4035 | 3b46e624 | ths | |
4036 | aa0aa4fa | bellard | little = (info->endian == BFD_ENDIAN_LITTLE); |
4037 | 4b0f1a8b | pbrook | is_thumb |= (pc & 1);
|
4038 | 4b0f1a8b | pbrook | pc &= ~(bfd_vma)1;
|
4039 | 4b0f1a8b | pbrook | #endif
|
4040 | aa0aa4fa | bellard | |
4041 | 4b0f1a8b | pbrook | if (force_thumb)
|
4042 | 4b0f1a8b | pbrook | is_thumb = TRUE; |
4043 | 3b46e624 | ths | |
4044 | 4b0f1a8b | pbrook | info->bytes_per_line = 4;
|
4045 | 3b46e624 | ths | |
4046 | 4b0f1a8b | pbrook | if (is_data)
|
4047 | 4b0f1a8b | pbrook | { |
4048 | 4b0f1a8b | pbrook | int i;
|
4049 | 4b0f1a8b | pbrook | |
4050 | 4b0f1a8b | pbrook | /* size was already set above. */
|
4051 | 4b0f1a8b | pbrook | info->bytes_per_chunk = size; |
4052 | 4b0f1a8b | pbrook | printer = print_insn_data; |
4053 | 3b46e624 | ths | |
4054 | 4b0f1a8b | pbrook | status = info->read_memory_func (pc, (bfd_byte *)b, size, info); |
4055 | 4b0f1a8b | pbrook | given = 0;
|
4056 | 4b0f1a8b | pbrook | if (little)
|
4057 | 4b0f1a8b | pbrook | for (i = size - 1; i >= 0; i--) |
4058 | 4b0f1a8b | pbrook | given = b[i] | (given << 8);
|
4059 | 4b0f1a8b | pbrook | else
|
4060 | 4b0f1a8b | pbrook | for (i = 0; i < (int) size; i++) |
4061 | 4b0f1a8b | pbrook | given = b[i] | (given << 8);
|
4062 | 4b0f1a8b | pbrook | } |
4063 | 4b0f1a8b | pbrook | else if (!is_thumb) |
4064 | 4b0f1a8b | pbrook | { |
4065 | 4b0f1a8b | pbrook | /* In ARM mode endianness is a straightforward issue: the instruction
|
4066 | 4b0f1a8b | pbrook | is four bytes long and is either ordered 0123 or 3210. */
|
4067 | 4b0f1a8b | pbrook | printer = print_insn_arm_internal; |
4068 | 4b0f1a8b | pbrook | info->bytes_per_chunk = 4;
|
4069 | 4b0f1a8b | pbrook | size = 4;
|
4070 | 4b0f1a8b | pbrook | |
4071 | 4b0f1a8b | pbrook | status = info->read_memory_func (pc, (bfd_byte *)b, 4, info);
|
4072 | 4b0f1a8b | pbrook | if (little)
|
4073 | 4b0f1a8b | pbrook | given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); |
4074 | 4b0f1a8b | pbrook | else
|
4075 | 4b0f1a8b | pbrook | given = (b[3]) | (b[2] << 8) | (b[1] << 16) | (b[0] << 24); |
4076 | aa0aa4fa | bellard | } |
4077 | aa0aa4fa | bellard | else
|
4078 | aa0aa4fa | bellard | { |
4079 | 4b0f1a8b | pbrook | /* In Thumb mode we have the additional wrinkle of two
|
4080 | 4b0f1a8b | pbrook | instruction lengths. Fortunately, the bits that determine
|
4081 | 4b0f1a8b | pbrook | the length of the current instruction are always to be found
|
4082 | 4b0f1a8b | pbrook | in the first two bytes. */
|
4083 | 4b0f1a8b | pbrook | printer = print_insn_thumb16; |
4084 | 4b0f1a8b | pbrook | info->bytes_per_chunk = 2;
|
4085 | 4b0f1a8b | pbrook | size = 2;
|
4086 | 4b0f1a8b | pbrook | |
4087 | 4b0f1a8b | pbrook | status = info->read_memory_func (pc, (bfd_byte *)b, 2, info);
|
4088 | 4b0f1a8b | pbrook | if (little)
|
4089 | 4b0f1a8b | pbrook | given = (b[0]) | (b[1] << 8); |
4090 | 4b0f1a8b | pbrook | else
|
4091 | 4b0f1a8b | pbrook | given = (b[1]) | (b[0] << 8); |
4092 | 3b46e624 | ths | |
4093 | 4b0f1a8b | pbrook | if (!status)
|
4094 | aa0aa4fa | bellard | { |
4095 | 4b0f1a8b | pbrook | /* These bit patterns signal a four-byte Thumb
|
4096 | 4b0f1a8b | pbrook | instruction. */
|
4097 | 4b0f1a8b | pbrook | if ((given & 0xF800) == 0xF800 |
4098 | 4b0f1a8b | pbrook | || (given & 0xF800) == 0xF000 |
4099 | 4b0f1a8b | pbrook | || (given & 0xF800) == 0xE800) |
4100 | aa0aa4fa | bellard | { |
4101 | 4b0f1a8b | pbrook | status = info->read_memory_func (pc + 2, (bfd_byte *)b, 2, info); |
4102 | 4b0f1a8b | pbrook | if (little)
|
4103 | 4b0f1a8b | pbrook | given = (b[0]) | (b[1] << 8) | (given << 16); |
4104 | 4b0f1a8b | pbrook | else
|
4105 | 4b0f1a8b | pbrook | given = (b[1]) | (b[0] << 8) | (given << 16); |
4106 | 3b46e624 | ths | |
4107 | 4b0f1a8b | pbrook | printer = print_insn_thumb32; |
4108 | 4b0f1a8b | pbrook | size = 4;
|
4109 | aa0aa4fa | bellard | } |
4110 | 4b0f1a8b | pbrook | } |
4111 | 4b0f1a8b | pbrook | |
4112 | 4b0f1a8b | pbrook | if (ifthen_address != pc)
|
4113 | 4b0f1a8b | pbrook | find_ifthen_state(pc, info, little); |
4114 | 4b0f1a8b | pbrook | |
4115 | 4b0f1a8b | pbrook | if (ifthen_state)
|
4116 | 4b0f1a8b | pbrook | { |
4117 | 4b0f1a8b | pbrook | if ((ifthen_state & 0xf) == 0x8) |
4118 | 4b0f1a8b | pbrook | ifthen_next_state = 0;
|
4119 | aa0aa4fa | bellard | else
|
4120 | 4b0f1a8b | pbrook | ifthen_next_state = (ifthen_state & 0xe0)
|
4121 | 4b0f1a8b | pbrook | | ((ifthen_state & 0xf) << 1); |
4122 | aa0aa4fa | bellard | } |
4123 | aa0aa4fa | bellard | } |
4124 | 3b46e624 | ths | |
4125 | 4b0f1a8b | pbrook | if (status)
|
4126 | 4b0f1a8b | pbrook | { |
4127 | 4b0f1a8b | pbrook | info->memory_error_func (status, pc, info); |
4128 | 4b0f1a8b | pbrook | return -1; |
4129 | 4b0f1a8b | pbrook | } |
4130 | aa0aa4fa | bellard | if (info->flags & INSN_HAS_RELOC)
|
4131 | aa0aa4fa | bellard | /* If the instruction has a reloc associated with it, then
|
4132 | aa0aa4fa | bellard | the offset field in the instruction will actually be the
|
4133 | aa0aa4fa | bellard | addend for the reloc. (We are using REL type relocs).
|
4134 | aa0aa4fa | bellard | In such cases, we can ignore the pc when computing
|
4135 | aa0aa4fa | bellard | addresses, since the addend is not currently pc-relative. */
|
4136 | aa0aa4fa | bellard | pc = 0;
|
4137 | aa0aa4fa | bellard | |
4138 | 4b0f1a8b | pbrook | printer (pc, info, given); |
4139 | 4b0f1a8b | pbrook | |
4140 | 4b0f1a8b | pbrook | if (is_thumb)
|
4141 | 4b0f1a8b | pbrook | { |
4142 | 4b0f1a8b | pbrook | ifthen_state = ifthen_next_state; |
4143 | 4b0f1a8b | pbrook | ifthen_address += size; |
4144 | 4b0f1a8b | pbrook | } |
4145 | 4b0f1a8b | pbrook | return size;
|
4146 | aa0aa4fa | bellard | } |
4147 | aa0aa4fa | bellard | |
4148 | aa0aa4fa | bellard | void
|
4149 | 4b0f1a8b | pbrook | print_arm_disassembler_options (FILE *stream) |
4150 | aa0aa4fa | bellard | { |
4151 | aa0aa4fa | bellard | int i;
|
4152 | aa0aa4fa | bellard | |
4153 | aa0aa4fa | bellard | fprintf (stream, _("\n\
|
4154 | aa0aa4fa | bellard | The following ARM specific disassembler options are supported for use with\n\
|
4155 | aa0aa4fa | bellard | the -M switch:\n"));
|
4156 | 3b46e624 | ths | |
4157 | aa0aa4fa | bellard | for (i = NUM_ARM_REGNAMES; i--;)
|
4158 | aa0aa4fa | bellard | fprintf (stream, " reg-names-%s %*c%s\n",
|
4159 | aa0aa4fa | bellard | regnames[i].name, |
4160 | aa0aa4fa | bellard | (int)(14 - strlen (regnames[i].name)), ' ', |
4161 | aa0aa4fa | bellard | regnames[i].description); |
4162 | aa0aa4fa | bellard | |
4163 | aa0aa4fa | bellard | fprintf (stream, " force-thumb Assume all insns are Thumb insns\n");
|
4164 | aa0aa4fa | bellard | fprintf (stream, " no-force-thumb Examine preceeding label to determine an insn's type\n\n");
|
4165 | aa0aa4fa | bellard | } |