root / hw / mips_pica61.c @ 92d88ecb
History | View | Annotate | Download (5.3 kB)
1 | ad6fe1d2 | ths | /*
|
---|---|---|---|
2 | ad6fe1d2 | ths | * QEMU Malta board support
|
3 | ad6fe1d2 | ths | *
|
4 | ad6fe1d2 | ths | * Copyright (c) 2007 Herv? Poussineau
|
5 | ad6fe1d2 | ths | *
|
6 | ad6fe1d2 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | ad6fe1d2 | ths | * of this software and associated documentation files (the "Software"), to deal
|
8 | ad6fe1d2 | ths | * in the Software without restriction, including without limitation the rights
|
9 | ad6fe1d2 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | ad6fe1d2 | ths | * copies of the Software, and to permit persons to whom the Software is
|
11 | ad6fe1d2 | ths | * furnished to do so, subject to the following conditions:
|
12 | ad6fe1d2 | ths | *
|
13 | ad6fe1d2 | ths | * The above copyright notice and this permission notice shall be included in
|
14 | ad6fe1d2 | ths | * all copies or substantial portions of the Software.
|
15 | ad6fe1d2 | ths | *
|
16 | ad6fe1d2 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | ad6fe1d2 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | ad6fe1d2 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | ad6fe1d2 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | ad6fe1d2 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | ad6fe1d2 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | ad6fe1d2 | ths | * THE SOFTWARE.
|
23 | ad6fe1d2 | ths | */
|
24 | ad6fe1d2 | ths | |
25 | ad6fe1d2 | ths | #include "vl.h" |
26 | ad6fe1d2 | ths | |
27 | ad6fe1d2 | ths | #ifdef TARGET_WORDS_BIGENDIAN
|
28 | ad6fe1d2 | ths | #define BIOS_FILENAME "mips_bios.bin" |
29 | ad6fe1d2 | ths | #else
|
30 | ad6fe1d2 | ths | #define BIOS_FILENAME "mipsel_bios.bin" |
31 | ad6fe1d2 | ths | #endif
|
32 | ad6fe1d2 | ths | |
33 | ad6fe1d2 | ths | #ifdef TARGET_MIPS64
|
34 | ad6fe1d2 | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffULL) |
35 | ad6fe1d2 | ths | #else
|
36 | ad6fe1d2 | ths | #define PHYS_TO_VIRT(x) ((x) | ~0x7fffffffU) |
37 | ad6fe1d2 | ths | #endif
|
38 | ad6fe1d2 | ths | |
39 | ad6fe1d2 | ths | #define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
40 | ad6fe1d2 | ths | |
41 | ad6fe1d2 | ths | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
42 | ad6fe1d2 | ths | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
43 | ad6fe1d2 | ths | static const int ide_irq[2] = { 14, 15 }; |
44 | ad6fe1d2 | ths | |
45 | ad6fe1d2 | ths | static uint32_t serial_base[MAX_SERIAL_PORTS] = { 0x80006000, 0x80007000 }; |
46 | ad6fe1d2 | ths | static int serial_irq[MAX_SERIAL_PORTS] = { 8, 9 }; |
47 | ad6fe1d2 | ths | |
48 | ad6fe1d2 | ths | extern FILE *logfile;
|
49 | ad6fe1d2 | ths | |
50 | ad6fe1d2 | ths | static void main_cpu_reset(void *opaque) |
51 | ad6fe1d2 | ths | { |
52 | ad6fe1d2 | ths | CPUState *env = opaque; |
53 | ad6fe1d2 | ths | cpu_reset(env); |
54 | ad6fe1d2 | ths | } |
55 | ad6fe1d2 | ths | |
56 | ad6fe1d2 | ths | static
|
57 | ad6fe1d2 | ths | void mips_pica61_init (int ram_size, int vga_ram_size, int boot_device, |
58 | ad6fe1d2 | ths | DisplayState *ds, const char **fd_filename, int snapshot, |
59 | ad6fe1d2 | ths | const char *kernel_filename, const char *kernel_cmdline, |
60 | ad6fe1d2 | ths | const char *initrd_filename, const char *cpu_model) |
61 | ad6fe1d2 | ths | { |
62 | ad6fe1d2 | ths | char buf[1024]; |
63 | ad6fe1d2 | ths | unsigned long bios_offset; |
64 | ad6fe1d2 | ths | int bios_size;
|
65 | ad6fe1d2 | ths | CPUState *env; |
66 | ad6fe1d2 | ths | int i;
|
67 | ad6fe1d2 | ths | mips_def_t *def; |
68 | ad6fe1d2 | ths | int available_ram;
|
69 | ad6fe1d2 | ths | qemu_irq *i8259; |
70 | ad6fe1d2 | ths | |
71 | ad6fe1d2 | ths | /* init CPUs */
|
72 | ad6fe1d2 | ths | if (cpu_model == NULL) { |
73 | ad6fe1d2 | ths | #ifdef TARGET_MIPS64
|
74 | ad6fe1d2 | ths | cpu_model = "R4000";
|
75 | ad6fe1d2 | ths | #else
|
76 | ad6fe1d2 | ths | cpu_model = "4KEc";
|
77 | ad6fe1d2 | ths | #endif
|
78 | ad6fe1d2 | ths | } |
79 | ad6fe1d2 | ths | if (mips_find_by_name(cpu_model, &def) != 0) |
80 | ad6fe1d2 | ths | def = NULL;
|
81 | ad6fe1d2 | ths | env = cpu_init(); |
82 | ad6fe1d2 | ths | cpu_mips_register(env, def); |
83 | ad6fe1d2 | ths | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
84 | ad6fe1d2 | ths | qemu_register_reset(main_cpu_reset, env); |
85 | ad6fe1d2 | ths | |
86 | ad6fe1d2 | ths | /* allocate RAM (limited to 256 MB) */
|
87 | ad6fe1d2 | ths | if (ram_size < 256 * 1024 * 1024) |
88 | ad6fe1d2 | ths | available_ram = ram_size; |
89 | ad6fe1d2 | ths | else
|
90 | ad6fe1d2 | ths | available_ram = 256 * 1024 * 1024; |
91 | ad6fe1d2 | ths | cpu_register_physical_memory(0, available_ram, IO_MEM_RAM);
|
92 | ad6fe1d2 | ths | |
93 | ad6fe1d2 | ths | /* load a BIOS image */
|
94 | ad6fe1d2 | ths | bios_offset = ram_size + vga_ram_size; |
95 | ad6fe1d2 | ths | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
96 | ad6fe1d2 | ths | bios_size = load_image(buf, phys_ram_base + bios_offset); |
97 | ad6fe1d2 | ths | if ((bios_size <= 0) || (bios_size > BIOS_SIZE)) { |
98 | ad6fe1d2 | ths | /* fatal */
|
99 | ad6fe1d2 | ths | fprintf(stderr, "qemu: Error, could not load MIPS bios '%s'\n",
|
100 | ad6fe1d2 | ths | buf); |
101 | ad6fe1d2 | ths | exit(1);
|
102 | ad6fe1d2 | ths | } |
103 | ad6fe1d2 | ths | cpu_register_physical_memory(0x1fc00000,
|
104 | ad6fe1d2 | ths | BIOS_SIZE, bios_offset | IO_MEM_ROM); |
105 | ad6fe1d2 | ths | |
106 | ad6fe1d2 | ths | /* Device map
|
107 | ad6fe1d2 | ths | *
|
108 | ad6fe1d2 | ths | * addr 0xe0004000: mc146818
|
109 | ad6fe1d2 | ths | * addr 0xe0005000 intr 6: ps2 keyboard
|
110 | ad6fe1d2 | ths | * addr 0xe0005000 intr 7: ps2 mouse
|
111 | ad6fe1d2 | ths | * addr 0xe0006000 intr 8: ns16550a,
|
112 | ad6fe1d2 | ths | * addr 0xe0007000 intr 9: ns16550a
|
113 | ad6fe1d2 | ths | * isa_io_base 0xe2000000 isa_mem_base 0xe3000000
|
114 | ad6fe1d2 | ths | */
|
115 | ad6fe1d2 | ths | |
116 | ad6fe1d2 | ths | /* Init CPU internal devices */
|
117 | ad6fe1d2 | ths | cpu_mips_irq_init_cpu(env); |
118 | ad6fe1d2 | ths | cpu_mips_clock_init(env); |
119 | ad6fe1d2 | ths | cpu_mips_irqctrl_init(); |
120 | ad6fe1d2 | ths | |
121 | ad6fe1d2 | ths | /* Register 64 KB of ISA IO space at 0x10000000 */
|
122 | ad6fe1d2 | ths | isa_mmio_init(0x10000000, 0x00010000); |
123 | ad6fe1d2 | ths | isa_mem_base = 0x11000000;
|
124 | ad6fe1d2 | ths | |
125 | ad6fe1d2 | ths | /* PC style IRQ (i8259/i8254) and DMA (i8257) */
|
126 | ad6fe1d2 | ths | /* The PIC is attached to the MIPS CPU INT0 pin */
|
127 | ad6fe1d2 | ths | i8259 = i8259_init(env->irq[2]);
|
128 | 18c6e2ff | ths | rtc_mm_init(0x80004070, 1, i8259[14]); |
129 | ad6fe1d2 | ths | pit_init(0x40, 0); |
130 | ad6fe1d2 | ths | |
131 | ad6fe1d2 | ths | /* Keyboard (i8042) */
|
132 | ad6fe1d2 | ths | i8042_mm_init(i8259[6], i8259[7], 0x80005060, 0); |
133 | ad6fe1d2 | ths | |
134 | ad6fe1d2 | ths | /* IDE controller */
|
135 | ad6fe1d2 | ths | for(i = 0; i < 2; i++) |
136 | ad6fe1d2 | ths | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
137 | ad6fe1d2 | ths | bs_table[2 * i], bs_table[2 * i + 1]); |
138 | ad6fe1d2 | ths | |
139 | ad6fe1d2 | ths | /* Network controller */
|
140 | ad6fe1d2 | ths | /* FIXME: missing NS SONIC DP83932 */
|
141 | ad6fe1d2 | ths | |
142 | ad6fe1d2 | ths | /* SCSI adapter */
|
143 | ad6fe1d2 | ths | /* FIXME: missing NCR 53C94 */
|
144 | ad6fe1d2 | ths | |
145 | ad6fe1d2 | ths | /* ISA devices (floppy, serial, parallel) */
|
146 | ad6fe1d2 | ths | fdctrl_init(i8259[1], 1, 1, 0x80003000, fd_table); |
147 | ad6fe1d2 | ths | for(i = 0; i < MAX_SERIAL_PORTS; i++) { |
148 | ad6fe1d2 | ths | if (serial_hds[i]) {
|
149 | ad6fe1d2 | ths | serial_mm_init(serial_base[i], 0, i8259[serial_irq[i]], serial_hds[i], 1); |
150 | ad6fe1d2 | ths | } |
151 | ad6fe1d2 | ths | } |
152 | ad6fe1d2 | ths | for (i = 0; i < MAX_PARALLEL_PORTS; i++) { |
153 | ad6fe1d2 | ths | if (parallel_hds[i]) {
|
154 | ad6fe1d2 | ths | /* FIXME: memory mapped! parallel_init(0x80008000, i8259[17], parallel_hds[i]); */
|
155 | ad6fe1d2 | ths | } |
156 | ad6fe1d2 | ths | } |
157 | ad6fe1d2 | ths | |
158 | ad6fe1d2 | ths | /* Sound card */
|
159 | ad6fe1d2 | ths | /* FIXME: missing Jazz sound, IRQ 18 */
|
160 | ad6fe1d2 | ths | |
161 | ad6fe1d2 | ths | /* LED indicator */
|
162 | ad6fe1d2 | ths | /* FIXME: missing LED indicator */
|
163 | ad6fe1d2 | ths | |
164 | ad6fe1d2 | ths | /* NVRAM */
|
165 | ad6fe1d2 | ths | ds1225y_init(0x80009000, "nvram"); |
166 | ad6fe1d2 | ths | |
167 | ad6fe1d2 | ths | /* Video card */
|
168 | ad6fe1d2 | ths | //isa_vga_init(ds, phys_ram_base + ram_size, ram_size, vga_ram_size);
|
169 | ad6fe1d2 | ths | } |
170 | ad6fe1d2 | ths | |
171 | ad6fe1d2 | ths | QEMUMachine mips_pica61_machine = { |
172 | ad6fe1d2 | ths | "pica61",
|
173 | ad6fe1d2 | ths | "Acer Pica 61",
|
174 | ad6fe1d2 | ths | mips_pica61_init, |
175 | ad6fe1d2 | ths | }; |