Statistics
| Branch: | Revision:

root / hw / ppc_chrp.c @ 92d88ecb

History | View | Annotate | Download (19.9 kB)

1 64201201 bellard
/*
2 64201201 bellard
 * QEMU PPC CHRP/PMAC hardware System Emulator
3 64201201 bellard
 * 
4 47103572 j_mayer
 * Copyright (c) 2004-2007 Fabrice Bellard
5 64201201 bellard
 * 
6 64201201 bellard
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 64201201 bellard
 * of this software and associated documentation files (the "Software"), to deal
8 64201201 bellard
 * in the Software without restriction, including without limitation the rights
9 64201201 bellard
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 64201201 bellard
 * copies of the Software, and to permit persons to whom the Software is
11 64201201 bellard
 * furnished to do so, subject to the following conditions:
12 64201201 bellard
 *
13 64201201 bellard
 * The above copyright notice and this permission notice shall be included in
14 64201201 bellard
 * all copies or substantial portions of the Software.
15 64201201 bellard
 *
16 64201201 bellard
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 64201201 bellard
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 64201201 bellard
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 64201201 bellard
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 64201201 bellard
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 64201201 bellard
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 64201201 bellard
 * THE SOFTWARE.
23 64201201 bellard
 */
24 64201201 bellard
#include "vl.h"
25 64201201 bellard
26 e9df014c j_mayer
/* SMP is not enabled, for now */
27 e9df014c j_mayer
#define MAX_CPUS 1
28 e9df014c j_mayer
29 64201201 bellard
#define BIOS_FILENAME "ppc_rom.bin"
30 d5295253 bellard
#define VGABIOS_FILENAME "video.x"
31 64201201 bellard
#define NVRAM_SIZE        0x2000
32 64201201 bellard
33 b6b8bd18 bellard
#define KERNEL_LOAD_ADDR 0x01000000
34 b6b8bd18 bellard
#define INITRD_LOAD_ADDR 0x01800000
35 b6b8bd18 bellard
36 267002cd bellard
/* MacIO devices (mapped inside the MacIO address space): CUDA, DBDMA,
37 e5733356 bellard
   NVRAM */
38 267002cd bellard
39 267002cd bellard
static int dbdma_mem_index;
40 267002cd bellard
static int cuda_mem_index;
41 0aa6a4a2 bellard
static int ide0_mem_index = -1;
42 0aa6a4a2 bellard
static int ide1_mem_index = -1;
43 0aa6a4a2 bellard
static int openpic_mem_index = -1;
44 0aa6a4a2 bellard
static int heathrow_pic_mem_index = -1;
45 e5733356 bellard
static int macio_nvram_mem_index = -1;
46 267002cd bellard
47 267002cd bellard
/* DBDMA: currently no op - should suffice right now */
48 267002cd bellard
49 267002cd bellard
static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
50 267002cd bellard
{
51 e96efcfc j_mayer
    printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
52 267002cd bellard
}
53 267002cd bellard
54 267002cd bellard
static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
55 267002cd bellard
{
56 267002cd bellard
}
57 267002cd bellard
58 267002cd bellard
static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
59 267002cd bellard
{
60 267002cd bellard
}
61 267002cd bellard
62 267002cd bellard
static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
63 267002cd bellard
{
64 e96efcfc j_mayer
    printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
65 267002cd bellard
    return 0;
66 267002cd bellard
}
67 267002cd bellard
68 267002cd bellard
static uint32_t dbdma_readw (void *opaque, target_phys_addr_t addr)
69 267002cd bellard
{
70 267002cd bellard
    return 0;
71 267002cd bellard
}
72 267002cd bellard
73 267002cd bellard
static uint32_t dbdma_readl (void *opaque, target_phys_addr_t addr)
74 267002cd bellard
{
75 267002cd bellard
    return 0;
76 267002cd bellard
}
77 267002cd bellard
78 267002cd bellard
static CPUWriteMemoryFunc *dbdma_write[] = {
79 267002cd bellard
    &dbdma_writeb,
80 267002cd bellard
    &dbdma_writew,
81 267002cd bellard
    &dbdma_writel,
82 267002cd bellard
};
83 267002cd bellard
84 267002cd bellard
static CPUReadMemoryFunc *dbdma_read[] = {
85 267002cd bellard
    &dbdma_readb,
86 267002cd bellard
    &dbdma_readw,
87 267002cd bellard
    &dbdma_readl,
88 267002cd bellard
};
89 267002cd bellard
90 e5733356 bellard
/* macio style NVRAM device */
91 e5733356 bellard
typedef struct MacIONVRAMState {
92 e5733356 bellard
    uint8_t data[0x2000];
93 e5733356 bellard
} MacIONVRAMState;
94 e5733356 bellard
95 e5733356 bellard
static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
96 e5733356 bellard
{
97 e5733356 bellard
    MacIONVRAMState *s = opaque;
98 e5733356 bellard
    addr = (addr >> 4) & 0x1fff;
99 e5733356 bellard
    s->data[addr] = value;
100 e5733356 bellard
    //    printf("macio_nvram_writeb %04x = %02x\n", addr, value);
101 e5733356 bellard
}
102 e5733356 bellard
103 e5733356 bellard
static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
104 e5733356 bellard
{
105 e5733356 bellard
    MacIONVRAMState *s = opaque;
106 e5733356 bellard
    uint32_t value;
107 e5733356 bellard
108 e5733356 bellard
    addr = (addr >> 4) & 0x1fff;
109 e5733356 bellard
    value = s->data[addr];
110 e5733356 bellard
    //    printf("macio_nvram_readb %04x = %02x\n", addr, value);
111 e5733356 bellard
    return value;
112 e5733356 bellard
}
113 e5733356 bellard
114 e5733356 bellard
static CPUWriteMemoryFunc *macio_nvram_write[] = {
115 e5733356 bellard
    &macio_nvram_writeb,
116 e5733356 bellard
    &macio_nvram_writeb,
117 e5733356 bellard
    &macio_nvram_writeb,
118 e5733356 bellard
};
119 e5733356 bellard
120 e5733356 bellard
static CPUReadMemoryFunc *macio_nvram_read[] = {
121 e5733356 bellard
    &macio_nvram_readb,
122 e5733356 bellard
    &macio_nvram_readb,
123 e5733356 bellard
    &macio_nvram_readb,
124 e5733356 bellard
};
125 e5733356 bellard
126 e5733356 bellard
static MacIONVRAMState *macio_nvram_init(void)
127 e5733356 bellard
{
128 e5733356 bellard
    MacIONVRAMState *s;
129 e5733356 bellard
    s = qemu_mallocz(sizeof(MacIONVRAMState));
130 e5733356 bellard
    if (!s)
131 e5733356 bellard
        return NULL;
132 e5733356 bellard
    macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read, 
133 e5733356 bellard
                                                   macio_nvram_write, s);
134 e5733356 bellard
    return s;
135 e5733356 bellard
}
136 e5733356 bellard
137 267002cd bellard
static void macio_map(PCIDevice *pci_dev, int region_num, 
138 267002cd bellard
                      uint32_t addr, uint32_t size, int type)
139 267002cd bellard
{
140 0aa6a4a2 bellard
    if (heathrow_pic_mem_index >= 0) {
141 0aa6a4a2 bellard
        cpu_register_physical_memory(addr + 0x00000, 0x1000, 
142 0aa6a4a2 bellard
                                     heathrow_pic_mem_index);
143 0aa6a4a2 bellard
    }
144 267002cd bellard
    cpu_register_physical_memory(addr + 0x08000, 0x1000, dbdma_mem_index);
145 267002cd bellard
    cpu_register_physical_memory(addr + 0x16000, 0x2000, cuda_mem_index);
146 0aa6a4a2 bellard
    if (ide0_mem_index >= 0)
147 0aa6a4a2 bellard
        cpu_register_physical_memory(addr + 0x1f000, 0x1000, ide0_mem_index);
148 0aa6a4a2 bellard
    if (ide1_mem_index >= 0)
149 0aa6a4a2 bellard
        cpu_register_physical_memory(addr + 0x20000, 0x1000, ide1_mem_index);
150 0aa6a4a2 bellard
    if (openpic_mem_index >= 0) {
151 0aa6a4a2 bellard
        cpu_register_physical_memory(addr + 0x40000, 0x40000, 
152 0aa6a4a2 bellard
                                     openpic_mem_index);
153 0aa6a4a2 bellard
    }
154 e5733356 bellard
    if (macio_nvram_mem_index >= 0)
155 e5733356 bellard
        cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index);
156 267002cd bellard
}
157 267002cd bellard
158 e5733356 bellard
static void macio_init(PCIBus *bus, int device_id)
159 267002cd bellard
{
160 267002cd bellard
    PCIDevice *d;
161 267002cd bellard
162 46e50e9d bellard
    d = pci_register_device(bus, "macio", sizeof(PCIDevice),
163 46e50e9d bellard
                            -1, NULL, NULL);
164 267002cd bellard
    /* Note: this code is strongly inspirated from the corresponding code
165 267002cd bellard
       in PearPC */
166 267002cd bellard
    d->config[0x00] = 0x6b; // vendor_id
167 267002cd bellard
    d->config[0x01] = 0x10;
168 e5733356 bellard
    d->config[0x02] = device_id;
169 e5733356 bellard
    d->config[0x03] = device_id >> 8;
170 267002cd bellard
171 267002cd bellard
    d->config[0x0a] = 0x00; // class_sub = pci2pci
172 267002cd bellard
    d->config[0x0b] = 0xff; // class_base = bridge
173 267002cd bellard
    d->config[0x0e] = 0x00; // header_type
174 267002cd bellard
175 267002cd bellard
    d->config[0x3d] = 0x01; // interrupt on pin 1
176 267002cd bellard
    
177 267002cd bellard
    dbdma_mem_index = cpu_register_io_memory(0, dbdma_read, dbdma_write, NULL);
178 267002cd bellard
179 267002cd bellard
    pci_register_io_region(d, 0, 0x80000, 
180 267002cd bellard
                           PCI_ADDRESS_SPACE_MEM, macio_map);
181 267002cd bellard
}
182 267002cd bellard
183 0aa6a4a2 bellard
/* UniN device */
184 0aa6a4a2 bellard
static void unin_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
185 0aa6a4a2 bellard
{
186 0aa6a4a2 bellard
}
187 0aa6a4a2 bellard
188 0aa6a4a2 bellard
static uint32_t unin_readl (void *opaque, target_phys_addr_t addr)
189 0aa6a4a2 bellard
{
190 0aa6a4a2 bellard
    return 0;
191 0aa6a4a2 bellard
}
192 0aa6a4a2 bellard
193 0aa6a4a2 bellard
static CPUWriteMemoryFunc *unin_write[] = {
194 0aa6a4a2 bellard
    &unin_writel,
195 0aa6a4a2 bellard
    &unin_writel,
196 0aa6a4a2 bellard
    &unin_writel,
197 0aa6a4a2 bellard
};
198 0aa6a4a2 bellard
199 0aa6a4a2 bellard
static CPUReadMemoryFunc *unin_read[] = {
200 0aa6a4a2 bellard
    &unin_readl,
201 0aa6a4a2 bellard
    &unin_readl,
202 0aa6a4a2 bellard
    &unin_readl,
203 0aa6a4a2 bellard
};
204 0aa6a4a2 bellard
205 0aa6a4a2 bellard
/* temporary frame buffer OSI calls for the video.x driver. The right
206 0aa6a4a2 bellard
   solution is to modify the driver to use VGA PCI I/Os */
207 0aa6a4a2 bellard
static int vga_osi_call(CPUState *env)
208 0aa6a4a2 bellard
{
209 0aa6a4a2 bellard
    static int vga_vbl_enabled;
210 0aa6a4a2 bellard
    int linesize;
211 0aa6a4a2 bellard
    
212 0aa6a4a2 bellard
    //    printf("osi_call R5=%d\n", env->gpr[5]);
213 0aa6a4a2 bellard
214 0aa6a4a2 bellard
    /* same handler as PearPC, coming from the original MOL video
215 0aa6a4a2 bellard
       driver. */
216 0aa6a4a2 bellard
    switch(env->gpr[5]) {
217 0aa6a4a2 bellard
    case 4:
218 0aa6a4a2 bellard
        break;
219 0aa6a4a2 bellard
    case 28: /* set_vmode */
220 0aa6a4a2 bellard
        if (env->gpr[6] != 1 || env->gpr[7] != 0)
221 0aa6a4a2 bellard
            env->gpr[3] = 1;
222 0aa6a4a2 bellard
        else
223 0aa6a4a2 bellard
            env->gpr[3] = 0;
224 0aa6a4a2 bellard
        break;
225 0aa6a4a2 bellard
    case 29: /* get_vmode_info */
226 0aa6a4a2 bellard
        if (env->gpr[6] != 0) {
227 0aa6a4a2 bellard
            if (env->gpr[6] != 1 || env->gpr[7] != 0) {
228 0aa6a4a2 bellard
                env->gpr[3] = 1;
229 0aa6a4a2 bellard
                break;
230 0aa6a4a2 bellard
            }
231 0aa6a4a2 bellard
        }
232 0aa6a4a2 bellard
        env->gpr[3] = 0; 
233 0aa6a4a2 bellard
        env->gpr[4] = (1 << 16) | 1; /* num_vmodes, cur_vmode */
234 0aa6a4a2 bellard
        env->gpr[5] = (1 << 16) | 0; /* num_depths, cur_depth_mode */
235 0aa6a4a2 bellard
        env->gpr[6] = (graphic_width << 16) | graphic_height; /* w, h */
236 0aa6a4a2 bellard
        env->gpr[7] = 85 << 16; /* refresh rate */
237 0aa6a4a2 bellard
        env->gpr[8] = (graphic_depth + 7) & ~7; /* depth (round to byte) */
238 0aa6a4a2 bellard
        linesize = ((graphic_depth + 7) >> 3) * graphic_width;
239 0aa6a4a2 bellard
        linesize = (linesize + 3) & ~3;
240 0aa6a4a2 bellard
        env->gpr[9] = (linesize << 16) | 0; /* row_bytes, offset */
241 0aa6a4a2 bellard
        break;
242 0aa6a4a2 bellard
    case 31: /* set_video power */
243 0aa6a4a2 bellard
        env->gpr[3] = 0;
244 0aa6a4a2 bellard
        break;
245 0aa6a4a2 bellard
    case 39: /* video_ctrl */
246 0aa6a4a2 bellard
        if (env->gpr[6] == 0 || env->gpr[6] == 1)
247 0aa6a4a2 bellard
            vga_vbl_enabled = env->gpr[6];
248 0aa6a4a2 bellard
        env->gpr[3] = 0;
249 0aa6a4a2 bellard
        break;
250 0aa6a4a2 bellard
    case 47:
251 0aa6a4a2 bellard
        break;
252 0aa6a4a2 bellard
    case 59: /* set_color */
253 0aa6a4a2 bellard
        /* R6 = index, R7 = RGB */
254 0aa6a4a2 bellard
        env->gpr[3] = 0;
255 0aa6a4a2 bellard
        break;
256 0aa6a4a2 bellard
    case 64: /* get color */
257 0aa6a4a2 bellard
        /* R6 = index */
258 0aa6a4a2 bellard
        env->gpr[3] = 0; 
259 0aa6a4a2 bellard
        break;
260 0aa6a4a2 bellard
    case 116: /* set hwcursor */
261 0aa6a4a2 bellard
        /* R6 = x, R7 = y, R8 = visible, R9 = data */
262 0aa6a4a2 bellard
        break;
263 0aa6a4a2 bellard
    default:
264 e96efcfc j_mayer
        fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
265 0aa6a4a2 bellard
        break;
266 0aa6a4a2 bellard
    }
267 0aa6a4a2 bellard
    return 1; /* osi_call handled */
268 0aa6a4a2 bellard
}
269 0aa6a4a2 bellard
270 e5733356 bellard
static uint8_t nvram_chksum(const uint8_t *buf, int n)
271 e5733356 bellard
{
272 e5733356 bellard
    int sum, i;
273 e5733356 bellard
    sum = 0;
274 e5733356 bellard
    for(i = 0; i < n; i++)
275 e5733356 bellard
        sum += buf[i];
276 e5733356 bellard
    return (sum & 0xff) + (sum >> 8);
277 e5733356 bellard
}
278 e5733356 bellard
279 e5733356 bellard
/* set a free Mac OS NVRAM partition */
280 e5733356 bellard
void pmac_format_nvram_partition(uint8_t *buf, int len)
281 e5733356 bellard
{
282 e5733356 bellard
    char partition_name[12] = "wwwwwwwwwwww";
283 e5733356 bellard
    
284 e5733356 bellard
    buf[0] = 0x7f; /* free partition magic */
285 e5733356 bellard
    buf[1] = 0; /* checksum */
286 e5733356 bellard
    buf[2] = len >> 8;
287 e5733356 bellard
    buf[3] = len;
288 e5733356 bellard
    memcpy(buf + 4, partition_name, 12);
289 e5733356 bellard
    buf[1] = nvram_chksum(buf, 16);
290 e5733356 bellard
}    
291 e5733356 bellard
292 0aa6a4a2 bellard
/* PowerPC CHRP hardware initialisation */
293 94fc95cd j_mayer
static void ppc_chrp_init (int ram_size, int vga_ram_size, int boot_device,
294 94fc95cd j_mayer
                           DisplayState *ds, const char **fd_filename,
295 94fc95cd j_mayer
                           int snapshot,
296 94fc95cd j_mayer
                           const char *kernel_filename,
297 94fc95cd j_mayer
                           const char *kernel_cmdline,
298 94fc95cd j_mayer
                           const char *initrd_filename,
299 94fc95cd j_mayer
                           const char *cpu_model,
300 94fc95cd j_mayer
                           int is_heathrow)
301 64201201 bellard
{
302 e9df014c j_mayer
    CPUState *env, *envs[MAX_CPUS];
303 64201201 bellard
    char buf[1024];
304 e9df014c j_mayer
    qemu_irq *pic, **openpic_irqs;
305 64201201 bellard
    m48t59_t *nvram;
306 aef445bd pbrook
    int unin_memory;
307 d5295253 bellard
    int linux_boot, i;
308 d5295253 bellard
    unsigned long bios_offset, vga_bios_offset;
309 b6b8bd18 bellard
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
310 3fc6c082 bellard
    ppc_def_t *def;
311 46e50e9d bellard
    PCIBus *pci_bus;
312 0aa6a4a2 bellard
    const char *arch_name;
313 d5295253 bellard
    int vga_bios_size, bios_size;
314 d537cf6c pbrook
    qemu_irq *dummy_irq;
315 46e50e9d bellard
316 64201201 bellard
    linux_boot = (kernel_filename != NULL);
317 64201201 bellard
318 c68ea704 bellard
    /* init CPUs */
319 c68ea704 bellard
    env = cpu_init();
320 0a032cbe j_mayer
    qemu_register_reset(&cpu_ppc_reset, env);
321 c68ea704 bellard
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
322 c68ea704 bellard
323 94fc95cd j_mayer
    /* Default CPU is a generic 74x/75x */
324 94fc95cd j_mayer
    if (cpu_model == NULL)
325 94fc95cd j_mayer
        cpu_model = "750";
326 c68ea704 bellard
    /* XXX: CPU model (or PVR) should be provided on command line */
327 c68ea704 bellard
    //    ppc_find_by_name("750gx", &def); // Linux boot OK
328 c68ea704 bellard
    //    ppc_find_by_name("750fx", &def); // Linux boot OK
329 c68ea704 bellard
    /* Linux does not boot on 750cxe (and probably other 750cx based)
330 c68ea704 bellard
     * because it assumes it has 8 IBAT & DBAT pairs as it only have 4.
331 c68ea704 bellard
     */
332 94fc95cd j_mayer
    ppc_find_by_name(cpu_model, &def);
333 c68ea704 bellard
    if (def == NULL) {
334 c68ea704 bellard
        cpu_abort(env, "Unable to find PowerPC CPU definition\n");
335 c68ea704 bellard
    }
336 e9df014c j_mayer
    for (i = 0; i < smp_cpus; i++) {
337 e9df014c j_mayer
        cpu_ppc_register(env, def);
338 e9df014c j_mayer
        /* Set time-base frequency to 100 Mhz */
339 e9df014c j_mayer
        cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
340 e9df014c j_mayer
        env->osi_call = vga_osi_call;
341 e9df014c j_mayer
        envs[i] = env;
342 e9df014c j_mayer
    }
343 c68ea704 bellard
344 64201201 bellard
    /* allocate RAM */
345 64201201 bellard
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
346 64201201 bellard
347 64201201 bellard
    /* allocate and load BIOS */
348 64201201 bellard
    bios_offset = ram_size + vga_ram_size;
349 64201201 bellard
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
350 d5295253 bellard
    bios_size = load_image(buf, phys_ram_base + bios_offset);
351 d5295253 bellard
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
352 d5295253 bellard
        fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n", buf);
353 64201201 bellard
        exit(1);
354 64201201 bellard
    }
355 d5295253 bellard
    bios_size = (bios_size + 0xfff) & ~0xfff;
356 d5295253 bellard
    cpu_register_physical_memory((uint32_t)(-bios_size), 
357 d5295253 bellard
                                 bios_size, bios_offset | IO_MEM_ROM);
358 d5295253 bellard
    
359 d5295253 bellard
    /* allocate and load VGA BIOS */
360 d5295253 bellard
    vga_bios_offset = bios_offset + bios_size;
361 d5295253 bellard
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, VGABIOS_FILENAME);
362 d5295253 bellard
    vga_bios_size = load_image(buf, phys_ram_base + vga_bios_offset + 8);
363 d5295253 bellard
    if (vga_bios_size < 0) {
364 d5295253 bellard
        /* if no bios is present, we can still work */
365 d5295253 bellard
        fprintf(stderr, "qemu: warning: could not load VGA bios '%s'\n", buf);
366 d5295253 bellard
        vga_bios_size = 0;
367 d5295253 bellard
    } else {
368 d5295253 bellard
        /* set a specific header (XXX: find real Apple format for NDRV
369 d5295253 bellard
           drivers) */
370 d5295253 bellard
        phys_ram_base[vga_bios_offset] = 'N';
371 d5295253 bellard
        phys_ram_base[vga_bios_offset + 1] = 'D';
372 d5295253 bellard
        phys_ram_base[vga_bios_offset + 2] = 'R';
373 d5295253 bellard
        phys_ram_base[vga_bios_offset + 3] = 'V';
374 d5295253 bellard
        cpu_to_be32w((uint32_t *)(phys_ram_base + vga_bios_offset + 4), 
375 d5295253 bellard
                     vga_bios_size);
376 d5295253 bellard
        vga_bios_size += 8;
377 d5295253 bellard
    }
378 d5295253 bellard
    vga_bios_size = (vga_bios_size + 0xfff) & ~0xfff;
379 d5295253 bellard
    
380 b6b8bd18 bellard
    if (linux_boot) {
381 b6b8bd18 bellard
        kernel_base = KERNEL_LOAD_ADDR;
382 b6b8bd18 bellard
        /* now we can load the kernel */
383 b6b8bd18 bellard
        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
384 b6b8bd18 bellard
        if (kernel_size < 0) {
385 b6b8bd18 bellard
            fprintf(stderr, "qemu: could not load kernel '%s'\n", 
386 b6b8bd18 bellard
                    kernel_filename);
387 b6b8bd18 bellard
            exit(1);
388 b6b8bd18 bellard
        }
389 b6b8bd18 bellard
        /* load initrd */
390 b6b8bd18 bellard
        if (initrd_filename) {
391 b6b8bd18 bellard
            initrd_base = INITRD_LOAD_ADDR;
392 b6b8bd18 bellard
            initrd_size = load_image(initrd_filename,
393 b6b8bd18 bellard
                                     phys_ram_base + initrd_base);
394 b6b8bd18 bellard
            if (initrd_size < 0) {
395 b6b8bd18 bellard
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 
396 b6b8bd18 bellard
                        initrd_filename);
397 b6b8bd18 bellard
                exit(1);
398 b6b8bd18 bellard
            }
399 b6b8bd18 bellard
        } else {
400 b6b8bd18 bellard
            initrd_base = 0;
401 b6b8bd18 bellard
            initrd_size = 0;
402 b6b8bd18 bellard
        }
403 b6b8bd18 bellard
        boot_device = 'm';
404 b6b8bd18 bellard
    } else {
405 b6b8bd18 bellard
        kernel_base = 0;
406 b6b8bd18 bellard
        kernel_size = 0;
407 b6b8bd18 bellard
        initrd_base = 0;
408 b6b8bd18 bellard
        initrd_size = 0;
409 b6b8bd18 bellard
    }
410 0aa6a4a2 bellard
411 0aa6a4a2 bellard
    if (is_heathrow) {
412 0aa6a4a2 bellard
        isa_mem_base = 0x80000000;
413 dd37a5e4 j_mayer
414 0aa6a4a2 bellard
        /* Register 2 MB of ISA IO space */
415 aef445bd pbrook
        isa_mmio_init(0xfe000000, 0x00200000);
416 aef445bd pbrook
417 0aa6a4a2 bellard
        /* init basic PC hardware */
418 dd37a5e4 j_mayer
        if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
419 dd37a5e4 j_mayer
            cpu_abort(env, "Only 6xx bus is supported on heathrow machine\n");
420 dd37a5e4 j_mayer
            exit(1);
421 dd37a5e4 j_mayer
        }
422 502a5395 pbrook
        pic = heathrow_pic_init(&heathrow_pic_mem_index);
423 502a5395 pbrook
        pci_bus = pci_grackle_init(0xfec00000, pic);
424 dd37a5e4 j_mayer
        pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
425 89b6b508 bellard
                     ram_size, vga_ram_size,
426 89b6b508 bellard
                     vga_bios_offset, vga_bios_size);
427 0aa6a4a2 bellard
428 0aa6a4a2 bellard
        /* XXX: suppress that */
429 d537cf6c pbrook
        dummy_irq = i8259_init(NULL);
430 0aa6a4a2 bellard
        
431 0aa6a4a2 bellard
        /* XXX: use Mac Serial port */
432 d537cf6c pbrook
        serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
433 0aa6a4a2 bellard
        
434 0aa6a4a2 bellard
        for(i = 0; i < nb_nics; i++) {
435 a41b2ff2 pbrook
            if (!nd_table[i].model)
436 a41b2ff2 pbrook
                nd_table[i].model = "ne2k_pci";
437 abcebc7e ths
            pci_nic_init(pci_bus, &nd_table[i], -1);
438 0aa6a4a2 bellard
        }
439 0aa6a4a2 bellard
        
440 0aa6a4a2 bellard
        pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
441 0aa6a4a2 bellard
442 0aa6a4a2 bellard
        /* cuda also initialize ADB */
443 d537cf6c pbrook
        cuda_mem_index = cuda_init(pic[0x12]);
444 0aa6a4a2 bellard
        
445 0aa6a4a2 bellard
        adb_kbd_init(&adb_bus);
446 0aa6a4a2 bellard
        adb_mouse_init(&adb_bus);
447 0aa6a4a2 bellard
        
448 e5733356 bellard
        {
449 e5733356 bellard
            MacIONVRAMState *nvr;
450 e5733356 bellard
            nvr = macio_nvram_init();
451 e5733356 bellard
            pmac_format_nvram_partition(nvr->data, 0x2000);
452 e5733356 bellard
        }
453 e5733356 bellard
454 e5733356 bellard
        macio_init(pci_bus, 0x0017);
455 47103572 j_mayer
456 d537cf6c pbrook
        nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
457 47103572 j_mayer
458 0aa6a4a2 bellard
        arch_name = "HEATHROW";
459 0aa6a4a2 bellard
    } else {
460 0aa6a4a2 bellard
        isa_mem_base = 0x80000000;
461 47103572 j_mayer
462 0aa6a4a2 bellard
        /* Register 8 MB of ISA IO space */
463 aef445bd pbrook
        isa_mmio_init(0xf2000000, 0x00800000);
464 47103572 j_mayer
465 0aa6a4a2 bellard
        /* UniN init */
466 0aa6a4a2 bellard
        unin_memory = cpu_register_io_memory(0, unin_read, unin_write, NULL);
467 0aa6a4a2 bellard
        cpu_register_physical_memory(0xf8000000, 0x00001000, unin_memory);
468 0aa6a4a2 bellard
469 e9df014c j_mayer
        openpic_irqs = qemu_mallocz(smp_cpus * sizeof(qemu_irq *));
470 e9df014c j_mayer
        openpic_irqs[0] =
471 e9df014c j_mayer
            qemu_mallocz(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
472 e9df014c j_mayer
        for (i = 0; i < smp_cpus; i++) {
473 e9df014c j_mayer
            /* Mac99 IRQ connection between OpenPIC outputs pins
474 e9df014c j_mayer
             * and PowerPC input pins
475 e9df014c j_mayer
             */
476 dd37a5e4 j_mayer
            switch (PPC_INPUT(env)) {
477 dd37a5e4 j_mayer
            case PPC_FLAGS_INPUT_6xx:
478 dd37a5e4 j_mayer
                openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
479 dd37a5e4 j_mayer
                openpic_irqs[i][OPENPIC_OUTPUT_INT] =
480 dd37a5e4 j_mayer
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
481 dd37a5e4 j_mayer
                openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
482 dd37a5e4 j_mayer
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_INT];
483 dd37a5e4 j_mayer
                openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
484 dd37a5e4 j_mayer
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_MCP];
485 dd37a5e4 j_mayer
                /* Not connected ? */
486 dd37a5e4 j_mayer
                openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
487 dd37a5e4 j_mayer
                /* Check this */
488 dd37a5e4 j_mayer
                openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
489 dd37a5e4 j_mayer
                    ((qemu_irq *)env->irq_inputs)[PPC6xx_INPUT_HRESET];
490 dd37a5e4 j_mayer
                break;
491 dd37a5e4 j_mayer
            case PPC_FLAGS_INPUT_970:
492 dd37a5e4 j_mayer
                openpic_irqs[i] = openpic_irqs[0] + (i * OPENPIC_OUTPUT_NB);
493 dd37a5e4 j_mayer
                openpic_irqs[i][OPENPIC_OUTPUT_INT] =
494 dd37a5e4 j_mayer
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
495 dd37a5e4 j_mayer
                openpic_irqs[i][OPENPIC_OUTPUT_CINT] =
496 dd37a5e4 j_mayer
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_INT];
497 dd37a5e4 j_mayer
                openpic_irqs[i][OPENPIC_OUTPUT_MCK] =
498 dd37a5e4 j_mayer
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_MCP];
499 dd37a5e4 j_mayer
                /* Not connected ? */
500 dd37a5e4 j_mayer
                openpic_irqs[i][OPENPIC_OUTPUT_DEBUG] = NULL;
501 dd37a5e4 j_mayer
                /* Check this */
502 dd37a5e4 j_mayer
                openpic_irqs[i][OPENPIC_OUTPUT_RESET] =
503 dd37a5e4 j_mayer
                    ((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
504 dd37a5e4 j_mayer
                break;
505 dd37a5e4 j_mayer
            default:
506 dd37a5e4 j_mayer
                cpu_abort(env,
507 dd37a5e4 j_mayer
                          "Only bus model not supported on mac99 machine\n");
508 dd37a5e4 j_mayer
                exit(1);
509 dd37a5e4 j_mayer
            }
510 e9df014c j_mayer
        }
511 e9df014c j_mayer
        pic = openpic_init(NULL, &openpic_mem_index, smp_cpus,
512 e9df014c j_mayer
                           openpic_irqs, NULL);
513 502a5395 pbrook
        pci_bus = pci_pmac_init(pic);
514 0aa6a4a2 bellard
        /* init basic PC hardware */
515 89b6b508 bellard
        pci_vga_init(pci_bus, ds, phys_ram_base + ram_size,
516 89b6b508 bellard
                     ram_size, vga_ram_size,
517 89b6b508 bellard
                     vga_bios_offset, vga_bios_size);
518 0aa6a4a2 bellard
519 0aa6a4a2 bellard
        /* XXX: suppress that */
520 d537cf6c pbrook
        dummy_irq = i8259_init(NULL);
521 3079c59a j_mayer
522 0aa6a4a2 bellard
        /* XXX: use Mac Serial port */
523 d537cf6c pbrook
        serial_init(0x3f8, dummy_irq[4], serial_hds[0]);
524 0aa6a4a2 bellard
        for(i = 0; i < nb_nics; i++) {
525 3079c59a j_mayer
            if (!nd_table[i].model)
526 3079c59a j_mayer
                nd_table[i].model = "ne2k_pci";
527 3079c59a j_mayer
            pci_nic_init(pci_bus, &nd_table[i], -1);
528 0aa6a4a2 bellard
        }
529 0aa6a4a2 bellard
#if 1
530 d537cf6c pbrook
        ide0_mem_index = pmac_ide_init(&bs_table[0], pic[0x13]);
531 d537cf6c pbrook
        ide1_mem_index = pmac_ide_init(&bs_table[2], pic[0x14]);
532 0aa6a4a2 bellard
#else
533 0aa6a4a2 bellard
        pci_cmd646_ide_init(pci_bus, &bs_table[0], 0);
534 0aa6a4a2 bellard
#endif
535 0aa6a4a2 bellard
        /* cuda also initialize ADB */
536 d537cf6c pbrook
        cuda_mem_index = cuda_init(pic[0x19]);
537 0aa6a4a2 bellard
        
538 0aa6a4a2 bellard
        adb_kbd_init(&adb_bus);
539 0aa6a4a2 bellard
        adb_mouse_init(&adb_bus);
540 0aa6a4a2 bellard
        
541 e5733356 bellard
        macio_init(pci_bus, 0x0022);
542 0aa6a4a2 bellard
        
543 d537cf6c pbrook
        nvram = m48t59_init(dummy_irq[8], 0xFFF04000, 0x0074, NVRAM_SIZE, 59);
544 0aa6a4a2 bellard
        
545 0aa6a4a2 bellard
        arch_name = "MAC99";
546 64201201 bellard
    }
547 0d92ed30 pbrook
548 0d92ed30 pbrook
    if (usb_enabled) {
549 e24ad6f1 pbrook
        usb_ohci_init_pci(pci_bus, 3, -1);
550 0d92ed30 pbrook
    }
551 0d92ed30 pbrook
552 b6b8bd18 bellard
    if (graphic_depth != 15 && graphic_depth != 32 && graphic_depth != 8)
553 b6b8bd18 bellard
        graphic_depth = 15;
554 64201201 bellard
555 0aa6a4a2 bellard
    PPC_NVRAM_set_params(nvram, NVRAM_SIZE, arch_name, ram_size, boot_device,
556 b6b8bd18 bellard
                         kernel_base, kernel_size,
557 b6b8bd18 bellard
                         kernel_cmdline,
558 b6b8bd18 bellard
                         initrd_base, initrd_size,
559 64201201 bellard
                         /* XXX: need an option to load a NVRAM image */
560 b6b8bd18 bellard
                         0,
561 b6b8bd18 bellard
                         graphic_width, graphic_height, graphic_depth);
562 b6b8bd18 bellard
    /* No PCI init: the BIOS will do it */
563 0aa6a4a2 bellard
564 0aa6a4a2 bellard
    /* Special port to get debug messages from Open-Firmware */
565 0aa6a4a2 bellard
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
566 0aa6a4a2 bellard
}
567 0aa6a4a2 bellard
568 94fc95cd j_mayer
static void ppc_core99_init (int ram_size, int vga_ram_size, int boot_device,
569 94fc95cd j_mayer
                             DisplayState *ds, const char **fd_filename,
570 94fc95cd j_mayer
                             int snapshot,
571 94fc95cd j_mayer
                             const char *kernel_filename,
572 94fc95cd j_mayer
                             const char *kernel_cmdline,
573 94fc95cd j_mayer
                             const char *initrd_filename,
574 94fc95cd j_mayer
                             const char *cpu_model)
575 0aa6a4a2 bellard
{
576 0aa6a4a2 bellard
    ppc_chrp_init(ram_size, vga_ram_size, boot_device,
577 0aa6a4a2 bellard
                  ds, fd_filename, snapshot,
578 0aa6a4a2 bellard
                  kernel_filename, kernel_cmdline,
579 94fc95cd j_mayer
                  initrd_filename, cpu_model, 0);
580 64201201 bellard
}
581 0aa6a4a2 bellard
    
582 94fc95cd j_mayer
static void ppc_heathrow_init (int ram_size, int vga_ram_size, int boot_device,
583 94fc95cd j_mayer
                               DisplayState *ds, const char **fd_filename,
584 94fc95cd j_mayer
                               int snapshot,
585 94fc95cd j_mayer
                               const char *kernel_filename,
586 94fc95cd j_mayer
                               const char *kernel_cmdline,
587 94fc95cd j_mayer
                               const char *initrd_filename,
588 94fc95cd j_mayer
                               const char *cpu_model)
589 0aa6a4a2 bellard
{
590 0aa6a4a2 bellard
    ppc_chrp_init(ram_size, vga_ram_size, boot_device,
591 0aa6a4a2 bellard
                  ds, fd_filename, snapshot,
592 0aa6a4a2 bellard
                  kernel_filename, kernel_cmdline,
593 94fc95cd j_mayer
                  initrd_filename, cpu_model, 1);
594 0aa6a4a2 bellard
}
595 0aa6a4a2 bellard
596 0aa6a4a2 bellard
QEMUMachine core99_machine = {
597 0289b2c1 bellard
    "mac99",
598 0289b2c1 bellard
    "Mac99 based PowerMAC",
599 0aa6a4a2 bellard
    ppc_core99_init,
600 0aa6a4a2 bellard
};
601 0aa6a4a2 bellard
602 0aa6a4a2 bellard
QEMUMachine heathrow_machine = {
603 0289b2c1 bellard
    "g3bw",
604 0aa6a4a2 bellard
    "Heathrow based PowerMAC",
605 0aa6a4a2 bellard
    ppc_heathrow_init,
606 0aa6a4a2 bellard
};