root / hw / prep_pci.c @ 92d88ecb
History | View | Annotate | Download (5.1 kB)
1 | 502a5395 | pbrook | /*
|
---|---|---|---|
2 | 502a5395 | pbrook | * QEMU PREP PCI host
|
3 | 502a5395 | pbrook | *
|
4 | 502a5395 | pbrook | * Copyright (c) 2006 Fabrice Bellard
|
5 | 502a5395 | pbrook | *
|
6 | 502a5395 | pbrook | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
7 | 502a5395 | pbrook | * of this software and associated documentation files (the "Software"), to deal
|
8 | 502a5395 | pbrook | * in the Software without restriction, including without limitation the rights
|
9 | 502a5395 | pbrook | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
10 | 502a5395 | pbrook | * copies of the Software, and to permit persons to whom the Software is
|
11 | 502a5395 | pbrook | * furnished to do so, subject to the following conditions:
|
12 | 502a5395 | pbrook | *
|
13 | 502a5395 | pbrook | * The above copyright notice and this permission notice shall be included in
|
14 | 502a5395 | pbrook | * all copies or substantial portions of the Software.
|
15 | 502a5395 | pbrook | *
|
16 | 502a5395 | pbrook | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
17 | 502a5395 | pbrook | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
18 | 502a5395 | pbrook | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
19 | 502a5395 | pbrook | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
20 | 502a5395 | pbrook | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
21 | 502a5395 | pbrook | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
22 | 502a5395 | pbrook | * THE SOFTWARE.
|
23 | 502a5395 | pbrook | */
|
24 | 502a5395 | pbrook | |
25 | 502a5395 | pbrook | #include "vl.h" |
26 | 502a5395 | pbrook | typedef uint32_t pci_addr_t;
|
27 | 502a5395 | pbrook | #include "pci_host.h" |
28 | 502a5395 | pbrook | |
29 | 502a5395 | pbrook | typedef PCIHostState PREPPCIState;
|
30 | 502a5395 | pbrook | |
31 | 502a5395 | pbrook | static void pci_prep_addr_writel(void* opaque, uint32_t addr, uint32_t val) |
32 | 502a5395 | pbrook | { |
33 | 502a5395 | pbrook | PREPPCIState *s = opaque; |
34 | 502a5395 | pbrook | s->config_reg = val; |
35 | 502a5395 | pbrook | } |
36 | 502a5395 | pbrook | |
37 | 502a5395 | pbrook | static uint32_t pci_prep_addr_readl(void* opaque, uint32_t addr) |
38 | 502a5395 | pbrook | { |
39 | 502a5395 | pbrook | PREPPCIState *s = opaque; |
40 | 502a5395 | pbrook | return s->config_reg;
|
41 | 502a5395 | pbrook | } |
42 | 502a5395 | pbrook | |
43 | 502a5395 | pbrook | static inline uint32_t PPC_PCIIO_config(target_phys_addr_t addr) |
44 | 502a5395 | pbrook | { |
45 | 502a5395 | pbrook | int i;
|
46 | 502a5395 | pbrook | |
47 | 502a5395 | pbrook | for(i = 0; i < 11; i++) { |
48 | 502a5395 | pbrook | if ((addr & (1 << (11 + i))) != 0) |
49 | 502a5395 | pbrook | break;
|
50 | 502a5395 | pbrook | } |
51 | 502a5395 | pbrook | return (addr & 0x7ff) | (i << 11); |
52 | 502a5395 | pbrook | } |
53 | 502a5395 | pbrook | |
54 | 502a5395 | pbrook | static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val) |
55 | 502a5395 | pbrook | { |
56 | 502a5395 | pbrook | PREPPCIState *s = opaque; |
57 | 502a5395 | pbrook | pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 1);
|
58 | 502a5395 | pbrook | } |
59 | 502a5395 | pbrook | |
60 | 502a5395 | pbrook | static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val) |
61 | 502a5395 | pbrook | { |
62 | 502a5395 | pbrook | PREPPCIState *s = opaque; |
63 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
|
64 | 502a5395 | pbrook | val = bswap16(val); |
65 | 502a5395 | pbrook | #endif
|
66 | 502a5395 | pbrook | pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 2);
|
67 | 502a5395 | pbrook | } |
68 | 502a5395 | pbrook | |
69 | 502a5395 | pbrook | static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val) |
70 | 502a5395 | pbrook | { |
71 | 502a5395 | pbrook | PREPPCIState *s = opaque; |
72 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
|
73 | 502a5395 | pbrook | val = bswap32(val); |
74 | 502a5395 | pbrook | #endif
|
75 | 502a5395 | pbrook | pci_data_write(s->bus, PPC_PCIIO_config(addr), val, 4);
|
76 | 502a5395 | pbrook | } |
77 | 502a5395 | pbrook | |
78 | 502a5395 | pbrook | static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr) |
79 | 502a5395 | pbrook | { |
80 | 502a5395 | pbrook | PREPPCIState *s = opaque; |
81 | 502a5395 | pbrook | uint32_t val; |
82 | 502a5395 | pbrook | val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 1);
|
83 | 502a5395 | pbrook | return val;
|
84 | 502a5395 | pbrook | } |
85 | 502a5395 | pbrook | |
86 | 502a5395 | pbrook | static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr) |
87 | 502a5395 | pbrook | { |
88 | 502a5395 | pbrook | PREPPCIState *s = opaque; |
89 | 502a5395 | pbrook | uint32_t val; |
90 | 502a5395 | pbrook | val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 2);
|
91 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
|
92 | 502a5395 | pbrook | val = bswap16(val); |
93 | 502a5395 | pbrook | #endif
|
94 | 502a5395 | pbrook | return val;
|
95 | 502a5395 | pbrook | } |
96 | 502a5395 | pbrook | |
97 | 502a5395 | pbrook | static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr) |
98 | 502a5395 | pbrook | { |
99 | 502a5395 | pbrook | PREPPCIState *s = opaque; |
100 | 502a5395 | pbrook | uint32_t val; |
101 | 502a5395 | pbrook | val = pci_data_read(s->bus, PPC_PCIIO_config(addr), 4);
|
102 | 502a5395 | pbrook | #ifdef TARGET_WORDS_BIGENDIAN
|
103 | 502a5395 | pbrook | val = bswap32(val); |
104 | 502a5395 | pbrook | #endif
|
105 | 502a5395 | pbrook | return val;
|
106 | 502a5395 | pbrook | } |
107 | 502a5395 | pbrook | |
108 | 502a5395 | pbrook | static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
|
109 | 502a5395 | pbrook | &PPC_PCIIO_writeb, |
110 | 502a5395 | pbrook | &PPC_PCIIO_writew, |
111 | 502a5395 | pbrook | &PPC_PCIIO_writel, |
112 | 502a5395 | pbrook | }; |
113 | 502a5395 | pbrook | |
114 | 502a5395 | pbrook | static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
|
115 | 502a5395 | pbrook | &PPC_PCIIO_readb, |
116 | 502a5395 | pbrook | &PPC_PCIIO_readw, |
117 | 502a5395 | pbrook | &PPC_PCIIO_readl, |
118 | 502a5395 | pbrook | }; |
119 | 502a5395 | pbrook | |
120 | d2b59317 | pbrook | /* Don't know if this matches real hardware, but it agrees with OHW. */
|
121 | d2b59317 | pbrook | static int prep_map_irq(PCIDevice *pci_dev, int irq_num) |
122 | 502a5395 | pbrook | { |
123 | 80b3ada7 | pbrook | return (irq_num + (pci_dev->devfn >> 3)) & 1; |
124 | d2b59317 | pbrook | } |
125 | d2b59317 | pbrook | |
126 | d537cf6c | pbrook | static void prep_set_irq(qemu_irq *pic, int irq_num, int level) |
127 | d2b59317 | pbrook | { |
128 | d537cf6c | pbrook | qemu_set_irq(pic[irq_num ? 11 : 9], level); |
129 | 502a5395 | pbrook | } |
130 | 502a5395 | pbrook | |
131 | d537cf6c | pbrook | PCIBus *pci_prep_init(qemu_irq *pic) |
132 | 502a5395 | pbrook | { |
133 | 502a5395 | pbrook | PREPPCIState *s; |
134 | 502a5395 | pbrook | PCIDevice *d; |
135 | 502a5395 | pbrook | int PPC_io_memory;
|
136 | 502a5395 | pbrook | |
137 | 502a5395 | pbrook | s = qemu_mallocz(sizeof(PREPPCIState));
|
138 | d537cf6c | pbrook | s->bus = pci_register_bus(prep_set_irq, prep_map_irq, pic, 0, 2); |
139 | 502a5395 | pbrook | |
140 | 502a5395 | pbrook | register_ioport_write(0xcf8, 4, 4, pci_prep_addr_writel, s); |
141 | 502a5395 | pbrook | register_ioport_read(0xcf8, 4, 4, pci_prep_addr_readl, s); |
142 | 502a5395 | pbrook | |
143 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 1, pci_host_data_writeb, s); |
144 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 2, pci_host_data_writew, s); |
145 | 502a5395 | pbrook | register_ioport_write(0xcfc, 4, 4, pci_host_data_writel, s); |
146 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 1, pci_host_data_readb, s); |
147 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 2, pci_host_data_readw, s); |
148 | 502a5395 | pbrook | register_ioport_read(0xcfc, 4, 4, pci_host_data_readl, s); |
149 | 502a5395 | pbrook | |
150 | 502a5395 | pbrook | PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
|
151 | 502a5395 | pbrook | PPC_PCIIO_write, s); |
152 | 502a5395 | pbrook | cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory); |
153 | 502a5395 | pbrook | |
154 | 502a5395 | pbrook | /* PCI host bridge */
|
155 | 502a5395 | pbrook | d = pci_register_device(s->bus, "PREP Host Bridge - Motorola Raven",
|
156 | 502a5395 | pbrook | sizeof(PCIDevice), 0, NULL, NULL); |
157 | 502a5395 | pbrook | d->config[0x00] = 0x57; // vendor_id : Motorola |
158 | 502a5395 | pbrook | d->config[0x01] = 0x10; |
159 | 502a5395 | pbrook | d->config[0x02] = 0x01; // device_id : Raven |
160 | 502a5395 | pbrook | d->config[0x03] = 0x48; |
161 | 502a5395 | pbrook | d->config[0x08] = 0x00; // revision |
162 | 502a5395 | pbrook | d->config[0x0A] = 0x00; // class_sub = pci host |
163 | 502a5395 | pbrook | d->config[0x0B] = 0x06; // class_base = PCI_bridge |
164 | 502a5395 | pbrook | d->config[0x0C] = 0x08; // cache_line_size |
165 | 502a5395 | pbrook | d->config[0x0D] = 0x10; // latency_timer |
166 | 502a5395 | pbrook | d->config[0x0E] = 0x00; // header_type |
167 | 502a5395 | pbrook | d->config[0x34] = 0x00; // capabilities_pointer |
168 | 502a5395 | pbrook | |
169 | 502a5395 | pbrook | return s->bus;
|
170 | 502a5395 | pbrook | } |