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/* opcodes/s390-dis.c revision 1.12 */
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/* s390-dis.c -- Disassemble S390 instructions
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Copyright 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc.
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Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
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This file is part of GDB, GAS and the GNU binutils.
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#include "qemu-common.h" |
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#include "dis-asm.h" |
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/* include/opcode/s390.h revision 1.9 */
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/* s390.h -- Header file for S390 opcode table
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Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
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Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
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This file is part of BFD, the Binary File Descriptor library.
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This program is free software; you can redistribute it and/or modify
|
| 34 |
it under the terms of the GNU General Public License as published by
|
| 35 |
the Free Software Foundation; either version 2 of the License, or
|
| 36 |
(at your option) any later version.
|
| 37 |
|
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 41 |
GNU General Public License for more details.
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| 42 |
|
| 43 |
You should have received a copy of the GNU General Public License
|
| 44 |
along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
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02110-1301, USA. */
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#ifndef S390_H
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#define S390_H
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/* List of instruction sets variations. */
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enum s390_opcode_mode_val
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{
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S390_OPCODE_ESA = 0,
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S390_OPCODE_ZARCH |
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}; |
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enum s390_opcode_cpu_val
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{
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S390_OPCODE_G5 = 0,
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S390_OPCODE_G6, |
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S390_OPCODE_Z900, |
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S390_OPCODE_Z990, |
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S390_OPCODE_Z9_109, |
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S390_OPCODE_Z9_EC, |
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S390_OPCODE_Z10 |
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}; |
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/* The opcode table is an array of struct s390_opcode. */
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struct s390_opcode
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{
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/* The opcode name. */
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const char * name; |
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/* The opcode itself. Those bits which will be filled in with
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operands are zeroes. */
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unsigned char opcode[6]; |
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/* The opcode mask. This is used by the disassembler. This is a
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mask containing ones indicating those bits which must match the
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opcode field, and zeroes indicating those bits which need not
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match (and are presumably filled in by operands). */
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unsigned char mask[6]; |
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/* The opcode length in bytes. */
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int oplen;
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/* An array of operand codes. Each code is an index into the
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operand table. They appear in the order which the operands must
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appear in assembly code, and are terminated by a zero. */
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unsigned char operands[6]; |
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/* Bitmask of execution modes this opcode is available for. */
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unsigned int modes; |
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/* First cpu this opcode is available for. */
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enum s390_opcode_cpu_val min_cpu;
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}; |
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/* The table itself is sorted by major opcode number, and is otherwise
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in the order in which the disassembler should consider
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instructions. */
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/* QEMU: Mark these static. */
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static const struct s390_opcode s390_opcodes[]; |
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static const int s390_num_opcodes; |
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/* A opcode format table for the .insn pseudo mnemonic. */
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static const struct s390_opcode s390_opformats[]; |
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static const int s390_num_opformats; |
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/* Values defined for the flags field of a struct powerpc_opcode. */
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/* The operands table is an array of struct s390_operand. */
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struct s390_operand
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{
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/* The number of bits in the operand. */
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int bits;
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/* How far the operand is left shifted in the instruction. */
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int shift;
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/* One bit syntax flags. */
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unsigned long flags; |
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}; |
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/* Elements in the table are retrieved by indexing with values from
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the operands field of the powerpc_opcodes table. */
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static const struct s390_operand s390_operands[]; |
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/* Values defined for the flags field of a struct s390_operand. */
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/* This operand names a register. The disassembler uses this to print
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register names with a leading 'r'. */
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#define S390_OPERAND_GPR 0x1 |
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/* This operand names a floating point register. The disassembler
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prints these with a leading 'f'. */
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#define S390_OPERAND_FPR 0x2 |
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/* This operand names an access register. The disassembler
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prints these with a leading 'a'. */
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#define S390_OPERAND_AR 0x4 |
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/* This operand names a control register. The disassembler
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prints these with a leading 'c'. */
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#define S390_OPERAND_CR 0x8 |
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/* This operand is a displacement. */
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#define S390_OPERAND_DISP 0x10 |
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/* This operand names a base register. */
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#define S390_OPERAND_BASE 0x20 |
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/* This operand names an index register, it can be skipped. */
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#define S390_OPERAND_INDEX 0x40 |
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/* This operand is a relative branch displacement. The disassembler
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prints these symbolically if possible. */
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#define S390_OPERAND_PCREL 0x80 |
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/* This operand takes signed values. */
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#define S390_OPERAND_SIGNED 0x100 |
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/* This operand is a length. */
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#define S390_OPERAND_LENGTH 0x200 |
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/* This operand is optional. Only a single operand at the end of
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the instruction may be optional. */
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#define S390_OPERAND_OPTIONAL 0x400 |
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/* QEMU-ADD */
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/* ??? Not quite the format the assembler takes, but easy to implement
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without recourse to the table generator. */
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#define S390_OPERAND_CCODE 0x800 |
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static const char s390_ccode_name[16][4] = { |
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"n", /* 0000 */ |
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"o", /* 0001 */ |
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"h", /* 0010 */ |
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"nle", /* 0011 */ |
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"l", /* 0100 */ |
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"nhe", /* 0101 */ |
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"lh", /* 0110 */ |
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"ne", /* 0111 */ |
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"e", /* 1000 */ |
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"nlh", /* 1001 */ |
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"he", /* 1010 */ |
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"nl", /* 1011 */ |
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"le", /* 1100 */ |
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"nh", /* 1101 */ |
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"no", /* 1110 */ |
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"a" /* 1111 */ |
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}; |
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/* QEMU-END */
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#endif /* S390_H */ |
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static int init_flag = 0; |
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static int opc_index[256]; |
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/* QEMU: We've disabled the architecture check below. */
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/* static int current_arch_mask = 0; */
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/* Set up index table for first opcode byte. */
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static void |
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init_disasm (struct disassemble_info *info)
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{
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const struct s390_opcode *opcode; |
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const struct s390_opcode *opcode_end; |
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memset (opc_index, 0, sizeof (opc_index)); |
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opcode_end = s390_opcodes + s390_num_opcodes; |
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for (opcode = s390_opcodes; opcode < opcode_end; opcode++)
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{
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opc_index[(int) opcode->opcode[0]] = opcode - s390_opcodes; |
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while ((opcode < opcode_end) &&
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(opcode[1].opcode[0] == opcode->opcode[0])) |
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opcode++; |
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} |
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#ifdef QEMU_DISABLE
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switch (info->mach)
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{
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case bfd_mach_s390_31:
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current_arch_mask = 1 << S390_OPCODE_ESA;
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break;
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case bfd_mach_s390_64:
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current_arch_mask = 1 << S390_OPCODE_ZARCH;
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break;
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default:
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abort (); |
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} |
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#endif /* QEMU_DISABLE */ |
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init_flag = 1;
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} |
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/* Extracts an operand value from an instruction. */
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static inline unsigned int |
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s390_extract_operand (unsigned char *insn, const struct s390_operand *operand) |
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{
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unsigned int val; |
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int bits;
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/* Extract fragments of the operand byte for byte. */
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insn += operand->shift / 8;
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bits = (operand->shift & 7) + operand->bits;
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val = 0;
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do
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{
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val <<= 8;
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val |= (unsigned int) *insn++; |
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bits -= 8;
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} |
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while (bits > 0); |
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val >>= -bits; |
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val &= ((1U << (operand->bits - 1)) << 1) - 1; |
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/* Check for special long displacement case. */
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if (operand->bits == 20 && operand->shift == 20) |
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val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; |
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/* Sign extend value if the operand is signed or pc relative. */
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if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL))
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&& (val & (1U << (operand->bits - 1)))) |
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val |= (-1U << (operand->bits - 1)) << 1; |
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/* Double value if the operand is pc relative. */
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if (operand->flags & S390_OPERAND_PCREL)
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val <<= 1;
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/* Length x in an instructions has real length x + 1. */
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if (operand->flags & S390_OPERAND_LENGTH)
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val++; |
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return val;
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} |
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/* Print a S390 instruction. */
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int
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print_insn_s390 (bfd_vma memaddr, struct disassemble_info *info)
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{
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bfd_byte buffer[6];
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const struct s390_opcode *opcode; |
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const struct s390_opcode *opcode_end; |
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unsigned int value; |
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int status, opsize, bufsize;
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char separator;
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if (init_flag == 0) |
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init_disasm (info); |
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/* The output looks better if we put 6 bytes on a line. */
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info->bytes_per_line = 6;
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/* Every S390 instruction is max 6 bytes long. */
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memset (buffer, 0, 6); |
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status = (*info->read_memory_func) (memaddr, buffer, 6, info);
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if (status != 0) |
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{
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for (bufsize = 0; bufsize < 6; bufsize++) |
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if ((*info->read_memory_func) (memaddr, buffer, bufsize + 1, info) != 0) |
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break;
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if (bufsize <= 0) |
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{
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(*info->memory_error_func) (status, memaddr, info); |
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return -1; |
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} |
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/* Opsize calculation looks strange but it works
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00xxxxxx -> 2 bytes, 01xxxxxx/10xxxxxx -> 4 bytes,
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11xxxxxx -> 6 bytes. */
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opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; |
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status = opsize > bufsize; |
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} |
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else
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{
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bufsize = 6;
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opsize = ((((buffer[0] >> 6) + 1) >> 1) + 1) << 1; |
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} |
| 326 |
|
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if (status == 0) |
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{
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/* Find the first match in the opcode table. */
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opcode_end = s390_opcodes + s390_num_opcodes; |
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for (opcode = s390_opcodes + opc_index[(int) buffer[0]]; |
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(opcode < opcode_end) && (buffer[0] == opcode->opcode[0]); |
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opcode++) |
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{
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const struct s390_operand *operand; |
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const unsigned char *opindex; |
| 337 |
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#ifdef QEMU_DISABLE
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/* Check architecture. */
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if (!(opcode->modes & current_arch_mask))
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continue;
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#endif /* QEMU_DISABLE */ |
| 343 |
|
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/* Check signature of the opcode. */
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if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1] |
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|| (buffer[2] & opcode->mask[2]) != opcode->opcode[2] |
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|| (buffer[3] & opcode->mask[3]) != opcode->opcode[3] |
| 348 |
|| (buffer[4] & opcode->mask[4]) != opcode->opcode[4] |
| 349 |
|| (buffer[5] & opcode->mask[5]) != opcode->opcode[5]) |
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continue;
|
| 351 |
|
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/* The instruction is valid. */
|
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/* QEMU-MOD */
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(*info->fprintf_func) (info->stream, "%s", opcode->name);
|
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|
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if (s390_operands[opcode->operands[0]].flags & S390_OPERAND_CCODE) |
| 357 |
separator = 0;
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else
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separator = '\t';
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/* QEMU-END */
|
| 361 |
|
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/* Extract the operands. */
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for (opindex = opcode->operands; *opindex != 0; opindex++) |
| 364 |
{
|
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unsigned int value; |
| 366 |
|
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operand = s390_operands + *opindex; |
| 368 |
value = s390_extract_operand (buffer, operand); |
| 369 |
|
| 370 |
if ((operand->flags & S390_OPERAND_INDEX) && value == 0) |
| 371 |
continue;
|
| 372 |
if ((operand->flags & S390_OPERAND_BASE) &&
|
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value == 0 && separator == '(') |
| 374 |
{
|
| 375 |
separator = ',';
|
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continue;
|
| 377 |
} |
| 378 |
|
| 379 |
if (separator)
|
| 380 |
(*info->fprintf_func) (info->stream, "%c", separator);
|
| 381 |
|
| 382 |
if (operand->flags & S390_OPERAND_GPR)
|
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(*info->fprintf_func) (info->stream, "%%r%i", value);
|
| 384 |
else if (operand->flags & S390_OPERAND_FPR) |
| 385 |
(*info->fprintf_func) (info->stream, "%%f%i", value);
|
| 386 |
else if (operand->flags & S390_OPERAND_AR) |
| 387 |
(*info->fprintf_func) (info->stream, "%%a%i", value);
|
| 388 |
else if (operand->flags & S390_OPERAND_CR) |
| 389 |
(*info->fprintf_func) (info->stream, "%%c%i", value);
|
| 390 |
else if (operand->flags & S390_OPERAND_PCREL) |
| 391 |
(*info->print_address_func) (memaddr + (int) value, info);
|
| 392 |
else if (operand->flags & S390_OPERAND_SIGNED) |
| 393 |
(*info->fprintf_func) (info->stream, "%i", (int) value); |
| 394 |
/* QEMU-ADD */
|
| 395 |
else if (operand->flags & S390_OPERAND_CCODE) |
| 396 |
{
|
| 397 |
(*info->fprintf_func) (info->stream, "%s",
|
| 398 |
s390_ccode_name[(int) value]);
|
| 399 |
separator = '\t';
|
| 400 |
continue;
|
| 401 |
} |
| 402 |
/* QEMU-END */
|
| 403 |
else
|
| 404 |
(*info->fprintf_func) (info->stream, "%u", value);
|
| 405 |
|
| 406 |
if (operand->flags & S390_OPERAND_DISP)
|
| 407 |
{
|
| 408 |
separator = '(';
|
| 409 |
} |
| 410 |
else if (operand->flags & S390_OPERAND_BASE) |
| 411 |
{
|
| 412 |
(*info->fprintf_func) (info->stream, ")");
|
| 413 |
separator = ',';
|
| 414 |
} |
| 415 |
else
|
| 416 |
separator = ',';
|
| 417 |
} |
| 418 |
|
| 419 |
/* Found instruction, printed it, return its size. */
|
| 420 |
return opsize;
|
| 421 |
} |
| 422 |
/* No matching instruction found, fall through to hex print. */
|
| 423 |
} |
| 424 |
|
| 425 |
if (bufsize >= 4) |
| 426 |
{
|
| 427 |
value = (unsigned int) buffer[0]; |
| 428 |
value = (value << 8) + (unsigned int) buffer[1]; |
| 429 |
value = (value << 8) + (unsigned int) buffer[2]; |
| 430 |
value = (value << 8) + (unsigned int) buffer[3]; |
| 431 |
(*info->fprintf_func) (info->stream, ".long\t0x%08x", value);
|
| 432 |
return 4; |
| 433 |
} |
| 434 |
else if (bufsize >= 2) |
| 435 |
{
|
| 436 |
value = (unsigned int) buffer[0]; |
| 437 |
value = (value << 8) + (unsigned int) buffer[1]; |
| 438 |
(*info->fprintf_func) (info->stream, ".short\t0x%04x", value);
|
| 439 |
return 2; |
| 440 |
} |
| 441 |
else
|
| 442 |
{
|
| 443 |
value = (unsigned int) buffer[0]; |
| 444 |
(*info->fprintf_func) (info->stream, ".byte\t0x%02x", value);
|
| 445 |
return 1; |
| 446 |
} |
| 447 |
} |
| 448 |
|
| 449 |
/* opcodes/s390-opc.c revision 1.16 */
|
| 450 |
/* s390-opc.c -- S390 opcode list
|
| 451 |
Copyright 2000, 2001, 2003 Free Software Foundation, Inc.
|
| 452 |
Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com).
|
| 453 |
|
| 454 |
This file is part of GDB, GAS, and the GNU binutils.
|
| 455 |
|
| 456 |
This program is free software; you can redistribute it and/or modify
|
| 457 |
it under the terms of the GNU General Public License as published by
|
| 458 |
the Free Software Foundation; either version 2 of the License, or
|
| 459 |
(at your option) any later version.
|
| 460 |
|
| 461 |
This program is distributed in the hope that it will be useful,
|
| 462 |
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 463 |
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 464 |
GNU General Public License for more details.
|
| 465 |
|
| 466 |
You should have received a copy of the GNU General Public License
|
| 467 |
along with this program; if not, write to the Free Software
|
| 468 |
Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA
|
| 469 |
02110-1301, USA. */
|
| 470 |
|
| 471 |
/* This file holds the S390 opcode table. The opcode table
|
| 472 |
includes almost all of the extended instruction mnemonics. This
|
| 473 |
permits the disassembler to use them, and simplifies the assembler
|
| 474 |
logic, at the cost of increasing the table size. The table is
|
| 475 |
strictly constant data, so the compiler should be able to put it in
|
| 476 |
the .text section.
|
| 477 |
|
| 478 |
This file also holds the operand table. All knowledge about
|
| 479 |
inserting operands into instructions and vice-versa is kept in this
|
| 480 |
file. */
|
| 481 |
|
| 482 |
/* The operands table.
|
| 483 |
The fields are bits, shift, insert, extract, flags. */
|
| 484 |
|
| 485 |
static const struct s390_operand s390_operands[] = |
| 486 |
{
|
| 487 |
#define UNUSED 0 |
| 488 |
{ 0, 0, 0 }, /* Indicates the end of the operand list */
|
| 489 |
|
| 490 |
#define R_8 1 /* GPR starting at position 8 */ |
| 491 |
{ 4, 8, S390_OPERAND_GPR },
|
| 492 |
#define R_12 2 /* GPR starting at position 12 */ |
| 493 |
{ 4, 12, S390_OPERAND_GPR },
|
| 494 |
#define R_16 3 /* GPR starting at position 16 */ |
| 495 |
{ 4, 16, S390_OPERAND_GPR },
|
| 496 |
#define R_20 4 /* GPR starting at position 20 */ |
| 497 |
{ 4, 20, S390_OPERAND_GPR },
|
| 498 |
#define R_24 5 /* GPR starting at position 24 */ |
| 499 |
{ 4, 24, S390_OPERAND_GPR },
|
| 500 |
#define R_28 6 /* GPR starting at position 28 */ |
| 501 |
{ 4, 28, S390_OPERAND_GPR },
|
| 502 |
#define R_32 7 /* GPR starting at position 32 */ |
| 503 |
{ 4, 32, S390_OPERAND_GPR },
|
| 504 |
|
| 505 |
#define F_8 8 /* FPR starting at position 8 */ |
| 506 |
{ 4, 8, S390_OPERAND_FPR },
|
| 507 |
#define F_12 9 /* FPR starting at position 12 */ |
| 508 |
{ 4, 12, S390_OPERAND_FPR },
|
| 509 |
#define F_16 10 /* FPR starting at position 16 */ |
| 510 |
{ 4, 16, S390_OPERAND_FPR },
|
| 511 |
#define F_20 11 /* FPR starting at position 16 */ |
| 512 |
{ 4, 16, S390_OPERAND_FPR },
|
| 513 |
#define F_24 12 /* FPR starting at position 24 */ |
| 514 |
{ 4, 24, S390_OPERAND_FPR },
|
| 515 |
#define F_28 13 /* FPR starting at position 28 */ |
| 516 |
{ 4, 28, S390_OPERAND_FPR },
|
| 517 |
#define F_32 14 /* FPR starting at position 32 */ |
| 518 |
{ 4, 32, S390_OPERAND_FPR },
|
| 519 |
|
| 520 |
#define A_8 15 /* Access reg. starting at position 8 */ |
| 521 |
{ 4, 8, S390_OPERAND_AR },
|
| 522 |
#define A_12 16 /* Access reg. starting at position 12 */ |
| 523 |
{ 4, 12, S390_OPERAND_AR },
|
| 524 |
#define A_24 17 /* Access reg. starting at position 24 */ |
| 525 |
{ 4, 24, S390_OPERAND_AR },
|
| 526 |
#define A_28 18 /* Access reg. starting at position 28 */ |
| 527 |
{ 4, 28, S390_OPERAND_AR },
|
| 528 |
|
| 529 |
#define C_8 19 /* Control reg. starting at position 8 */ |
| 530 |
{ 4, 8, S390_OPERAND_CR },
|
| 531 |
#define C_12 20 /* Control reg. starting at position 12 */ |
| 532 |
{ 4, 12, S390_OPERAND_CR },
|
| 533 |
|
| 534 |
#define B_16 21 /* Base register starting at position 16 */ |
| 535 |
{ 4, 16, S390_OPERAND_BASE|S390_OPERAND_GPR },
|
| 536 |
#define B_32 22 /* Base register starting at position 32 */ |
| 537 |
{ 4, 32, S390_OPERAND_BASE|S390_OPERAND_GPR },
|
| 538 |
|
| 539 |
#define X_12 23 /* Index register starting at position 12 */ |
| 540 |
{ 4, 12, S390_OPERAND_INDEX|S390_OPERAND_GPR },
|
| 541 |
|
| 542 |
#define D_20 24 /* Displacement starting at position 20 */ |
| 543 |
{ 12, 20, S390_OPERAND_DISP },
|
| 544 |
#define D_36 25 /* Displacement starting at position 36 */ |
| 545 |
{ 12, 36, S390_OPERAND_DISP },
|
| 546 |
#define D20_20 26 /* 20 bit displacement starting at 20 */ |
| 547 |
{ 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED },
|
| 548 |
|
| 549 |
#define L4_8 27 /* 4 bit length starting at position 8 */ |
| 550 |
{ 4, 8, S390_OPERAND_LENGTH },
|
| 551 |
#define L4_12 28 /* 4 bit length starting at position 12 */ |
| 552 |
{ 4, 12, S390_OPERAND_LENGTH },
|
| 553 |
#define L8_8 29 /* 8 bit length starting at position 8 */ |
| 554 |
{ 8, 8, S390_OPERAND_LENGTH },
|
| 555 |
|
| 556 |
#define U4_8 30 /* 4 bit unsigned value starting at 8 */ |
| 557 |
{ 4, 8, 0 },
|
| 558 |
#define U4_12 31 /* 4 bit unsigned value starting at 12 */ |
| 559 |
{ 4, 12, 0 },
|
| 560 |
#define U4_16 32 /* 4 bit unsigned value starting at 16 */ |
| 561 |
{ 4, 16, 0 },
|
| 562 |
#define U4_20 33 /* 4 bit unsigned value starting at 20 */ |
| 563 |
{ 4, 20, 0 },
|
| 564 |
#define U8_8 34 /* 8 bit unsigned value starting at 8 */ |
| 565 |
{ 8, 8, 0 },
|
| 566 |
#define U8_16 35 /* 8 bit unsigned value starting at 16 */ |
| 567 |
{ 8, 16, 0 },
|
| 568 |
#define I16_16 36 /* 16 bit signed value starting at 16 */ |
| 569 |
{ 16, 16, S390_OPERAND_SIGNED },
|
| 570 |
#define U16_16 37 /* 16 bit unsigned value starting at 16 */ |
| 571 |
{ 16, 16, 0 },
|
| 572 |
#define J16_16 38 /* PC relative jump offset at 16 */ |
| 573 |
{ 16, 16, S390_OPERAND_PCREL },
|
| 574 |
#define J32_16 39 /* PC relative long offset at 16 */ |
| 575 |
{ 32, 16, S390_OPERAND_PCREL },
|
| 576 |
#define I32_16 40 /* 32 bit signed value starting at 16 */ |
| 577 |
{ 32, 16, S390_OPERAND_SIGNED },
|
| 578 |
#define U32_16 41 /* 32 bit unsigned value starting at 16 */ |
| 579 |
{ 32, 16, 0 },
|
| 580 |
#define M_16 42 /* 4 bit optional mask starting at 16 */ |
| 581 |
{ 4, 16, S390_OPERAND_OPTIONAL },
|
| 582 |
#define RO_28 43 /* optional GPR starting at position 28 */ |
| 583 |
{ 4, 28, (S390_OPERAND_GPR | S390_OPERAND_OPTIONAL) },
|
| 584 |
|
| 585 |
/* QEMU-ADD: */
|
| 586 |
#define M4_12 44 /* 4-bit condition-code starting at 12 */ |
| 587 |
{ 4, 12, S390_OPERAND_CCODE },
|
| 588 |
#define M4_32 45 /* 4-bit condition-code starting at 32 */ |
| 589 |
{ 4, 32, S390_OPERAND_CCODE },
|
| 590 |
#define I8_32 46 /* 8 bit signed value starting at 32 */ |
| 591 |
{ 8, 32, S390_OPERAND_SIGNED },
|
| 592 |
/* QEMU-END */
|
| 593 |
}; |
| 594 |
|
| 595 |
|
| 596 |
/* Macros used to form opcodes. */
|
| 597 |
|
| 598 |
/* 8/16/48 bit opcodes. */
|
| 599 |
#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 600 |
#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } |
| 601 |
#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ |
| 602 |
(x >> 16) & 255, (x >> 8) & 255, x & 255} |
| 603 |
|
| 604 |
/* The new format of the INSTR_x_y and MASK_x_y defines is based
|
| 605 |
on the following rules:
|
| 606 |
1) the middle part of the definition (x in INSTR_x_y) is the official
|
| 607 |
names of the instruction format that you can find in the principals
|
| 608 |
of operation.
|
| 609 |
2) the last part of the definition (y in INSTR_x_y) gives you an idea
|
| 610 |
which operands the binary represenation of the instruction has.
|
| 611 |
The meanings of the letters in y are:
|
| 612 |
a - access register
|
| 613 |
c - control register
|
| 614 |
d - displacement, 12 bit
|
| 615 |
f - floating pointer register
|
| 616 |
i - signed integer, 4, 8, 16 or 32 bit
|
| 617 |
l - length, 4 or 8 bit
|
| 618 |
p - pc relative
|
| 619 |
r - general purpose register
|
| 620 |
u - unsigned integer, 4, 8, 16 or 32 bit
|
| 621 |
m - mode field, 4 bit
|
| 622 |
0 - operand skipped.
|
| 623 |
The order of the letters reflects the layout of the format in
|
| 624 |
storage and not the order of the paramaters of the instructions.
|
| 625 |
The use of the letters is not a 100% match with the PoP but it is
|
| 626 |
quite close.
|
| 627 |
|
| 628 |
For example the instruction "mvo" is defined in the PoP as follows:
|
| 629 |
|
| 630 |
MVO D1(L1,B1),D2(L2,B2) [SS]
|
| 631 |
|
| 632 |
--------------------------------------
|
| 633 |
| 'F1' | L1 | L2 | B1 | D1 | B2 | D2 |
|
| 634 |
--------------------------------------
|
| 635 |
0 8 12 16 20 32 36
|
| 636 |
|
| 637 |
The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */
|
| 638 |
|
| 639 |
#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ |
| 640 |
#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ |
| 641 |
#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ |
| 642 |
#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ |
| 643 |
#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ |
| 644 |
#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ |
| 645 |
#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ |
| 646 |
#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ |
| 647 |
#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ |
| 648 |
#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ |
| 649 |
#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ |
| 650 |
#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ |
| 651 |
#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ |
| 652 |
#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ |
| 653 |
#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ |
| 654 |
#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ |
| 655 |
#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. sqer */ |
| 656 |
#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ |
| 657 |
#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ |
| 658 |
#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ |
| 659 |
#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. cefbr */ |
| 660 |
#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ |
| 661 |
#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ |
| 662 |
/* Actually efpc and sfpc do not take an optional operand.
|
| 663 |
This is just a workaround for existing code e.g. glibc. */
|
| 664 |
#define INSTR_RRE_RR_OPT 4, { R_24,RO_28,0,0,0,0 } /* efpc, sfpc */ |
| 665 |
#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ |
| 666 |
#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ |
| 667 |
#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ |
| 668 |
#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ |
| 669 |
#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ |
| 670 |
#define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ |
| 671 |
#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fixr */ |
| 672 |
#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ |
| 673 |
#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ |
| 674 |
#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ |
| 675 |
#define INSTR_RRF_FFFU 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. qadtr */ |
| 676 |
#define INSTR_RRF_M0RR 4, { R_24,R_28,M_16,0,0,0 } /* e.g. sske */ |
| 677 |
#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ |
| 678 |
#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ |
| 679 |
#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ |
| 680 |
#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ |
| 681 |
#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ |
| 682 |
#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ |
| 683 |
#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ |
| 684 |
#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ |
| 685 |
#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lmh */ |
| 686 |
#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ |
| 687 |
#define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ |
| 688 |
#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ |
| 689 |
#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ |
| 690 |
#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ |
| 691 |
#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
| 692 |
#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. lamy */ |
| 693 |
#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ |
| 694 |
#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ |
| 695 |
#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ |
| 696 |
#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ |
| 697 |
#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ |
| 698 |
#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. axbr */ |
| 699 |
#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ |
| 700 |
#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ |
| 701 |
#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ |
| 702 |
#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ |
| 703 |
#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ |
| 704 |
#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ |
| 705 |
#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ |
| 706 |
#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ |
| 707 |
#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ |
| 708 |
#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ |
| 709 |
#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ |
| 710 |
#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ |
| 711 |
#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ |
| 712 |
#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ |
| 713 |
#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ |
| 714 |
#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ |
| 715 |
#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ |
| 716 |
#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ |
| 717 |
#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ |
| 718 |
#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ |
| 719 |
#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ |
| 720 |
#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ |
| 721 |
|
| 722 |
#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 723 |
#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 724 |
#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 725 |
#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 726 |
#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 727 |
#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 728 |
#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 729 |
#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 730 |
#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 731 |
#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 732 |
#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 733 |
#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 734 |
#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
| 735 |
#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } |
| 736 |
#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 737 |
#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 738 |
#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
| 739 |
#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 740 |
#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } |
| 741 |
#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 742 |
#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 743 |
#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 744 |
#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 745 |
#define MASK_RRE_RR_OPT { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } |
| 746 |
#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 747 |
#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 748 |
#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 749 |
#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 750 |
#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 751 |
#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 752 |
#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 753 |
#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 754 |
#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 755 |
#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } |
| 756 |
#define MASK_RRF_FFFU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 757 |
#define MASK_RRF_M0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 758 |
#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| 759 |
#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 760 |
#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 761 |
#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 762 |
#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 763 |
#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 764 |
#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } |
| 765 |
#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 766 |
#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 767 |
#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 768 |
#define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 769 |
#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 770 |
#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 771 |
#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 772 |
#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 773 |
#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 774 |
#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 775 |
#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 776 |
#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 777 |
#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 778 |
#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 779 |
#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 780 |
#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 781 |
#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 782 |
#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 783 |
#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 784 |
#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 785 |
#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } |
| 786 |
#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 787 |
#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 788 |
#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 789 |
#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 790 |
#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 791 |
#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 792 |
#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 793 |
#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 794 |
#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 795 |
#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 796 |
#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 797 |
#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 798 |
#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } |
| 799 |
#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } |
| 800 |
#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } |
| 801 |
#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } |
| 802 |
|
| 803 |
/* QEMU-ADD: */
|
| 804 |
#define INSTR_RIE_MRRP 6, { M4_32,R_8,R_12,J16_16,0,0 } /* e.g. crj */ |
| 805 |
#define MASK_RIE_MRRP { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } |
| 806 |
|
| 807 |
#define INSTR_RIE_MRIP 6, { M4_12,R_8,I8_32,J16_16,0,0 } /* e.g. cij */ |
| 808 |
#define MASK_RIE_MRIP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } |
| 809 |
/* QEMU-END */
|
| 810 |
|
| 811 |
/* The opcode formats table (blueprints for .insn pseudo mnemonic). */
|
| 812 |
|
| 813 |
static const struct s390_opcode s390_opformats[] = |
| 814 |
{
|
| 815 |
{ "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 },
|
| 816 |
{ "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 },
|
| 817 |
{ "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 },
|
| 818 |
{ "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 },
|
| 819 |
{ "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 },
|
| 820 |
{ "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 },
|
| 821 |
{ "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 },
|
| 822 |
{ "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 },
|
| 823 |
{ "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 },
|
| 824 |
{ "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 },
|
| 825 |
{ "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 },
|
| 826 |
{ "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 },
|
| 827 |
{ "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 },
|
| 828 |
{ "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 },
|
| 829 |
{ "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 },
|
| 830 |
{ "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 },
|
| 831 |
{ "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 },
|
| 832 |
{ "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 },
|
| 833 |
{ "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 },
|
| 834 |
{ "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 },
|
| 835 |
{ "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 },
|
| 836 |
{ "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 },
|
| 837 |
}; |
| 838 |
|
| 839 |
static const int s390_num_opformats = |
| 840 |
sizeof (s390_opformats) / sizeof (s390_opformats[0]); |
| 841 |
|
| 842 |
/* include "s390-opc.tab" generated from opcodes/s390-opc.txt rev 1.17 */
|
| 843 |
/* The opcode table. This file was generated by s390-mkopc.
|
| 844 |
|
| 845 |
The format of the opcode table is:
|
| 846 |
|
| 847 |
NAME OPCODE MASK OPERANDS
|
| 848 |
|
| 849 |
Name is the name of the instruction.
|
| 850 |
OPCODE is the instruction opcode.
|
| 851 |
MASK is the opcode mask; this is used to tell the disassembler
|
| 852 |
which bits in the actual opcode must match OPCODE.
|
| 853 |
OPERANDS is the list of operands.
|
| 854 |
|
| 855 |
The disassembler reads the table in order and prints the first
|
| 856 |
instruction which matches. */
|
| 857 |
|
| 858 |
static const struct s390_opcode s390_opcodes[] = |
| 859 |
{
|
| 860 |
{ "dp", OP8(0xfdLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
|
| 861 |
{ "mp", OP8(0xfcLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
|
| 862 |
{ "sp", OP8(0xfbLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
|
| 863 |
{ "ap", OP8(0xfaLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
|
| 864 |
{ "cp", OP8(0xf9LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
|
| 865 |
{ "zap", OP8(0xf8LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
|
| 866 |
{ "unpk", OP8(0xf3LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
|
| 867 |
{ "pack", OP8(0xf2LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
|
| 868 |
{ "mvo", OP8(0xf1LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0},
|
| 869 |
{ "srp", OP8(0xf0LL), MASK_SS_LIRDRD, INSTR_SS_LIRDRD, 3, 0},
|
| 870 |
{ "lmd", OP8(0xefLL), MASK_SS_RRRDRD3, INSTR_SS_RRRDRD3, 2, 2},
|
| 871 |
{ "plo", OP8(0xeeLL), MASK_SS_RRRDRD2, INSTR_SS_RRRDRD2, 3, 0},
|
| 872 |
{ "stdy", OP48(0xed0000000067LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
|
| 873 |
{ "stey", OP48(0xed0000000066LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
|
| 874 |
{ "ldy", OP48(0xed0000000065LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
|
| 875 |
{ "ley", OP48(0xed0000000064LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3},
|
| 876 |
{ "tgxt", OP48(0xed0000000059LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
|
| 877 |
{ "tcxt", OP48(0xed0000000058LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
|
| 878 |
{ "tgdt", OP48(0xed0000000055LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
|
| 879 |
{ "tcdt", OP48(0xed0000000054LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
|
| 880 |
{ "tget", OP48(0xed0000000051LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
|
| 881 |
{ "tcet", OP48(0xed0000000050LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5},
|
| 882 |
{ "srxt", OP48(0xed0000000049LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
|
| 883 |
{ "slxt", OP48(0xed0000000048LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
|
| 884 |
{ "srdt", OP48(0xed0000000041LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
|
| 885 |
{ "sldt", OP48(0xed0000000040LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5},
|
| 886 |
{ "msd", OP48(0xed000000003fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
|
| 887 |
{ "mad", OP48(0xed000000003eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
|
| 888 |
{ "myh", OP48(0xed000000003dLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
|
| 889 |
{ "mayh", OP48(0xed000000003cLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
|
| 890 |
{ "my", OP48(0xed000000003bLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
|
| 891 |
{ "may", OP48(0xed000000003aLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
|
| 892 |
{ "myl", OP48(0xed0000000039LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
|
| 893 |
{ "mayl", OP48(0xed0000000038LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4},
|
| 894 |
{ "mee", OP48(0xed0000000037LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 895 |
{ "sqe", OP48(0xed0000000034LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 896 |
{ "mse", OP48(0xed000000002fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
|
| 897 |
{ "mae", OP48(0xed000000002eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3},
|
| 898 |
{ "lxe", OP48(0xed0000000026LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 899 |
{ "lxd", OP48(0xed0000000025LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 900 |
{ "lde", OP48(0xed0000000024LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 901 |
{ "msdb", OP48(0xed000000001fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
|
| 902 |
{ "madb", OP48(0xed000000001eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
|
| 903 |
{ "ddb", OP48(0xed000000001dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 904 |
{ "mdb", OP48(0xed000000001cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 905 |
{ "sdb", OP48(0xed000000001bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 906 |
{ "adb", OP48(0xed000000001aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 907 |
{ "cdb", OP48(0xed0000000019LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 908 |
{ "kdb", OP48(0xed0000000018LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 909 |
{ "meeb", OP48(0xed0000000017LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 910 |
{ "sqdb", OP48(0xed0000000015LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 911 |
{ "sqeb", OP48(0xed0000000014LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 912 |
{ "tcxb", OP48(0xed0000000012LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 913 |
{ "tcdb", OP48(0xed0000000011LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 914 |
{ "tceb", OP48(0xed0000000010LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 915 |
{ "mseb", OP48(0xed000000000fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
|
| 916 |
{ "maeb", OP48(0xed000000000eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0},
|
| 917 |
{ "deb", OP48(0xed000000000dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 918 |
{ "mdeb", OP48(0xed000000000cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 919 |
{ "seb", OP48(0xed000000000bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 920 |
{ "aeb", OP48(0xed000000000aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 921 |
{ "ceb", OP48(0xed0000000009LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 922 |
{ "keb", OP48(0xed0000000008LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 923 |
{ "mxdb", OP48(0xed0000000007LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 924 |
{ "lxeb", OP48(0xed0000000006LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 925 |
{ "lxdb", OP48(0xed0000000005LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 926 |
{ "ldeb", OP48(0xed0000000004LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0},
|
| 927 |
{ "brxlg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2},
|
| 928 |
{ "brxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2},
|
| 929 |
{ "tp", OP48(0xeb00000000c0LL), MASK_RSL_R0RD, INSTR_RSL_R0RD, 3, 0},
|
| 930 |
{ "stamy", OP48(0xeb000000009bLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3},
|
| 931 |
{ "lamy", OP48(0xeb000000009aLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3},
|
| 932 |
{ "lmy", OP48(0xeb0000000098LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 933 |
{ "lmh", OP48(0xeb0000000096LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 934 |
{ "lmh", OP48(0xeb0000000096LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 935 |
{ "stmy", OP48(0xeb0000000090LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 936 |
{ "clclu", OP48(0xeb000000008fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 937 |
{ "mvclu", OP48(0xeb000000008eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3},
|
| 938 |
{ "mvclu", OP48(0xeb000000008eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0},
|
| 939 |
{ "icmy", OP48(0xeb0000000081LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
|
| 940 |
{ "icmh", OP48(0xeb0000000080LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
|
| 941 |
{ "icmh", OP48(0xeb0000000080LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
|
| 942 |
{ "xiy", OP48(0xeb0000000057LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
|
| 943 |
{ "oiy", OP48(0xeb0000000056LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
|
| 944 |
{ "cliy", OP48(0xeb0000000055LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
|
| 945 |
{ "niy", OP48(0xeb0000000054LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
|
| 946 |
{ "mviy", OP48(0xeb0000000052LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
|
| 947 |
{ "tmy", OP48(0xeb0000000051LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3},
|
| 948 |
{ "bxleg", OP48(0xeb0000000045LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 949 |
{ "bxleg", OP48(0xeb0000000045LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 950 |
{ "bxhg", OP48(0xeb0000000044LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 951 |
{ "bxhg", OP48(0xeb0000000044LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 952 |
{ "cdsg", OP48(0xeb000000003eLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 953 |
{ "cdsg", OP48(0xeb000000003eLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 954 |
{ "cdsy", OP48(0xeb0000000031LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 955 |
{ "csg", OP48(0xeb0000000030LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 956 |
{ "csg", OP48(0xeb0000000030LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 957 |
{ "lctlg", OP48(0xeb000000002fLL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3},
|
| 958 |
{ "lctlg", OP48(0xeb000000002fLL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2},
|
| 959 |
{ "stcmy", OP48(0xeb000000002dLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
|
| 960 |
{ "stcmh", OP48(0xeb000000002cLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
|
| 961 |
{ "stcmh", OP48(0xeb000000002cLL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
|
| 962 |
{ "stmh", OP48(0xeb0000000026LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 963 |
{ "stmh", OP48(0xeb0000000026LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 964 |
{ "stctg", OP48(0xeb0000000025LL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3},
|
| 965 |
{ "stctg", OP48(0xeb0000000025LL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2},
|
| 966 |
{ "stmg", OP48(0xeb0000000024LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 967 |
{ "stmg", OP48(0xeb0000000024LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 968 |
{ "clmy", OP48(0xeb0000000021LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
|
| 969 |
{ "clmh", OP48(0xeb0000000020LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3},
|
| 970 |
{ "clmh", OP48(0xeb0000000020LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2},
|
| 971 |
{ "rll", OP48(0xeb000000001dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3},
|
| 972 |
{ "rll", OP48(0xeb000000001dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 2},
|
| 973 |
{ "rllg", OP48(0xeb000000001cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 974 |
{ "rllg", OP48(0xeb000000001cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 975 |
{ "csy", OP48(0xeb0000000014LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 976 |
{ "tracg", OP48(0xeb000000000fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 977 |
{ "tracg", OP48(0xeb000000000fLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 978 |
{ "sllg", OP48(0xeb000000000dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 979 |
{ "sllg", OP48(0xeb000000000dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 980 |
{ "srlg", OP48(0xeb000000000cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 981 |
{ "srlg", OP48(0xeb000000000cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 982 |
{ "slag", OP48(0xeb000000000bLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 983 |
{ "slag", OP48(0xeb000000000bLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 984 |
{ "srag", OP48(0xeb000000000aLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 985 |
{ "srag", OP48(0xeb000000000aLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 986 |
{ "lmg", OP48(0xeb0000000004LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3},
|
| 987 |
{ "lmg", OP48(0xeb0000000004LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2},
|
| 988 |
{ "unpka", OP8(0xeaLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 989 |
{ "pka", OP8(0xe9LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0},
|
| 990 |
{ "mvcin", OP8(0xe8LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 991 |
{ "mvcdk", OP16(0xe50fLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
|
| 992 |
{ "mvcsk", OP16(0xe50eLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
|
| 993 |
{ "tprot", OP16(0xe501LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
|
| 994 |
{ "strag", OP48(0xe50000000002LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 2},
|
| 995 |
{ "lasp", OP16(0xe500LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0},
|
| 996 |
{ "slb", OP48(0xe30000000099LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
|
| 997 |
{ "slb", OP48(0xe30000000099LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
|
| 998 |
{ "alc", OP48(0xe30000000098LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
|
| 999 |
{ "alc", OP48(0xe30000000098LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
|
| 1000 |
{ "dl", OP48(0xe30000000097LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
|
| 1001 |
{ "dl", OP48(0xe30000000097LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
|
| 1002 |
{ "ml", OP48(0xe30000000096LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
|
| 1003 |
{ "ml", OP48(0xe30000000096LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
|
| 1004 |
{ "llh", OP48(0xe30000000095LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
|
| 1005 |
{ "llc", OP48(0xe30000000094LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
|
| 1006 |
{ "llgh", OP48(0xe30000000091LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1007 |
{ "llgh", OP48(0xe30000000091LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1008 |
{ "llgc", OP48(0xe30000000090LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1009 |
{ "llgc", OP48(0xe30000000090LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1010 |
{ "lpq", OP48(0xe3000000008fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1011 |
{ "lpq", OP48(0xe3000000008fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1012 |
{ "stpq", OP48(0xe3000000008eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1013 |
{ "stpq", OP48(0xe3000000008eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1014 |
{ "slbg", OP48(0xe30000000089LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1015 |
{ "slbg", OP48(0xe30000000089LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1016 |
{ "alcg", OP48(0xe30000000088LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1017 |
{ "alcg", OP48(0xe30000000088LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1018 |
{ "dlg", OP48(0xe30000000087LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1019 |
{ "dlg", OP48(0xe30000000087LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1020 |
{ "mlg", OP48(0xe30000000086LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1021 |
{ "mlg", OP48(0xe30000000086LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1022 |
{ "xg", OP48(0xe30000000082LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1023 |
{ "xg", OP48(0xe30000000082LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1024 |
{ "og", OP48(0xe30000000081LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1025 |
{ "og", OP48(0xe30000000081LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1026 |
{ "ng", OP48(0xe30000000080LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1027 |
{ "ng", OP48(0xe30000000080LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1028 |
{ "shy", OP48(0xe3000000007bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1029 |
{ "ahy", OP48(0xe3000000007aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1030 |
{ "chy", OP48(0xe30000000079LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1031 |
{ "lhy", OP48(0xe30000000078LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1032 |
{ "lgb", OP48(0xe30000000077LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1033 |
{ "lb", OP48(0xe30000000076LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1034 |
{ "icy", OP48(0xe30000000073LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1035 |
{ "stcy", OP48(0xe30000000072LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1036 |
{ "lay", OP48(0xe30000000071LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1037 |
{ "sthy", OP48(0xe30000000070LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1038 |
{ "sly", OP48(0xe3000000005fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1039 |
{ "aly", OP48(0xe3000000005eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1040 |
{ "sy", OP48(0xe3000000005bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1041 |
{ "ay", OP48(0xe3000000005aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1042 |
{ "cy", OP48(0xe30000000059LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1043 |
{ "ly", OP48(0xe30000000058LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1044 |
{ "xy", OP48(0xe30000000057LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1045 |
{ "oy", OP48(0xe30000000056LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1046 |
{ "cly", OP48(0xe30000000055LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1047 |
{ "ny", OP48(0xe30000000054LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1048 |
{ "msy", OP48(0xe30000000051LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1049 |
{ "sty", OP48(0xe30000000050LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1050 |
{ "bctg", OP48(0xe30000000046LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1051 |
{ "bctg", OP48(0xe30000000046LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1052 |
{ "strvh", OP48(0xe3000000003fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1053 |
{ "strvh", OP48(0xe3000000003fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
|
| 1054 |
{ "strv", OP48(0xe3000000003eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
|
| 1055 |
{ "strv", OP48(0xe3000000003eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
|
| 1056 |
{ "clgf", OP48(0xe30000000031LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1057 |
{ "clgf", OP48(0xe30000000031LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1058 |
{ "cgf", OP48(0xe30000000030LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1059 |
{ "cgf", OP48(0xe30000000030LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1060 |
{ "strvg", OP48(0xe3000000002fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1061 |
{ "strvg", OP48(0xe3000000002fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1062 |
{ "cvdg", OP48(0xe3000000002eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1063 |
{ "cvdg", OP48(0xe3000000002eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1064 |
{ "cvdy", OP48(0xe30000000026LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1065 |
{ "stg", OP48(0xe30000000024LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1066 |
{ "stg", OP48(0xe30000000024LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1067 |
{ "clg", OP48(0xe30000000021LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1068 |
{ "clg", OP48(0xe30000000021LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1069 |
{ "cg", OP48(0xe30000000020LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1070 |
{ "cg", OP48(0xe30000000020LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1071 |
{ "lrvh", OP48(0xe3000000001fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
|
| 1072 |
{ "lrvh", OP48(0xe3000000001fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
|
| 1073 |
{ "lrv", OP48(0xe3000000001eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3},
|
| 1074 |
{ "lrv", OP48(0xe3000000001eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2},
|
| 1075 |
{ "dsgf", OP48(0xe3000000001dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1076 |
{ "dsgf", OP48(0xe3000000001dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1077 |
{ "msgf", OP48(0xe3000000001cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1078 |
{ "msgf", OP48(0xe3000000001cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1079 |
{ "slgf", OP48(0xe3000000001bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1080 |
{ "slgf", OP48(0xe3000000001bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1081 |
{ "algf", OP48(0xe3000000001aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1082 |
{ "algf", OP48(0xe3000000001aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1083 |
{ "sgf", OP48(0xe30000000019LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1084 |
{ "sgf", OP48(0xe30000000019LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1085 |
{ "agf", OP48(0xe30000000018LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1086 |
{ "agf", OP48(0xe30000000018LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1087 |
{ "llgt", OP48(0xe30000000017LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1088 |
{ "llgt", OP48(0xe30000000017LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1089 |
{ "llgf", OP48(0xe30000000016LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1090 |
{ "llgf", OP48(0xe30000000016LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1091 |
{ "lgh", OP48(0xe30000000015LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1092 |
{ "lgh", OP48(0xe30000000015LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1093 |
{ "lgf", OP48(0xe30000000014LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1094 |
{ "lgf", OP48(0xe30000000014LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1095 |
{ "lray", OP48(0xe30000000013LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1096 |
{ "lt", OP48(0xe30000000012LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
|
| 1097 |
{ "lrvg", OP48(0xe3000000000fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1098 |
{ "lrvg", OP48(0xe3000000000fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1099 |
{ "cvbg", OP48(0xe3000000000eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1100 |
{ "cvbg", OP48(0xe3000000000eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1101 |
{ "dsg", OP48(0xe3000000000dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1102 |
{ "dsg", OP48(0xe3000000000dLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1103 |
{ "msg", OP48(0xe3000000000cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1104 |
{ "msg", OP48(0xe3000000000cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1105 |
{ "slg", OP48(0xe3000000000bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1106 |
{ "slg", OP48(0xe3000000000bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1107 |
{ "alg", OP48(0xe3000000000aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1108 |
{ "alg", OP48(0xe3000000000aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1109 |
{ "sg", OP48(0xe30000000009LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1110 |
{ "sg", OP48(0xe30000000009LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1111 |
{ "ag", OP48(0xe30000000008LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1112 |
{ "ag", OP48(0xe30000000008LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1113 |
{ "cvby", OP48(0xe30000000006LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1114 |
{ "lg", OP48(0xe30000000004LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1115 |
{ "lg", OP48(0xe30000000004LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1116 |
{ "lrag", OP48(0xe30000000003LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3},
|
| 1117 |
{ "lrag", OP48(0xe30000000003LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2},
|
| 1118 |
{ "ltg", OP48(0xe30000000002LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4},
|
| 1119 |
{ "unpku", OP8(0xe2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1120 |
{ "pku", OP8(0xe1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1121 |
{ "edmk", OP8(0xdfLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1122 |
{ "ed", OP8(0xdeLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1123 |
{ "trt", OP8(0xddLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1124 |
{ "tr", OP8(0xdcLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1125 |
{ "mvcs", OP8(0xdbLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
|
| 1126 |
{ "mvcp", OP8(0xdaLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
|
| 1127 |
{ "mvck", OP8(0xd9LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0},
|
| 1128 |
{ "xc", OP8(0xd7LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1129 |
{ "oc", OP8(0xd6LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1130 |
{ "clc", OP8(0xd5LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1131 |
{ "nc", OP8(0xd4LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1132 |
{ "mvz", OP8(0xd3LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1133 |
{ "mvc", OP8(0xd2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1134 |
{ "mvn", OP8(0xd1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0},
|
| 1135 |
{ "csst", OP16(0xc802LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5},
|
| 1136 |
{ "ectg", OP16(0xc801LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5},
|
| 1137 |
{ "mvcos", OP16(0xc800LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 4},
|
| 1138 |
{ "clfi", OP16(0xc20fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1139 |
{ "clgfi", OP16(0xc20eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1140 |
{ "cfi", OP16(0xc20dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
|
| 1141 |
{ "cgfi", OP16(0xc20cLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
|
| 1142 |
{ "alfi", OP16(0xc20bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1143 |
{ "algfi", OP16(0xc20aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1144 |
{ "afi", OP16(0xc209LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
|
| 1145 |
{ "agfi", OP16(0xc208LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
|
| 1146 |
{ "slfi", OP16(0xc205LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1147 |
{ "slgfi", OP16(0xc204LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1148 |
/* QEMU-ADD: */
|
| 1149 |
{ "msfi", OP16(0xc201ll), MASK_RIL_RI, INSTR_RIL_RI, 3, 6},
|
| 1150 |
{ "msgfi", OP16(0xc200ll), MASK_RIL_RI, INSTR_RIL_RI, 3, 6},
|
| 1151 |
/* QEMU-END */
|
| 1152 |
{ "jg", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1153 |
{ "jgno", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1154 |
{ "jgnh", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1155 |
{ "jgnp", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1156 |
{ "jgle", OP16(0xc0c4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1157 |
{ "jgnl", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1158 |
{ "jgnm", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1159 |
{ "jghe", OP16(0xc0a4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1160 |
{ "jgnlh", OP16(0xc094LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1161 |
{ "jge", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1162 |
{ "jgz", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1163 |
{ "jgne", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1164 |
{ "jgnz", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1165 |
{ "jglh", OP16(0xc064LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1166 |
{ "jgnhe", OP16(0xc054LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1167 |
{ "jgl", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1168 |
{ "jgm", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1169 |
{ "jgnle", OP16(0xc034LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1170 |
{ "jgh", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1171 |
{ "jgp", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1172 |
{ "jgo", OP16(0xc014LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2},
|
| 1173 |
{ "llilf", OP16(0xc00fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1174 |
{ "llihf", OP16(0xc00eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1175 |
{ "oilf", OP16(0xc00dLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1176 |
{ "oihf", OP16(0xc00cLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1177 |
{ "nilf", OP16(0xc00bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1178 |
{ "nihf", OP16(0xc00aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1179 |
{ "iilf", OP16(0xc009LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1180 |
{ "iihf", OP16(0xc008LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1181 |
{ "xilf", OP16(0xc007LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1182 |
{ "xihf", OP16(0xc006LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4},
|
| 1183 |
{ "brasl", OP16(0xc005LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2},
|
| 1184 |
{ "brcl", OP16(0xc004LL), MASK_RIL_UP, INSTR_RIL_UP, 3, 2},
|
| 1185 |
{ "lgfi", OP16(0xc001LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4},
|
| 1186 |
{ "larl", OP16(0xc000LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2},
|
| 1187 |
{ "icm", OP8(0xbfLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
|
| 1188 |
{ "stcm", OP8(0xbeLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
|
| 1189 |
{ "clm", OP8(0xbdLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0},
|
| 1190 |
{ "cds", OP8(0xbbLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1191 |
{ "cs", OP8(0xbaLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1192 |
{ "cu42", OP16(0xb9b3LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
|
| 1193 |
{ "cu41", OP16(0xb9b2LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
|
| 1194 |
{ "cu24", OP16(0xb9b1LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
|
| 1195 |
{ "cu14", OP16(0xb9b0LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
|
| 1196 |
{ "lptea", OP16(0xb9aaLL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 4},
|
| 1197 |
{ "esea", OP16(0xb99dLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 2},
|
| 1198 |
{ "slbr", OP16(0xb999LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
|
| 1199 |
{ "alcr", OP16(0xb998LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
|
| 1200 |
{ "dlr", OP16(0xb997LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
|
| 1201 |
{ "mlr", OP16(0xb996LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
|
| 1202 |
{ "llhr", OP16(0xb995LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
|
| 1203 |
{ "llcr", OP16(0xb994LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
|
| 1204 |
{ "troo", OP16(0xb993LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
|
| 1205 |
{ "troo", OP16(0xb993LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1206 |
{ "trot", OP16(0xb992LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
|
| 1207 |
{ "trot", OP16(0xb992LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1208 |
{ "trto", OP16(0xb991LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
|
| 1209 |
{ "trto", OP16(0xb991LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1210 |
{ "trtt", OP16(0xb990LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 3, 4},
|
| 1211 |
{ "trtt", OP16(0xb990LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1212 |
{ "idte", OP16(0xb98eLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 2, 3},
|
| 1213 |
{ "epsw", OP16(0xb98dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
|
| 1214 |
{ "cspg", OP16(0xb98aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 3},
|
| 1215 |
{ "slbgr", OP16(0xb989LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1216 |
{ "alcgr", OP16(0xb988LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1217 |
{ "dlgr", OP16(0xb987LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1218 |
{ "mlgr", OP16(0xb986LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1219 |
{ "llghr", OP16(0xb985LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
|
| 1220 |
{ "llgcr", OP16(0xb984LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
|
| 1221 |
{ "flogr", OP16(0xb983LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
|
| 1222 |
{ "xgr", OP16(0xb982LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1223 |
{ "ogr", OP16(0xb981LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1224 |
{ "ngr", OP16(0xb980LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1225 |
{ "bctgr", OP16(0xb946LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1226 |
{ "klmd", OP16(0xb93fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
|
| 1227 |
{ "kimd", OP16(0xb93eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
|
| 1228 |
{ "clgfr", OP16(0xb931LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1229 |
{ "cgfr", OP16(0xb930LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1230 |
{ "kmc", OP16(0xb92fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
|
| 1231 |
{ "km", OP16(0xb92eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
|
| 1232 |
{ "lhr", OP16(0xb927LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
|
| 1233 |
{ "lbr", OP16(0xb926LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
|
| 1234 |
{ "sturg", OP16(0xb925LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1235 |
{ "clgr", OP16(0xb921LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1236 |
{ "cgr", OP16(0xb920LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1237 |
{ "lrvr", OP16(0xb91fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2},
|
| 1238 |
{ "kmac", OP16(0xb91eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3},
|
| 1239 |
{ "dsgfr", OP16(0xb91dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1240 |
{ "msgfr", OP16(0xb91cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1241 |
{ "slgfr", OP16(0xb91bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1242 |
{ "algfr", OP16(0xb91aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1243 |
{ "sgfr", OP16(0xb919LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1244 |
{ "agfr", OP16(0xb918LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1245 |
{ "llgtr", OP16(0xb917LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1246 |
{ "llgfr", OP16(0xb916LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1247 |
{ "lgfr", OP16(0xb914LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1248 |
{ "lcgfr", OP16(0xb913LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1249 |
{ "ltgfr", OP16(0xb912LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1250 |
{ "lngfr", OP16(0xb911LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1251 |
{ "lpgfr", OP16(0xb910LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1252 |
{ "lrvgr", OP16(0xb90fLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1253 |
{ "eregg", OP16(0xb90eLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1254 |
{ "dsgr", OP16(0xb90dLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1255 |
{ "msgr", OP16(0xb90cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1256 |
{ "slgr", OP16(0xb90bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1257 |
{ "algr", OP16(0xb90aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1258 |
{ "sgr", OP16(0xb909LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1259 |
{ "agr", OP16(0xb908LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1260 |
{ "lghr", OP16(0xb907LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
|
| 1261 |
{ "lgbr", OP16(0xb906LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4},
|
| 1262 |
{ "lurag", OP16(0xb905LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1263 |
{ "lgr", OP16(0xb904LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1264 |
{ "lcgr", OP16(0xb903LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1265 |
{ "ltgr", OP16(0xb902LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1266 |
{ "lngr", OP16(0xb901LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1267 |
{ "lpgr", OP16(0xb900LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1268 |
{ "lctl", OP8(0xb7LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0},
|
| 1269 |
{ "stctl", OP8(0xb6LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0},
|
| 1270 |
{ "rrxtr", OP16(0xb3ffLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
|
| 1271 |
{ "iextr", OP16(0xb3feLL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5},
|
| 1272 |
{ "qaxtr", OP16(0xb3fdLL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
|
| 1273 |
{ "cextr", OP16(0xb3fcLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1274 |
{ "cxstr", OP16(0xb3fbLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
|
| 1275 |
{ "cxutr", OP16(0xb3faLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
|
| 1276 |
{ "cxgtr", OP16(0xb3f9LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
|
| 1277 |
{ "rrdtr", OP16(0xb3f7LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
|
| 1278 |
{ "iedtr", OP16(0xb3f6LL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5},
|
| 1279 |
{ "qadtr", OP16(0xb3f5LL), MASK_RRF_FFFU, INSTR_RRF_FFFU, 2, 5},
|
| 1280 |
{ "cedtr", OP16(0xb3f4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1281 |
{ "cdstr", OP16(0xb3f3LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
|
| 1282 |
{ "cdutr", OP16(0xb3f2LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
|
| 1283 |
{ "cdgtr", OP16(0xb3f1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
|
| 1284 |
{ "esxtr", OP16(0xb3efLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
|
| 1285 |
{ "eextr", OP16(0xb3edLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
|
| 1286 |
{ "cxtr", OP16(0xb3ecLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1287 |
{ "csxtr", OP16(0xb3ebLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
|
| 1288 |
{ "cuxtr", OP16(0xb3eaLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
|
| 1289 |
{ "cgxtr", OP16(0xb3e9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5},
|
| 1290 |
{ "kxtr", OP16(0xb3e8LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1291 |
{ "esdtr", OP16(0xb3e7LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
|
| 1292 |
{ "eedtr", OP16(0xb3e5LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
|
| 1293 |
{ "cdtr", OP16(0xb3e4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1294 |
{ "csdtr", OP16(0xb3e3LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
|
| 1295 |
{ "cudtr", OP16(0xb3e2LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
|
| 1296 |
{ "cgdtr", OP16(0xb3e1LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5},
|
| 1297 |
{ "kdtr", OP16(0xb3e0LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1298 |
{ "fixtr", OP16(0xb3dfLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
|
| 1299 |
{ "ltxtr", OP16(0xb3deLL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1300 |
{ "ldxtr", OP16(0xb3ddLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
|
| 1301 |
{ "lxdtr", OP16(0xb3dcLL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5},
|
| 1302 |
{ "sxtr", OP16(0xb3dbLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
|
| 1303 |
{ "axtr", OP16(0xb3daLL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
|
| 1304 |
{ "dxtr", OP16(0xb3d9LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
|
| 1305 |
{ "mxtr", OP16(0xb3d8LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
|
| 1306 |
{ "fidtr", OP16(0xb3d7LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
|
| 1307 |
{ "ltdtr", OP16(0xb3d6LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1308 |
{ "ledtr", OP16(0xb3d5LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5},
|
| 1309 |
{ "ldetr", OP16(0xb3d4LL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5},
|
| 1310 |
{ "sdtr", OP16(0xb3d3LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
|
| 1311 |
{ "adtr", OP16(0xb3d2LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
|
| 1312 |
{ "ddtr", OP16(0xb3d1LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
|
| 1313 |
{ "mdtr", OP16(0xb3d0LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5},
|
| 1314 |
{ "lgdr", OP16(0xb3cdLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5},
|
| 1315 |
{ "cgxr", OP16(0xb3caLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
|
| 1316 |
{ "cgdr", OP16(0xb3c9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
|
| 1317 |
{ "cger", OP16(0xb3c8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
|
| 1318 |
{ "cxgr", OP16(0xb3c6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1319 |
{ "cdgr", OP16(0xb3c5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1320 |
{ "cegr", OP16(0xb3c4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1321 |
{ "ldgr", OP16(0xb3c1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5},
|
| 1322 |
{ "cfxr", OP16(0xb3baLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
|
| 1323 |
{ "cfdr", OP16(0xb3b9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
|
| 1324 |
{ "cfer", OP16(0xb3b8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
|
| 1325 |
{ "cxfr", OP16(0xb3b6LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
|
| 1326 |
{ "cdfr", OP16(0xb3b5LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
|
| 1327 |
{ "cefr", OP16(0xb3b4LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
|
| 1328 |
{ "cgxbr", OP16(0xb3aaLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
|
| 1329 |
{ "cgdbr", OP16(0xb3a9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
|
| 1330 |
{ "cgebr", OP16(0xb3a8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2},
|
| 1331 |
{ "cxgbr", OP16(0xb3a6LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1332 |
{ "cdgbr", OP16(0xb3a5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1333 |
{ "cegbr", OP16(0xb3a4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2},
|
| 1334 |
{ "cfxbr", OP16(0xb39aLL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
|
| 1335 |
{ "cfdbr", OP16(0xb399LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
|
| 1336 |
{ "cfebr", OP16(0xb398LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0},
|
| 1337 |
{ "cxfbr", OP16(0xb396LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
|
| 1338 |
{ "cdfbr", OP16(0xb395LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
|
| 1339 |
{ "cefbr", OP16(0xb394LL), MASK_RRE_RF, INSTR_RRE_RF, 3, 0},
|
| 1340 |
{ "efpc", OP16(0xb38cLL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0},
|
| 1341 |
{ "sfasr", OP16(0xb385LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 5},
|
| 1342 |
{ "sfpc", OP16(0xb384LL), MASK_RRE_RR_OPT, INSTR_RRE_RR_OPT, 3, 0},
|
| 1343 |
{ "fidr", OP16(0xb37fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
|
| 1344 |
{ "fier", OP16(0xb377LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
|
| 1345 |
{ "lzxr", OP16(0xb376LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
|
| 1346 |
{ "lzdr", OP16(0xb375LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
|
| 1347 |
{ "lzer", OP16(0xb374LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
|
| 1348 |
{ "lcdfr", OP16(0xb373LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1349 |
{ "cpsdr", OP16(0xb372LL), MASK_RRF_F0FF2, INSTR_RRF_F0FF2, 2, 5},
|
| 1350 |
{ "lndfr", OP16(0xb371LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1351 |
{ "lpdfr", OP16(0xb370LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5},
|
| 1352 |
{ "cxr", OP16(0xb369LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1353 |
{ "fixr", OP16(0xb367LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
|
| 1354 |
{ "lexr", OP16(0xb366LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1355 |
{ "lxr", OP16(0xb365LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1356 |
{ "lcxr", OP16(0xb363LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1357 |
{ "ltxr", OP16(0xb362LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1358 |
{ "lnxr", OP16(0xb361LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1359 |
{ "lpxr", OP16(0xb360LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1360 |
{ "fidbr", OP16(0xb35fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
|
| 1361 |
{ "didbr", OP16(0xb35bLL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0},
|
| 1362 |
{ "thdr", OP16(0xb359LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1363 |
{ "thder", OP16(0xb358LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1364 |
{ "fiebr", OP16(0xb357LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
|
| 1365 |
{ "diebr", OP16(0xb353LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0},
|
| 1366 |
{ "tbdr", OP16(0xb351LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
|
| 1367 |
{ "tbedr", OP16(0xb350LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
|
| 1368 |
{ "dxbr", OP16(0xb34dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1369 |
{ "mxbr", OP16(0xb34cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1370 |
{ "sxbr", OP16(0xb34bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1371 |
{ "axbr", OP16(0xb34aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1372 |
{ "cxbr", OP16(0xb349LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1373 |
{ "kxbr", OP16(0xb348LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1374 |
{ "fixbr", OP16(0xb347LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0},
|
| 1375 |
{ "lexbr", OP16(0xb346LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1376 |
{ "ldxbr", OP16(0xb345LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1377 |
{ "ledbr", OP16(0xb344LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1378 |
{ "lcxbr", OP16(0xb343LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1379 |
{ "ltxbr", OP16(0xb342LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1380 |
{ "lnxbr", OP16(0xb341LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1381 |
{ "lpxbr", OP16(0xb340LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1382 |
{ "msdr", OP16(0xb33fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
|
| 1383 |
{ "madr", OP16(0xb33eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
|
| 1384 |
{ "myhr", OP16(0xb33dLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
|
| 1385 |
{ "mayhr", OP16(0xb33cLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
|
| 1386 |
{ "myr", OP16(0xb33bLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
|
| 1387 |
{ "mayr", OP16(0xb33aLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
|
| 1388 |
{ "mylr", OP16(0xb339LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
|
| 1389 |
{ "maylr", OP16(0xb338LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4},
|
| 1390 |
{ "meer", OP16(0xb337LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1391 |
{ "sqxr", OP16(0xb336LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1392 |
{ "mser", OP16(0xb32fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
|
| 1393 |
{ "maer", OP16(0xb32eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3},
|
| 1394 |
{ "lxer", OP16(0xb326LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1395 |
{ "lxdr", OP16(0xb325LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1396 |
{ "lder", OP16(0xb324LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1397 |
{ "msdbr", OP16(0xb31fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
|
| 1398 |
{ "madbr", OP16(0xb31eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
|
| 1399 |
{ "ddbr", OP16(0xb31dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1400 |
{ "mdbr", OP16(0xb31cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1401 |
{ "sdbr", OP16(0xb31bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1402 |
{ "adbr", OP16(0xb31aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1403 |
{ "cdbr", OP16(0xb319LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1404 |
{ "kdbr", OP16(0xb318LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1405 |
{ "meebr", OP16(0xb317LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1406 |
{ "sqxbr", OP16(0xb316LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1407 |
{ "sqdbr", OP16(0xb315LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1408 |
{ "sqebr", OP16(0xb314LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1409 |
{ "lcdbr", OP16(0xb313LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1410 |
{ "ltdbr", OP16(0xb312LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1411 |
{ "lndbr", OP16(0xb311LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1412 |
{ "lpdbr", OP16(0xb310LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1413 |
{ "msebr", OP16(0xb30fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
|
| 1414 |
{ "maebr", OP16(0xb30eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0},
|
| 1415 |
{ "debr", OP16(0xb30dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1416 |
{ "mdebr", OP16(0xb30cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1417 |
{ "sebr", OP16(0xb30bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1418 |
{ "aebr", OP16(0xb30aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1419 |
{ "cebr", OP16(0xb309LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1420 |
{ "kebr", OP16(0xb308LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1421 |
{ "mxdbr", OP16(0xb307LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1422 |
{ "lxebr", OP16(0xb306LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1423 |
{ "lxdbr", OP16(0xb305LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1424 |
{ "ldebr", OP16(0xb304LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1425 |
{ "lcebr", OP16(0xb303LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1426 |
{ "ltebr", OP16(0xb302LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1427 |
{ "lnebr", OP16(0xb301LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1428 |
{ "lpebr", OP16(0xb300LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0},
|
| 1429 |
{ "trap4", OP16(0xb2ffLL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1430 |
{ "lfas", OP16(0xb2bdLL), MASK_S_RD, INSTR_S_RD, 2, 5},
|
| 1431 |
{ "srnmt", OP16(0xb2b9LL), MASK_S_RD, INSTR_S_RD, 2, 5},
|
| 1432 |
{ "lpswe", OP16(0xb2b2LL), MASK_S_RD, INSTR_S_RD, 2, 2},
|
| 1433 |
{ "stfl", OP16(0xb2b1LL), MASK_S_RD, INSTR_S_RD, 3, 2},
|
| 1434 |
{ "stfle", OP16(0xb2b0LL), MASK_S_RD, INSTR_S_RD, 2, 4},
|
| 1435 |
{ "cu12", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
|
| 1436 |
{ "cutfu", OP16(0xb2a7LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
|
| 1437 |
{ "cutfu", OP16(0xb2a7LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1438 |
{ "cu21", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
|
| 1439 |
{ "cuutf", OP16(0xb2a6LL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
|
| 1440 |
{ "cuutf", OP16(0xb2a6LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1441 |
{ "tre", OP16(0xb2a5LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1442 |
{ "lfpc", OP16(0xb29dLL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1443 |
{ "stfpc", OP16(0xb29cLL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1444 |
{ "srnm", OP16(0xb299LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1445 |
{ "stsi", OP16(0xb27dLL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1446 |
{ "stckf", OP16(0xb27cLL), MASK_S_RD, INSTR_S_RD, 2, 4},
|
| 1447 |
{ "sacf", OP16(0xb279LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1448 |
{ "stcke", OP16(0xb278LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1449 |
{ "rp", OP16(0xb277LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1450 |
{ "xsch", OP16(0xb276LL), MASK_S_00, INSTR_S_00, 3, 0},
|
| 1451 |
{ "siga", OP16(0xb274LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1452 |
{ "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1453 |
{ "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1454 |
{ "srst", OP16(0xb25eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1455 |
{ "clst", OP16(0xb25dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1456 |
{ "bsa", OP16(0xb25aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1457 |
{ "bsg", OP16(0xb258LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1458 |
{ "cuse", OP16(0xb257LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1459 |
{ "mvst", OP16(0xb255LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1460 |
{ "mvpg", OP16(0xb254LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1461 |
{ "msr", OP16(0xb252LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1462 |
{ "csp", OP16(0xb250LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1463 |
{ "ear", OP16(0xb24fLL), MASK_RRE_RA, INSTR_RRE_RA, 3, 0},
|
| 1464 |
{ "sar", OP16(0xb24eLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0},
|
| 1465 |
{ "cpya", OP16(0xb24dLL), MASK_RRE_AA, INSTR_RRE_AA, 3, 0},
|
| 1466 |
{ "tar", OP16(0xb24cLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0},
|
| 1467 |
{ "lura", OP16(0xb24bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1468 |
{ "esta", OP16(0xb24aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1469 |
{ "ereg", OP16(0xb249LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1470 |
{ "palb", OP16(0xb248LL), MASK_RRE_00, INSTR_RRE_00, 3, 0},
|
| 1471 |
{ "msta", OP16(0xb247LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
|
| 1472 |
{ "stura", OP16(0xb246LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1473 |
{ "sqer", OP16(0xb245LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
|
| 1474 |
{ "sqdr", OP16(0xb244LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
|
| 1475 |
{ "cksm", OP16(0xb241LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1476 |
{ "bakr", OP16(0xb240LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1477 |
{ "schm", OP16(0xb23cLL), MASK_S_00, INSTR_S_00, 3, 0},
|
| 1478 |
{ "rchp", OP16(0xb23bLL), MASK_S_00, INSTR_S_00, 3, 0},
|
| 1479 |
{ "stcps", OP16(0xb23aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1480 |
{ "stcrw", OP16(0xb239LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1481 |
{ "rsch", OP16(0xb238LL), MASK_S_00, INSTR_S_00, 3, 0},
|
| 1482 |
{ "sal", OP16(0xb237LL), MASK_S_00, INSTR_S_00, 3, 0},
|
| 1483 |
{ "tpi", OP16(0xb236LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1484 |
{ "tsch", OP16(0xb235LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1485 |
{ "stsch", OP16(0xb234LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1486 |
{ "ssch", OP16(0xb233LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1487 |
{ "msch", OP16(0xb232LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1488 |
{ "hsch", OP16(0xb231LL), MASK_S_00, INSTR_S_00, 3, 0},
|
| 1489 |
{ "csch", OP16(0xb230LL), MASK_S_00, INSTR_S_00, 3, 0},
|
| 1490 |
{ "pgout", OP16(0xb22fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1491 |
{ "pgin", OP16(0xb22eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1492 |
{ "dxr", OP16(0xb22dLL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0},
|
| 1493 |
{ "tb", OP16(0xb22cLL), MASK_RRE_0R, INSTR_RRE_0R, 3, 0},
|
| 1494 |
{ "sske", OP16(0xb22bLL), MASK_RRF_M0RR, INSTR_RRF_M0RR, 2, 4},
|
| 1495 |
{ "sske", OP16(0xb22bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1496 |
{ "rrbe", OP16(0xb22aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1497 |
{ "iske", OP16(0xb229LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1498 |
{ "pt", OP16(0xb228LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1499 |
{ "esar", OP16(0xb227LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
|
| 1500 |
{ "epar", OP16(0xb226LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
|
| 1501 |
{ "ssar", OP16(0xb225LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
|
| 1502 |
{ "iac", OP16(0xb224LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
|
| 1503 |
{ "ivsk", OP16(0xb223LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1504 |
{ "ipm", OP16(0xb222LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0},
|
| 1505 |
{ "ipte", OP16(0xb221LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0},
|
| 1506 |
{ "cfc", OP16(0xb21aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1507 |
{ "sac", OP16(0xb219LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1508 |
{ "pc", OP16(0xb218LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1509 |
{ "sie", OP16(0xb214LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1510 |
{ "stap", OP16(0xb212LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1511 |
{ "stpx", OP16(0xb211LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1512 |
{ "spx", OP16(0xb210LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1513 |
{ "ptlb", OP16(0xb20dLL), MASK_S_00, INSTR_S_00, 3, 0},
|
| 1514 |
{ "ipk", OP16(0xb20bLL), MASK_S_00, INSTR_S_00, 3, 0},
|
| 1515 |
{ "spka", OP16(0xb20aLL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1516 |
{ "stpt", OP16(0xb209LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1517 |
{ "spt", OP16(0xb208LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1518 |
{ "stckc", OP16(0xb207LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1519 |
{ "sckc", OP16(0xb206LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1520 |
{ "stck", OP16(0xb205LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1521 |
{ "sck", OP16(0xb204LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1522 |
{ "stidp", OP16(0xb202LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1523 |
{ "lra", OP8(0xb1LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1524 |
{ "mc", OP8(0xafLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
|
| 1525 |
{ "sigp", OP8(0xaeLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1526 |
{ "stosm", OP8(0xadLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
|
| 1527 |
{ "stnsm", OP8(0xacLL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
|
| 1528 |
{ "clcle", OP8(0xa9LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1529 |
{ "mvcle", OP8(0xa8LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1530 |
{ "j", OP16(0xa7f4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1531 |
{ "jno", OP16(0xa7e4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1532 |
{ "jnh", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1533 |
{ "jnp", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1534 |
{ "jle", OP16(0xa7c4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1535 |
{ "jnl", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1536 |
{ "jnm", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1537 |
{ "jhe", OP16(0xa7a4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1538 |
{ "jnlh", OP16(0xa794LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1539 |
{ "je", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1540 |
{ "jz", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1541 |
{ "jne", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1542 |
{ "jnz", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1543 |
{ "jlh", OP16(0xa764LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1544 |
{ "jnhe", OP16(0xa754LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1545 |
{ "jl", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1546 |
{ "jm", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1547 |
{ "jnle", OP16(0xa734LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1548 |
{ "jh", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1549 |
{ "jp", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1550 |
{ "jo", OP16(0xa714LL), MASK_RI_0P, INSTR_RI_0P, 3, 0},
|
| 1551 |
{ "cghi", OP16(0xa70fLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
|
| 1552 |
{ "chi", OP16(0xa70eLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
|
| 1553 |
{ "mghi", OP16(0xa70dLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
|
| 1554 |
{ "mhi", OP16(0xa70cLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
|
| 1555 |
{ "aghi", OP16(0xa70bLL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
|
| 1556 |
{ "ahi", OP16(0xa70aLL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
|
| 1557 |
{ "lghi", OP16(0xa709LL), MASK_RI_RI, INSTR_RI_RI, 2, 2},
|
| 1558 |
{ "lhi", OP16(0xa708LL), MASK_RI_RI, INSTR_RI_RI, 3, 0},
|
| 1559 |
{ "brctg", OP16(0xa707LL), MASK_RI_RP, INSTR_RI_RP, 2, 2},
|
| 1560 |
{ "brct", OP16(0xa706LL), MASK_RI_RP, INSTR_RI_RP, 3, 0},
|
| 1561 |
{ "bras", OP16(0xa705LL), MASK_RI_RP, INSTR_RI_RP, 3, 0},
|
| 1562 |
{ "brc", OP16(0xa704LL), MASK_RI_UP, INSTR_RI_UP, 3, 0},
|
| 1563 |
{ "tmhl", OP16(0xa703LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1564 |
{ "tmhh", OP16(0xa702LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1565 |
{ "tml", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
|
| 1566 |
{ "tmll", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
|
| 1567 |
{ "tmh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
|
| 1568 |
{ "tmlh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0},
|
| 1569 |
{ "llill", OP16(0xa50fLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1570 |
{ "llilh", OP16(0xa50eLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1571 |
{ "llihl", OP16(0xa50dLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1572 |
{ "llihh", OP16(0xa50cLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1573 |
{ "oill", OP16(0xa50bLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1574 |
{ "oilh", OP16(0xa50aLL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1575 |
{ "oihl", OP16(0xa509LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1576 |
{ "oihh", OP16(0xa508LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1577 |
{ "nill", OP16(0xa507LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1578 |
{ "nilh", OP16(0xa506LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1579 |
{ "nihl", OP16(0xa505LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1580 |
{ "nihh", OP16(0xa504LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1581 |
{ "iill", OP16(0xa503LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1582 |
{ "iilh", OP16(0xa502LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1583 |
{ "iihl", OP16(0xa501LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1584 |
{ "iihh", OP16(0xa500LL), MASK_RI_RU, INSTR_RI_RU, 2, 2},
|
| 1585 |
{ "stam", OP8(0x9bLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0},
|
| 1586 |
{ "lam", OP8(0x9aLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0},
|
| 1587 |
{ "trace", OP8(0x99LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1588 |
{ "lm", OP8(0x98LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1589 |
{ "xi", OP8(0x97LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
|
| 1590 |
{ "oi", OP8(0x96LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
|
| 1591 |
{ "cli", OP8(0x95LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
|
| 1592 |
{ "ni", OP8(0x94LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
|
| 1593 |
{ "ts", OP8(0x93LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1594 |
{ "mvi", OP8(0x92LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
|
| 1595 |
{ "tm", OP8(0x91LL), MASK_SI_URD, INSTR_SI_URD, 3, 0},
|
| 1596 |
{ "stm", OP8(0x90LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1597 |
{ "slda", OP8(0x8fLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
|
| 1598 |
{ "srda", OP8(0x8eLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
|
| 1599 |
{ "sldl", OP8(0x8dLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
|
| 1600 |
{ "srdl", OP8(0x8cLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
|
| 1601 |
{ "sla", OP8(0x8bLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
|
| 1602 |
{ "sra", OP8(0x8aLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
|
| 1603 |
{ "sll", OP8(0x89LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
|
| 1604 |
{ "srl", OP8(0x88LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0},
|
| 1605 |
{ "bxle", OP8(0x87LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1606 |
{ "bxh", OP8(0x86LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1607 |
{ "brxle", OP8(0x85LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0},
|
| 1608 |
{ "brxh", OP8(0x84LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0},
|
| 1609 |
{ "diag", OP8(0x83LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0},
|
| 1610 |
{ "lpsw", OP8(0x82LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1611 |
{ "ssm", OP8(0x80LL), MASK_S_RD, INSTR_S_RD, 3, 0},
|
| 1612 |
{ "su", OP8(0x7fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1613 |
{ "au", OP8(0x7eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1614 |
{ "de", OP8(0x7dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1615 |
{ "me", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1616 |
{ "mde", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1617 |
{ "se", OP8(0x7bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1618 |
{ "ae", OP8(0x7aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1619 |
{ "ce", OP8(0x79LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1620 |
{ "le", OP8(0x78LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1621 |
{ "ms", OP8(0x71LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1622 |
{ "ste", OP8(0x70LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1623 |
{ "sw", OP8(0x6fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1624 |
{ "aw", OP8(0x6eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1625 |
{ "dd", OP8(0x6dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1626 |
{ "md", OP8(0x6cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1627 |
{ "sd", OP8(0x6bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1628 |
{ "ad", OP8(0x6aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1629 |
{ "cd", OP8(0x69LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1630 |
{ "ld", OP8(0x68LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1631 |
{ "mxd", OP8(0x67LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1632 |
{ "std", OP8(0x60LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0},
|
| 1633 |
{ "sl", OP8(0x5fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1634 |
{ "al", OP8(0x5eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1635 |
{ "d", OP8(0x5dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1636 |
{ "m", OP8(0x5cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1637 |
{ "s", OP8(0x5bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1638 |
{ "a", OP8(0x5aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1639 |
{ "c", OP8(0x59LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1640 |
{ "l", OP8(0x58LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1641 |
{ "x", OP8(0x57LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1642 |
{ "o", OP8(0x56LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1643 |
{ "cl", OP8(0x55LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1644 |
{ "n", OP8(0x54LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1645 |
{ "lae", OP8(0x51LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1646 |
{ "st", OP8(0x50LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1647 |
{ "cvb", OP8(0x4fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1648 |
{ "cvd", OP8(0x4eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1649 |
{ "bas", OP8(0x4dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1650 |
{ "mh", OP8(0x4cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1651 |
{ "sh", OP8(0x4bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1652 |
{ "ah", OP8(0x4aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1653 |
{ "ch", OP8(0x49LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1654 |
{ "lh", OP8(0x48LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1655 |
{ "b", OP16(0x47f0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1656 |
{ "bno", OP16(0x47e0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1657 |
{ "bnh", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1658 |
{ "bnp", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1659 |
{ "ble", OP16(0x47c0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1660 |
{ "bnl", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1661 |
{ "bnm", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1662 |
{ "bhe", OP16(0x47a0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1663 |
{ "bnlh", OP16(0x4790LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1664 |
{ "be", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1665 |
{ "bz", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1666 |
{ "bne", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1667 |
{ "bnz", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1668 |
{ "blh", OP16(0x4760LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1669 |
{ "bnhe", OP16(0x4750LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1670 |
{ "bl", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1671 |
{ "bm", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1672 |
{ "bnle", OP16(0x4730LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1673 |
{ "bh", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1674 |
{ "bp", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1675 |
{ "bo", OP16(0x4710LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1676 |
{ "bc", OP8(0x47LL), MASK_RX_URRD, INSTR_RX_URRD, 3, 0},
|
| 1677 |
{ "nop", OP16(0x4700LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0},
|
| 1678 |
{ "bct", OP8(0x46LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1679 |
{ "bal", OP8(0x45LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1680 |
{ "ex", OP8(0x44LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1681 |
{ "ic", OP8(0x43LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1682 |
{ "stc", OP8(0x42LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1683 |
{ "la", OP8(0x41LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1684 |
{ "sth", OP8(0x40LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0},
|
| 1685 |
{ "sur", OP8(0x3fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1686 |
{ "aur", OP8(0x3eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1687 |
{ "der", OP8(0x3dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1688 |
{ "mer", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1689 |
{ "mder", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1690 |
{ "ser", OP8(0x3bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1691 |
{ "aer", OP8(0x3aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1692 |
{ "cer", OP8(0x39LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1693 |
{ "ler", OP8(0x38LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1694 |
{ "sxr", OP8(0x37LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1695 |
{ "axr", OP8(0x36LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1696 |
{ "lrer", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1697 |
{ "ledr", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1698 |
{ "her", OP8(0x34LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1699 |
{ "lcer", OP8(0x33LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1700 |
{ "lter", OP8(0x32LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1701 |
{ "lner", OP8(0x31LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1702 |
{ "lper", OP8(0x30LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1703 |
{ "swr", OP8(0x2fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1704 |
{ "awr", OP8(0x2eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1705 |
{ "ddr", OP8(0x2dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1706 |
{ "mdr", OP8(0x2cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1707 |
{ "sdr", OP8(0x2bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1708 |
{ "adr", OP8(0x2aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1709 |
{ "cdr", OP8(0x29LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1710 |
{ "ldr", OP8(0x28LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1711 |
{ "mxdr", OP8(0x27LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1712 |
{ "mxr", OP8(0x26LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1713 |
{ "lrdr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1714 |
{ "ldxr", OP8(0x25LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1715 |
{ "hdr", OP8(0x24LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1716 |
{ "lcdr", OP8(0x23LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1717 |
{ "ltdr", OP8(0x22LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1718 |
{ "lndr", OP8(0x21LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1719 |
{ "lpdr", OP8(0x20LL), MASK_RR_FF, INSTR_RR_FF, 3, 0},
|
| 1720 |
{ "slr", OP8(0x1fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1721 |
{ "alr", OP8(0x1eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1722 |
{ "dr", OP8(0x1dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1723 |
{ "mr", OP8(0x1cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1724 |
{ "sr", OP8(0x1bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1725 |
{ "ar", OP8(0x1aLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1726 |
{ "cr", OP8(0x19LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1727 |
{ "lr", OP8(0x18LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1728 |
{ "xr", OP8(0x17LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1729 |
{ "or", OP8(0x16LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1730 |
{ "clr", OP8(0x15LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1731 |
{ "nr", OP8(0x14LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1732 |
{ "lcr", OP8(0x13LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1733 |
{ "ltr", OP8(0x12LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1734 |
{ "lnr", OP8(0x11LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1735 |
{ "lpr", OP8(0x10LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1736 |
{ "clcl", OP8(0x0fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1737 |
{ "mvcl", OP8(0x0eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1738 |
{ "basr", OP8(0x0dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1739 |
{ "bassm", OP8(0x0cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1740 |
{ "bsm", OP8(0x0bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1741 |
{ "svc", OP8(0x0aLL), MASK_RR_U0, INSTR_RR_U0, 3, 0},
|
| 1742 |
{ "br", OP16(0x07f0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1743 |
{ "bnor", OP16(0x07e0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1744 |
{ "bnhr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1745 |
{ "bnpr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1746 |
{ "bler", OP16(0x07c0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1747 |
{ "bnlr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1748 |
{ "bnmr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1749 |
{ "bher", OP16(0x07a0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1750 |
{ "bnlhr", OP16(0x0790LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1751 |
{ "ber", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1752 |
{ "bzr", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1753 |
{ "bner", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1754 |
{ "bnzr", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1755 |
{ "blhr", OP16(0x0760LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1756 |
{ "bnher", OP16(0x0750LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1757 |
{ "blr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1758 |
{ "bmr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1759 |
{ "bnler", OP16(0x0730LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1760 |
{ "bhr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1761 |
{ "bpr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1762 |
{ "bor", OP16(0x0710LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1763 |
{ "bcr", OP8(0x07LL), MASK_RR_UR, INSTR_RR_UR, 3, 0},
|
| 1764 |
{ "nopr", OP16(0x0700LL), MASK_RR_0R, INSTR_RR_0R, 3, 0},
|
| 1765 |
{ "bctr", OP8(0x06LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1766 |
{ "balr", OP8(0x05LL), MASK_RR_RR, INSTR_RR_RR, 3, 0},
|
| 1767 |
{ "spm", OP8(0x04LL), MASK_RR_R0, INSTR_RR_R0, 3, 0},
|
| 1768 |
{ "trap2", OP16(0x01ffLL), MASK_E, INSTR_E, 3, 0},
|
| 1769 |
{ "sam64", OP16(0x010eLL), MASK_E, INSTR_E, 2, 2},
|
| 1770 |
{ "sam31", OP16(0x010dLL), MASK_E, INSTR_E, 3, 2},
|
| 1771 |
{ "sam24", OP16(0x010cLL), MASK_E, INSTR_E, 3, 2},
|
| 1772 |
{ "tam", OP16(0x010bLL), MASK_E, INSTR_E, 3, 2},
|
| 1773 |
{ "pfpo", OP16(0x010aLL), MASK_E, INSTR_E, 2, 5},
|
| 1774 |
{ "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0},
|
| 1775 |
{ "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0},
|
| 1776 |
{ "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0},
|
| 1777 |
|
| 1778 |
/* QEMU-ADD: */
|
| 1779 |
{ "crj", OP48(0xec0000000076LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
|
| 1780 |
{ "cgrj", OP48(0xec0000000064LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
|
| 1781 |
{ "clrj", OP48(0xec0000000077LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
|
| 1782 |
{ "clgrj", OP48(0xec0000000065LL), MASK_RIE_MRRP, INSTR_RIE_MRRP, 3, 6},
|
| 1783 |
|
| 1784 |
{ "cij", OP48(0xec000000007eLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
|
| 1785 |
{ "cgij", OP48(0xec000000007cLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
|
| 1786 |
{ "clij", OP48(0xec000000007fLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
|
| 1787 |
{ "clgij", OP48(0xec000000007dLL), MASK_RIE_MRIP, INSTR_RIE_MRIP, 3, 6},
|
| 1788 |
|
| 1789 |
{ "lrl", OP16(0xc40dll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
|
| 1790 |
{ "lgrl", OP16(0xc408ll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
|
| 1791 |
{ "lgfrl", OP16(0xc40cll), MASK_RIL_RP, INSTR_RIL_RP, 3, 6},
|
| 1792 |
/* QEMU-END */
|
| 1793 |
}; |
| 1794 |
|
| 1795 |
static const int s390_num_opcodes = |
| 1796 |
sizeof (s390_opcodes) / sizeof (s390_opcodes[0]); |