Statistics
| Branch: | Revision:

root / target-sparc / translate.c @ 9322a4bf

History | View | Annotate | Download (173.6 kB)

1 7a3f1944 bellard
/*
2 7a3f1944 bellard
   SPARC translation
3 7a3f1944 bellard

4 7a3f1944 bellard
   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5 3475187d bellard
   Copyright (C) 2003-2005 Fabrice Bellard
6 7a3f1944 bellard

7 7a3f1944 bellard
   This library is free software; you can redistribute it and/or
8 7a3f1944 bellard
   modify it under the terms of the GNU Lesser General Public
9 7a3f1944 bellard
   License as published by the Free Software Foundation; either
10 7a3f1944 bellard
   version 2 of the License, or (at your option) any later version.
11 7a3f1944 bellard

12 7a3f1944 bellard
   This library is distributed in the hope that it will be useful,
13 7a3f1944 bellard
   but WITHOUT ANY WARRANTY; without even the implied warranty of
14 7a3f1944 bellard
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
15 7a3f1944 bellard
   Lesser General Public License for more details.
16 7a3f1944 bellard

17 7a3f1944 bellard
   You should have received a copy of the GNU Lesser General Public
18 7a3f1944 bellard
   License along with this library; if not, write to the Free Software
19 7a3f1944 bellard
   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20 7a3f1944 bellard
 */
21 7a3f1944 bellard
22 7a3f1944 bellard
/*
23 7a3f1944 bellard
   TODO-list:
24 7a3f1944 bellard

25 3475187d bellard
   Rest of V9 instructions, VIS instructions
26 bd497938 bellard
   NPC/PC static optimisations (use JUMP_TB when possible)
27 7a3f1944 bellard
   Optimize synthetic instructions
28 bd497938 bellard
*/
29 7a3f1944 bellard
30 7a3f1944 bellard
#include <stdarg.h>
31 7a3f1944 bellard
#include <stdlib.h>
32 7a3f1944 bellard
#include <stdio.h>
33 7a3f1944 bellard
#include <string.h>
34 7a3f1944 bellard
#include <inttypes.h>
35 7a3f1944 bellard
36 7a3f1944 bellard
#include "cpu.h"
37 7a3f1944 bellard
#include "exec-all.h"
38 7a3f1944 bellard
#include "disas.h"
39 1a2fb1c0 blueswir1
#include "helper.h"
40 57fec1fe bellard
#include "tcg-op.h"
41 7a3f1944 bellard
42 7a3f1944 bellard
#define DEBUG_DISAS
43 7a3f1944 bellard
44 72cbca10 bellard
#define DYNAMIC_PC  1 /* dynamic pc value */
45 72cbca10 bellard
#define JUMP_PC     2 /* dynamic pc value which takes only two values
46 72cbca10 bellard
                         according to jump_pc[T2] */
47 72cbca10 bellard
48 1a2fb1c0 blueswir1
/* global register indexes */
49 d9bdab86 blueswir1
static TCGv cpu_env, cpu_T[3], cpu_regwptr, cpu_cc_src, cpu_cc_src2, cpu_cc_dst;
50 48d5c82b blueswir1
static TCGv cpu_psr, cpu_fsr, cpu_pc, cpu_npc, cpu_gregs[8];
51 6ae20372 blueswir1
static TCGv cpu_cond, cpu_src1, cpu_src2, cpu_dst, cpu_addr, cpu_val;
52 dc99a3f2 blueswir1
#ifdef TARGET_SPARC64
53 dc99a3f2 blueswir1
static TCGv cpu_xcc;
54 dc99a3f2 blueswir1
#endif
55 1a2fb1c0 blueswir1
/* local register indexes (only used inside old micro ops) */
56 8911f501 blueswir1
static TCGv cpu_tmp0, cpu_tmp32, cpu_tmp64;
57 1a2fb1c0 blueswir1
58 7a3f1944 bellard
typedef struct DisasContext {
59 0f8a249a blueswir1
    target_ulong pc;    /* current Program Counter: integer or DYNAMIC_PC */
60 0f8a249a blueswir1
    target_ulong npc;   /* next PC: integer or DYNAMIC_PC or JUMP_PC */
61 72cbca10 bellard
    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
62 cf495bcf bellard
    int is_br;
63 e8af50a3 bellard
    int mem_idx;
64 a80dde08 bellard
    int fpu_enabled;
65 cf495bcf bellard
    struct TranslationBlock *tb;
66 7a3f1944 bellard
} DisasContext;
67 7a3f1944 bellard
68 7a3f1944 bellard
extern FILE *logfile;
69 7a3f1944 bellard
extern int loglevel;
70 7a3f1944 bellard
71 3475187d bellard
// This function uses non-native bit order
72 7a3f1944 bellard
#define GET_FIELD(X, FROM, TO) \
73 7a3f1944 bellard
  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
74 7a3f1944 bellard
75 3475187d bellard
// This function uses the order in the manuals, i.e. bit 0 is 2^0
76 3475187d bellard
#define GET_FIELD_SP(X, FROM, TO) \
77 3475187d bellard
    GET_FIELD(X, 31 - (TO), 31 - (FROM))
78 3475187d bellard
79 3475187d bellard
#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
80 46d38ba8 blueswir1
#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), ((b) - (a) + 1))
81 3475187d bellard
82 3475187d bellard
#ifdef TARGET_SPARC64
83 19f329ad blueswir1
#define FFPREG(r) (r)
84 0387d928 blueswir1
#define DFPREG(r) (((r & 1) << 5) | (r & 0x1e))
85 1f587329 blueswir1
#define QFPREG(r) (((r & 1) << 5) | (r & 0x1c))
86 3475187d bellard
#else
87 19f329ad blueswir1
#define FFPREG(r) (r)
88 c185970a blueswir1
#define DFPREG(r) (r & 0x1e)
89 1f587329 blueswir1
#define QFPREG(r) (r & 0x1c)
90 3475187d bellard
#endif
91 3475187d bellard
92 3475187d bellard
static int sign_extend(int x, int len)
93 3475187d bellard
{
94 3475187d bellard
    len = 32 - len;
95 3475187d bellard
    return (x << len) >> len;
96 3475187d bellard
}
97 3475187d bellard
98 7a3f1944 bellard
#define IS_IMM (insn & (1<<13))
99 7a3f1944 bellard
100 ff07ec83 blueswir1
/* floating point registers moves */
101 ff07ec83 blueswir1
static void gen_op_load_fpr_FT0(unsigned int src)
102 ff07ec83 blueswir1
{
103 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
104 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
105 3475187d bellard
}
106 ff07ec83 blueswir1
107 ff07ec83 blueswir1
static void gen_op_load_fpr_FT1(unsigned int src)
108 ff07ec83 blueswir1
{
109 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
110 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft1));
111 e8af50a3 bellard
}
112 e8af50a3 bellard
113 ff07ec83 blueswir1
static void gen_op_store_FT0_fpr(unsigned int dst)
114 ff07ec83 blueswir1
{
115 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ft0));
116 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
117 ff07ec83 blueswir1
}
118 ff07ec83 blueswir1
119 ff07ec83 blueswir1
static void gen_op_load_fpr_DT0(unsigned int src)
120 ff07ec83 blueswir1
{
121 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
122 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
123 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
124 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
125 ff07ec83 blueswir1
}
126 ff07ec83 blueswir1
127 ff07ec83 blueswir1
static void gen_op_load_fpr_DT1(unsigned int src)
128 ff07ec83 blueswir1
{
129 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
130 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.upper));
131 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
132 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt1) + offsetof(CPU_DoubleU, l.lower));
133 ff07ec83 blueswir1
}
134 ff07ec83 blueswir1
135 ff07ec83 blueswir1
static void gen_op_store_DT0_fpr(unsigned int dst)
136 ff07ec83 blueswir1
{
137 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.upper));
138 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
139 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, dt0) + offsetof(CPU_DoubleU, l.lower));
140 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
141 ff07ec83 blueswir1
}
142 ff07ec83 blueswir1
143 ff07ec83 blueswir1
#ifdef CONFIG_USER_ONLY
144 ff07ec83 blueswir1
static void gen_op_load_fpr_QT0(unsigned int src)
145 ff07ec83 blueswir1
{
146 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
147 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
148 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
149 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
150 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
151 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
152 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
153 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
154 ff07ec83 blueswir1
}
155 ff07ec83 blueswir1
156 ff07ec83 blueswir1
static void gen_op_load_fpr_QT1(unsigned int src)
157 ff07ec83 blueswir1
{
158 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src]));
159 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upmost));
160 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 1]));
161 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.upper));
162 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 2]));
163 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lower));
164 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[src + 3]));
165 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt1) + offsetof(CPU_QuadU, l.lowest));
166 ff07ec83 blueswir1
}
167 ff07ec83 blueswir1
168 ff07ec83 blueswir1
static void gen_op_store_QT0_fpr(unsigned int dst)
169 ff07ec83 blueswir1
{
170 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upmost));
171 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst]));
172 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.upper));
173 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 1]));
174 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lower));
175 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 2]));
176 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, qt0) + offsetof(CPU_QuadU, l.lowest));
177 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fpr[dst + 3]));
178 ff07ec83 blueswir1
}
179 1f587329 blueswir1
#endif
180 1f587329 blueswir1
181 81ad8ba2 blueswir1
/* moves */
182 81ad8ba2 blueswir1
#ifdef CONFIG_USER_ONLY
183 3475187d bellard
#define supervisor(dc) 0
184 81ad8ba2 blueswir1
#ifdef TARGET_SPARC64
185 e9ebed4d blueswir1
#define hypervisor(dc) 0
186 81ad8ba2 blueswir1
#endif
187 3475187d bellard
#define gen_op_ldst(name)        gen_op_##name##_raw()
188 3475187d bellard
#else
189 6f27aba6 blueswir1
#define supervisor(dc) (dc->mem_idx >= 1)
190 81ad8ba2 blueswir1
#ifdef TARGET_SPARC64
191 81ad8ba2 blueswir1
#define hypervisor(dc) (dc->mem_idx == 2)
192 6f27aba6 blueswir1
#define OP_LD_TABLE(width)                                              \
193 6f27aba6 blueswir1
    static GenOpFunc * const gen_op_##width[] = {                       \
194 6f27aba6 blueswir1
        &gen_op_##width##_user,                                         \
195 6f27aba6 blueswir1
        &gen_op_##width##_kernel,                                       \
196 6f27aba6 blueswir1
        &gen_op_##width##_hypv,                                         \
197 6f27aba6 blueswir1
    };
198 6f27aba6 blueswir1
#else
199 0f8a249a blueswir1
#define OP_LD_TABLE(width)                                              \
200 a68156d0 blueswir1
    static GenOpFunc * const gen_op_##width[] = {                       \
201 0f8a249a blueswir1
        &gen_op_##width##_user,                                         \
202 0f8a249a blueswir1
        &gen_op_##width##_kernel,                                       \
203 81ad8ba2 blueswir1
    };
204 3475187d bellard
#endif
205 6f27aba6 blueswir1
#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
206 6f27aba6 blueswir1
#endif
207 e8af50a3 bellard
208 81ad8ba2 blueswir1
#ifndef CONFIG_USER_ONLY
209 b25deda7 blueswir1
#ifdef __i386__
210 b25deda7 blueswir1
OP_LD_TABLE(std);
211 b25deda7 blueswir1
#endif /* __i386__ */
212 e8af50a3 bellard
OP_LD_TABLE(stdf);
213 e8af50a3 bellard
OP_LD_TABLE(lddf);
214 81ad8ba2 blueswir1
#endif
215 81ad8ba2 blueswir1
216 1a2fb1c0 blueswir1
#ifdef TARGET_ABI32
217 8911f501 blueswir1
#define ABI32_MASK(addr) tcg_gen_andi_tl(addr, addr, 0xffffffffULL);
218 1a2fb1c0 blueswir1
#else
219 1a2fb1c0 blueswir1
#define ABI32_MASK(addr)
220 1a2fb1c0 blueswir1
#endif
221 3391c818 blueswir1
222 1a2fb1c0 blueswir1
static inline void gen_movl_reg_TN(int reg, TCGv tn)
223 81ad8ba2 blueswir1
{
224 1a2fb1c0 blueswir1
    if (reg == 0)
225 1a2fb1c0 blueswir1
        tcg_gen_movi_tl(tn, 0);
226 1a2fb1c0 blueswir1
    else if (reg < 8)
227 f5069b26 blueswir1
        tcg_gen_mov_tl(tn, cpu_gregs[reg]);
228 1a2fb1c0 blueswir1
    else {
229 1a2fb1c0 blueswir1
        tcg_gen_ld_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
230 81ad8ba2 blueswir1
    }
231 81ad8ba2 blueswir1
}
232 81ad8ba2 blueswir1
233 1a2fb1c0 blueswir1
static inline void gen_movl_TN_reg(int reg, TCGv tn)
234 81ad8ba2 blueswir1
{
235 1a2fb1c0 blueswir1
    if (reg == 0)
236 1a2fb1c0 blueswir1
        return;
237 1a2fb1c0 blueswir1
    else if (reg < 8)
238 f5069b26 blueswir1
        tcg_gen_mov_tl(cpu_gregs[reg], tn);
239 1a2fb1c0 blueswir1
    else {
240 1a2fb1c0 blueswir1
        tcg_gen_st_tl(tn, cpu_regwptr, (reg - 8) * sizeof(target_ulong));
241 81ad8ba2 blueswir1
    }
242 81ad8ba2 blueswir1
}
243 81ad8ba2 blueswir1
244 5fafdf24 ths
static inline void gen_goto_tb(DisasContext *s, int tb_num,
245 6e256c93 bellard
                               target_ulong pc, target_ulong npc)
246 6e256c93 bellard
{
247 6e256c93 bellard
    TranslationBlock *tb;
248 6e256c93 bellard
249 6e256c93 bellard
    tb = s->tb;
250 6e256c93 bellard
    if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) &&
251 6e256c93 bellard
        (npc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK))  {
252 6e256c93 bellard
        /* jump to same page: we can use a direct jump */
253 57fec1fe bellard
        tcg_gen_goto_tb(tb_num);
254 2f5680ee blueswir1
        tcg_gen_movi_tl(cpu_pc, pc);
255 2f5680ee blueswir1
        tcg_gen_movi_tl(cpu_npc, npc);
256 57fec1fe bellard
        tcg_gen_exit_tb((long)tb + tb_num);
257 6e256c93 bellard
    } else {
258 6e256c93 bellard
        /* jump to another page: currently not optimized */
259 2f5680ee blueswir1
        tcg_gen_movi_tl(cpu_pc, pc);
260 2f5680ee blueswir1
        tcg_gen_movi_tl(cpu_npc, npc);
261 57fec1fe bellard
        tcg_gen_exit_tb(0);
262 6e256c93 bellard
    }
263 6e256c93 bellard
}
264 6e256c93 bellard
265 19f329ad blueswir1
// XXX suboptimal
266 19f329ad blueswir1
static inline void gen_mov_reg_N(TCGv reg, TCGv src)
267 19f329ad blueswir1
{
268 8911f501 blueswir1
    tcg_gen_extu_i32_tl(reg, src);
269 8911f501 blueswir1
    tcg_gen_shri_tl(reg, reg, 23);
270 19f329ad blueswir1
    tcg_gen_andi_tl(reg, reg, 0x1);
271 19f329ad blueswir1
}
272 19f329ad blueswir1
273 19f329ad blueswir1
static inline void gen_mov_reg_Z(TCGv reg, TCGv src)
274 19f329ad blueswir1
{
275 8911f501 blueswir1
    tcg_gen_extu_i32_tl(reg, src);
276 8911f501 blueswir1
    tcg_gen_shri_tl(reg, reg, 22);
277 19f329ad blueswir1
    tcg_gen_andi_tl(reg, reg, 0x1);
278 19f329ad blueswir1
}
279 19f329ad blueswir1
280 19f329ad blueswir1
static inline void gen_mov_reg_V(TCGv reg, TCGv src)
281 19f329ad blueswir1
{
282 8911f501 blueswir1
    tcg_gen_extu_i32_tl(reg, src);
283 8911f501 blueswir1
    tcg_gen_shri_tl(reg, reg, 21);
284 19f329ad blueswir1
    tcg_gen_andi_tl(reg, reg, 0x1);
285 19f329ad blueswir1
}
286 19f329ad blueswir1
287 19f329ad blueswir1
static inline void gen_mov_reg_C(TCGv reg, TCGv src)
288 19f329ad blueswir1
{
289 8911f501 blueswir1
    tcg_gen_extu_i32_tl(reg, src);
290 8911f501 blueswir1
    tcg_gen_shri_tl(reg, reg, 20);
291 19f329ad blueswir1
    tcg_gen_andi_tl(reg, reg, 0x1);
292 19f329ad blueswir1
}
293 19f329ad blueswir1
294 ce5b3c3d blueswir1
static inline void gen_cc_clear_icc(void)
295 dc99a3f2 blueswir1
{
296 dc99a3f2 blueswir1
    tcg_gen_movi_i32(cpu_psr, 0);
297 ce5b3c3d blueswir1
}
298 ce5b3c3d blueswir1
299 dc99a3f2 blueswir1
#ifdef TARGET_SPARC64
300 ce5b3c3d blueswir1
static inline void gen_cc_clear_xcc(void)
301 ce5b3c3d blueswir1
{
302 dc99a3f2 blueswir1
    tcg_gen_movi_i32(cpu_xcc, 0);
303 dc99a3f2 blueswir1
}
304 ce5b3c3d blueswir1
#endif
305 dc99a3f2 blueswir1
306 dc99a3f2 blueswir1
/* old op:
307 dc99a3f2 blueswir1
    if (!T0)
308 dc99a3f2 blueswir1
        env->psr |= PSR_ZERO;
309 dc99a3f2 blueswir1
    if ((int32_t) T0 < 0)
310 dc99a3f2 blueswir1
        env->psr |= PSR_NEG;
311 dc99a3f2 blueswir1
*/
312 ce5b3c3d blueswir1
static inline void gen_cc_NZ_icc(TCGv dst)
313 dc99a3f2 blueswir1
{
314 8911f501 blueswir1
    TCGv r_temp;
315 dc99a3f2 blueswir1
    int l1, l2;
316 dc99a3f2 blueswir1
317 dc99a3f2 blueswir1
    l1 = gen_new_label();
318 dc99a3f2 blueswir1
    l2 = gen_new_label();
319 8911f501 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_TL);
320 8911f501 blueswir1
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
321 8911f501 blueswir1
    tcg_gen_brcond_tl(TCG_COND_NE, r_temp, tcg_const_tl(0), l1);
322 dc99a3f2 blueswir1
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_ZERO);
323 dc99a3f2 blueswir1
    gen_set_label(l1);
324 bdf46ea2 blueswir1
    tcg_gen_ext_i32_tl(r_temp, dst);
325 8911f501 blueswir1
    tcg_gen_brcond_tl(TCG_COND_GE, r_temp, tcg_const_tl(0), l2);
326 dc99a3f2 blueswir1
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_NEG);
327 dc99a3f2 blueswir1
    gen_set_label(l2);
328 ce5b3c3d blueswir1
}
329 ce5b3c3d blueswir1
330 dc99a3f2 blueswir1
#ifdef TARGET_SPARC64
331 ce5b3c3d blueswir1
static inline void gen_cc_NZ_xcc(TCGv dst)
332 ce5b3c3d blueswir1
{
333 ce5b3c3d blueswir1
    int l1, l2;
334 ce5b3c3d blueswir1
335 ce5b3c3d blueswir1
    l1 = gen_new_label();
336 ce5b3c3d blueswir1
    l2 = gen_new_label();
337 ce5b3c3d blueswir1
    tcg_gen_brcond_tl(TCG_COND_NE, dst, tcg_const_tl(0), l1);
338 ce5b3c3d blueswir1
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_ZERO);
339 ce5b3c3d blueswir1
    gen_set_label(l1);
340 ce5b3c3d blueswir1
    tcg_gen_brcond_tl(TCG_COND_GE, dst, tcg_const_tl(0), l2);
341 ce5b3c3d blueswir1
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_NEG);
342 ce5b3c3d blueswir1
    gen_set_label(l2);
343 dc99a3f2 blueswir1
}
344 ce5b3c3d blueswir1
#endif
345 dc99a3f2 blueswir1
346 dc99a3f2 blueswir1
/* old op:
347 dc99a3f2 blueswir1
    if (T0 < src1)
348 dc99a3f2 blueswir1
        env->psr |= PSR_CARRY;
349 dc99a3f2 blueswir1
*/
350 ce5b3c3d blueswir1
static inline void gen_cc_C_add_icc(TCGv dst, TCGv src1)
351 dc99a3f2 blueswir1
{
352 8911f501 blueswir1
    TCGv r_temp;
353 dc99a3f2 blueswir1
    int l1;
354 dc99a3f2 blueswir1
355 dc99a3f2 blueswir1
    l1 = gen_new_label();
356 8911f501 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_TL);
357 8911f501 blueswir1
    tcg_gen_andi_tl(r_temp, dst, 0xffffffffULL);
358 8911f501 blueswir1
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
359 dc99a3f2 blueswir1
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
360 dc99a3f2 blueswir1
    gen_set_label(l1);
361 ce5b3c3d blueswir1
}
362 ce5b3c3d blueswir1
363 dc99a3f2 blueswir1
#ifdef TARGET_SPARC64
364 ce5b3c3d blueswir1
static inline void gen_cc_C_add_xcc(TCGv dst, TCGv src1)
365 ce5b3c3d blueswir1
{
366 ce5b3c3d blueswir1
    int l1;
367 dc99a3f2 blueswir1
368 ce5b3c3d blueswir1
    l1 = gen_new_label();
369 ce5b3c3d blueswir1
    tcg_gen_brcond_tl(TCG_COND_GEU, dst, src1, l1);
370 ce5b3c3d blueswir1
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
371 ce5b3c3d blueswir1
    gen_set_label(l1);
372 dc99a3f2 blueswir1
}
373 ce5b3c3d blueswir1
#endif
374 dc99a3f2 blueswir1
375 dc99a3f2 blueswir1
/* old op:
376 dc99a3f2 blueswir1
    if (((src1 ^ T1 ^ -1) & (src1 ^ T0)) & (1 << 31))
377 dc99a3f2 blueswir1
        env->psr |= PSR_OVF;
378 dc99a3f2 blueswir1
*/
379 ce5b3c3d blueswir1
static inline void gen_cc_V_add_icc(TCGv dst, TCGv src1, TCGv src2)
380 dc99a3f2 blueswir1
{
381 0425bee5 blueswir1
    TCGv r_temp;
382 dc99a3f2 blueswir1
    int l1;
383 dc99a3f2 blueswir1
384 dc99a3f2 blueswir1
    l1 = gen_new_label();
385 dc99a3f2 blueswir1
386 dc99a3f2 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_TL);
387 dc99a3f2 blueswir1
    tcg_gen_xor_tl(r_temp, src1, src2);
388 dc99a3f2 blueswir1
    tcg_gen_xori_tl(r_temp, r_temp, -1);
389 0425bee5 blueswir1
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
390 0425bee5 blueswir1
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
391 0425bee5 blueswir1
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
392 8911f501 blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
393 dc99a3f2 blueswir1
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
394 dc99a3f2 blueswir1
    gen_set_label(l1);
395 ce5b3c3d blueswir1
}
396 ce5b3c3d blueswir1
397 dc99a3f2 blueswir1
#ifdef TARGET_SPARC64
398 ce5b3c3d blueswir1
static inline void gen_cc_V_add_xcc(TCGv dst, TCGv src1, TCGv src2)
399 ce5b3c3d blueswir1
{
400 ce5b3c3d blueswir1
    TCGv r_temp;
401 ce5b3c3d blueswir1
    int l1;
402 ce5b3c3d blueswir1
403 ce5b3c3d blueswir1
    l1 = gen_new_label();
404 ce5b3c3d blueswir1
405 ce5b3c3d blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_TL);
406 ce5b3c3d blueswir1
    tcg_gen_xor_tl(r_temp, src1, src2);
407 ce5b3c3d blueswir1
    tcg_gen_xori_tl(r_temp, r_temp, -1);
408 ce5b3c3d blueswir1
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
409 ce5b3c3d blueswir1
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
410 ce5b3c3d blueswir1
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
411 ce5b3c3d blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
412 ce5b3c3d blueswir1
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
413 ce5b3c3d blueswir1
    gen_set_label(l1);
414 dc99a3f2 blueswir1
}
415 ce5b3c3d blueswir1
#endif
416 dc99a3f2 blueswir1
417 dc99a3f2 blueswir1
static inline void gen_add_tv(TCGv dst, TCGv src1, TCGv src2)
418 dc99a3f2 blueswir1
{
419 0425bee5 blueswir1
    TCGv r_temp;
420 dc99a3f2 blueswir1
    int l1;
421 dc99a3f2 blueswir1
422 dc99a3f2 blueswir1
    l1 = gen_new_label();
423 dc99a3f2 blueswir1
424 dc99a3f2 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_TL);
425 dc99a3f2 blueswir1
    tcg_gen_xor_tl(r_temp, src1, src2);
426 dc99a3f2 blueswir1
    tcg_gen_xori_tl(r_temp, r_temp, -1);
427 0425bee5 blueswir1
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
428 0425bee5 blueswir1
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
429 0425bee5 blueswir1
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
430 8911f501 blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
431 2f5680ee blueswir1
    tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
432 dc99a3f2 blueswir1
    gen_set_label(l1);
433 dc99a3f2 blueswir1
}
434 dc99a3f2 blueswir1
435 dc99a3f2 blueswir1
static inline void gen_cc_V_tag(TCGv src1, TCGv src2)
436 dc99a3f2 blueswir1
{
437 dc99a3f2 blueswir1
    int l1;
438 dc99a3f2 blueswir1
439 dc99a3f2 blueswir1
    l1 = gen_new_label();
440 0425bee5 blueswir1
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
441 0425bee5 blueswir1
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
442 0425bee5 blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
443 dc99a3f2 blueswir1
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
444 dc99a3f2 blueswir1
    gen_set_label(l1);
445 dc99a3f2 blueswir1
}
446 dc99a3f2 blueswir1
447 dc99a3f2 blueswir1
static inline void gen_tag_tv(TCGv src1, TCGv src2)
448 dc99a3f2 blueswir1
{
449 dc99a3f2 blueswir1
    int l1;
450 dc99a3f2 blueswir1
451 dc99a3f2 blueswir1
    l1 = gen_new_label();
452 0425bee5 blueswir1
    tcg_gen_or_tl(cpu_tmp0, src1, src2);
453 0425bee5 blueswir1
    tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0x3);
454 0425bee5 blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
455 2f5680ee blueswir1
    tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
456 dc99a3f2 blueswir1
    gen_set_label(l1);
457 dc99a3f2 blueswir1
}
458 dc99a3f2 blueswir1
459 4af984a7 blueswir1
static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
460 dc99a3f2 blueswir1
{
461 4af984a7 blueswir1
    tcg_gen_mov_tl(cpu_cc_src, src1);
462 4af984a7 blueswir1
    tcg_gen_add_tl(dst, src1, src2);
463 ce5b3c3d blueswir1
    gen_cc_clear_icc();
464 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
465 4af984a7 blueswir1
    gen_cc_C_add_icc(dst, cpu_cc_src);
466 4af984a7 blueswir1
    gen_cc_V_add_icc(dst, cpu_cc_src, src2);
467 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
468 ce5b3c3d blueswir1
    gen_cc_clear_xcc();
469 4af984a7 blueswir1
    gen_cc_NZ_xcc(dst);
470 4af984a7 blueswir1
    gen_cc_C_add_xcc(dst, cpu_cc_src);
471 4af984a7 blueswir1
    gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
472 ce5b3c3d blueswir1
#endif
473 dc99a3f2 blueswir1
}
474 dc99a3f2 blueswir1
475 4af984a7 blueswir1
static inline void gen_op_addx_cc(TCGv dst, TCGv src1, TCGv src2)
476 dc99a3f2 blueswir1
{
477 4af984a7 blueswir1
    tcg_gen_mov_tl(cpu_cc_src, src1);
478 dc99a3f2 blueswir1
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
479 4af984a7 blueswir1
    tcg_gen_add_tl(dst, src1, cpu_tmp0);
480 ce5b3c3d blueswir1
    gen_cc_clear_icc();
481 4af984a7 blueswir1
    gen_cc_C_add_icc(dst, cpu_cc_src);
482 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
483 ce5b3c3d blueswir1
    gen_cc_clear_xcc();
484 4af984a7 blueswir1
    gen_cc_C_add_xcc(dst, cpu_cc_src);
485 ce5b3c3d blueswir1
#endif
486 4af984a7 blueswir1
    tcg_gen_add_tl(dst, dst, src2);
487 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
488 4af984a7 blueswir1
    gen_cc_C_add_icc(dst, cpu_cc_src);
489 4af984a7 blueswir1
    gen_cc_V_add_icc(dst, cpu_cc_src, src2);
490 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
491 4af984a7 blueswir1
    gen_cc_NZ_xcc(dst);
492 4af984a7 blueswir1
    gen_cc_C_add_xcc(dst, cpu_cc_src);
493 4af984a7 blueswir1
    gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
494 ce5b3c3d blueswir1
#endif
495 dc99a3f2 blueswir1
}
496 dc99a3f2 blueswir1
497 4af984a7 blueswir1
static inline void gen_op_tadd_cc(TCGv dst, TCGv src1, TCGv src2)
498 dc99a3f2 blueswir1
{
499 4af984a7 blueswir1
    tcg_gen_mov_tl(cpu_cc_src, src1);
500 4af984a7 blueswir1
    tcg_gen_add_tl(dst, src1, src2);
501 ce5b3c3d blueswir1
    gen_cc_clear_icc();
502 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
503 4af984a7 blueswir1
    gen_cc_C_add_icc(dst, cpu_cc_src);
504 4af984a7 blueswir1
    gen_cc_V_add_icc(dst, cpu_cc_src, src2);
505 4af984a7 blueswir1
    gen_cc_V_tag(cpu_cc_src, src2);
506 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
507 ce5b3c3d blueswir1
    gen_cc_clear_xcc();
508 4af984a7 blueswir1
    gen_cc_NZ_xcc(dst);
509 4af984a7 blueswir1
    gen_cc_C_add_xcc(dst, cpu_cc_src);
510 4af984a7 blueswir1
    gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
511 ce5b3c3d blueswir1
#endif
512 dc99a3f2 blueswir1
}
513 dc99a3f2 blueswir1
514 4af984a7 blueswir1
static inline void gen_op_tadd_ccTV(TCGv dst, TCGv src1, TCGv src2)
515 dc99a3f2 blueswir1
{
516 4af984a7 blueswir1
    gen_tag_tv(src1, src2);
517 4af984a7 blueswir1
    tcg_gen_mov_tl(cpu_cc_src, src1);
518 4af984a7 blueswir1
    tcg_gen_add_tl(dst, src1, src2);
519 4af984a7 blueswir1
    gen_add_tv(dst, cpu_cc_src, src2);
520 ce5b3c3d blueswir1
    gen_cc_clear_icc();
521 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
522 4af984a7 blueswir1
    gen_cc_C_add_icc(dst, cpu_cc_src);
523 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
524 ce5b3c3d blueswir1
    gen_cc_clear_xcc();
525 4af984a7 blueswir1
    gen_cc_NZ_xcc(dst);
526 4af984a7 blueswir1
    gen_cc_C_add_xcc(dst, cpu_cc_src);
527 4af984a7 blueswir1
    gen_cc_V_add_xcc(dst, cpu_cc_src, src2);
528 ce5b3c3d blueswir1
#endif
529 dc99a3f2 blueswir1
}
530 dc99a3f2 blueswir1
531 dc99a3f2 blueswir1
/* old op:
532 dc99a3f2 blueswir1
    if (src1 < T1)
533 dc99a3f2 blueswir1
        env->psr |= PSR_CARRY;
534 dc99a3f2 blueswir1
*/
535 ce5b3c3d blueswir1
static inline void gen_cc_C_sub_icc(TCGv src1, TCGv src2)
536 dc99a3f2 blueswir1
{
537 8911f501 blueswir1
    TCGv r_temp1, r_temp2;
538 dc99a3f2 blueswir1
    int l1;
539 dc99a3f2 blueswir1
540 dc99a3f2 blueswir1
    l1 = gen_new_label();
541 8911f501 blueswir1
    r_temp1 = tcg_temp_new(TCG_TYPE_TL);
542 8911f501 blueswir1
    r_temp2 = tcg_temp_new(TCG_TYPE_TL);
543 8911f501 blueswir1
    tcg_gen_andi_tl(r_temp1, src1, 0xffffffffULL);
544 8911f501 blueswir1
    tcg_gen_andi_tl(r_temp2, src2, 0xffffffffULL);
545 8911f501 blueswir1
    tcg_gen_brcond_tl(TCG_COND_GEU, r_temp1, r_temp2, l1);
546 dc99a3f2 blueswir1
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_CARRY);
547 dc99a3f2 blueswir1
    gen_set_label(l1);
548 ce5b3c3d blueswir1
}
549 ce5b3c3d blueswir1
550 dc99a3f2 blueswir1
#ifdef TARGET_SPARC64
551 ce5b3c3d blueswir1
static inline void gen_cc_C_sub_xcc(TCGv src1, TCGv src2)
552 ce5b3c3d blueswir1
{
553 ce5b3c3d blueswir1
    int l1;
554 dc99a3f2 blueswir1
555 ce5b3c3d blueswir1
    l1 = gen_new_label();
556 ce5b3c3d blueswir1
    tcg_gen_brcond_tl(TCG_COND_GEU, src1, src2, l1);
557 ce5b3c3d blueswir1
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_CARRY);
558 ce5b3c3d blueswir1
    gen_set_label(l1);
559 dc99a3f2 blueswir1
}
560 ce5b3c3d blueswir1
#endif
561 dc99a3f2 blueswir1
562 dc99a3f2 blueswir1
/* old op:
563 dc99a3f2 blueswir1
    if (((src1 ^ T1) & (src1 ^ T0)) & (1 << 31))
564 dc99a3f2 blueswir1
        env->psr |= PSR_OVF;
565 dc99a3f2 blueswir1
*/
566 ce5b3c3d blueswir1
static inline void gen_cc_V_sub_icc(TCGv dst, TCGv src1, TCGv src2)
567 dc99a3f2 blueswir1
{
568 0425bee5 blueswir1
    TCGv r_temp;
569 dc99a3f2 blueswir1
    int l1;
570 dc99a3f2 blueswir1
571 dc99a3f2 blueswir1
    l1 = gen_new_label();
572 dc99a3f2 blueswir1
573 dc99a3f2 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_TL);
574 dc99a3f2 blueswir1
    tcg_gen_xor_tl(r_temp, src1, src2);
575 0425bee5 blueswir1
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
576 0425bee5 blueswir1
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
577 0425bee5 blueswir1
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
578 8911f501 blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
579 dc99a3f2 blueswir1
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
580 dc99a3f2 blueswir1
    gen_set_label(l1);
581 ce5b3c3d blueswir1
}
582 ce5b3c3d blueswir1
583 dc99a3f2 blueswir1
#ifdef TARGET_SPARC64
584 ce5b3c3d blueswir1
static inline void gen_cc_V_sub_xcc(TCGv dst, TCGv src1, TCGv src2)
585 ce5b3c3d blueswir1
{
586 ce5b3c3d blueswir1
    TCGv r_temp;
587 ce5b3c3d blueswir1
    int l1;
588 ce5b3c3d blueswir1
589 ce5b3c3d blueswir1
    l1 = gen_new_label();
590 ce5b3c3d blueswir1
591 ce5b3c3d blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_TL);
592 ce5b3c3d blueswir1
    tcg_gen_xor_tl(r_temp, src1, src2);
593 ce5b3c3d blueswir1
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
594 ce5b3c3d blueswir1
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
595 ce5b3c3d blueswir1
    tcg_gen_andi_tl(r_temp, r_temp, (1ULL << 63));
596 ce5b3c3d blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
597 ce5b3c3d blueswir1
    tcg_gen_ori_i32(cpu_xcc, cpu_xcc, PSR_OVF);
598 ce5b3c3d blueswir1
    gen_set_label(l1);
599 dc99a3f2 blueswir1
}
600 ce5b3c3d blueswir1
#endif
601 dc99a3f2 blueswir1
602 dc99a3f2 blueswir1
static inline void gen_sub_tv(TCGv dst, TCGv src1, TCGv src2)
603 dc99a3f2 blueswir1
{
604 0425bee5 blueswir1
    TCGv r_temp;
605 dc99a3f2 blueswir1
    int l1;
606 dc99a3f2 blueswir1
607 dc99a3f2 blueswir1
    l1 = gen_new_label();
608 dc99a3f2 blueswir1
609 dc99a3f2 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_TL);
610 dc99a3f2 blueswir1
    tcg_gen_xor_tl(r_temp, src1, src2);
611 0425bee5 blueswir1
    tcg_gen_xor_tl(cpu_tmp0, src1, dst);
612 0425bee5 blueswir1
    tcg_gen_and_tl(r_temp, r_temp, cpu_tmp0);
613 0425bee5 blueswir1
    tcg_gen_andi_tl(r_temp, r_temp, (1 << 31));
614 8911f501 blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, r_temp, tcg_const_tl(0), l1);
615 2f5680ee blueswir1
    tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_TOVF));
616 dc99a3f2 blueswir1
    gen_set_label(l1);
617 0425bee5 blueswir1
    tcg_gen_discard_tl(r_temp);
618 dc99a3f2 blueswir1
}
619 dc99a3f2 blueswir1
620 4af984a7 blueswir1
static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
621 dc99a3f2 blueswir1
{
622 4af984a7 blueswir1
    tcg_gen_mov_tl(cpu_cc_src, src1);
623 4af984a7 blueswir1
    tcg_gen_sub_tl(dst, src1, src2);
624 ce5b3c3d blueswir1
    gen_cc_clear_icc();
625 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
626 4af984a7 blueswir1
    gen_cc_C_sub_icc(cpu_cc_src, src2);
627 4af984a7 blueswir1
    gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
628 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
629 ce5b3c3d blueswir1
    gen_cc_clear_xcc();
630 4af984a7 blueswir1
    gen_cc_NZ_xcc(dst);
631 4af984a7 blueswir1
    gen_cc_C_sub_xcc(cpu_cc_src, src2);
632 4af984a7 blueswir1
    gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
633 ce5b3c3d blueswir1
#endif
634 dc99a3f2 blueswir1
}
635 dc99a3f2 blueswir1
636 4af984a7 blueswir1
static inline void gen_op_subx_cc(TCGv dst, TCGv src1, TCGv src2)
637 dc99a3f2 blueswir1
{
638 4af984a7 blueswir1
    tcg_gen_mov_tl(cpu_cc_src, src1);
639 dc99a3f2 blueswir1
    gen_mov_reg_C(cpu_tmp0, cpu_psr);
640 4af984a7 blueswir1
    tcg_gen_sub_tl(dst, src1, cpu_tmp0);
641 ce5b3c3d blueswir1
    gen_cc_clear_icc();
642 4af984a7 blueswir1
    gen_cc_C_sub_icc(dst, cpu_cc_src);
643 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
644 ce5b3c3d blueswir1
    gen_cc_clear_xcc();
645 4af984a7 blueswir1
    gen_cc_C_sub_xcc(dst, cpu_cc_src);
646 ce5b3c3d blueswir1
#endif
647 4af984a7 blueswir1
    tcg_gen_sub_tl(dst, dst, src2);
648 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
649 4af984a7 blueswir1
    gen_cc_C_sub_icc(dst, cpu_cc_src);
650 4af984a7 blueswir1
    gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
651 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
652 4af984a7 blueswir1
    gen_cc_NZ_xcc(dst);
653 4af984a7 blueswir1
    gen_cc_C_sub_xcc(dst, cpu_cc_src);
654 4af984a7 blueswir1
    gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
655 ce5b3c3d blueswir1
#endif
656 dc99a3f2 blueswir1
}
657 dc99a3f2 blueswir1
658 4af984a7 blueswir1
static inline void gen_op_tsub_cc(TCGv dst, TCGv src1, TCGv src2)
659 dc99a3f2 blueswir1
{
660 4af984a7 blueswir1
    tcg_gen_mov_tl(cpu_cc_src, src1);
661 4af984a7 blueswir1
    tcg_gen_sub_tl(dst, src1, src2);
662 ce5b3c3d blueswir1
    gen_cc_clear_icc();
663 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
664 4af984a7 blueswir1
    gen_cc_C_sub_icc(cpu_cc_src, src2);
665 4af984a7 blueswir1
    gen_cc_V_sub_icc(dst, cpu_cc_src, src2);
666 4af984a7 blueswir1
    gen_cc_V_tag(cpu_cc_src, src2);
667 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
668 ce5b3c3d blueswir1
    gen_cc_clear_xcc();
669 4af984a7 blueswir1
    gen_cc_NZ_xcc(dst);
670 4af984a7 blueswir1
    gen_cc_C_sub_xcc(cpu_cc_src, src2);
671 4af984a7 blueswir1
    gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
672 ce5b3c3d blueswir1
#endif
673 dc99a3f2 blueswir1
}
674 dc99a3f2 blueswir1
675 4af984a7 blueswir1
static inline void gen_op_tsub_ccTV(TCGv dst, TCGv src1, TCGv src2)
676 dc99a3f2 blueswir1
{
677 4af984a7 blueswir1
    gen_tag_tv(src1, src2);
678 4af984a7 blueswir1
    tcg_gen_mov_tl(cpu_cc_src, src1);
679 4af984a7 blueswir1
    tcg_gen_sub_tl(dst, src1, src2);
680 4af984a7 blueswir1
    gen_sub_tv(dst, cpu_cc_src, src2);
681 ce5b3c3d blueswir1
    gen_cc_clear_icc();
682 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
683 4af984a7 blueswir1
    gen_cc_C_sub_icc(cpu_cc_src, src2);
684 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
685 ce5b3c3d blueswir1
    gen_cc_clear_xcc();
686 4af984a7 blueswir1
    gen_cc_NZ_xcc(dst);
687 4af984a7 blueswir1
    gen_cc_C_sub_xcc(cpu_cc_src, src2);
688 4af984a7 blueswir1
    gen_cc_V_sub_xcc(dst, cpu_cc_src, src2);
689 ce5b3c3d blueswir1
#endif
690 dc99a3f2 blueswir1
}
691 dc99a3f2 blueswir1
692 4af984a7 blueswir1
static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
693 d9bdab86 blueswir1
{
694 7127fe84 blueswir1
    TCGv r_temp, r_temp2;
695 d9bdab86 blueswir1
    int l1, l2;
696 d9bdab86 blueswir1
697 d9bdab86 blueswir1
    l1 = gen_new_label();
698 d9bdab86 blueswir1
    l2 = gen_new_label();
699 d9bdab86 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_TL);
700 7127fe84 blueswir1
    r_temp2 = tcg_temp_new(TCG_TYPE_I32);
701 d9bdab86 blueswir1
702 d9bdab86 blueswir1
    /* old op:
703 d9bdab86 blueswir1
    if (!(env->y & 1))
704 d9bdab86 blueswir1
        T1 = 0;
705 d9bdab86 blueswir1
    */
706 7127fe84 blueswir1
    tcg_gen_ld32u_tl(r_temp, cpu_env, offsetof(CPUSPARCState, y));
707 7127fe84 blueswir1
    tcg_gen_trunc_tl_i32(r_temp2, r_temp);
708 7127fe84 blueswir1
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
709 7127fe84 blueswir1
    tcg_gen_brcond_i32(TCG_COND_EQ, r_temp2, tcg_const_i32(0), l1);
710 4af984a7 blueswir1
    tcg_gen_mov_tl(cpu_cc_src2, src2);
711 06b3e1b3 blueswir1
    tcg_gen_br(l2);
712 d9bdab86 blueswir1
    gen_set_label(l1);
713 d9bdab86 blueswir1
    tcg_gen_movi_tl(cpu_cc_src2, 0);
714 d9bdab86 blueswir1
    gen_set_label(l2);
715 d9bdab86 blueswir1
716 d9bdab86 blueswir1
    // b2 = T0 & 1;
717 d9bdab86 blueswir1
    // env->y = (b2 << 31) | (env->y >> 1);
718 4af984a7 blueswir1
    tcg_gen_trunc_tl_i32(r_temp2, src1);
719 7127fe84 blueswir1
    tcg_gen_andi_i32(r_temp2, r_temp2, 0x1);
720 7127fe84 blueswir1
    tcg_gen_shli_i32(r_temp2, r_temp2, 31);
721 8911f501 blueswir1
    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
722 8911f501 blueswir1
    tcg_gen_shri_i32(cpu_tmp32, cpu_tmp32, 1);
723 7127fe84 blueswir1
    tcg_gen_or_i32(cpu_tmp32, cpu_tmp32, r_temp2);
724 8911f501 blueswir1
    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, y));
725 d9bdab86 blueswir1
726 d9bdab86 blueswir1
    // b1 = N ^ V;
727 d9bdab86 blueswir1
    gen_mov_reg_N(cpu_tmp0, cpu_psr);
728 d9bdab86 blueswir1
    gen_mov_reg_V(r_temp, cpu_psr);
729 d9bdab86 blueswir1
    tcg_gen_xor_tl(cpu_tmp0, cpu_tmp0, r_temp);
730 d9bdab86 blueswir1
731 d9bdab86 blueswir1
    // T0 = (b1 << 31) | (T0 >> 1);
732 d9bdab86 blueswir1
    // src1 = T0;
733 d9bdab86 blueswir1
    tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, 31);
734 4af984a7 blueswir1
    tcg_gen_shri_tl(cpu_cc_src, src1, 1);
735 d9bdab86 blueswir1
    tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
736 d9bdab86 blueswir1
737 d9bdab86 blueswir1
    /* do addition and update flags */
738 4af984a7 blueswir1
    tcg_gen_add_tl(dst, cpu_cc_src, cpu_cc_src2);
739 d9bdab86 blueswir1
    tcg_gen_discard_tl(r_temp);
740 d9bdab86 blueswir1
741 ce5b3c3d blueswir1
    gen_cc_clear_icc();
742 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
743 4af984a7 blueswir1
    gen_cc_V_add_icc(dst, cpu_cc_src, cpu_cc_src2);
744 4af984a7 blueswir1
    gen_cc_C_add_icc(dst, cpu_cc_src);
745 d9bdab86 blueswir1
}
746 d9bdab86 blueswir1
747 4af984a7 blueswir1
static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
748 8879d139 blueswir1
{
749 8879d139 blueswir1
    TCGv r_temp, r_temp2;
750 8879d139 blueswir1
751 8879d139 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_I64);
752 8879d139 blueswir1
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
753 8879d139 blueswir1
754 4af984a7 blueswir1
    tcg_gen_extu_tl_i64(r_temp, src2);
755 4af984a7 blueswir1
    tcg_gen_extu_tl_i64(r_temp2, src1);
756 8879d139 blueswir1
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
757 8879d139 blueswir1
758 8879d139 blueswir1
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
759 8879d139 blueswir1
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
760 8879d139 blueswir1
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
761 8879d139 blueswir1
#ifdef TARGET_SPARC64
762 4af984a7 blueswir1
    tcg_gen_mov_i64(dst, r_temp2);
763 8879d139 blueswir1
#else
764 4af984a7 blueswir1
    tcg_gen_trunc_i64_tl(dst, r_temp2);
765 8879d139 blueswir1
#endif
766 8879d139 blueswir1
767 8879d139 blueswir1
    tcg_gen_discard_i64(r_temp);
768 8879d139 blueswir1
    tcg_gen_discard_i64(r_temp2);
769 8879d139 blueswir1
}
770 8879d139 blueswir1
771 4af984a7 blueswir1
static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
772 8879d139 blueswir1
{
773 8879d139 blueswir1
    TCGv r_temp, r_temp2;
774 8879d139 blueswir1
775 8879d139 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_I64);
776 8879d139 blueswir1
    r_temp2 = tcg_temp_new(TCG_TYPE_I64);
777 8879d139 blueswir1
778 4af984a7 blueswir1
    tcg_gen_ext_tl_i64(r_temp, src2);
779 4af984a7 blueswir1
    tcg_gen_ext_tl_i64(r_temp2, src1);
780 8879d139 blueswir1
    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
781 8879d139 blueswir1
782 8879d139 blueswir1
    tcg_gen_shri_i64(r_temp, r_temp2, 32);
783 8879d139 blueswir1
    tcg_gen_trunc_i64_i32(r_temp, r_temp);
784 8879d139 blueswir1
    tcg_gen_st_i32(r_temp, cpu_env, offsetof(CPUSPARCState, y));
785 8879d139 blueswir1
#ifdef TARGET_SPARC64
786 4af984a7 blueswir1
    tcg_gen_mov_i64(dst, r_temp2);
787 8879d139 blueswir1
#else
788 4af984a7 blueswir1
    tcg_gen_trunc_i64_tl(dst, r_temp2);
789 8879d139 blueswir1
#endif
790 8879d139 blueswir1
791 8879d139 blueswir1
    tcg_gen_discard_i64(r_temp);
792 8879d139 blueswir1
    tcg_gen_discard_i64(r_temp2);
793 8879d139 blueswir1
}
794 8879d139 blueswir1
795 1a7b60e7 blueswir1
#ifdef TARGET_SPARC64
796 8911f501 blueswir1
static inline void gen_trap_ifdivzero_tl(TCGv divisor)
797 1a7b60e7 blueswir1
{
798 1a7b60e7 blueswir1
    int l1;
799 1a7b60e7 blueswir1
800 1a7b60e7 blueswir1
    l1 = gen_new_label();
801 8911f501 blueswir1
    tcg_gen_brcond_tl(TCG_COND_NE, divisor, tcg_const_tl(0), l1);
802 2f5680ee blueswir1
    tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_DIV_ZERO));
803 1a7b60e7 blueswir1
    gen_set_label(l1);
804 1a7b60e7 blueswir1
}
805 1a7b60e7 blueswir1
806 4af984a7 blueswir1
static inline void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
807 1a7b60e7 blueswir1
{
808 1a7b60e7 blueswir1
    int l1, l2;
809 1a7b60e7 blueswir1
810 1a7b60e7 blueswir1
    l1 = gen_new_label();
811 1a7b60e7 blueswir1
    l2 = gen_new_label();
812 4af984a7 blueswir1
    gen_trap_ifdivzero_tl(src2);
813 4af984a7 blueswir1
    tcg_gen_brcond_tl(TCG_COND_NE, src1, tcg_const_tl(INT64_MIN), l1);
814 4af984a7 blueswir1
    tcg_gen_brcond_tl(TCG_COND_NE, src2, tcg_const_tl(-1), l1);
815 4af984a7 blueswir1
    tcg_gen_movi_i64(dst, INT64_MIN);
816 06b3e1b3 blueswir1
    tcg_gen_br(l2);
817 1a7b60e7 blueswir1
    gen_set_label(l1);
818 4af984a7 blueswir1
    tcg_gen_div_i64(dst, src1, src2);
819 1a7b60e7 blueswir1
    gen_set_label(l2);
820 1a7b60e7 blueswir1
}
821 1a7b60e7 blueswir1
#endif
822 1a7b60e7 blueswir1
823 4af984a7 blueswir1
static inline void gen_op_div_cc(TCGv dst)
824 dc99a3f2 blueswir1
{
825 dc99a3f2 blueswir1
    int l1;
826 dc99a3f2 blueswir1
827 ce5b3c3d blueswir1
    gen_cc_clear_icc();
828 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
829 dc99a3f2 blueswir1
    l1 = gen_new_label();
830 3b89f26c blueswir1
    tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUSPARCState, cc_src2));
831 3b89f26c blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, cpu_tmp0, tcg_const_tl(0), l1);
832 dc99a3f2 blueswir1
    tcg_gen_ori_i32(cpu_psr, cpu_psr, PSR_OVF);
833 dc99a3f2 blueswir1
    gen_set_label(l1);
834 dc99a3f2 blueswir1
}
835 dc99a3f2 blueswir1
836 4af984a7 blueswir1
static inline void gen_op_logic_cc(TCGv dst)
837 dc99a3f2 blueswir1
{
838 ce5b3c3d blueswir1
    gen_cc_clear_icc();
839 4af984a7 blueswir1
    gen_cc_NZ_icc(dst);
840 ce5b3c3d blueswir1
#ifdef TARGET_SPARC64
841 ce5b3c3d blueswir1
    gen_cc_clear_xcc();
842 4af984a7 blueswir1
    gen_cc_NZ_xcc(dst);
843 ce5b3c3d blueswir1
#endif
844 dc99a3f2 blueswir1
}
845 dc99a3f2 blueswir1
846 19f329ad blueswir1
// 1
847 19f329ad blueswir1
static inline void gen_op_eval_ba(TCGv dst)
848 19f329ad blueswir1
{
849 19f329ad blueswir1
    tcg_gen_movi_tl(dst, 1);
850 19f329ad blueswir1
}
851 19f329ad blueswir1
852 19f329ad blueswir1
// Z
853 19f329ad blueswir1
static inline void gen_op_eval_be(TCGv dst, TCGv src)
854 19f329ad blueswir1
{
855 19f329ad blueswir1
    gen_mov_reg_Z(dst, src);
856 19f329ad blueswir1
}
857 19f329ad blueswir1
858 19f329ad blueswir1
// Z | (N ^ V)
859 19f329ad blueswir1
static inline void gen_op_eval_ble(TCGv dst, TCGv src)
860 19f329ad blueswir1
{
861 0425bee5 blueswir1
    gen_mov_reg_N(cpu_tmp0, src);
862 19f329ad blueswir1
    gen_mov_reg_V(dst, src);
863 0425bee5 blueswir1
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
864 0425bee5 blueswir1
    gen_mov_reg_Z(cpu_tmp0, src);
865 0425bee5 blueswir1
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
866 19f329ad blueswir1
}
867 19f329ad blueswir1
868 19f329ad blueswir1
// N ^ V
869 19f329ad blueswir1
static inline void gen_op_eval_bl(TCGv dst, TCGv src)
870 19f329ad blueswir1
{
871 0425bee5 blueswir1
    gen_mov_reg_V(cpu_tmp0, src);
872 19f329ad blueswir1
    gen_mov_reg_N(dst, src);
873 0425bee5 blueswir1
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
874 19f329ad blueswir1
}
875 19f329ad blueswir1
876 19f329ad blueswir1
// C | Z
877 19f329ad blueswir1
static inline void gen_op_eval_bleu(TCGv dst, TCGv src)
878 19f329ad blueswir1
{
879 0425bee5 blueswir1
    gen_mov_reg_Z(cpu_tmp0, src);
880 19f329ad blueswir1
    gen_mov_reg_C(dst, src);
881 0425bee5 blueswir1
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
882 19f329ad blueswir1
}
883 19f329ad blueswir1
884 19f329ad blueswir1
// C
885 19f329ad blueswir1
static inline void gen_op_eval_bcs(TCGv dst, TCGv src)
886 19f329ad blueswir1
{
887 19f329ad blueswir1
    gen_mov_reg_C(dst, src);
888 19f329ad blueswir1
}
889 19f329ad blueswir1
890 19f329ad blueswir1
// V
891 19f329ad blueswir1
static inline void gen_op_eval_bvs(TCGv dst, TCGv src)
892 19f329ad blueswir1
{
893 19f329ad blueswir1
    gen_mov_reg_V(dst, src);
894 19f329ad blueswir1
}
895 19f329ad blueswir1
896 19f329ad blueswir1
// 0
897 19f329ad blueswir1
static inline void gen_op_eval_bn(TCGv dst)
898 19f329ad blueswir1
{
899 19f329ad blueswir1
    tcg_gen_movi_tl(dst, 0);
900 19f329ad blueswir1
}
901 19f329ad blueswir1
902 19f329ad blueswir1
// N
903 19f329ad blueswir1
static inline void gen_op_eval_bneg(TCGv dst, TCGv src)
904 19f329ad blueswir1
{
905 19f329ad blueswir1
    gen_mov_reg_N(dst, src);
906 19f329ad blueswir1
}
907 19f329ad blueswir1
908 19f329ad blueswir1
// !Z
909 19f329ad blueswir1
static inline void gen_op_eval_bne(TCGv dst, TCGv src)
910 19f329ad blueswir1
{
911 19f329ad blueswir1
    gen_mov_reg_Z(dst, src);
912 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
913 19f329ad blueswir1
}
914 19f329ad blueswir1
915 19f329ad blueswir1
// !(Z | (N ^ V))
916 19f329ad blueswir1
static inline void gen_op_eval_bg(TCGv dst, TCGv src)
917 19f329ad blueswir1
{
918 0425bee5 blueswir1
    gen_mov_reg_N(cpu_tmp0, src);
919 19f329ad blueswir1
    gen_mov_reg_V(dst, src);
920 0425bee5 blueswir1
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
921 0425bee5 blueswir1
    gen_mov_reg_Z(cpu_tmp0, src);
922 0425bee5 blueswir1
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
923 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
924 19f329ad blueswir1
}
925 19f329ad blueswir1
926 19f329ad blueswir1
// !(N ^ V)
927 19f329ad blueswir1
static inline void gen_op_eval_bge(TCGv dst, TCGv src)
928 19f329ad blueswir1
{
929 0425bee5 blueswir1
    gen_mov_reg_V(cpu_tmp0, src);
930 19f329ad blueswir1
    gen_mov_reg_N(dst, src);
931 0425bee5 blueswir1
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
932 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
933 19f329ad blueswir1
}
934 19f329ad blueswir1
935 19f329ad blueswir1
// !(C | Z)
936 19f329ad blueswir1
static inline void gen_op_eval_bgu(TCGv dst, TCGv src)
937 19f329ad blueswir1
{
938 0425bee5 blueswir1
    gen_mov_reg_Z(cpu_tmp0, src);
939 19f329ad blueswir1
    gen_mov_reg_C(dst, src);
940 0425bee5 blueswir1
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
941 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
942 19f329ad blueswir1
}
943 19f329ad blueswir1
944 19f329ad blueswir1
// !C
945 19f329ad blueswir1
static inline void gen_op_eval_bcc(TCGv dst, TCGv src)
946 19f329ad blueswir1
{
947 19f329ad blueswir1
    gen_mov_reg_C(dst, src);
948 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
949 19f329ad blueswir1
}
950 19f329ad blueswir1
951 19f329ad blueswir1
// !N
952 19f329ad blueswir1
static inline void gen_op_eval_bpos(TCGv dst, TCGv src)
953 19f329ad blueswir1
{
954 19f329ad blueswir1
    gen_mov_reg_N(dst, src);
955 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
956 19f329ad blueswir1
}
957 19f329ad blueswir1
958 19f329ad blueswir1
// !V
959 19f329ad blueswir1
static inline void gen_op_eval_bvc(TCGv dst, TCGv src)
960 19f329ad blueswir1
{
961 19f329ad blueswir1
    gen_mov_reg_V(dst, src);
962 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
963 19f329ad blueswir1
}
964 19f329ad blueswir1
965 19f329ad blueswir1
/*
966 19f329ad blueswir1
  FPSR bit field FCC1 | FCC0:
967 19f329ad blueswir1
   0 =
968 19f329ad blueswir1
   1 <
969 19f329ad blueswir1
   2 >
970 19f329ad blueswir1
   3 unordered
971 19f329ad blueswir1
*/
972 19f329ad blueswir1
static inline void gen_mov_reg_FCC0(TCGv reg, TCGv src,
973 19f329ad blueswir1
                                    unsigned int fcc_offset)
974 19f329ad blueswir1
{
975 8911f501 blueswir1
    tcg_gen_extu_i32_tl(reg, src);
976 8911f501 blueswir1
    tcg_gen_shri_tl(reg, reg, 10 + fcc_offset);
977 19f329ad blueswir1
    tcg_gen_andi_tl(reg, reg, 0x1);
978 19f329ad blueswir1
}
979 19f329ad blueswir1
980 19f329ad blueswir1
static inline void gen_mov_reg_FCC1(TCGv reg, TCGv src,
981 19f329ad blueswir1
                                    unsigned int fcc_offset)
982 19f329ad blueswir1
{
983 8911f501 blueswir1
    tcg_gen_extu_i32_tl(reg, src);
984 8911f501 blueswir1
    tcg_gen_shri_tl(reg, reg, 11 + fcc_offset);
985 19f329ad blueswir1
    tcg_gen_andi_tl(reg, reg, 0x1);
986 19f329ad blueswir1
}
987 19f329ad blueswir1
988 19f329ad blueswir1
// !0: FCC0 | FCC1
989 19f329ad blueswir1
static inline void gen_op_eval_fbne(TCGv dst, TCGv src,
990 19f329ad blueswir1
                                    unsigned int fcc_offset)
991 19f329ad blueswir1
{
992 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
993 0425bee5 blueswir1
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
994 0425bee5 blueswir1
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
995 19f329ad blueswir1
}
996 19f329ad blueswir1
997 19f329ad blueswir1
// 1 or 2: FCC0 ^ FCC1
998 19f329ad blueswir1
static inline void gen_op_eval_fblg(TCGv dst, TCGv src,
999 19f329ad blueswir1
                                    unsigned int fcc_offset)
1000 19f329ad blueswir1
{
1001 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1002 0425bee5 blueswir1
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1003 0425bee5 blueswir1
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1004 19f329ad blueswir1
}
1005 19f329ad blueswir1
1006 19f329ad blueswir1
// 1 or 3: FCC0
1007 19f329ad blueswir1
static inline void gen_op_eval_fbul(TCGv dst, TCGv src,
1008 19f329ad blueswir1
                                    unsigned int fcc_offset)
1009 19f329ad blueswir1
{
1010 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1011 19f329ad blueswir1
}
1012 19f329ad blueswir1
1013 19f329ad blueswir1
// 1: FCC0 & !FCC1
1014 19f329ad blueswir1
static inline void gen_op_eval_fbl(TCGv dst, TCGv src,
1015 19f329ad blueswir1
                                    unsigned int fcc_offset)
1016 19f329ad blueswir1
{
1017 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1018 0425bee5 blueswir1
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1019 0425bee5 blueswir1
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1020 0425bee5 blueswir1
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1021 19f329ad blueswir1
}
1022 19f329ad blueswir1
1023 19f329ad blueswir1
// 2 or 3: FCC1
1024 19f329ad blueswir1
static inline void gen_op_eval_fbug(TCGv dst, TCGv src,
1025 19f329ad blueswir1
                                    unsigned int fcc_offset)
1026 19f329ad blueswir1
{
1027 19f329ad blueswir1
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1028 19f329ad blueswir1
}
1029 19f329ad blueswir1
1030 19f329ad blueswir1
// 2: !FCC0 & FCC1
1031 19f329ad blueswir1
static inline void gen_op_eval_fbg(TCGv dst, TCGv src,
1032 19f329ad blueswir1
                                    unsigned int fcc_offset)
1033 19f329ad blueswir1
{
1034 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1035 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
1036 0425bee5 blueswir1
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1037 0425bee5 blueswir1
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1038 19f329ad blueswir1
}
1039 19f329ad blueswir1
1040 19f329ad blueswir1
// 3: FCC0 & FCC1
1041 19f329ad blueswir1
static inline void gen_op_eval_fbu(TCGv dst, TCGv src,
1042 19f329ad blueswir1
                                    unsigned int fcc_offset)
1043 19f329ad blueswir1
{
1044 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1045 0425bee5 blueswir1
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1046 0425bee5 blueswir1
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1047 19f329ad blueswir1
}
1048 19f329ad blueswir1
1049 19f329ad blueswir1
// 0: !(FCC0 | FCC1)
1050 19f329ad blueswir1
static inline void gen_op_eval_fbe(TCGv dst, TCGv src,
1051 19f329ad blueswir1
                                    unsigned int fcc_offset)
1052 19f329ad blueswir1
{
1053 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1054 0425bee5 blueswir1
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1055 0425bee5 blueswir1
    tcg_gen_or_tl(dst, dst, cpu_tmp0);
1056 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
1057 19f329ad blueswir1
}
1058 19f329ad blueswir1
1059 19f329ad blueswir1
// 0 or 3: !(FCC0 ^ FCC1)
1060 19f329ad blueswir1
static inline void gen_op_eval_fbue(TCGv dst, TCGv src,
1061 19f329ad blueswir1
                                    unsigned int fcc_offset)
1062 19f329ad blueswir1
{
1063 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1064 0425bee5 blueswir1
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1065 0425bee5 blueswir1
    tcg_gen_xor_tl(dst, dst, cpu_tmp0);
1066 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
1067 19f329ad blueswir1
}
1068 19f329ad blueswir1
1069 19f329ad blueswir1
// 0 or 2: !FCC0
1070 19f329ad blueswir1
static inline void gen_op_eval_fbge(TCGv dst, TCGv src,
1071 19f329ad blueswir1
                                    unsigned int fcc_offset)
1072 19f329ad blueswir1
{
1073 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1074 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
1075 19f329ad blueswir1
}
1076 19f329ad blueswir1
1077 19f329ad blueswir1
// !1: !(FCC0 & !FCC1)
1078 19f329ad blueswir1
static inline void gen_op_eval_fbuge(TCGv dst, TCGv src,
1079 19f329ad blueswir1
                                    unsigned int fcc_offset)
1080 19f329ad blueswir1
{
1081 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1082 0425bee5 blueswir1
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1083 0425bee5 blueswir1
    tcg_gen_xori_tl(cpu_tmp0, cpu_tmp0, 0x1);
1084 0425bee5 blueswir1
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1085 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
1086 19f329ad blueswir1
}
1087 19f329ad blueswir1
1088 19f329ad blueswir1
// 0 or 1: !FCC1
1089 19f329ad blueswir1
static inline void gen_op_eval_fble(TCGv dst, TCGv src,
1090 19f329ad blueswir1
                                    unsigned int fcc_offset)
1091 19f329ad blueswir1
{
1092 19f329ad blueswir1
    gen_mov_reg_FCC1(dst, src, fcc_offset);
1093 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
1094 19f329ad blueswir1
}
1095 19f329ad blueswir1
1096 19f329ad blueswir1
// !2: !(!FCC0 & FCC1)
1097 19f329ad blueswir1
static inline void gen_op_eval_fbule(TCGv dst, TCGv src,
1098 19f329ad blueswir1
                                    unsigned int fcc_offset)
1099 19f329ad blueswir1
{
1100 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1101 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
1102 0425bee5 blueswir1
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1103 0425bee5 blueswir1
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1104 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
1105 19f329ad blueswir1
}
1106 19f329ad blueswir1
1107 19f329ad blueswir1
// !3: !(FCC0 & FCC1)
1108 19f329ad blueswir1
static inline void gen_op_eval_fbo(TCGv dst, TCGv src,
1109 19f329ad blueswir1
                                    unsigned int fcc_offset)
1110 19f329ad blueswir1
{
1111 19f329ad blueswir1
    gen_mov_reg_FCC0(dst, src, fcc_offset);
1112 0425bee5 blueswir1
    gen_mov_reg_FCC1(cpu_tmp0, src, fcc_offset);
1113 0425bee5 blueswir1
    tcg_gen_and_tl(dst, dst, cpu_tmp0);
1114 19f329ad blueswir1
    tcg_gen_xori_tl(dst, dst, 0x1);
1115 19f329ad blueswir1
}
1116 19f329ad blueswir1
1117 46525e1f blueswir1
static inline void gen_branch2(DisasContext *dc, target_ulong pc1,
1118 19f329ad blueswir1
                               target_ulong pc2, TCGv r_cond)
1119 83469015 bellard
{
1120 83469015 bellard
    int l1;
1121 83469015 bellard
1122 83469015 bellard
    l1 = gen_new_label();
1123 83469015 bellard
1124 0425bee5 blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1125 83469015 bellard
1126 6e256c93 bellard
    gen_goto_tb(dc, 0, pc1, pc1 + 4);
1127 83469015 bellard
1128 83469015 bellard
    gen_set_label(l1);
1129 6e256c93 bellard
    gen_goto_tb(dc, 1, pc2, pc2 + 4);
1130 83469015 bellard
}
1131 83469015 bellard
1132 46525e1f blueswir1
static inline void gen_branch_a(DisasContext *dc, target_ulong pc1,
1133 19f329ad blueswir1
                                target_ulong pc2, TCGv r_cond)
1134 83469015 bellard
{
1135 83469015 bellard
    int l1;
1136 83469015 bellard
1137 83469015 bellard
    l1 = gen_new_label();
1138 83469015 bellard
1139 0425bee5 blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1140 83469015 bellard
1141 6e256c93 bellard
    gen_goto_tb(dc, 0, pc2, pc1);
1142 83469015 bellard
1143 83469015 bellard
    gen_set_label(l1);
1144 6e256c93 bellard
    gen_goto_tb(dc, 1, pc2 + 4, pc2 + 8);
1145 83469015 bellard
}
1146 83469015 bellard
1147 19f329ad blueswir1
static inline void gen_generic_branch(target_ulong npc1, target_ulong npc2,
1148 19f329ad blueswir1
                                      TCGv r_cond)
1149 83469015 bellard
{
1150 83469015 bellard
    int l1, l2;
1151 83469015 bellard
1152 83469015 bellard
    l1 = gen_new_label();
1153 83469015 bellard
    l2 = gen_new_label();
1154 19f329ad blueswir1
1155 0425bee5 blueswir1
    tcg_gen_brcond_tl(TCG_COND_EQ, r_cond, tcg_const_tl(0), l1);
1156 83469015 bellard
1157 2f5680ee blueswir1
    tcg_gen_movi_tl(cpu_npc, npc1);
1158 06b3e1b3 blueswir1
    tcg_gen_br(l2);
1159 83469015 bellard
1160 83469015 bellard
    gen_set_label(l1);
1161 2f5680ee blueswir1
    tcg_gen_movi_tl(cpu_npc, npc2);
1162 83469015 bellard
    gen_set_label(l2);
1163 83469015 bellard
}
1164 83469015 bellard
1165 4af984a7 blueswir1
/* call this function before using the condition register as it may
1166 4af984a7 blueswir1
   have been set for a jump */
1167 4af984a7 blueswir1
static inline void flush_cond(DisasContext *dc, TCGv cond)
1168 83469015 bellard
{
1169 83469015 bellard
    if (dc->npc == JUMP_PC) {
1170 4af984a7 blueswir1
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1171 83469015 bellard
        dc->npc = DYNAMIC_PC;
1172 83469015 bellard
    }
1173 83469015 bellard
}
1174 83469015 bellard
1175 4af984a7 blueswir1
static inline void save_npc(DisasContext *dc, TCGv cond)
1176 72cbca10 bellard
{
1177 72cbca10 bellard
    if (dc->npc == JUMP_PC) {
1178 4af984a7 blueswir1
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1179 72cbca10 bellard
        dc->npc = DYNAMIC_PC;
1180 72cbca10 bellard
    } else if (dc->npc != DYNAMIC_PC) {
1181 2f5680ee blueswir1
        tcg_gen_movi_tl(cpu_npc, dc->npc);
1182 72cbca10 bellard
    }
1183 72cbca10 bellard
}
1184 72cbca10 bellard
1185 4af984a7 blueswir1
static inline void save_state(DisasContext *dc, TCGv cond)
1186 72cbca10 bellard
{
1187 2f5680ee blueswir1
    tcg_gen_movi_tl(cpu_pc, dc->pc);
1188 4af984a7 blueswir1
    save_npc(dc, cond);
1189 72cbca10 bellard
}
1190 72cbca10 bellard
1191 4af984a7 blueswir1
static inline void gen_mov_pc_npc(DisasContext *dc, TCGv cond)
1192 0bee699e bellard
{
1193 0bee699e bellard
    if (dc->npc == JUMP_PC) {
1194 4af984a7 blueswir1
        gen_generic_branch(dc->jump_pc[0], dc->jump_pc[1], cond);
1195 48d5c82b blueswir1
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1196 0bee699e bellard
        dc->pc = DYNAMIC_PC;
1197 0bee699e bellard
    } else if (dc->npc == DYNAMIC_PC) {
1198 48d5c82b blueswir1
        tcg_gen_mov_tl(cpu_pc, cpu_npc);
1199 0bee699e bellard
        dc->pc = DYNAMIC_PC;
1200 0bee699e bellard
    } else {
1201 0bee699e bellard
        dc->pc = dc->npc;
1202 0bee699e bellard
    }
1203 0bee699e bellard
}
1204 0bee699e bellard
1205 38bc628b blueswir1
static inline void gen_op_next_insn(void)
1206 38bc628b blueswir1
{
1207 48d5c82b blueswir1
    tcg_gen_mov_tl(cpu_pc, cpu_npc);
1208 48d5c82b blueswir1
    tcg_gen_addi_tl(cpu_npc, cpu_npc, 4);
1209 38bc628b blueswir1
}
1210 38bc628b blueswir1
1211 19f329ad blueswir1
static inline void gen_cond(TCGv r_dst, unsigned int cc, unsigned int cond)
1212 19f329ad blueswir1
{
1213 19f329ad blueswir1
    TCGv r_src;
1214 3475187d bellard
1215 3475187d bellard
#ifdef TARGET_SPARC64
1216 19f329ad blueswir1
    if (cc)
1217 dc99a3f2 blueswir1
        r_src = cpu_xcc;
1218 19f329ad blueswir1
    else
1219 dc99a3f2 blueswir1
        r_src = cpu_psr;
1220 3475187d bellard
#else
1221 dc99a3f2 blueswir1
    r_src = cpu_psr;
1222 3475187d bellard
#endif
1223 19f329ad blueswir1
    switch (cond) {
1224 19f329ad blueswir1
    case 0x0:
1225 19f329ad blueswir1
        gen_op_eval_bn(r_dst);
1226 19f329ad blueswir1
        break;
1227 19f329ad blueswir1
    case 0x1:
1228 19f329ad blueswir1
        gen_op_eval_be(r_dst, r_src);
1229 19f329ad blueswir1
        break;
1230 19f329ad blueswir1
    case 0x2:
1231 19f329ad blueswir1
        gen_op_eval_ble(r_dst, r_src);
1232 19f329ad blueswir1
        break;
1233 19f329ad blueswir1
    case 0x3:
1234 19f329ad blueswir1
        gen_op_eval_bl(r_dst, r_src);
1235 19f329ad blueswir1
        break;
1236 19f329ad blueswir1
    case 0x4:
1237 19f329ad blueswir1
        gen_op_eval_bleu(r_dst, r_src);
1238 19f329ad blueswir1
        break;
1239 19f329ad blueswir1
    case 0x5:
1240 19f329ad blueswir1
        gen_op_eval_bcs(r_dst, r_src);
1241 19f329ad blueswir1
        break;
1242 19f329ad blueswir1
    case 0x6:
1243 19f329ad blueswir1
        gen_op_eval_bneg(r_dst, r_src);
1244 19f329ad blueswir1
        break;
1245 19f329ad blueswir1
    case 0x7:
1246 19f329ad blueswir1
        gen_op_eval_bvs(r_dst, r_src);
1247 19f329ad blueswir1
        break;
1248 19f329ad blueswir1
    case 0x8:
1249 19f329ad blueswir1
        gen_op_eval_ba(r_dst);
1250 19f329ad blueswir1
        break;
1251 19f329ad blueswir1
    case 0x9:
1252 19f329ad blueswir1
        gen_op_eval_bne(r_dst, r_src);
1253 19f329ad blueswir1
        break;
1254 19f329ad blueswir1
    case 0xa:
1255 19f329ad blueswir1
        gen_op_eval_bg(r_dst, r_src);
1256 19f329ad blueswir1
        break;
1257 19f329ad blueswir1
    case 0xb:
1258 19f329ad blueswir1
        gen_op_eval_bge(r_dst, r_src);
1259 19f329ad blueswir1
        break;
1260 19f329ad blueswir1
    case 0xc:
1261 19f329ad blueswir1
        gen_op_eval_bgu(r_dst, r_src);
1262 19f329ad blueswir1
        break;
1263 19f329ad blueswir1
    case 0xd:
1264 19f329ad blueswir1
        gen_op_eval_bcc(r_dst, r_src);
1265 19f329ad blueswir1
        break;
1266 19f329ad blueswir1
    case 0xe:
1267 19f329ad blueswir1
        gen_op_eval_bpos(r_dst, r_src);
1268 19f329ad blueswir1
        break;
1269 19f329ad blueswir1
    case 0xf:
1270 19f329ad blueswir1
        gen_op_eval_bvc(r_dst, r_src);
1271 19f329ad blueswir1
        break;
1272 19f329ad blueswir1
    }
1273 19f329ad blueswir1
}
1274 7a3f1944 bellard
1275 19f329ad blueswir1
static inline void gen_fcond(TCGv r_dst, unsigned int cc, unsigned int cond)
1276 e8af50a3 bellard
{
1277 19f329ad blueswir1
    unsigned int offset;
1278 19f329ad blueswir1
1279 19f329ad blueswir1
    switch (cc) {
1280 19f329ad blueswir1
    default:
1281 19f329ad blueswir1
    case 0x0:
1282 19f329ad blueswir1
        offset = 0;
1283 19f329ad blueswir1
        break;
1284 19f329ad blueswir1
    case 0x1:
1285 19f329ad blueswir1
        offset = 32 - 10;
1286 19f329ad blueswir1
        break;
1287 19f329ad blueswir1
    case 0x2:
1288 19f329ad blueswir1
        offset = 34 - 10;
1289 19f329ad blueswir1
        break;
1290 19f329ad blueswir1
    case 0x3:
1291 19f329ad blueswir1
        offset = 36 - 10;
1292 19f329ad blueswir1
        break;
1293 19f329ad blueswir1
    }
1294 19f329ad blueswir1
1295 19f329ad blueswir1
    switch (cond) {
1296 19f329ad blueswir1
    case 0x0:
1297 19f329ad blueswir1
        gen_op_eval_bn(r_dst);
1298 19f329ad blueswir1
        break;
1299 19f329ad blueswir1
    case 0x1:
1300 87e92502 blueswir1
        gen_op_eval_fbne(r_dst, cpu_fsr, offset);
1301 19f329ad blueswir1
        break;
1302 19f329ad blueswir1
    case 0x2:
1303 87e92502 blueswir1
        gen_op_eval_fblg(r_dst, cpu_fsr, offset);
1304 19f329ad blueswir1
        break;
1305 19f329ad blueswir1
    case 0x3:
1306 87e92502 blueswir1
        gen_op_eval_fbul(r_dst, cpu_fsr, offset);
1307 19f329ad blueswir1
        break;
1308 19f329ad blueswir1
    case 0x4:
1309 87e92502 blueswir1
        gen_op_eval_fbl(r_dst, cpu_fsr, offset);
1310 19f329ad blueswir1
        break;
1311 19f329ad blueswir1
    case 0x5:
1312 87e92502 blueswir1
        gen_op_eval_fbug(r_dst, cpu_fsr, offset);
1313 19f329ad blueswir1
        break;
1314 19f329ad blueswir1
    case 0x6:
1315 87e92502 blueswir1
        gen_op_eval_fbg(r_dst, cpu_fsr, offset);
1316 19f329ad blueswir1
        break;
1317 19f329ad blueswir1
    case 0x7:
1318 87e92502 blueswir1
        gen_op_eval_fbu(r_dst, cpu_fsr, offset);
1319 19f329ad blueswir1
        break;
1320 19f329ad blueswir1
    case 0x8:
1321 19f329ad blueswir1
        gen_op_eval_ba(r_dst);
1322 19f329ad blueswir1
        break;
1323 19f329ad blueswir1
    case 0x9:
1324 87e92502 blueswir1
        gen_op_eval_fbe(r_dst, cpu_fsr, offset);
1325 19f329ad blueswir1
        break;
1326 19f329ad blueswir1
    case 0xa:
1327 87e92502 blueswir1
        gen_op_eval_fbue(r_dst, cpu_fsr, offset);
1328 19f329ad blueswir1
        break;
1329 19f329ad blueswir1
    case 0xb:
1330 87e92502 blueswir1
        gen_op_eval_fbge(r_dst, cpu_fsr, offset);
1331 19f329ad blueswir1
        break;
1332 19f329ad blueswir1
    case 0xc:
1333 87e92502 blueswir1
        gen_op_eval_fbuge(r_dst, cpu_fsr, offset);
1334 19f329ad blueswir1
        break;
1335 19f329ad blueswir1
    case 0xd:
1336 87e92502 blueswir1
        gen_op_eval_fble(r_dst, cpu_fsr, offset);
1337 19f329ad blueswir1
        break;
1338 19f329ad blueswir1
    case 0xe:
1339 87e92502 blueswir1
        gen_op_eval_fbule(r_dst, cpu_fsr, offset);
1340 19f329ad blueswir1
        break;
1341 19f329ad blueswir1
    case 0xf:
1342 87e92502 blueswir1
        gen_op_eval_fbo(r_dst, cpu_fsr, offset);
1343 19f329ad blueswir1
        break;
1344 19f329ad blueswir1
    }
1345 e8af50a3 bellard
}
1346 00f219bf blueswir1
1347 19f329ad blueswir1
#ifdef TARGET_SPARC64
1348 00f219bf blueswir1
// Inverted logic
1349 00f219bf blueswir1
static const int gen_tcg_cond_reg[8] = {
1350 00f219bf blueswir1
    -1,
1351 00f219bf blueswir1
    TCG_COND_NE,
1352 00f219bf blueswir1
    TCG_COND_GT,
1353 00f219bf blueswir1
    TCG_COND_GE,
1354 00f219bf blueswir1
    -1,
1355 00f219bf blueswir1
    TCG_COND_EQ,
1356 00f219bf blueswir1
    TCG_COND_LE,
1357 00f219bf blueswir1
    TCG_COND_LT,
1358 00f219bf blueswir1
};
1359 19f329ad blueswir1
1360 4af984a7 blueswir1
static inline void gen_cond_reg(TCGv r_dst, int cond, TCGv r_src)
1361 19f329ad blueswir1
{
1362 19f329ad blueswir1
    int l1;
1363 19f329ad blueswir1
1364 19f329ad blueswir1
    l1 = gen_new_label();
1365 0425bee5 blueswir1
    tcg_gen_movi_tl(r_dst, 0);
1366 4af984a7 blueswir1
    tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], r_src, tcg_const_tl(0), l1);
1367 19f329ad blueswir1
    tcg_gen_movi_tl(r_dst, 1);
1368 19f329ad blueswir1
    gen_set_label(l1);
1369 19f329ad blueswir1
}
1370 3475187d bellard
#endif
1371 cf495bcf bellard
1372 0bee699e bellard
/* XXX: potentially incorrect if dynamic npc */
1373 4af984a7 blueswir1
static void do_branch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1374 4af984a7 blueswir1
                      TCGv r_cond)
1375 7a3f1944 bellard
{
1376 cf495bcf bellard
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1377 af7bf89b bellard
    target_ulong target = dc->pc + offset;
1378 5fafdf24 ths
1379 cf495bcf bellard
    if (cond == 0x0) {
1380 0f8a249a blueswir1
        /* unconditional not taken */
1381 0f8a249a blueswir1
        if (a) {
1382 0f8a249a blueswir1
            dc->pc = dc->npc + 4;
1383 0f8a249a blueswir1
            dc->npc = dc->pc + 4;
1384 0f8a249a blueswir1
        } else {
1385 0f8a249a blueswir1
            dc->pc = dc->npc;
1386 0f8a249a blueswir1
            dc->npc = dc->pc + 4;
1387 0f8a249a blueswir1
        }
1388 cf495bcf bellard
    } else if (cond == 0x8) {
1389 0f8a249a blueswir1
        /* unconditional taken */
1390 0f8a249a blueswir1
        if (a) {
1391 0f8a249a blueswir1
            dc->pc = target;
1392 0f8a249a blueswir1
            dc->npc = dc->pc + 4;
1393 0f8a249a blueswir1
        } else {
1394 0f8a249a blueswir1
            dc->pc = dc->npc;
1395 0f8a249a blueswir1
            dc->npc = target;
1396 0f8a249a blueswir1
        }
1397 cf495bcf bellard
    } else {
1398 4af984a7 blueswir1
        flush_cond(dc, r_cond);
1399 4af984a7 blueswir1
        gen_cond(r_cond, cc, cond);
1400 0f8a249a blueswir1
        if (a) {
1401 4af984a7 blueswir1
            gen_branch_a(dc, target, dc->npc, r_cond);
1402 cf495bcf bellard
            dc->is_br = 1;
1403 0f8a249a blueswir1
        } else {
1404 cf495bcf bellard
            dc->pc = dc->npc;
1405 72cbca10 bellard
            dc->jump_pc[0] = target;
1406 72cbca10 bellard
            dc->jump_pc[1] = dc->npc + 4;
1407 72cbca10 bellard
            dc->npc = JUMP_PC;
1408 0f8a249a blueswir1
        }
1409 cf495bcf bellard
    }
1410 7a3f1944 bellard
}
1411 7a3f1944 bellard
1412 0bee699e bellard
/* XXX: potentially incorrect if dynamic npc */
1413 4af984a7 blueswir1
static void do_fbranch(DisasContext *dc, int32_t offset, uint32_t insn, int cc,
1414 4af984a7 blueswir1
                      TCGv r_cond)
1415 e8af50a3 bellard
{
1416 e8af50a3 bellard
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
1417 af7bf89b bellard
    target_ulong target = dc->pc + offset;
1418 af7bf89b bellard
1419 e8af50a3 bellard
    if (cond == 0x0) {
1420 0f8a249a blueswir1
        /* unconditional not taken */
1421 0f8a249a blueswir1
        if (a) {
1422 0f8a249a blueswir1
            dc->pc = dc->npc + 4;
1423 0f8a249a blueswir1
            dc->npc = dc->pc + 4;
1424 0f8a249a blueswir1
        } else {
1425 0f8a249a blueswir1
            dc->pc = dc->npc;
1426 0f8a249a blueswir1
            dc->npc = dc->pc + 4;
1427 0f8a249a blueswir1
        }
1428 e8af50a3 bellard
    } else if (cond == 0x8) {
1429 0f8a249a blueswir1
        /* unconditional taken */
1430 0f8a249a blueswir1
        if (a) {
1431 0f8a249a blueswir1
            dc->pc = target;
1432 0f8a249a blueswir1
            dc->npc = dc->pc + 4;
1433 0f8a249a blueswir1
        } else {
1434 0f8a249a blueswir1
            dc->pc = dc->npc;
1435 0f8a249a blueswir1
            dc->npc = target;
1436 0f8a249a blueswir1
        }
1437 e8af50a3 bellard
    } else {
1438 4af984a7 blueswir1
        flush_cond(dc, r_cond);
1439 4af984a7 blueswir1
        gen_fcond(r_cond, cc, cond);
1440 0f8a249a blueswir1
        if (a) {
1441 4af984a7 blueswir1
            gen_branch_a(dc, target, dc->npc, r_cond);
1442 e8af50a3 bellard
            dc->is_br = 1;
1443 0f8a249a blueswir1
        } else {
1444 e8af50a3 bellard
            dc->pc = dc->npc;
1445 e8af50a3 bellard
            dc->jump_pc[0] = target;
1446 e8af50a3 bellard
            dc->jump_pc[1] = dc->npc + 4;
1447 e8af50a3 bellard
            dc->npc = JUMP_PC;
1448 0f8a249a blueswir1
        }
1449 e8af50a3 bellard
    }
1450 e8af50a3 bellard
}
1451 e8af50a3 bellard
1452 3475187d bellard
#ifdef TARGET_SPARC64
1453 3475187d bellard
/* XXX: potentially incorrect if dynamic npc */
1454 4af984a7 blueswir1
static void do_branch_reg(DisasContext *dc, int32_t offset, uint32_t insn,
1455 4af984a7 blueswir1
                          TCGv r_cond, TCGv r_reg)
1456 7a3f1944 bellard
{
1457 3475187d bellard
    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
1458 3475187d bellard
    target_ulong target = dc->pc + offset;
1459 3475187d bellard
1460 4af984a7 blueswir1
    flush_cond(dc, r_cond);
1461 4af984a7 blueswir1
    gen_cond_reg(r_cond, cond, r_reg);
1462 3475187d bellard
    if (a) {
1463 4af984a7 blueswir1
        gen_branch_a(dc, target, dc->npc, r_cond);
1464 0f8a249a blueswir1
        dc->is_br = 1;
1465 3475187d bellard
    } else {
1466 0f8a249a blueswir1
        dc->pc = dc->npc;
1467 0f8a249a blueswir1
        dc->jump_pc[0] = target;
1468 0f8a249a blueswir1
        dc->jump_pc[1] = dc->npc + 4;
1469 0f8a249a blueswir1
        dc->npc = JUMP_PC;
1470 3475187d bellard
    }
1471 7a3f1944 bellard
}
1472 7a3f1944 bellard
1473 3475187d bellard
static GenOpFunc * const gen_fcmps[4] = {
1474 7e8c2b6c blueswir1
    helper_fcmps,
1475 7e8c2b6c blueswir1
    helper_fcmps_fcc1,
1476 7e8c2b6c blueswir1
    helper_fcmps_fcc2,
1477 7e8c2b6c blueswir1
    helper_fcmps_fcc3,
1478 3475187d bellard
};
1479 3475187d bellard
1480 3475187d bellard
static GenOpFunc * const gen_fcmpd[4] = {
1481 7e8c2b6c blueswir1
    helper_fcmpd,
1482 7e8c2b6c blueswir1
    helper_fcmpd_fcc1,
1483 7e8c2b6c blueswir1
    helper_fcmpd_fcc2,
1484 7e8c2b6c blueswir1
    helper_fcmpd_fcc3,
1485 3475187d bellard
};
1486 417454b0 blueswir1
1487 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
1488 1f587329 blueswir1
static GenOpFunc * const gen_fcmpq[4] = {
1489 7e8c2b6c blueswir1
    helper_fcmpq,
1490 7e8c2b6c blueswir1
    helper_fcmpq_fcc1,
1491 7e8c2b6c blueswir1
    helper_fcmpq_fcc2,
1492 7e8c2b6c blueswir1
    helper_fcmpq_fcc3,
1493 1f587329 blueswir1
};
1494 1f587329 blueswir1
#endif
1495 1f587329 blueswir1
1496 417454b0 blueswir1
static GenOpFunc * const gen_fcmpes[4] = {
1497 7e8c2b6c blueswir1
    helper_fcmpes,
1498 7e8c2b6c blueswir1
    helper_fcmpes_fcc1,
1499 7e8c2b6c blueswir1
    helper_fcmpes_fcc2,
1500 7e8c2b6c blueswir1
    helper_fcmpes_fcc3,
1501 417454b0 blueswir1
};
1502 417454b0 blueswir1
1503 417454b0 blueswir1
static GenOpFunc * const gen_fcmped[4] = {
1504 7e8c2b6c blueswir1
    helper_fcmped,
1505 7e8c2b6c blueswir1
    helper_fcmped_fcc1,
1506 7e8c2b6c blueswir1
    helper_fcmped_fcc2,
1507 7e8c2b6c blueswir1
    helper_fcmped_fcc3,
1508 417454b0 blueswir1
};
1509 417454b0 blueswir1
1510 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
1511 1f587329 blueswir1
static GenOpFunc * const gen_fcmpeq[4] = {
1512 7e8c2b6c blueswir1
    helper_fcmpeq,
1513 7e8c2b6c blueswir1
    helper_fcmpeq_fcc1,
1514 7e8c2b6c blueswir1
    helper_fcmpeq_fcc2,
1515 7e8c2b6c blueswir1
    helper_fcmpeq_fcc3,
1516 1f587329 blueswir1
};
1517 1f587329 blueswir1
#endif
1518 7e8c2b6c blueswir1
1519 7e8c2b6c blueswir1
static inline void gen_op_fcmps(int fccno)
1520 7e8c2b6c blueswir1
{
1521 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(gen_fcmps[fccno]);
1522 7e8c2b6c blueswir1
}
1523 7e8c2b6c blueswir1
1524 7e8c2b6c blueswir1
static inline void gen_op_fcmpd(int fccno)
1525 7e8c2b6c blueswir1
{
1526 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(gen_fcmpd[fccno]);
1527 7e8c2b6c blueswir1
}
1528 7e8c2b6c blueswir1
1529 7e8c2b6c blueswir1
#if defined(CONFIG_USER_ONLY)
1530 7e8c2b6c blueswir1
static inline void gen_op_fcmpq(int fccno)
1531 7e8c2b6c blueswir1
{
1532 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(gen_fcmpq[fccno]);
1533 7e8c2b6c blueswir1
}
1534 7e8c2b6c blueswir1
#endif
1535 7e8c2b6c blueswir1
1536 7e8c2b6c blueswir1
static inline void gen_op_fcmpes(int fccno)
1537 7e8c2b6c blueswir1
{
1538 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(gen_fcmpes[fccno]);
1539 7e8c2b6c blueswir1
}
1540 7e8c2b6c blueswir1
1541 7e8c2b6c blueswir1
static inline void gen_op_fcmped(int fccno)
1542 7e8c2b6c blueswir1
{
1543 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(gen_fcmped[fccno]);
1544 7e8c2b6c blueswir1
}
1545 7e8c2b6c blueswir1
1546 7e8c2b6c blueswir1
#if defined(CONFIG_USER_ONLY)
1547 7e8c2b6c blueswir1
static inline void gen_op_fcmpeq(int fccno)
1548 7e8c2b6c blueswir1
{
1549 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(gen_fcmpeq[fccno]);
1550 7e8c2b6c blueswir1
}
1551 7e8c2b6c blueswir1
#endif
1552 7e8c2b6c blueswir1
1553 7e8c2b6c blueswir1
#else
1554 7e8c2b6c blueswir1
1555 7e8c2b6c blueswir1
static inline void gen_op_fcmps(int fccno)
1556 7e8c2b6c blueswir1
{
1557 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(helper_fcmps);
1558 7e8c2b6c blueswir1
}
1559 7e8c2b6c blueswir1
1560 7e8c2b6c blueswir1
static inline void gen_op_fcmpd(int fccno)
1561 7e8c2b6c blueswir1
{
1562 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(helper_fcmpd);
1563 7e8c2b6c blueswir1
}
1564 7e8c2b6c blueswir1
1565 7e8c2b6c blueswir1
#if defined(CONFIG_USER_ONLY)
1566 7e8c2b6c blueswir1
static inline void gen_op_fcmpq(int fccno)
1567 7e8c2b6c blueswir1
{
1568 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(helper_fcmpq);
1569 7e8c2b6c blueswir1
}
1570 7e8c2b6c blueswir1
#endif
1571 7e8c2b6c blueswir1
1572 7e8c2b6c blueswir1
static inline void gen_op_fcmpes(int fccno)
1573 7e8c2b6c blueswir1
{
1574 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(helper_fcmpes);
1575 7e8c2b6c blueswir1
}
1576 7e8c2b6c blueswir1
1577 7e8c2b6c blueswir1
static inline void gen_op_fcmped(int fccno)
1578 7e8c2b6c blueswir1
{
1579 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(helper_fcmped);
1580 7e8c2b6c blueswir1
}
1581 7e8c2b6c blueswir1
1582 7e8c2b6c blueswir1
#if defined(CONFIG_USER_ONLY)
1583 7e8c2b6c blueswir1
static inline void gen_op_fcmpeq(int fccno)
1584 7e8c2b6c blueswir1
{
1585 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(helper_fcmpeq);
1586 7e8c2b6c blueswir1
}
1587 7e8c2b6c blueswir1
#endif
1588 7e8c2b6c blueswir1
1589 3475187d bellard
#endif
1590 3475187d bellard
1591 134d77a1 blueswir1
static inline void gen_op_fpexception_im(int fsr_flags)
1592 134d77a1 blueswir1
{
1593 87e92502 blueswir1
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~FSR_FTT_MASK);
1594 87e92502 blueswir1
    tcg_gen_ori_tl(cpu_fsr, cpu_fsr, fsr_flags);
1595 2f5680ee blueswir1
    tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_FP_EXCP));
1596 134d77a1 blueswir1
}
1597 134d77a1 blueswir1
1598 4af984a7 blueswir1
static int gen_trap_ifnofpu(DisasContext *dc, TCGv r_cond)
1599 a80dde08 bellard
{
1600 a80dde08 bellard
#if !defined(CONFIG_USER_ONLY)
1601 a80dde08 bellard
    if (!dc->fpu_enabled) {
1602 4af984a7 blueswir1
        save_state(dc, r_cond);
1603 2f5680ee blueswir1
        tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NFPU_INSN));
1604 a80dde08 bellard
        dc->is_br = 1;
1605 a80dde08 bellard
        return 1;
1606 a80dde08 bellard
    }
1607 a80dde08 bellard
#endif
1608 a80dde08 bellard
    return 0;
1609 a80dde08 bellard
}
1610 a80dde08 bellard
1611 7e8c2b6c blueswir1
static inline void gen_op_clear_ieee_excp_and_FTT(void)
1612 7e8c2b6c blueswir1
{
1613 87e92502 blueswir1
    tcg_gen_andi_tl(cpu_fsr, cpu_fsr, ~(FSR_FTT_MASK | FSR_CEXC_MASK));
1614 7e8c2b6c blueswir1
}
1615 7e8c2b6c blueswir1
1616 7e8c2b6c blueswir1
static inline void gen_clear_float_exceptions(void)
1617 7e8c2b6c blueswir1
{
1618 7e8c2b6c blueswir1
    tcg_gen_helper_0_0(helper_clear_float_exceptions);
1619 7e8c2b6c blueswir1
}
1620 7e8c2b6c blueswir1
1621 1a2fb1c0 blueswir1
/* asi moves */
1622 1a2fb1c0 blueswir1
#ifdef TARGET_SPARC64
1623 0425bee5 blueswir1
static inline TCGv gen_get_asi(int insn, TCGv r_addr)
1624 1a2fb1c0 blueswir1
{
1625 1a2fb1c0 blueswir1
    int asi, offset;
1626 0425bee5 blueswir1
    TCGv r_asi;
1627 1a2fb1c0 blueswir1
1628 1a2fb1c0 blueswir1
    if (IS_IMM) {
1629 0425bee5 blueswir1
        r_asi = tcg_temp_new(TCG_TYPE_I32);
1630 1a2fb1c0 blueswir1
        offset = GET_FIELD(insn, 25, 31);
1631 0425bee5 blueswir1
        tcg_gen_addi_tl(r_addr, r_addr, offset);
1632 0425bee5 blueswir1
        tcg_gen_ld_i32(r_asi, cpu_env, offsetof(CPUSPARCState, asi));
1633 1a2fb1c0 blueswir1
    } else {
1634 1a2fb1c0 blueswir1
        asi = GET_FIELD(insn, 19, 26);
1635 0425bee5 blueswir1
        r_asi = tcg_const_i32(asi);
1636 1a2fb1c0 blueswir1
    }
1637 0425bee5 blueswir1
    return r_asi;
1638 0425bee5 blueswir1
}
1639 0425bee5 blueswir1
1640 4af984a7 blueswir1
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1641 0425bee5 blueswir1
{
1642 0425bee5 blueswir1
    TCGv r_asi;
1643 0425bee5 blueswir1
1644 4af984a7 blueswir1
    r_asi = gen_get_asi(insn, addr);
1645 4af984a7 blueswir1
    tcg_gen_helper_1_4(helper_ld_asi, dst, addr, r_asi,
1646 0425bee5 blueswir1
                       tcg_const_i32(size), tcg_const_i32(sign));
1647 0425bee5 blueswir1
    tcg_gen_discard_i32(r_asi);
1648 1a2fb1c0 blueswir1
}
1649 1a2fb1c0 blueswir1
1650 4af984a7 blueswir1
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1651 1a2fb1c0 blueswir1
{
1652 0425bee5 blueswir1
    TCGv r_asi;
1653 1a2fb1c0 blueswir1
1654 4af984a7 blueswir1
    r_asi = gen_get_asi(insn, addr);
1655 4af984a7 blueswir1
    tcg_gen_helper_0_4(helper_st_asi, addr, src, r_asi, tcg_const_i32(size));
1656 0425bee5 blueswir1
    tcg_gen_discard_i32(r_asi);
1657 1a2fb1c0 blueswir1
}
1658 1a2fb1c0 blueswir1
1659 4af984a7 blueswir1
static inline void gen_ldf_asi(TCGv addr, int insn, int size, int rd)
1660 1a2fb1c0 blueswir1
{
1661 0425bee5 blueswir1
    TCGv r_asi;
1662 1a2fb1c0 blueswir1
1663 4af984a7 blueswir1
    r_asi = gen_get_asi(insn, addr);
1664 4af984a7 blueswir1
    tcg_gen_helper_0_4(helper_ldf_asi, addr, r_asi, tcg_const_i32(size),
1665 0425bee5 blueswir1
                       tcg_const_i32(rd));
1666 0425bee5 blueswir1
    tcg_gen_discard_i32(r_asi);
1667 1a2fb1c0 blueswir1
}
1668 1a2fb1c0 blueswir1
1669 4af984a7 blueswir1
static inline void gen_stf_asi(TCGv addr, int insn, int size, int rd)
1670 1a2fb1c0 blueswir1
{
1671 0425bee5 blueswir1
    TCGv r_asi;
1672 1a2fb1c0 blueswir1
1673 31741a27 blueswir1
    r_asi = gen_get_asi(insn, addr);
1674 31741a27 blueswir1
    tcg_gen_helper_0_4(helper_stf_asi, addr, r_asi, tcg_const_i32(size),
1675 0425bee5 blueswir1
                       tcg_const_i32(rd));
1676 0425bee5 blueswir1
    tcg_gen_discard_i32(r_asi);
1677 1a2fb1c0 blueswir1
}
1678 1a2fb1c0 blueswir1
1679 4af984a7 blueswir1
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1680 1a2fb1c0 blueswir1
{
1681 0425bee5 blueswir1
    TCGv r_temp, r_asi;
1682 1a2fb1c0 blueswir1
1683 1a2fb1c0 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_I32);
1684 4af984a7 blueswir1
    r_asi = gen_get_asi(insn, addr);
1685 4af984a7 blueswir1
    tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, r_asi,
1686 0425bee5 blueswir1
                       tcg_const_i32(4), tcg_const_i32(0));
1687 4af984a7 blueswir1
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, r_asi,
1688 0425bee5 blueswir1
                       tcg_const_i32(4));
1689 4af984a7 blueswir1
    tcg_gen_extu_i32_tl(dst, r_temp);
1690 0425bee5 blueswir1
    tcg_gen_discard_i32(r_asi);
1691 0425bee5 blueswir1
    tcg_gen_discard_i32(r_temp);
1692 1a2fb1c0 blueswir1
}
1693 1a2fb1c0 blueswir1
1694 4af984a7 blueswir1
static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1695 1a2fb1c0 blueswir1
{
1696 8911f501 blueswir1
    TCGv r_asi;
1697 1a2fb1c0 blueswir1
1698 4af984a7 blueswir1
    r_asi = gen_get_asi(insn, addr);
1699 4af984a7 blueswir1
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, r_asi,
1700 0425bee5 blueswir1
                       tcg_const_i32(8), tcg_const_i32(0));
1701 4af984a7 blueswir1
    tcg_gen_andi_i64(lo, cpu_tmp64, 0xffffffffULL);
1702 8911f501 blueswir1
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1703 4af984a7 blueswir1
    tcg_gen_andi_i64(hi, cpu_tmp64, 0xffffffffULL);
1704 0425bee5 blueswir1
    tcg_gen_discard_i32(r_asi);
1705 0425bee5 blueswir1
}
1706 0425bee5 blueswir1
1707 4af984a7 blueswir1
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1708 0425bee5 blueswir1
{
1709 8911f501 blueswir1
    TCGv r_temp, r_asi;
1710 0425bee5 blueswir1
1711 0425bee5 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_I32);
1712 0425bee5 blueswir1
    gen_movl_reg_TN(rd + 1, r_temp);
1713 4af984a7 blueswir1
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi,
1714 0425bee5 blueswir1
                       r_temp);
1715 4af984a7 blueswir1
    r_asi = gen_get_asi(insn, addr);
1716 4af984a7 blueswir1
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, r_asi,
1717 0425bee5 blueswir1
                       tcg_const_i32(8));
1718 0425bee5 blueswir1
    tcg_gen_discard_i32(r_asi);
1719 0425bee5 blueswir1
    tcg_gen_discard_i32(r_temp);
1720 1a2fb1c0 blueswir1
}
1721 1a2fb1c0 blueswir1
1722 4af984a7 blueswir1
static inline void gen_cas_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1723 1a2fb1c0 blueswir1
{
1724 1a2fb1c0 blueswir1
    TCGv r_val1, r_asi;
1725 1a2fb1c0 blueswir1
1726 1a2fb1c0 blueswir1
    r_val1 = tcg_temp_new(TCG_TYPE_I32);
1727 1a2fb1c0 blueswir1
    gen_movl_reg_TN(rd, r_val1);
1728 4af984a7 blueswir1
    r_asi = gen_get_asi(insn, addr);
1729 4af984a7 blueswir1
    tcg_gen_helper_1_4(helper_cas_asi, dst, addr, r_val1, val2, r_asi);
1730 0425bee5 blueswir1
    tcg_gen_discard_i32(r_asi);
1731 0425bee5 blueswir1
    tcg_gen_discard_i32(r_val1);
1732 1a2fb1c0 blueswir1
}
1733 1a2fb1c0 blueswir1
1734 4af984a7 blueswir1
static inline void gen_casx_asi(TCGv dst, TCGv addr, TCGv val2, int insn, int rd)
1735 1a2fb1c0 blueswir1
{
1736 8911f501 blueswir1
    TCGv r_asi;
1737 1a2fb1c0 blueswir1
1738 8911f501 blueswir1
    gen_movl_reg_TN(rd, cpu_tmp64);
1739 4af984a7 blueswir1
    r_asi = gen_get_asi(insn, addr);
1740 4af984a7 blueswir1
    tcg_gen_helper_1_4(helper_casx_asi, dst, addr, cpu_tmp64, val2, r_asi);
1741 0425bee5 blueswir1
    tcg_gen_discard_i32(r_asi);
1742 1a2fb1c0 blueswir1
}
1743 1a2fb1c0 blueswir1
1744 1a2fb1c0 blueswir1
#elif !defined(CONFIG_USER_ONLY)
1745 1a2fb1c0 blueswir1
1746 4af984a7 blueswir1
static inline void gen_ld_asi(TCGv dst, TCGv addr, int insn, int size, int sign)
1747 1a2fb1c0 blueswir1
{
1748 1a2fb1c0 blueswir1
    int asi;
1749 1a2fb1c0 blueswir1
1750 1a2fb1c0 blueswir1
    asi = GET_FIELD(insn, 19, 26);
1751 4af984a7 blueswir1
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1752 0425bee5 blueswir1
                       tcg_const_i32(size), tcg_const_i32(sign));
1753 4af984a7 blueswir1
    tcg_gen_trunc_i64_tl(dst, cpu_tmp64);
1754 1a2fb1c0 blueswir1
}
1755 1a2fb1c0 blueswir1
1756 4af984a7 blueswir1
static inline void gen_st_asi(TCGv src, TCGv addr, int insn, int size)
1757 1a2fb1c0 blueswir1
{
1758 1a2fb1c0 blueswir1
    int asi;
1759 1a2fb1c0 blueswir1
1760 4af984a7 blueswir1
    tcg_gen_extu_tl_i64(cpu_tmp64, src);
1761 1a2fb1c0 blueswir1
    asi = GET_FIELD(insn, 19, 26);
1762 4af984a7 blueswir1
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1763 0425bee5 blueswir1
                       tcg_const_i32(size));
1764 1a2fb1c0 blueswir1
}
1765 1a2fb1c0 blueswir1
1766 4af984a7 blueswir1
static inline void gen_swap_asi(TCGv dst, TCGv addr, int insn)
1767 1a2fb1c0 blueswir1
{
1768 1a2fb1c0 blueswir1
    int asi;
1769 0425bee5 blueswir1
    TCGv r_temp;
1770 1a2fb1c0 blueswir1
1771 1a2fb1c0 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_I32);
1772 1a2fb1c0 blueswir1
    asi = GET_FIELD(insn, 19, 26);
1773 4af984a7 blueswir1
    tcg_gen_helper_1_4(helper_ld_asi, r_temp, addr, tcg_const_i32(asi),
1774 0425bee5 blueswir1
                       tcg_const_i32(4), tcg_const_i32(0));
1775 4af984a7 blueswir1
    tcg_gen_helper_0_4(helper_st_asi, addr, dst, tcg_const_i32(asi),
1776 0425bee5 blueswir1
                       tcg_const_i32(4));
1777 4af984a7 blueswir1
    tcg_gen_extu_i32_tl(dst, r_temp);
1778 0425bee5 blueswir1
    tcg_gen_discard_i32(r_temp);
1779 1a2fb1c0 blueswir1
}
1780 1a2fb1c0 blueswir1
1781 4af984a7 blueswir1
static inline void gen_ldda_asi(TCGv lo, TCGv hi, TCGv addr, int insn)
1782 1a2fb1c0 blueswir1
{
1783 1a2fb1c0 blueswir1
    int asi;
1784 1a2fb1c0 blueswir1
1785 1a2fb1c0 blueswir1
    asi = GET_FIELD(insn, 19, 26);
1786 4af984a7 blueswir1
    tcg_gen_helper_1_4(helper_ld_asi, cpu_tmp64, addr, tcg_const_i32(asi),
1787 0425bee5 blueswir1
                       tcg_const_i32(8), tcg_const_i32(0));
1788 4af984a7 blueswir1
    tcg_gen_trunc_i64_tl(lo, cpu_tmp64);
1789 8911f501 blueswir1
    tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
1790 4af984a7 blueswir1
    tcg_gen_trunc_i64_tl(hi, cpu_tmp64);
1791 0425bee5 blueswir1
}
1792 0425bee5 blueswir1
1793 4af984a7 blueswir1
static inline void gen_stda_asi(TCGv hi, TCGv addr, int insn, int rd)
1794 0425bee5 blueswir1
{
1795 0425bee5 blueswir1
    int asi;
1796 8911f501 blueswir1
    TCGv r_temp;
1797 0425bee5 blueswir1
1798 0425bee5 blueswir1
    r_temp = tcg_temp_new(TCG_TYPE_I32);
1799 0425bee5 blueswir1
    gen_movl_reg_TN(rd + 1, r_temp);
1800 4af984a7 blueswir1
    tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, hi, r_temp);
1801 0425bee5 blueswir1
    asi = GET_FIELD(insn, 19, 26);
1802 4af984a7 blueswir1
    tcg_gen_helper_0_4(helper_st_asi, addr, cpu_tmp64, tcg_const_i32(asi),
1803 0425bee5 blueswir1
                       tcg_const_i32(8));
1804 1a2fb1c0 blueswir1
}
1805 1a2fb1c0 blueswir1
#endif
1806 1a2fb1c0 blueswir1
1807 1a2fb1c0 blueswir1
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
1808 4af984a7 blueswir1
static inline void gen_ldstub_asi(TCGv dst, TCGv addr, int insn)
1809 1a2fb1c0 blueswir1
{
1810 1a2fb1c0 blueswir1
    int asi;
1811 1a2fb1c0 blueswir1
1812 4af984a7 blueswir1
    gen_ld_asi(dst, addr, insn, 1, 0);
1813 1a2fb1c0 blueswir1
1814 1a2fb1c0 blueswir1
    asi = GET_FIELD(insn, 19, 26);
1815 4af984a7 blueswir1
    tcg_gen_helper_0_4(helper_st_asi, addr, tcg_const_i64(0xffULL),
1816 0425bee5 blueswir1
                       tcg_const_i32(asi), tcg_const_i32(1));
1817 1a2fb1c0 blueswir1
}
1818 1a2fb1c0 blueswir1
#endif
1819 1a2fb1c0 blueswir1
1820 9322a4bf blueswir1
static inline TCGv get_src1(unsigned int insn, TCGv def)
1821 9322a4bf blueswir1
{
1822 9322a4bf blueswir1
    TCGv r_rs1 = def;
1823 9322a4bf blueswir1
    unsigned int rs1;
1824 9322a4bf blueswir1
1825 9322a4bf blueswir1
    rs1 = GET_FIELD(insn, 13, 17);
1826 9322a4bf blueswir1
    if (rs1 == 0)
1827 9322a4bf blueswir1
        //r_rs1 = tcg_const_tl(0);
1828 9322a4bf blueswir1
        tcg_gen_movi_tl(def, 0);
1829 9322a4bf blueswir1
    else if (rs1 < 8)
1830 9322a4bf blueswir1
        //r_rs1 = cpu_gregs[rs1];
1831 9322a4bf blueswir1
        tcg_gen_mov_tl(def, cpu_gregs[rs1]);
1832 9322a4bf blueswir1
    else
1833 9322a4bf blueswir1
        tcg_gen_ld_tl(def, cpu_regwptr, (rs1 - 8) * sizeof(target_ulong));
1834 9322a4bf blueswir1
    return r_rs1;
1835 9322a4bf blueswir1
}
1836 9322a4bf blueswir1
1837 0bee699e bellard
/* before an instruction, dc->pc must be static */
1838 cf495bcf bellard
static void disas_sparc_insn(DisasContext * dc)
1839 cf495bcf bellard
{
1840 cf495bcf bellard
    unsigned int insn, opc, rs1, rs2, rd;
1841 7a3f1944 bellard
1842 0fa85d43 bellard
    insn = ldl_code(dc->pc);
1843 cf495bcf bellard
    opc = GET_FIELD(insn, 0, 1);
1844 7a3f1944 bellard
1845 cf495bcf bellard
    rd = GET_FIELD(insn, 2, 6);
1846 6ae20372 blueswir1
1847 6ae20372 blueswir1
    cpu_dst = cpu_T[0];
1848 6ae20372 blueswir1
    cpu_src1 = cpu_T[0]; // const
1849 6ae20372 blueswir1
    cpu_src2 = cpu_T[1]; // const
1850 6ae20372 blueswir1
1851 6ae20372 blueswir1
    // loads and stores
1852 6ae20372 blueswir1
    cpu_addr = cpu_T[0];
1853 6ae20372 blueswir1
    cpu_val = cpu_T[1];
1854 6ae20372 blueswir1
1855 cf495bcf bellard
    switch (opc) {
1856 0f8a249a blueswir1
    case 0:                     /* branches/sethi */
1857 0f8a249a blueswir1
        {
1858 0f8a249a blueswir1
            unsigned int xop = GET_FIELD(insn, 7, 9);
1859 0f8a249a blueswir1
            int32_t target;
1860 0f8a249a blueswir1
            switch (xop) {
1861 3475187d bellard
#ifdef TARGET_SPARC64
1862 0f8a249a blueswir1
            case 0x1:           /* V9 BPcc */
1863 0f8a249a blueswir1
                {
1864 0f8a249a blueswir1
                    int cc;
1865 0f8a249a blueswir1
1866 0f8a249a blueswir1
                    target = GET_FIELD_SP(insn, 0, 18);
1867 0f8a249a blueswir1
                    target = sign_extend(target, 18);
1868 0f8a249a blueswir1
                    target <<= 2;
1869 0f8a249a blueswir1
                    cc = GET_FIELD_SP(insn, 20, 21);
1870 0f8a249a blueswir1
                    if (cc == 0)
1871 6ae20372 blueswir1
                        do_branch(dc, target, insn, 0, cpu_cond);
1872 0f8a249a blueswir1
                    else if (cc == 2)
1873 6ae20372 blueswir1
                        do_branch(dc, target, insn, 1, cpu_cond);
1874 0f8a249a blueswir1
                    else
1875 0f8a249a blueswir1
                        goto illegal_insn;
1876 0f8a249a blueswir1
                    goto jmp_insn;
1877 0f8a249a blueswir1
                }
1878 0f8a249a blueswir1
            case 0x3:           /* V9 BPr */
1879 0f8a249a blueswir1
                {
1880 0f8a249a blueswir1
                    target = GET_FIELD_SP(insn, 0, 13) |
1881 13846e70 bellard
                        (GET_FIELD_SP(insn, 20, 21) << 14);
1882 0f8a249a blueswir1
                    target = sign_extend(target, 16);
1883 0f8a249a blueswir1
                    target <<= 2;
1884 9322a4bf blueswir1
                    cpu_src1 = get_src1(insn, cpu_src1);
1885 6ae20372 blueswir1
                    do_branch_reg(dc, target, insn, cpu_cond, cpu_src1);
1886 0f8a249a blueswir1
                    goto jmp_insn;
1887 0f8a249a blueswir1
                }
1888 0f8a249a blueswir1
            case 0x5:           /* V9 FBPcc */
1889 0f8a249a blueswir1
                {
1890 0f8a249a blueswir1
                    int cc = GET_FIELD_SP(insn, 20, 21);
1891 6ae20372 blueswir1
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1892 a80dde08 bellard
                        goto jmp_insn;
1893 0f8a249a blueswir1
                    target = GET_FIELD_SP(insn, 0, 18);
1894 0f8a249a blueswir1
                    target = sign_extend(target, 19);
1895 0f8a249a blueswir1
                    target <<= 2;
1896 6ae20372 blueswir1
                    do_fbranch(dc, target, insn, cc, cpu_cond);
1897 0f8a249a blueswir1
                    goto jmp_insn;
1898 0f8a249a blueswir1
                }
1899 a4d17f19 blueswir1
#else
1900 0f8a249a blueswir1
            case 0x7:           /* CBN+x */
1901 0f8a249a blueswir1
                {
1902 0f8a249a blueswir1
                    goto ncp_insn;
1903 0f8a249a blueswir1
                }
1904 0f8a249a blueswir1
#endif
1905 0f8a249a blueswir1
            case 0x2:           /* BN+x */
1906 0f8a249a blueswir1
                {
1907 0f8a249a blueswir1
                    target = GET_FIELD(insn, 10, 31);
1908 0f8a249a blueswir1
                    target = sign_extend(target, 22);
1909 0f8a249a blueswir1
                    target <<= 2;
1910 6ae20372 blueswir1
                    do_branch(dc, target, insn, 0, cpu_cond);
1911 0f8a249a blueswir1
                    goto jmp_insn;
1912 0f8a249a blueswir1
                }
1913 0f8a249a blueswir1
            case 0x6:           /* FBN+x */
1914 0f8a249a blueswir1
                {
1915 6ae20372 blueswir1
                    if (gen_trap_ifnofpu(dc, cpu_cond))
1916 a80dde08 bellard
                        goto jmp_insn;
1917 0f8a249a blueswir1
                    target = GET_FIELD(insn, 10, 31);
1918 0f8a249a blueswir1
                    target = sign_extend(target, 22);
1919 0f8a249a blueswir1
                    target <<= 2;
1920 6ae20372 blueswir1
                    do_fbranch(dc, target, insn, 0, cpu_cond);
1921 0f8a249a blueswir1
                    goto jmp_insn;
1922 0f8a249a blueswir1
                }
1923 0f8a249a blueswir1
            case 0x4:           /* SETHI */
1924 e80cfcfc bellard
#define OPTIM
1925 e80cfcfc bellard
#if defined(OPTIM)
1926 0f8a249a blueswir1
                if (rd) { // nop
1927 e80cfcfc bellard
#endif
1928 0f8a249a blueswir1
                    uint32_t value = GET_FIELD(insn, 10, 31);
1929 6ae20372 blueswir1
                    tcg_gen_movi_tl(cpu_dst, value << 10);
1930 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
1931 e80cfcfc bellard
#if defined(OPTIM)
1932 0f8a249a blueswir1
                }
1933 e80cfcfc bellard
#endif
1934 0f8a249a blueswir1
                break;
1935 0f8a249a blueswir1
            case 0x0:           /* UNIMPL */
1936 0f8a249a blueswir1
            default:
1937 3475187d bellard
                goto illegal_insn;
1938 0f8a249a blueswir1
            }
1939 0f8a249a blueswir1
            break;
1940 0f8a249a blueswir1
        }
1941 0f8a249a blueswir1
        break;
1942 cf495bcf bellard
    case 1:
1943 0f8a249a blueswir1
        /*CALL*/ {
1944 0f8a249a blueswir1
            target_long target = GET_FIELDs(insn, 2, 31) << 2;
1945 cf495bcf bellard
1946 48d5c82b blueswir1
            gen_movl_TN_reg(15, tcg_const_tl(dc->pc));
1947 0f8a249a blueswir1
            target += dc->pc;
1948 6ae20372 blueswir1
            gen_mov_pc_npc(dc, cpu_cond);
1949 0f8a249a blueswir1
            dc->npc = target;
1950 0f8a249a blueswir1
        }
1951 0f8a249a blueswir1
        goto jmp_insn;
1952 0f8a249a blueswir1
    case 2:                     /* FPU & Logical Operations */
1953 0f8a249a blueswir1
        {
1954 0f8a249a blueswir1
            unsigned int xop = GET_FIELD(insn, 7, 12);
1955 0f8a249a blueswir1
            if (xop == 0x3a) {  /* generate trap */
1956 cf495bcf bellard
                int cond;
1957 3475187d bellard
1958 9322a4bf blueswir1
                cpu_src1 = get_src1(insn, cpu_src1);
1959 0f8a249a blueswir1
                if (IS_IMM) {
1960 0f8a249a blueswir1
                    rs2 = GET_FIELD(insn, 25, 31);
1961 6ae20372 blueswir1
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, rs2);
1962 cf495bcf bellard
                } else {
1963 cf495bcf bellard
                    rs2 = GET_FIELD(insn, 27, 31);
1964 e80cfcfc bellard
#if defined(OPTIM)
1965 0f8a249a blueswir1
                    if (rs2 != 0) {
1966 e80cfcfc bellard
#endif
1967 6ae20372 blueswir1
                        gen_movl_reg_TN(rs2, cpu_src2);
1968 6ae20372 blueswir1
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
1969 e80cfcfc bellard
#if defined(OPTIM)
1970 0f8a249a blueswir1
                    }
1971 e80cfcfc bellard
#endif
1972 cf495bcf bellard
                }
1973 cf495bcf bellard
                cond = GET_FIELD(insn, 3, 6);
1974 cf495bcf bellard
                if (cond == 0x8) {
1975 6ae20372 blueswir1
                    save_state(dc, cpu_cond);
1976 6ae20372 blueswir1
                    tcg_gen_helper_0_1(helper_trap, cpu_dst);
1977 af7bf89b bellard
                } else if (cond != 0) {
1978 748b9d8e blueswir1
                    TCGv r_cond = tcg_temp_new(TCG_TYPE_TL);
1979 3475187d bellard
#ifdef TARGET_SPARC64
1980 0f8a249a blueswir1
                    /* V9 icc/xcc */
1981 0f8a249a blueswir1
                    int cc = GET_FIELD_SP(insn, 11, 12);
1982 748b9d8e blueswir1
1983 6ae20372 blueswir1
                    save_state(dc, cpu_cond);
1984 0f8a249a blueswir1
                    if (cc == 0)
1985 748b9d8e blueswir1
                        gen_cond(r_cond, 0, cond);
1986 0f8a249a blueswir1
                    else if (cc == 2)
1987 748b9d8e blueswir1
                        gen_cond(r_cond, 1, cond);
1988 0f8a249a blueswir1
                    else
1989 0f8a249a blueswir1
                        goto illegal_insn;
1990 3475187d bellard
#else
1991 6ae20372 blueswir1
                    save_state(dc, cpu_cond);
1992 748b9d8e blueswir1
                    gen_cond(r_cond, 0, cond);
1993 3475187d bellard
#endif
1994 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_trapcc, cpu_dst, r_cond);
1995 0425bee5 blueswir1
                    tcg_gen_discard_tl(r_cond);
1996 cf495bcf bellard
                }
1997 a80dde08 bellard
                gen_op_next_insn();
1998 57fec1fe bellard
                tcg_gen_exit_tb(0);
1999 a80dde08 bellard
                dc->is_br = 1;
2000 a80dde08 bellard
                goto jmp_insn;
2001 cf495bcf bellard
            } else if (xop == 0x28) {
2002 cf495bcf bellard
                rs1 = GET_FIELD(insn, 13, 17);
2003 cf495bcf bellard
                switch(rs1) {
2004 cf495bcf bellard
                case 0: /* rdy */
2005 65fe7b09 blueswir1
#ifndef TARGET_SPARC64
2006 65fe7b09 blueswir1
                case 0x01 ... 0x0e: /* undefined in the SPARCv8
2007 65fe7b09 blueswir1
                                       manual, rdy on the microSPARC
2008 65fe7b09 blueswir1
                                       II */
2009 65fe7b09 blueswir1
                case 0x0f:          /* stbar in the SPARCv8 manual,
2010 65fe7b09 blueswir1
                                       rdy on the microSPARC II */
2011 65fe7b09 blueswir1
                case 0x10 ... 0x1f: /* implementation-dependent in the
2012 65fe7b09 blueswir1
                                       SPARCv8 manual, rdy on the
2013 65fe7b09 blueswir1
                                       microSPARC II */
2014 65fe7b09 blueswir1
#endif
2015 6ae20372 blueswir1
                    tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
2016 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
2017 cf495bcf bellard
                    break;
2018 3475187d bellard
#ifdef TARGET_SPARC64
2019 0f8a249a blueswir1
                case 0x2: /* V9 rdccr */
2020 6ae20372 blueswir1
                    tcg_gen_helper_1_0(helper_rdccr, cpu_dst);
2021 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
2022 3475187d bellard
                    break;
2023 0f8a249a blueswir1
                case 0x3: /* V9 rdasi */
2024 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
2025 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2026 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
2027 3475187d bellard
                    break;
2028 0f8a249a blueswir1
                case 0x4: /* V9 rdtick */
2029 ccd4a219 blueswir1
                    {
2030 ccd4a219 blueswir1
                        TCGv r_tickptr;
2031 ccd4a219 blueswir1
2032 ccd4a219 blueswir1
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2033 ccd4a219 blueswir1
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2034 ccd4a219 blueswir1
                                       offsetof(CPUState, tick));
2035 6ae20372 blueswir1
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2036 ccd4a219 blueswir1
                                           r_tickptr);
2037 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
2038 0425bee5 blueswir1
                        tcg_gen_discard_ptr(r_tickptr);
2039 ccd4a219 blueswir1
                    }
2040 3475187d bellard
                    break;
2041 0f8a249a blueswir1
                case 0x5: /* V9 rdpc */
2042 6ae20372 blueswir1
                    tcg_gen_movi_tl(cpu_dst, dc->pc);
2043 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
2044 0f8a249a blueswir1
                    break;
2045 0f8a249a blueswir1
                case 0x6: /* V9 rdfprs */
2046 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
2047 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2048 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
2049 3475187d bellard
                    break;
2050 65fe7b09 blueswir1
                case 0xf: /* V9 membar */
2051 65fe7b09 blueswir1
                    break; /* no effect */
2052 0f8a249a blueswir1
                case 0x13: /* Graphics Status */
2053 6ae20372 blueswir1
                    if (gen_trap_ifnofpu(dc, cpu_cond))
2054 725cb90b bellard
                        goto jmp_insn;
2055 6ae20372 blueswir1
                    tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
2056 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
2057 725cb90b bellard
                    break;
2058 0f8a249a blueswir1
                case 0x17: /* Tick compare */
2059 6ae20372 blueswir1
                    tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tick_cmpr));
2060 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
2061 83469015 bellard
                    break;
2062 0f8a249a blueswir1
                case 0x18: /* System tick */
2063 ccd4a219 blueswir1
                    {
2064 ccd4a219 blueswir1
                        TCGv r_tickptr;
2065 ccd4a219 blueswir1
2066 ccd4a219 blueswir1
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2067 ccd4a219 blueswir1
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2068 ccd4a219 blueswir1
                                       offsetof(CPUState, stick));
2069 6ae20372 blueswir1
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2070 ccd4a219 blueswir1
                                           r_tickptr);
2071 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
2072 0425bee5 blueswir1
                        tcg_gen_discard_ptr(r_tickptr);
2073 ccd4a219 blueswir1
                    }
2074 83469015 bellard
                    break;
2075 0f8a249a blueswir1
                case 0x19: /* System tick compare */
2076 6ae20372 blueswir1
                    tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, stick_cmpr));
2077 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
2078 83469015 bellard
                    break;
2079 0f8a249a blueswir1
                case 0x10: /* Performance Control */
2080 0f8a249a blueswir1
                case 0x11: /* Performance Instrumentation Counter */
2081 0f8a249a blueswir1
                case 0x12: /* Dispatch Control */
2082 0f8a249a blueswir1
                case 0x14: /* Softint set, WO */
2083 0f8a249a blueswir1
                case 0x15: /* Softint clear, WO */
2084 0f8a249a blueswir1
                case 0x16: /* Softint write */
2085 3475187d bellard
#endif
2086 3475187d bellard
                default:
2087 cf495bcf bellard
                    goto illegal_insn;
2088 cf495bcf bellard
                }
2089 e8af50a3 bellard
#if !defined(CONFIG_USER_ONLY)
2090 e9ebed4d blueswir1
            } else if (xop == 0x29) { /* rdpsr / UA2005 rdhpr */
2091 3475187d bellard
#ifndef TARGET_SPARC64
2092 0f8a249a blueswir1
                if (!supervisor(dc))
2093 0f8a249a blueswir1
                    goto priv_insn;
2094 6ae20372 blueswir1
                tcg_gen_helper_1_0(helper_rdpsr, cpu_dst);
2095 e9ebed4d blueswir1
#else
2096 e9ebed4d blueswir1
                if (!hypervisor(dc))
2097 e9ebed4d blueswir1
                    goto priv_insn;
2098 e9ebed4d blueswir1
                rs1 = GET_FIELD(insn, 13, 17);
2099 e9ebed4d blueswir1
                switch (rs1) {
2100 e9ebed4d blueswir1
                case 0: // hpstate
2101 e9ebed4d blueswir1
                    // gen_op_rdhpstate();
2102 e9ebed4d blueswir1
                    break;
2103 e9ebed4d blueswir1
                case 1: // htstate
2104 e9ebed4d blueswir1
                    // gen_op_rdhtstate();
2105 e9ebed4d blueswir1
                    break;
2106 e9ebed4d blueswir1
                case 3: // hintp
2107 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
2108 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2109 e9ebed4d blueswir1
                    break;
2110 e9ebed4d blueswir1
                case 5: // htba
2111 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
2112 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2113 e9ebed4d blueswir1
                    break;
2114 e9ebed4d blueswir1
                case 6: // hver
2115 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hver));
2116 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2117 e9ebed4d blueswir1
                    break;
2118 e9ebed4d blueswir1
                case 31: // hstick_cmpr
2119 6ae20372 blueswir1
                    tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
2120 2f5680ee blueswir1
                    tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hstick_cmpr));
2121 e9ebed4d blueswir1
                    break;
2122 e9ebed4d blueswir1
                default:
2123 e9ebed4d blueswir1
                    goto illegal_insn;
2124 e9ebed4d blueswir1
                }
2125 e9ebed4d blueswir1
#endif
2126 6ae20372 blueswir1
                gen_movl_TN_reg(rd, cpu_dst);
2127 e8af50a3 bellard
                break;
2128 3475187d bellard
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
2129 0f8a249a blueswir1
                if (!supervisor(dc))
2130 0f8a249a blueswir1
                    goto priv_insn;
2131 3475187d bellard
#ifdef TARGET_SPARC64
2132 3475187d bellard
                rs1 = GET_FIELD(insn, 13, 17);
2133 0f8a249a blueswir1
                switch (rs1) {
2134 0f8a249a blueswir1
                case 0: // tpc
2135 375ee38b blueswir1
                    {
2136 375ee38b blueswir1
                        TCGv r_tsptr;
2137 375ee38b blueswir1
2138 375ee38b blueswir1
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2139 375ee38b blueswir1
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2140 375ee38b blueswir1
                                       offsetof(CPUState, tsptr));
2141 6ae20372 blueswir1
                        tcg_gen_ld_tl(cpu_dst, r_tsptr,
2142 375ee38b blueswir1
                                      offsetof(trap_state, tpc));
2143 0425bee5 blueswir1
                        tcg_gen_discard_ptr(r_tsptr);
2144 375ee38b blueswir1
                    }
2145 0f8a249a blueswir1
                    break;
2146 0f8a249a blueswir1
                case 1: // tnpc
2147 375ee38b blueswir1
                    {
2148 375ee38b blueswir1
                        TCGv r_tsptr;
2149 375ee38b blueswir1
2150 375ee38b blueswir1
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2151 375ee38b blueswir1
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2152 375ee38b blueswir1
                                       offsetof(CPUState, tsptr));
2153 6ae20372 blueswir1
                        tcg_gen_ld_tl(cpu_dst, r_tsptr,
2154 375ee38b blueswir1
                                      offsetof(trap_state, tnpc));
2155 0425bee5 blueswir1
                        tcg_gen_discard_ptr(r_tsptr);
2156 375ee38b blueswir1
                    }
2157 0f8a249a blueswir1
                    break;
2158 0f8a249a blueswir1
                case 2: // tstate
2159 375ee38b blueswir1
                    {
2160 375ee38b blueswir1
                        TCGv r_tsptr;
2161 375ee38b blueswir1
2162 375ee38b blueswir1
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2163 375ee38b blueswir1
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2164 375ee38b blueswir1
                                       offsetof(CPUState, tsptr));
2165 6ae20372 blueswir1
                        tcg_gen_ld_tl(cpu_dst, r_tsptr,
2166 375ee38b blueswir1
                                      offsetof(trap_state, tstate));
2167 0425bee5 blueswir1
                        tcg_gen_discard_ptr(r_tsptr);
2168 375ee38b blueswir1
                    }
2169 0f8a249a blueswir1
                    break;
2170 0f8a249a blueswir1
                case 3: // tt
2171 375ee38b blueswir1
                    {
2172 375ee38b blueswir1
                        TCGv r_tsptr;
2173 375ee38b blueswir1
2174 375ee38b blueswir1
                        r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
2175 375ee38b blueswir1
                        tcg_gen_ld_ptr(r_tsptr, cpu_env,
2176 375ee38b blueswir1
                                       offsetof(CPUState, tsptr));
2177 6ae20372 blueswir1
                        tcg_gen_ld_i32(cpu_dst, r_tsptr,
2178 375ee38b blueswir1
                                       offsetof(trap_state, tt));
2179 0425bee5 blueswir1
                        tcg_gen_discard_ptr(r_tsptr);
2180 375ee38b blueswir1
                    }
2181 0f8a249a blueswir1
                    break;
2182 0f8a249a blueswir1
                case 4: // tick
2183 ccd4a219 blueswir1
                    {
2184 ccd4a219 blueswir1
                        TCGv r_tickptr;
2185 ccd4a219 blueswir1
2186 ccd4a219 blueswir1
                        r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
2187 ccd4a219 blueswir1
                        tcg_gen_ld_ptr(r_tickptr, cpu_env,
2188 ccd4a219 blueswir1
                                       offsetof(CPUState, tick));
2189 6ae20372 blueswir1
                        tcg_gen_helper_1_1(helper_tick_get_count, cpu_dst,
2190 ccd4a219 blueswir1
                                           r_tickptr);
2191 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
2192 0425bee5 blueswir1
                        tcg_gen_discard_ptr(r_tickptr);
2193 ccd4a219 blueswir1
                    }
2194 0f8a249a blueswir1
                    break;
2195 0f8a249a blueswir1
                case 5: // tba
2196 6ae20372 blueswir1
                    tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2197 0f8a249a blueswir1
                    break;
2198 0f8a249a blueswir1
                case 6: // pstate
2199 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, pstate));
2200 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2201 0f8a249a blueswir1
                    break;
2202 0f8a249a blueswir1
                case 7: // tl
2203 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
2204 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2205 0f8a249a blueswir1
                    break;
2206 0f8a249a blueswir1
                case 8: // pil
2207 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
2208 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2209 0f8a249a blueswir1
                    break;
2210 0f8a249a blueswir1
                case 9: // cwp
2211 6ae20372 blueswir1
                    tcg_gen_helper_1_0(helper_rdcwp, cpu_dst);
2212 0f8a249a blueswir1
                    break;
2213 0f8a249a blueswir1
                case 10: // cansave
2214 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
2215 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2216 0f8a249a blueswir1
                    break;
2217 0f8a249a blueswir1
                case 11: // canrestore
2218 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
2219 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2220 0f8a249a blueswir1
                    break;
2221 0f8a249a blueswir1
                case 12: // cleanwin
2222 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
2223 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2224 0f8a249a blueswir1
                    break;
2225 0f8a249a blueswir1
                case 13: // otherwin
2226 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
2227 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2228 0f8a249a blueswir1
                    break;
2229 0f8a249a blueswir1
                case 14: // wstate
2230 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
2231 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2232 0f8a249a blueswir1
                    break;
2233 e9ebed4d blueswir1
                case 16: // UA2005 gl
2234 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
2235 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2236 e9ebed4d blueswir1
                    break;
2237 e9ebed4d blueswir1
                case 26: // UA2005 strand status
2238 e9ebed4d blueswir1
                    if (!hypervisor(dc))
2239 e9ebed4d blueswir1
                        goto priv_insn;
2240 2f5680ee blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
2241 6ae20372 blueswir1
                    tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2242 e9ebed4d blueswir1
                    break;
2243 0f8a249a blueswir1
                case 31: // ver
2244 6ae20372 blueswir1
                    tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, version));
2245 0f8a249a blueswir1
                    break;
2246 0f8a249a blueswir1
                case 15: // fq
2247 0f8a249a blueswir1
                default:
2248 0f8a249a blueswir1
                    goto illegal_insn;
2249 0f8a249a blueswir1
                }
2250 3475187d bellard
#else
2251 2f5680ee blueswir1
                tcg_gen_ld_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
2252 6ae20372 blueswir1
                tcg_gen_ext_i32_tl(cpu_dst, cpu_tmp32);
2253 3475187d bellard
#endif
2254 6ae20372 blueswir1
                gen_movl_TN_reg(rd, cpu_dst);
2255 e8af50a3 bellard
                break;
2256 3475187d bellard
            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
2257 3475187d bellard
#ifdef TARGET_SPARC64
2258 72a9747b blueswir1
                tcg_gen_helper_0_0(helper_flushw);
2259 3475187d bellard
#else
2260 0f8a249a blueswir1
                if (!supervisor(dc))
2261 0f8a249a blueswir1
                    goto priv_insn;
2262 6ae20372 blueswir1
                tcg_gen_ld_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
2263 6ae20372 blueswir1
                gen_movl_TN_reg(rd, cpu_dst);
2264 3475187d bellard
#endif
2265 e8af50a3 bellard
                break;
2266 e8af50a3 bellard
#endif
2267 0f8a249a blueswir1
            } else if (xop == 0x34) {   /* FPU Operations */
2268 6ae20372 blueswir1
                if (gen_trap_ifnofpu(dc, cpu_cond))
2269 a80dde08 bellard
                    goto jmp_insn;
2270 0f8a249a blueswir1
                gen_op_clear_ieee_excp_and_FTT();
2271 e8af50a3 bellard
                rs1 = GET_FIELD(insn, 13, 17);
2272 0f8a249a blueswir1
                rs2 = GET_FIELD(insn, 27, 31);
2273 0f8a249a blueswir1
                xop = GET_FIELD(insn, 18, 26);
2274 0f8a249a blueswir1
                switch (xop) {
2275 0f8a249a blueswir1
                    case 0x1: /* fmovs */
2276 0f8a249a blueswir1
                        gen_op_load_fpr_FT0(rs2);
2277 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2278 0f8a249a blueswir1
                        break;
2279 0f8a249a blueswir1
                    case 0x5: /* fnegs */
2280 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2281 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fnegs);
2282 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2283 0f8a249a blueswir1
                        break;
2284 0f8a249a blueswir1
                    case 0x9: /* fabss */
2285 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2286 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_fabss);
2287 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2288 0f8a249a blueswir1
                        break;
2289 0f8a249a blueswir1
                    case 0x29: /* fsqrts */
2290 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2291 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2292 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_fsqrts);
2293 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2294 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2295 0f8a249a blueswir1
                        break;
2296 0f8a249a blueswir1
                    case 0x2a: /* fsqrtd */
2297 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2298 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2299 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_fsqrtd);
2300 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2301 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2302 0f8a249a blueswir1
                        break;
2303 0f8a249a blueswir1
                    case 0x2b: /* fsqrtq */
2304 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2305 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2306 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2307 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_fsqrtq);
2308 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2309 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2310 1f587329 blueswir1
                        break;
2311 1f587329 blueswir1
#else
2312 0f8a249a blueswir1
                        goto nfpu_insn;
2313 1f587329 blueswir1
#endif
2314 0f8a249a blueswir1
                    case 0x41:
2315 0f8a249a blueswir1
                        gen_op_load_fpr_FT0(rs1);
2316 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2317 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2318 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fadds);
2319 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2320 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2321 0f8a249a blueswir1
                        break;
2322 0f8a249a blueswir1
                    case 0x42:
2323 0f8a249a blueswir1
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2324 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2325 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2326 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_faddd);
2327 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2328 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2329 0f8a249a blueswir1
                        break;
2330 0f8a249a blueswir1
                    case 0x43: /* faddq */
2331 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2332 1f587329 blueswir1
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2333 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2334 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2335 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_faddq);
2336 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2337 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2338 1f587329 blueswir1
                        break;
2339 1f587329 blueswir1
#else
2340 0f8a249a blueswir1
                        goto nfpu_insn;
2341 1f587329 blueswir1
#endif
2342 0f8a249a blueswir1
                    case 0x45:
2343 0f8a249a blueswir1
                        gen_op_load_fpr_FT0(rs1);
2344 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2345 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2346 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fsubs);
2347 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2348 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2349 0f8a249a blueswir1
                        break;
2350 0f8a249a blueswir1
                    case 0x46:
2351 0f8a249a blueswir1
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2352 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2353 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2354 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fsubd);
2355 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2356 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2357 0f8a249a blueswir1
                        break;
2358 0f8a249a blueswir1
                    case 0x47: /* fsubq */
2359 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2360 1f587329 blueswir1
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2361 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2362 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2363 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fsubq);
2364 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2365 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2366 1f587329 blueswir1
                        break;
2367 1f587329 blueswir1
#else
2368 0f8a249a blueswir1
                        goto nfpu_insn;
2369 1f587329 blueswir1
#endif
2370 0f8a249a blueswir1
                    case 0x49:
2371 0f8a249a blueswir1
                        gen_op_load_fpr_FT0(rs1);
2372 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2373 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2374 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fmuls);
2375 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2376 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2377 0f8a249a blueswir1
                        break;
2378 0f8a249a blueswir1
                    case 0x4a:
2379 0f8a249a blueswir1
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2380 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2381 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2382 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fmuld);
2383 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2384 2382dc6b blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2385 0f8a249a blueswir1
                        break;
2386 0f8a249a blueswir1
                    case 0x4b: /* fmulq */
2387 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2388 1f587329 blueswir1
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2389 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2390 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2391 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fmulq);
2392 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2393 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2394 1f587329 blueswir1
                        break;
2395 1f587329 blueswir1
#else
2396 0f8a249a blueswir1
                        goto nfpu_insn;
2397 1f587329 blueswir1
#endif
2398 0f8a249a blueswir1
                    case 0x4d:
2399 0f8a249a blueswir1
                        gen_op_load_fpr_FT0(rs1);
2400 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2401 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2402 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fdivs);
2403 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2404 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2405 0f8a249a blueswir1
                        break;
2406 0f8a249a blueswir1
                    case 0x4e:
2407 0f8a249a blueswir1
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2408 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2409 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2410 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fdivd);
2411 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2412 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2413 0f8a249a blueswir1
                        break;
2414 0f8a249a blueswir1
                    case 0x4f: /* fdivq */
2415 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2416 1f587329 blueswir1
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2417 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2418 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2419 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fdivq);
2420 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2421 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2422 1f587329 blueswir1
                        break;
2423 1f587329 blueswir1
#else
2424 0f8a249a blueswir1
                        goto nfpu_insn;
2425 1f587329 blueswir1
#endif
2426 0f8a249a blueswir1
                    case 0x69:
2427 0f8a249a blueswir1
                        gen_op_load_fpr_FT0(rs1);
2428 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2429 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2430 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fsmuld);
2431 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2432 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2433 0f8a249a blueswir1
                        break;
2434 0f8a249a blueswir1
                    case 0x6e: /* fdmulq */
2435 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2436 1f587329 blueswir1
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2437 1f587329 blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2438 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2439 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fdmulq);
2440 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2441 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2442 1f587329 blueswir1
                        break;
2443 1f587329 blueswir1
#else
2444 0f8a249a blueswir1
                        goto nfpu_insn;
2445 1f587329 blueswir1
#endif
2446 0f8a249a blueswir1
                    case 0xc4:
2447 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2448 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2449 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fitos);
2450 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2451 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2452 0f8a249a blueswir1
                        break;
2453 0f8a249a blueswir1
                    case 0xc6:
2454 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2455 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2456 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fdtos);
2457 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2458 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2459 0f8a249a blueswir1
                        break;
2460 0f8a249a blueswir1
                    case 0xc7: /* fqtos */
2461 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2462 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2463 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2464 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fqtos);
2465 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2466 1f587329 blueswir1
                        gen_op_store_FT0_fpr(rd);
2467 1f587329 blueswir1
                        break;
2468 1f587329 blueswir1
#else
2469 0f8a249a blueswir1
                        goto nfpu_insn;
2470 1f587329 blueswir1
#endif
2471 0f8a249a blueswir1
                    case 0xc8:
2472 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2473 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fitod);
2474 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2475 0f8a249a blueswir1
                        break;
2476 0f8a249a blueswir1
                    case 0xc9:
2477 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2478 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fstod);
2479 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2480 0f8a249a blueswir1
                        break;
2481 0f8a249a blueswir1
                    case 0xcb: /* fqtod */
2482 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2483 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2484 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2485 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fqtod);
2486 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2487 1f587329 blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2488 1f587329 blueswir1
                        break;
2489 1f587329 blueswir1
#else
2490 0f8a249a blueswir1
                        goto nfpu_insn;
2491 1f587329 blueswir1
#endif
2492 0f8a249a blueswir1
                    case 0xcc: /* fitoq */
2493 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2494 1f587329 blueswir1
                        gen_op_load_fpr_FT1(rs2);
2495 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fitoq);
2496 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2497 1f587329 blueswir1
                        break;
2498 1f587329 blueswir1
#else
2499 0f8a249a blueswir1
                        goto nfpu_insn;
2500 1f587329 blueswir1
#endif
2501 0f8a249a blueswir1
                    case 0xcd: /* fstoq */
2502 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2503 1f587329 blueswir1
                        gen_op_load_fpr_FT1(rs2);
2504 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fstoq);
2505 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2506 1f587329 blueswir1
                        break;
2507 1f587329 blueswir1
#else
2508 0f8a249a blueswir1
                        goto nfpu_insn;
2509 1f587329 blueswir1
#endif
2510 0f8a249a blueswir1
                    case 0xce: /* fdtoq */
2511 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2512 1f587329 blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2513 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fdtoq);
2514 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2515 1f587329 blueswir1
                        break;
2516 1f587329 blueswir1
#else
2517 0f8a249a blueswir1
                        goto nfpu_insn;
2518 1f587329 blueswir1
#endif
2519 0f8a249a blueswir1
                    case 0xd1:
2520 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2521 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2522 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fstoi);
2523 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2524 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2525 0f8a249a blueswir1
                        break;
2526 0f8a249a blueswir1
                    case 0xd2:
2527 2382dc6b blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2528 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2529 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fdtoi);
2530 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2531 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2532 0f8a249a blueswir1
                        break;
2533 0f8a249a blueswir1
                    case 0xd3: /* fqtoi */
2534 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2535 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2536 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2537 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fqtoi);
2538 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2539 1f587329 blueswir1
                        gen_op_store_FT0_fpr(rd);
2540 1f587329 blueswir1
                        break;
2541 1f587329 blueswir1
#else
2542 0f8a249a blueswir1
                        goto nfpu_insn;
2543 1f587329 blueswir1
#endif
2544 3475187d bellard
#ifdef TARGET_SPARC64
2545 0f8a249a blueswir1
                    case 0x2: /* V9 fmovd */
2546 0f8a249a blueswir1
                        gen_op_load_fpr_DT0(DFPREG(rs2));
2547 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2548 0f8a249a blueswir1
                        break;
2549 1f587329 blueswir1
                    case 0x3: /* V9 fmovq */
2550 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2551 1f587329 blueswir1
                        gen_op_load_fpr_QT0(QFPREG(rs2));
2552 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2553 1f587329 blueswir1
                        break;
2554 1f587329 blueswir1
#else
2555 1f587329 blueswir1
                        goto nfpu_insn;
2556 1f587329 blueswir1
#endif
2557 0f8a249a blueswir1
                    case 0x6: /* V9 fnegd */
2558 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2559 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fnegd);
2560 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2561 0f8a249a blueswir1
                        break;
2562 1f587329 blueswir1
                    case 0x7: /* V9 fnegq */
2563 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2564 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2565 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fnegq);
2566 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2567 1f587329 blueswir1
                        break;
2568 1f587329 blueswir1
#else
2569 1f587329 blueswir1
                        goto nfpu_insn;
2570 1f587329 blueswir1
#endif
2571 0f8a249a blueswir1
                    case 0xa: /* V9 fabsd */
2572 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2573 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_fabsd);
2574 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2575 0f8a249a blueswir1
                        break;
2576 1f587329 blueswir1
                    case 0xb: /* V9 fabsq */
2577 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2578 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2579 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_fabsq);
2580 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2581 1f587329 blueswir1
                        break;
2582 1f587329 blueswir1
#else
2583 1f587329 blueswir1
                        goto nfpu_insn;
2584 1f587329 blueswir1
#endif
2585 0f8a249a blueswir1
                    case 0x81: /* V9 fstox */
2586 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2587 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2588 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fstox);
2589 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2590 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2591 0f8a249a blueswir1
                        break;
2592 0f8a249a blueswir1
                    case 0x82: /* V9 fdtox */
2593 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2594 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2595 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fdtox);
2596 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2597 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2598 0f8a249a blueswir1
                        break;
2599 1f587329 blueswir1
                    case 0x83: /* V9 fqtox */
2600 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2601 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2602 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2603 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fqtox);
2604 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2605 1f587329 blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2606 1f587329 blueswir1
                        break;
2607 1f587329 blueswir1
#else
2608 1f587329 blueswir1
                        goto nfpu_insn;
2609 1f587329 blueswir1
#endif
2610 0f8a249a blueswir1
                    case 0x84: /* V9 fxtos */
2611 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2612 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2613 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fxtos);
2614 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2615 0f8a249a blueswir1
                        gen_op_store_FT0_fpr(rd);
2616 0f8a249a blueswir1
                        break;
2617 0f8a249a blueswir1
                    case 0x88: /* V9 fxtod */
2618 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2619 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2620 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fxtod);
2621 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2622 0f8a249a blueswir1
                        gen_op_store_DT0_fpr(DFPREG(rd));
2623 0f8a249a blueswir1
                        break;
2624 0f8a249a blueswir1
                    case 0x8c: /* V9 fxtoq */
2625 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2626 1f587329 blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2627 7e8c2b6c blueswir1
                        gen_clear_float_exceptions();
2628 44e7757c blueswir1
                        tcg_gen_helper_0_0(helper_fxtoq);
2629 7e8c2b6c blueswir1
                        tcg_gen_helper_0_0(helper_check_ieee_exceptions);
2630 1f587329 blueswir1
                        gen_op_store_QT0_fpr(QFPREG(rd));
2631 1f587329 blueswir1
                        break;
2632 1f587329 blueswir1
#else
2633 0f8a249a blueswir1
                        goto nfpu_insn;
2634 0f8a249a blueswir1
#endif
2635 1f587329 blueswir1
#endif
2636 0f8a249a blueswir1
                    default:
2637 0f8a249a blueswir1
                        goto illegal_insn;
2638 0f8a249a blueswir1
                }
2639 0f8a249a blueswir1
            } else if (xop == 0x35) {   /* FPU Operations */
2640 3475187d bellard
#ifdef TARGET_SPARC64
2641 0f8a249a blueswir1
                int cond;
2642 3475187d bellard
#endif
2643 6ae20372 blueswir1
                if (gen_trap_ifnofpu(dc, cpu_cond))
2644 a80dde08 bellard
                    goto jmp_insn;
2645 0f8a249a blueswir1
                gen_op_clear_ieee_excp_and_FTT();
2646 cf495bcf bellard
                rs1 = GET_FIELD(insn, 13, 17);
2647 0f8a249a blueswir1
                rs2 = GET_FIELD(insn, 27, 31);
2648 0f8a249a blueswir1
                xop = GET_FIELD(insn, 18, 26);
2649 3475187d bellard
#ifdef TARGET_SPARC64
2650 0f8a249a blueswir1
                if ((xop & 0x11f) == 0x005) { // V9 fmovsr
2651 dcf24905 blueswir1
                    int l1;
2652 dcf24905 blueswir1
2653 dcf24905 blueswir1
                    l1 = gen_new_label();
2654 0f8a249a blueswir1
                    cond = GET_FIELD_SP(insn, 14, 17);
2655 9322a4bf blueswir1
                    cpu_src1 = get_src1(insn, cpu_src1);
2656 6ae20372 blueswir1
                    tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2657 0425bee5 blueswir1
                                      tcg_const_tl(0), l1);
2658 19f329ad blueswir1
                    gen_op_load_fpr_FT0(rs2);
2659 0f8a249a blueswir1
                    gen_op_store_FT0_fpr(rd);
2660 dcf24905 blueswir1
                    gen_set_label(l1);
2661 0f8a249a blueswir1
                    break;
2662 0f8a249a blueswir1
                } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
2663 dcf24905 blueswir1
                    int l1;
2664 dcf24905 blueswir1
2665 dcf24905 blueswir1
                    l1 = gen_new_label();
2666 0f8a249a blueswir1
                    cond = GET_FIELD_SP(insn, 14, 17);
2667 9322a4bf blueswir1
                    cpu_src1 = get_src1(insn, cpu_src1);
2668 6ae20372 blueswir1
                    tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2669 0425bee5 blueswir1
                                      tcg_const_tl(0), l1);
2670 19f329ad blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs2));
2671 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
2672 dcf24905 blueswir1
                    gen_set_label(l1);
2673 0f8a249a blueswir1
                    break;
2674 0f8a249a blueswir1
                } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
2675 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2676 dcf24905 blueswir1
                    int l1;
2677 dcf24905 blueswir1
2678 dcf24905 blueswir1
                    l1 = gen_new_label();
2679 1f587329 blueswir1
                    cond = GET_FIELD_SP(insn, 14, 17);
2680 9322a4bf blueswir1
                    cpu_src1 = get_src1(insn, cpu_src1);
2681 6ae20372 blueswir1
                    tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
2682 0425bee5 blueswir1
                                      tcg_const_tl(0), l1);
2683 19f329ad blueswir1
                    gen_op_load_fpr_QT0(QFPREG(rs2));
2684 1f587329 blueswir1
                    gen_op_store_QT0_fpr(QFPREG(rd));
2685 dcf24905 blueswir1
                    gen_set_label(l1);
2686 1f587329 blueswir1
                    break;
2687 1f587329 blueswir1
#else
2688 0f8a249a blueswir1
                    goto nfpu_insn;
2689 1f587329 blueswir1
#endif
2690 0f8a249a blueswir1
                }
2691 0f8a249a blueswir1
#endif
2692 0f8a249a blueswir1
                switch (xop) {
2693 3475187d bellard
#ifdef TARGET_SPARC64
2694 19f329ad blueswir1
#define FMOVCC(size_FDQ, fcc)                                           \
2695 19f329ad blueswir1
                    {                                                   \
2696 0425bee5 blueswir1
                        TCGv r_cond;                                    \
2697 19f329ad blueswir1
                        int l1;                                         \
2698 19f329ad blueswir1
                                                                        \
2699 19f329ad blueswir1
                        l1 = gen_new_label();                           \
2700 19f329ad blueswir1
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2701 19f329ad blueswir1
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2702 19f329ad blueswir1
                        gen_fcond(r_cond, fcc, cond);                   \
2703 0425bee5 blueswir1
                        tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,          \
2704 0425bee5 blueswir1
                                          tcg_const_tl(0), l1);         \
2705 19f329ad blueswir1
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2706 19f329ad blueswir1
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2707 19f329ad blueswir1
                        gen_set_label(l1);                              \
2708 0425bee5 blueswir1
                        tcg_gen_discard_tl(r_cond);                     \
2709 19f329ad blueswir1
                    }
2710 0f8a249a blueswir1
                    case 0x001: /* V9 fmovscc %fcc0 */
2711 19f329ad blueswir1
                        FMOVCC(F, 0);
2712 0f8a249a blueswir1
                        break;
2713 0f8a249a blueswir1
                    case 0x002: /* V9 fmovdcc %fcc0 */
2714 19f329ad blueswir1
                        FMOVCC(D, 0);
2715 0f8a249a blueswir1
                        break;
2716 0f8a249a blueswir1
                    case 0x003: /* V9 fmovqcc %fcc0 */
2717 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2718 19f329ad blueswir1
                        FMOVCC(Q, 0);
2719 1f587329 blueswir1
                        break;
2720 1f587329 blueswir1
#else
2721 0f8a249a blueswir1
                        goto nfpu_insn;
2722 1f587329 blueswir1
#endif
2723 0f8a249a blueswir1
                    case 0x041: /* V9 fmovscc %fcc1 */
2724 19f329ad blueswir1
                        FMOVCC(F, 1);
2725 0f8a249a blueswir1
                        break;
2726 0f8a249a blueswir1
                    case 0x042: /* V9 fmovdcc %fcc1 */
2727 19f329ad blueswir1
                        FMOVCC(D, 1);
2728 0f8a249a blueswir1
                        break;
2729 0f8a249a blueswir1
                    case 0x043: /* V9 fmovqcc %fcc1 */
2730 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2731 19f329ad blueswir1
                        FMOVCC(Q, 1);
2732 1f587329 blueswir1
                        break;
2733 1f587329 blueswir1
#else
2734 0f8a249a blueswir1
                        goto nfpu_insn;
2735 1f587329 blueswir1
#endif
2736 0f8a249a blueswir1
                    case 0x081: /* V9 fmovscc %fcc2 */
2737 19f329ad blueswir1
                        FMOVCC(F, 2);
2738 0f8a249a blueswir1
                        break;
2739 0f8a249a blueswir1
                    case 0x082: /* V9 fmovdcc %fcc2 */
2740 19f329ad blueswir1
                        FMOVCC(D, 2);
2741 0f8a249a blueswir1
                        break;
2742 0f8a249a blueswir1
                    case 0x083: /* V9 fmovqcc %fcc2 */
2743 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2744 19f329ad blueswir1
                        FMOVCC(Q, 2);
2745 1f587329 blueswir1
                        break;
2746 1f587329 blueswir1
#else
2747 0f8a249a blueswir1
                        goto nfpu_insn;
2748 1f587329 blueswir1
#endif
2749 0f8a249a blueswir1
                    case 0x0c1: /* V9 fmovscc %fcc3 */
2750 19f329ad blueswir1
                        FMOVCC(F, 3);
2751 0f8a249a blueswir1
                        break;
2752 0f8a249a blueswir1
                    case 0x0c2: /* V9 fmovdcc %fcc3 */
2753 19f329ad blueswir1
                        FMOVCC(D, 3);
2754 0f8a249a blueswir1
                        break;
2755 0f8a249a blueswir1
                    case 0x0c3: /* V9 fmovqcc %fcc3 */
2756 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2757 19f329ad blueswir1
                        FMOVCC(Q, 3);
2758 1f587329 blueswir1
                        break;
2759 1f587329 blueswir1
#else
2760 0f8a249a blueswir1
                        goto nfpu_insn;
2761 1f587329 blueswir1
#endif
2762 19f329ad blueswir1
#undef FMOVCC
2763 19f329ad blueswir1
#define FMOVCC(size_FDQ, icc)                                           \
2764 19f329ad blueswir1
                    {                                                   \
2765 0425bee5 blueswir1
                        TCGv r_cond;                                    \
2766 19f329ad blueswir1
                        int l1;                                         \
2767 19f329ad blueswir1
                                                                        \
2768 19f329ad blueswir1
                        l1 = gen_new_label();                           \
2769 19f329ad blueswir1
                        r_cond = tcg_temp_new(TCG_TYPE_TL);             \
2770 19f329ad blueswir1
                        cond = GET_FIELD_SP(insn, 14, 17);              \
2771 19f329ad blueswir1
                        gen_cond(r_cond, icc, cond);                    \
2772 0425bee5 blueswir1
                        tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,          \
2773 0425bee5 blueswir1
                                          tcg_const_tl(0), l1);         \
2774 19f329ad blueswir1
                        glue(glue(gen_op_load_fpr_, size_FDQ), T0)(glue(size_FDQ, FPREG(rs2))); \
2775 19f329ad blueswir1
                        glue(glue(gen_op_store_, size_FDQ), T0_fpr)(glue(size_FDQ, FPREG(rd))); \
2776 19f329ad blueswir1
                        gen_set_label(l1);                              \
2777 0425bee5 blueswir1
                        tcg_gen_discard_tl(r_cond);                     \
2778 19f329ad blueswir1
                    }
2779 19f329ad blueswir1
2780 0f8a249a blueswir1
                    case 0x101: /* V9 fmovscc %icc */
2781 19f329ad blueswir1
                        FMOVCC(F, 0);
2782 0f8a249a blueswir1
                        break;
2783 0f8a249a blueswir1
                    case 0x102: /* V9 fmovdcc %icc */
2784 19f329ad blueswir1
                        FMOVCC(D, 0);
2785 0f8a249a blueswir1
                    case 0x103: /* V9 fmovqcc %icc */
2786 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2787 19f329ad blueswir1
                        FMOVCC(D, 0);
2788 1f587329 blueswir1
                        break;
2789 1f587329 blueswir1
#else
2790 0f8a249a blueswir1
                        goto nfpu_insn;
2791 1f587329 blueswir1
#endif
2792 0f8a249a blueswir1
                    case 0x181: /* V9 fmovscc %xcc */
2793 19f329ad blueswir1
                        FMOVCC(F, 1);
2794 0f8a249a blueswir1
                        break;
2795 0f8a249a blueswir1
                    case 0x182: /* V9 fmovdcc %xcc */
2796 19f329ad blueswir1
                        FMOVCC(D, 1);
2797 0f8a249a blueswir1
                        break;
2798 0f8a249a blueswir1
                    case 0x183: /* V9 fmovqcc %xcc */
2799 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2800 19f329ad blueswir1
                        FMOVCC(Q, 1);
2801 1f587329 blueswir1
                        break;
2802 1f587329 blueswir1
#else
2803 0f8a249a blueswir1
                        goto nfpu_insn;
2804 0f8a249a blueswir1
#endif
2805 19f329ad blueswir1
#undef FMOVCC
2806 1f587329 blueswir1
#endif
2807 1f587329 blueswir1
                    case 0x51: /* fcmps, V9 %fcc */
2808 0f8a249a blueswir1
                        gen_op_load_fpr_FT0(rs1);
2809 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2810 7e8c2b6c blueswir1
                        gen_op_fcmps(rd & 3);
2811 0f8a249a blueswir1
                        break;
2812 1f587329 blueswir1
                    case 0x52: /* fcmpd, V9 %fcc */
2813 0f8a249a blueswir1
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2814 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2815 7e8c2b6c blueswir1
                        gen_op_fcmpd(rd & 3);
2816 0f8a249a blueswir1
                        break;
2817 1f587329 blueswir1
                    case 0x53: /* fcmpq, V9 %fcc */
2818 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2819 1f587329 blueswir1
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2820 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2821 7e8c2b6c blueswir1
                        gen_op_fcmpq(rd & 3);
2822 1f587329 blueswir1
                        break;
2823 1f587329 blueswir1
#else /* !defined(CONFIG_USER_ONLY) */
2824 0f8a249a blueswir1
                        goto nfpu_insn;
2825 1f587329 blueswir1
#endif
2826 0f8a249a blueswir1
                    case 0x55: /* fcmpes, V9 %fcc */
2827 0f8a249a blueswir1
                        gen_op_load_fpr_FT0(rs1);
2828 0f8a249a blueswir1
                        gen_op_load_fpr_FT1(rs2);
2829 7e8c2b6c blueswir1
                        gen_op_fcmpes(rd & 3);
2830 0f8a249a blueswir1
                        break;
2831 0f8a249a blueswir1
                    case 0x56: /* fcmped, V9 %fcc */
2832 0f8a249a blueswir1
                        gen_op_load_fpr_DT0(DFPREG(rs1));
2833 0f8a249a blueswir1
                        gen_op_load_fpr_DT1(DFPREG(rs2));
2834 7e8c2b6c blueswir1
                        gen_op_fcmped(rd & 3);
2835 0f8a249a blueswir1
                        break;
2836 1f587329 blueswir1
                    case 0x57: /* fcmpeq, V9 %fcc */
2837 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
2838 1f587329 blueswir1
                        gen_op_load_fpr_QT0(QFPREG(rs1));
2839 1f587329 blueswir1
                        gen_op_load_fpr_QT1(QFPREG(rs2));
2840 7e8c2b6c blueswir1
                        gen_op_fcmpeq(rd & 3);
2841 1f587329 blueswir1
                        break;
2842 1f587329 blueswir1
#else/* !defined(CONFIG_USER_ONLY) */
2843 0f8a249a blueswir1
                        goto nfpu_insn;
2844 1f587329 blueswir1
#endif
2845 0f8a249a blueswir1
                    default:
2846 0f8a249a blueswir1
                        goto illegal_insn;
2847 0f8a249a blueswir1
                }
2848 e80cfcfc bellard
#if defined(OPTIM)
2849 0f8a249a blueswir1
            } else if (xop == 0x2) {
2850 0f8a249a blueswir1
                // clr/mov shortcut
2851 e80cfcfc bellard
2852 e80cfcfc bellard
                rs1 = GET_FIELD(insn, 13, 17);
2853 0f8a249a blueswir1
                if (rs1 == 0) {
2854 1a2fb1c0 blueswir1
                    // or %g0, x, y -> mov T0, x; mov y, T0
2855 0f8a249a blueswir1
                    if (IS_IMM) {       /* immediate */
2856 0f8a249a blueswir1
                        rs2 = GET_FIELDs(insn, 19, 31);
2857 6ae20372 blueswir1
                        tcg_gen_movi_tl(cpu_dst, (int)rs2);
2858 0f8a249a blueswir1
                    } else {            /* register */
2859 0f8a249a blueswir1
                        rs2 = GET_FIELD(insn, 27, 31);
2860 6ae20372 blueswir1
                        gen_movl_reg_TN(rs2, cpu_dst);
2861 0f8a249a blueswir1
                    }
2862 0f8a249a blueswir1
                } else {
2863 9322a4bf blueswir1
                    cpu_src1 = get_src1(insn, cpu_src1);
2864 0f8a249a blueswir1
                    if (IS_IMM) {       /* immediate */
2865 0f8a249a blueswir1
                        rs2 = GET_FIELDs(insn, 19, 31);
2866 6ae20372 blueswir1
                        tcg_gen_ori_tl(cpu_dst, cpu_src1, (int)rs2);
2867 0f8a249a blueswir1
                    } else {            /* register */
2868 0f8a249a blueswir1
                        // or x, %g0, y -> mov T1, x; mov y, T1
2869 0f8a249a blueswir1
                        rs2 = GET_FIELD(insn, 27, 31);
2870 0f8a249a blueswir1
                        if (rs2 != 0) {
2871 6ae20372 blueswir1
                            gen_movl_reg_TN(rs2, cpu_src2);
2872 6ae20372 blueswir1
                            tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2873 0f8a249a blueswir1
                        }
2874 0f8a249a blueswir1
                    }
2875 0f8a249a blueswir1
                }
2876 6ae20372 blueswir1
                gen_movl_TN_reg(rd, cpu_dst);
2877 e80cfcfc bellard
#endif
2878 83469015 bellard
#ifdef TARGET_SPARC64
2879 0f8a249a blueswir1
            } else if (xop == 0x25) { /* sll, V9 sllx */
2880 9322a4bf blueswir1
                cpu_src1 = get_src1(insn, cpu_src1);
2881 0f8a249a blueswir1
                if (IS_IMM) {   /* immediate */
2882 83469015 bellard
                    rs2 = GET_FIELDs(insn, 20, 31);
2883 1a2fb1c0 blueswir1
                    if (insn & (1 << 12)) {
2884 6ae20372 blueswir1
                        tcg_gen_shli_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2885 1a2fb1c0 blueswir1
                    } else {
2886 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2887 6ae20372 blueswir1
                        tcg_gen_shli_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2888 1a2fb1c0 blueswir1
                    }
2889 0f8a249a blueswir1
                } else {                /* register */
2890 83469015 bellard
                    rs2 = GET_FIELD(insn, 27, 31);
2891 6ae20372 blueswir1
                    gen_movl_reg_TN(rs2, cpu_src2);
2892 1a2fb1c0 blueswir1
                    if (insn & (1 << 12)) {
2893 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2894 6ae20372 blueswir1
                        tcg_gen_shl_i64(cpu_dst, cpu_src1, cpu_tmp0);
2895 1a2fb1c0 blueswir1
                    } else {
2896 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2897 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2898 6ae20372 blueswir1
                        tcg_gen_shl_i64(cpu_dst, cpu_dst, cpu_tmp0);
2899 1a2fb1c0 blueswir1
                    }
2900 83469015 bellard
                }
2901 6ae20372 blueswir1
                gen_movl_TN_reg(rd, cpu_dst);
2902 0f8a249a blueswir1
            } else if (xop == 0x26) { /* srl, V9 srlx */
2903 9322a4bf blueswir1
                cpu_src1 = get_src1(insn, cpu_src1);
2904 0f8a249a blueswir1
                if (IS_IMM) {   /* immediate */
2905 83469015 bellard
                    rs2 = GET_FIELDs(insn, 20, 31);
2906 1a2fb1c0 blueswir1
                    if (insn & (1 << 12)) {
2907 6ae20372 blueswir1
                        tcg_gen_shri_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2908 1a2fb1c0 blueswir1
                    } else {
2909 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2910 6ae20372 blueswir1
                        tcg_gen_shri_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2911 1a2fb1c0 blueswir1
                    }
2912 0f8a249a blueswir1
                } else {                /* register */
2913 83469015 bellard
                    rs2 = GET_FIELD(insn, 27, 31);
2914 6ae20372 blueswir1
                    gen_movl_reg_TN(rs2, cpu_src2);
2915 1a2fb1c0 blueswir1
                    if (insn & (1 << 12)) {
2916 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2917 6ae20372 blueswir1
                        tcg_gen_shr_i64(cpu_dst, cpu_src1, cpu_tmp0);
2918 1a2fb1c0 blueswir1
                    } else {
2919 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2920 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2921 6ae20372 blueswir1
                        tcg_gen_shr_i64(cpu_dst, cpu_dst, cpu_tmp0);
2922 1a2fb1c0 blueswir1
                    }
2923 83469015 bellard
                }
2924 6ae20372 blueswir1
                gen_movl_TN_reg(rd, cpu_dst);
2925 0f8a249a blueswir1
            } else if (xop == 0x27) { /* sra, V9 srax */
2926 9322a4bf blueswir1
                cpu_src1 = get_src1(insn, cpu_src1);
2927 0f8a249a blueswir1
                if (IS_IMM) {   /* immediate */
2928 83469015 bellard
                    rs2 = GET_FIELDs(insn, 20, 31);
2929 1a2fb1c0 blueswir1
                    if (insn & (1 << 12)) {
2930 6ae20372 blueswir1
                        tcg_gen_sari_i64(cpu_dst, cpu_src1, rs2 & 0x3f);
2931 1a2fb1c0 blueswir1
                    } else {
2932 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2933 6ae20372 blueswir1
                        tcg_gen_ext_i32_i64(cpu_dst, cpu_dst);
2934 6ae20372 blueswir1
                        tcg_gen_sari_i64(cpu_dst, cpu_dst, rs2 & 0x1f);
2935 1a2fb1c0 blueswir1
                    }
2936 0f8a249a blueswir1
                } else {                /* register */
2937 83469015 bellard
                    rs2 = GET_FIELD(insn, 27, 31);
2938 6ae20372 blueswir1
                    gen_movl_reg_TN(rs2, cpu_src2);
2939 1a2fb1c0 blueswir1
                    if (insn & (1 << 12)) {
2940 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x3f);
2941 6ae20372 blueswir1
                        tcg_gen_sar_i64(cpu_dst, cpu_src1, cpu_tmp0);
2942 1a2fb1c0 blueswir1
                    } else {
2943 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_tmp0, cpu_src2, 0x1f);
2944 6ae20372 blueswir1
                        tcg_gen_andi_i64(cpu_dst, cpu_src1, 0xffffffffULL);
2945 6ae20372 blueswir1
                        tcg_gen_sar_i64(cpu_dst, cpu_dst, cpu_tmp0);
2946 1a2fb1c0 blueswir1
                    }
2947 83469015 bellard
                }
2948 6ae20372 blueswir1
                gen_movl_TN_reg(rd, cpu_dst);
2949 83469015 bellard
#endif
2950 fcc72045 blueswir1
            } else if (xop < 0x36) {
2951 9322a4bf blueswir1
                cpu_src1 = get_src1(insn, cpu_src1);
2952 0f8a249a blueswir1
                if (IS_IMM) {   /* immediate */
2953 cf495bcf bellard
                    rs2 = GET_FIELDs(insn, 19, 31);
2954 6ae20372 blueswir1
                    tcg_gen_movi_tl(cpu_src2, (int)rs2);
2955 0f8a249a blueswir1
                } else {                /* register */
2956 cf495bcf bellard
                    rs2 = GET_FIELD(insn, 27, 31);
2957 6ae20372 blueswir1
                    gen_movl_reg_TN(rs2, cpu_src2);
2958 cf495bcf bellard
                }
2959 cf495bcf bellard
                if (xop < 0x20) {
2960 cf495bcf bellard
                    switch (xop & ~0x10) {
2961 cf495bcf bellard
                    case 0x0:
2962 cf495bcf bellard
                        if (xop & 0x10)
2963 6ae20372 blueswir1
                            gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2);
2964 cf495bcf bellard
                        else
2965 6ae20372 blueswir1
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
2966 cf495bcf bellard
                        break;
2967 cf495bcf bellard
                    case 0x1:
2968 6ae20372 blueswir1
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_src2);
2969 cf495bcf bellard
                        if (xop & 0x10)
2970 6ae20372 blueswir1
                            gen_op_logic_cc(cpu_dst);
2971 cf495bcf bellard
                        break;
2972 cf495bcf bellard
                    case 0x2:
2973 6ae20372 blueswir1
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_src2);
2974 0f8a249a blueswir1
                        if (xop & 0x10)
2975 6ae20372 blueswir1
                            gen_op_logic_cc(cpu_dst);
2976 0f8a249a blueswir1
                        break;
2977 cf495bcf bellard
                    case 0x3:
2978 6ae20372 blueswir1
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
2979 cf495bcf bellard
                        if (xop & 0x10)
2980 6ae20372 blueswir1
                            gen_op_logic_cc(cpu_dst);
2981 cf495bcf bellard
                        break;
2982 cf495bcf bellard
                    case 0x4:
2983 cf495bcf bellard
                        if (xop & 0x10)
2984 6ae20372 blueswir1
                            gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2);
2985 cf495bcf bellard
                        else
2986 6ae20372 blueswir1
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_src2);
2987 cf495bcf bellard
                        break;
2988 cf495bcf bellard
                    case 0x5:
2989 6ae20372 blueswir1
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2990 6ae20372 blueswir1
                        tcg_gen_and_tl(cpu_dst, cpu_src1, cpu_tmp0);
2991 cf495bcf bellard
                        if (xop & 0x10)
2992 6ae20372 blueswir1
                            gen_op_logic_cc(cpu_dst);
2993 cf495bcf bellard
                        break;
2994 cf495bcf bellard
                    case 0x6:
2995 6ae20372 blueswir1
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
2996 6ae20372 blueswir1
                        tcg_gen_or_tl(cpu_dst, cpu_src1, cpu_tmp0);
2997 cf495bcf bellard
                        if (xop & 0x10)
2998 6ae20372 blueswir1
                            gen_op_logic_cc(cpu_dst);
2999 cf495bcf bellard
                        break;
3000 cf495bcf bellard
                    case 0x7:
3001 6ae20372 blueswir1
                        tcg_gen_xori_tl(cpu_tmp0, cpu_src2, -1);
3002 6ae20372 blueswir1
                        tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_tmp0);
3003 cf495bcf bellard
                        if (xop & 0x10)
3004 6ae20372 blueswir1
                            gen_op_logic_cc(cpu_dst);
3005 cf495bcf bellard
                        break;
3006 cf495bcf bellard
                    case 0x8:
3007 cf495bcf bellard
                        if (xop & 0x10)
3008 6ae20372 blueswir1
                            gen_op_addx_cc(cpu_dst, cpu_src1, cpu_src2);
3009 38bc628b blueswir1
                        else {
3010 dc99a3f2 blueswir1
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3011 6ae20372 blueswir1
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3012 6ae20372 blueswir1
                            tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_tmp0);
3013 38bc628b blueswir1
                        }
3014 cf495bcf bellard
                        break;
3015 ded3ab80 pbrook
#ifdef TARGET_SPARC64
3016 0f8a249a blueswir1
                    case 0x9: /* V9 mulx */
3017 6ae20372 blueswir1
                        tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2);
3018 ded3ab80 pbrook
                        break;
3019 ded3ab80 pbrook
#endif
3020 cf495bcf bellard
                    case 0xa:
3021 6ae20372 blueswir1
                        gen_op_umul(cpu_dst, cpu_src1, cpu_src2);
3022 cf495bcf bellard
                        if (xop & 0x10)
3023 6ae20372 blueswir1
                            gen_op_logic_cc(cpu_dst);
3024 cf495bcf bellard
                        break;
3025 cf495bcf bellard
                    case 0xb:
3026 6ae20372 blueswir1
                        gen_op_smul(cpu_dst, cpu_src1, cpu_src2);
3027 cf495bcf bellard
                        if (xop & 0x10)
3028 6ae20372 blueswir1
                            gen_op_logic_cc(cpu_dst);
3029 cf495bcf bellard
                        break;
3030 cf495bcf bellard
                    case 0xc:
3031 cf495bcf bellard
                        if (xop & 0x10)
3032 6ae20372 blueswir1
                            gen_op_subx_cc(cpu_dst, cpu_src1, cpu_src2);
3033 38bc628b blueswir1
                        else {
3034 dc99a3f2 blueswir1
                            gen_mov_reg_C(cpu_tmp0, cpu_psr);
3035 6ae20372 blueswir1
                            tcg_gen_add_tl(cpu_tmp0, cpu_src2, cpu_tmp0);
3036 6ae20372 blueswir1
                            tcg_gen_sub_tl(cpu_dst, cpu_src1, cpu_tmp0);
3037 38bc628b blueswir1
                        }
3038 cf495bcf bellard
                        break;
3039 ded3ab80 pbrook
#ifdef TARGET_SPARC64
3040 0f8a249a blueswir1
                    case 0xd: /* V9 udivx */
3041 6ae20372 blueswir1
                        gen_trap_ifdivzero_tl(cpu_src2);
3042 6ae20372 blueswir1
                        tcg_gen_divu_i64(cpu_dst, cpu_src1, cpu_src2);
3043 ded3ab80 pbrook
                        break;
3044 ded3ab80 pbrook
#endif
3045 cf495bcf bellard
                    case 0xe:
3046 6ae20372 blueswir1
                        tcg_gen_helper_1_2(helper_udiv, cpu_dst, cpu_src1, cpu_src2);
3047 cf495bcf bellard
                        if (xop & 0x10)
3048 6ae20372 blueswir1
                            gen_op_div_cc(cpu_dst);
3049 cf495bcf bellard
                        break;
3050 cf495bcf bellard
                    case 0xf:
3051 6ae20372 blueswir1
                        tcg_gen_helper_1_2(helper_sdiv, cpu_dst, cpu_src1, cpu_src2);
3052 cf495bcf bellard
                        if (xop & 0x10)
3053 6ae20372 blueswir1
                            gen_op_div_cc(cpu_dst);
3054 cf495bcf bellard
                        break;
3055 cf495bcf bellard
                    default:
3056 cf495bcf bellard
                        goto illegal_insn;
3057 cf495bcf bellard
                    }
3058 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
3059 cf495bcf bellard
                } else {
3060 cf495bcf bellard
                    switch (xop) {
3061 0f8a249a blueswir1
                    case 0x20: /* taddcc */
3062 6ae20372 blueswir1
                        gen_op_tadd_cc(cpu_dst, cpu_src1, cpu_src2);
3063 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
3064 0f8a249a blueswir1
                        break;
3065 0f8a249a blueswir1
                    case 0x21: /* tsubcc */
3066 6ae20372 blueswir1
                        gen_op_tsub_cc(cpu_dst, cpu_src1, cpu_src2);
3067 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
3068 0f8a249a blueswir1
                        break;
3069 0f8a249a blueswir1
                    case 0x22: /* taddcctv */
3070 6ae20372 blueswir1
                        save_state(dc, cpu_cond);
3071 6ae20372 blueswir1
                        gen_op_tadd_ccTV(cpu_dst, cpu_src1, cpu_src2);
3072 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
3073 0f8a249a blueswir1
                        break;
3074 0f8a249a blueswir1
                    case 0x23: /* tsubcctv */
3075 6ae20372 blueswir1
                        save_state(dc, cpu_cond);
3076 6ae20372 blueswir1
                        gen_op_tsub_ccTV(cpu_dst, cpu_src1, cpu_src2);
3077 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
3078 0f8a249a blueswir1
                        break;
3079 cf495bcf bellard
                    case 0x24: /* mulscc */
3080 6ae20372 blueswir1
                        gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2);
3081 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
3082 cf495bcf bellard
                        break;
3083 83469015 bellard
#ifndef TARGET_SPARC64
3084 0f8a249a blueswir1
                    case 0x25:  /* sll */
3085 6ae20372 blueswir1
                        tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3086 6ae20372 blueswir1
                        tcg_gen_shl_tl(cpu_dst, cpu_src1, cpu_tmp0);
3087 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
3088 cf495bcf bellard
                        break;
3089 83469015 bellard
                    case 0x26:  /* srl */
3090 6ae20372 blueswir1
                        tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3091 6ae20372 blueswir1
                        tcg_gen_shr_tl(cpu_dst, cpu_src1, cpu_tmp0);
3092 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
3093 cf495bcf bellard
                        break;
3094 83469015 bellard
                    case 0x27:  /* sra */
3095 6ae20372 blueswir1
                        tcg_gen_andi_tl(cpu_tmp0, cpu_src2, 0x1f);
3096 6ae20372 blueswir1
                        tcg_gen_sar_tl(cpu_dst, cpu_src1, cpu_tmp0);
3097 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
3098 cf495bcf bellard
                        break;
3099 83469015 bellard
#endif
3100 cf495bcf bellard
                    case 0x30:
3101 cf495bcf bellard
                        {
3102 cf495bcf bellard
                            switch(rd) {
3103 3475187d bellard
                            case 0: /* wry */
3104 6ae20372 blueswir1
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3105 6ae20372 blueswir1
                                tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, y));
3106 cf495bcf bellard
                                break;
3107 65fe7b09 blueswir1
#ifndef TARGET_SPARC64
3108 65fe7b09 blueswir1
                            case 0x01 ... 0x0f: /* undefined in the
3109 65fe7b09 blueswir1
                                                   SPARCv8 manual, nop
3110 65fe7b09 blueswir1
                                                   on the microSPARC
3111 65fe7b09 blueswir1
                                                   II */
3112 65fe7b09 blueswir1
                            case 0x10 ... 0x1f: /* implementation-dependent
3113 65fe7b09 blueswir1
                                                   in the SPARCv8
3114 65fe7b09 blueswir1
                                                   manual, nop on the
3115 65fe7b09 blueswir1
                                                   microSPARC II */
3116 65fe7b09 blueswir1
                                break;
3117 65fe7b09 blueswir1
#else
3118 0f8a249a blueswir1
                            case 0x2: /* V9 wrccr */
3119 6ae20372 blueswir1
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3120 6ae20372 blueswir1
                                tcg_gen_helper_0_1(helper_wrccr, cpu_dst);
3121 0f8a249a blueswir1
                                break;
3122 0f8a249a blueswir1
                            case 0x3: /* V9 wrasi */
3123 6ae20372 blueswir1
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3124 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3125 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, asi));
3126 0f8a249a blueswir1
                                break;
3127 0f8a249a blueswir1
                            case 0x6: /* V9 wrfprs */
3128 6ae20372 blueswir1
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3129 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3130 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, fprs));
3131 6ae20372 blueswir1
                                save_state(dc, cpu_cond);
3132 3299908c blueswir1
                                gen_op_next_insn();
3133 57fec1fe bellard
                                tcg_gen_exit_tb(0);
3134 3299908c blueswir1
                                dc->is_br = 1;
3135 0f8a249a blueswir1
                                break;
3136 0f8a249a blueswir1
                            case 0xf: /* V9 sir, nop if user */
3137 3475187d bellard
#if !defined(CONFIG_USER_ONLY)
3138 0f8a249a blueswir1
                                if (supervisor(dc))
3139 1a2fb1c0 blueswir1
                                    ; // XXX
3140 3475187d bellard
#endif
3141 0f8a249a blueswir1
                                break;
3142 0f8a249a blueswir1
                            case 0x13: /* Graphics Status */
3143 6ae20372 blueswir1
                                if (gen_trap_ifnofpu(dc, cpu_cond))
3144 725cb90b bellard
                                    goto jmp_insn;
3145 6ae20372 blueswir1
                                tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3146 6ae20372 blueswir1
                                tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, gsr));
3147 0f8a249a blueswir1
                                break;
3148 0f8a249a blueswir1
                            case 0x17: /* Tick compare */
3149 83469015 bellard
#if !defined(CONFIG_USER_ONLY)
3150 0f8a249a blueswir1
                                if (!supervisor(dc))
3151 0f8a249a blueswir1
                                    goto illegal_insn;
3152 83469015 bellard
#endif
3153 ccd4a219 blueswir1
                                {
3154 ccd4a219 blueswir1
                                    TCGv r_tickptr;
3155 ccd4a219 blueswir1
3156 6ae20372 blueswir1
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3157 6ae20372 blueswir1
                                                   cpu_src2);
3158 6ae20372 blueswir1
                                    tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3159 ccd4a219 blueswir1
                                                                 tick_cmpr));
3160 ccd4a219 blueswir1
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3161 ccd4a219 blueswir1
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3162 ccd4a219 blueswir1
                                                   offsetof(CPUState, tick));
3163 ccd4a219 blueswir1
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3164 6ae20372 blueswir1
                                                       r_tickptr, cpu_dst);
3165 0425bee5 blueswir1
                                    tcg_gen_discard_ptr(r_tickptr);
3166 ccd4a219 blueswir1
                                }
3167 0f8a249a blueswir1
                                break;
3168 0f8a249a blueswir1
                            case 0x18: /* System tick */
3169 83469015 bellard
#if !defined(CONFIG_USER_ONLY)
3170 0f8a249a blueswir1
                                if (!supervisor(dc))
3171 0f8a249a blueswir1
                                    goto illegal_insn;
3172 83469015 bellard
#endif
3173 ccd4a219 blueswir1
                                {
3174 ccd4a219 blueswir1
                                    TCGv r_tickptr;
3175 ccd4a219 blueswir1
3176 6ae20372 blueswir1
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3177 6ae20372 blueswir1
                                                   cpu_src2);
3178 ccd4a219 blueswir1
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3179 ccd4a219 blueswir1
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3180 ccd4a219 blueswir1
                                                   offsetof(CPUState, stick));
3181 ccd4a219 blueswir1
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3182 6ae20372 blueswir1
                                                       r_tickptr, cpu_dst);
3183 0425bee5 blueswir1
                                    tcg_gen_discard_ptr(r_tickptr);
3184 ccd4a219 blueswir1
                                }
3185 0f8a249a blueswir1
                                break;
3186 0f8a249a blueswir1
                            case 0x19: /* System tick compare */
3187 83469015 bellard
#if !defined(CONFIG_USER_ONLY)
3188 0f8a249a blueswir1
                                if (!supervisor(dc))
3189 0f8a249a blueswir1
                                    goto illegal_insn;
3190 3475187d bellard
#endif
3191 ccd4a219 blueswir1
                                {
3192 ccd4a219 blueswir1
                                    TCGv r_tickptr;
3193 ccd4a219 blueswir1
3194 6ae20372 blueswir1
                                    tcg_gen_xor_tl(cpu_dst, cpu_src1,
3195 6ae20372 blueswir1
                                                   cpu_src2);
3196 6ae20372 blueswir1
                                    tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3197 ccd4a219 blueswir1
                                                                 stick_cmpr));
3198 ccd4a219 blueswir1
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3199 ccd4a219 blueswir1
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3200 ccd4a219 blueswir1
                                                   offsetof(CPUState, stick));
3201 ccd4a219 blueswir1
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3202 6ae20372 blueswir1
                                                       r_tickptr, cpu_dst);
3203 0425bee5 blueswir1
                                    tcg_gen_discard_ptr(r_tickptr);
3204 ccd4a219 blueswir1
                                }
3205 0f8a249a blueswir1
                                break;
3206 83469015 bellard
3207 0f8a249a blueswir1
                            case 0x10: /* Performance Control */
3208 0f8a249a blueswir1
                            case 0x11: /* Performance Instrumentation Counter */
3209 0f8a249a blueswir1
                            case 0x12: /* Dispatch Control */
3210 0f8a249a blueswir1
                            case 0x14: /* Softint set */
3211 0f8a249a blueswir1
                            case 0x15: /* Softint clear */
3212 0f8a249a blueswir1
                            case 0x16: /* Softint write */
3213 83469015 bellard
#endif
3214 3475187d bellard
                            default:
3215 cf495bcf bellard
                                goto illegal_insn;
3216 cf495bcf bellard
                            }
3217 cf495bcf bellard
                        }
3218 cf495bcf bellard
                        break;
3219 e8af50a3 bellard
#if !defined(CONFIG_USER_ONLY)
3220 af7bf89b bellard
                    case 0x31: /* wrpsr, V9 saved, restored */
3221 e8af50a3 bellard
                        {
3222 0f8a249a blueswir1
                            if (!supervisor(dc))
3223 0f8a249a blueswir1
                                goto priv_insn;
3224 3475187d bellard
#ifdef TARGET_SPARC64
3225 0f8a249a blueswir1
                            switch (rd) {
3226 0f8a249a blueswir1
                            case 0:
3227 72a9747b blueswir1
                                tcg_gen_helper_0_0(helper_saved);
3228 0f8a249a blueswir1
                                break;
3229 0f8a249a blueswir1
                            case 1:
3230 72a9747b blueswir1
                                tcg_gen_helper_0_0(helper_restored);
3231 0f8a249a blueswir1
                                break;
3232 e9ebed4d blueswir1
                            case 2: /* UA2005 allclean */
3233 e9ebed4d blueswir1
                            case 3: /* UA2005 otherw */
3234 e9ebed4d blueswir1
                            case 4: /* UA2005 normalw */
3235 e9ebed4d blueswir1
                            case 5: /* UA2005 invalw */
3236 e9ebed4d blueswir1
                                // XXX
3237 0f8a249a blueswir1
                            default:
3238 3475187d bellard
                                goto illegal_insn;
3239 3475187d bellard
                            }
3240 3475187d bellard
#else
3241 6ae20372 blueswir1
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3242 6ae20372 blueswir1
                            tcg_gen_helper_0_1(helper_wrpsr, cpu_dst);
3243 6ae20372 blueswir1
                            save_state(dc, cpu_cond);
3244 9e61bde5 bellard
                            gen_op_next_insn();
3245 57fec1fe bellard
                            tcg_gen_exit_tb(0);
3246 0f8a249a blueswir1
                            dc->is_br = 1;
3247 3475187d bellard
#endif
3248 e8af50a3 bellard
                        }
3249 e8af50a3 bellard
                        break;
3250 af7bf89b bellard
                    case 0x32: /* wrwim, V9 wrpr */
3251 e8af50a3 bellard
                        {
3252 0f8a249a blueswir1
                            if (!supervisor(dc))
3253 0f8a249a blueswir1
                                goto priv_insn;
3254 6ae20372 blueswir1
                            tcg_gen_xor_tl(cpu_dst, cpu_src1, cpu_src2);
3255 3475187d bellard
#ifdef TARGET_SPARC64
3256 0f8a249a blueswir1
                            switch (rd) {
3257 0f8a249a blueswir1
                            case 0: // tpc
3258 375ee38b blueswir1
                                {
3259 375ee38b blueswir1
                                    TCGv r_tsptr;
3260 375ee38b blueswir1
3261 375ee38b blueswir1
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3262 375ee38b blueswir1
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3263 375ee38b blueswir1
                                                   offsetof(CPUState, tsptr));
3264 6ae20372 blueswir1
                                    tcg_gen_st_tl(cpu_dst, r_tsptr,
3265 375ee38b blueswir1
                                                  offsetof(trap_state, tpc));
3266 0425bee5 blueswir1
                                    tcg_gen_discard_ptr(r_tsptr);
3267 375ee38b blueswir1
                                }
3268 0f8a249a blueswir1
                                break;
3269 0f8a249a blueswir1
                            case 1: // tnpc
3270 375ee38b blueswir1
                                {
3271 375ee38b blueswir1
                                    TCGv r_tsptr;
3272 375ee38b blueswir1
3273 375ee38b blueswir1
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3274 375ee38b blueswir1
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3275 375ee38b blueswir1
                                                   offsetof(CPUState, tsptr));
3276 6ae20372 blueswir1
                                    tcg_gen_st_tl(cpu_dst, r_tsptr,
3277 375ee38b blueswir1
                                                  offsetof(trap_state, tnpc));
3278 0425bee5 blueswir1
                                    tcg_gen_discard_ptr(r_tsptr);
3279 375ee38b blueswir1
                                }
3280 0f8a249a blueswir1
                                break;
3281 0f8a249a blueswir1
                            case 2: // tstate
3282 375ee38b blueswir1
                                {
3283 375ee38b blueswir1
                                    TCGv r_tsptr;
3284 375ee38b blueswir1
3285 375ee38b blueswir1
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3286 375ee38b blueswir1
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3287 375ee38b blueswir1
                                                   offsetof(CPUState, tsptr));
3288 6ae20372 blueswir1
                                    tcg_gen_st_tl(cpu_dst, r_tsptr,
3289 375ee38b blueswir1
                                                  offsetof(trap_state, tstate));
3290 0425bee5 blueswir1
                                    tcg_gen_discard_ptr(r_tsptr);
3291 375ee38b blueswir1
                                }
3292 0f8a249a blueswir1
                                break;
3293 0f8a249a blueswir1
                            case 3: // tt
3294 375ee38b blueswir1
                                {
3295 375ee38b blueswir1
                                    TCGv r_tsptr;
3296 375ee38b blueswir1
3297 375ee38b blueswir1
                                    r_tsptr = tcg_temp_new(TCG_TYPE_PTR);
3298 375ee38b blueswir1
                                    tcg_gen_ld_ptr(r_tsptr, cpu_env,
3299 375ee38b blueswir1
                                                   offsetof(CPUState, tsptr));
3300 6ae20372 blueswir1
                                    tcg_gen_st_i32(cpu_dst, r_tsptr,
3301 375ee38b blueswir1
                                                   offsetof(trap_state, tt));
3302 0425bee5 blueswir1
                                    tcg_gen_discard_ptr(r_tsptr);
3303 375ee38b blueswir1
                                }
3304 0f8a249a blueswir1
                                break;
3305 0f8a249a blueswir1
                            case 4: // tick
3306 ccd4a219 blueswir1
                                {
3307 ccd4a219 blueswir1
                                    TCGv r_tickptr;
3308 ccd4a219 blueswir1
3309 ccd4a219 blueswir1
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3310 ccd4a219 blueswir1
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3311 ccd4a219 blueswir1
                                                   offsetof(CPUState, tick));
3312 ccd4a219 blueswir1
                                    tcg_gen_helper_0_2(helper_tick_set_count,
3313 6ae20372 blueswir1
                                                       r_tickptr, cpu_dst);
3314 0425bee5 blueswir1
                                    tcg_gen_discard_ptr(r_tickptr);
3315 ccd4a219 blueswir1
                                }
3316 0f8a249a blueswir1
                                break;
3317 0f8a249a blueswir1
                            case 5: // tba
3318 6ae20372 blueswir1
                                tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
3319 0f8a249a blueswir1
                                break;
3320 0f8a249a blueswir1
                            case 6: // pstate
3321 6ae20372 blueswir1
                                save_state(dc, cpu_cond);
3322 6ae20372 blueswir1
                                tcg_gen_helper_0_1(helper_wrpstate, cpu_dst);
3323 ded3ab80 pbrook
                                gen_op_next_insn();
3324 57fec1fe bellard
                                tcg_gen_exit_tb(0);
3325 ded3ab80 pbrook
                                dc->is_br = 1;
3326 0f8a249a blueswir1
                                break;
3327 0f8a249a blueswir1
                            case 7: // tl
3328 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3329 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, tl));
3330 0f8a249a blueswir1
                                break;
3331 0f8a249a blueswir1
                            case 8: // pil
3332 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3333 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, psrpil));
3334 0f8a249a blueswir1
                                break;
3335 0f8a249a blueswir1
                            case 9: // cwp
3336 6ae20372 blueswir1
                                tcg_gen_helper_0_1(helper_wrcwp, cpu_dst);
3337 0f8a249a blueswir1
                                break;
3338 0f8a249a blueswir1
                            case 10: // cansave
3339 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3340 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cansave));
3341 0f8a249a blueswir1
                                break;
3342 0f8a249a blueswir1
                            case 11: // canrestore
3343 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3344 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, canrestore));
3345 0f8a249a blueswir1
                                break;
3346 0f8a249a blueswir1
                            case 12: // cleanwin
3347 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3348 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, cleanwin));
3349 0f8a249a blueswir1
                                break;
3350 0f8a249a blueswir1
                            case 13: // otherwin
3351 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3352 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, otherwin));
3353 0f8a249a blueswir1
                                break;
3354 0f8a249a blueswir1
                            case 14: // wstate
3355 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3356 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wstate));
3357 0f8a249a blueswir1
                                break;
3358 e9ebed4d blueswir1
                            case 16: // UA2005 gl
3359 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3360 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, gl));
3361 e9ebed4d blueswir1
                                break;
3362 e9ebed4d blueswir1
                            case 26: // UA2005 strand status
3363 e9ebed4d blueswir1
                                if (!hypervisor(dc))
3364 e9ebed4d blueswir1
                                    goto priv_insn;
3365 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3366 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, ssr));
3367 e9ebed4d blueswir1
                                break;
3368 0f8a249a blueswir1
                            default:
3369 0f8a249a blueswir1
                                goto illegal_insn;
3370 0f8a249a blueswir1
                            }
3371 3475187d bellard
#else
3372 6ae20372 blueswir1
                            tcg_gen_andi_tl(cpu_dst, cpu_dst, ((1 << NWINDOWS) - 1));
3373 6ae20372 blueswir1
                            tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3374 2f5680ee blueswir1
                            tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, wim));
3375 3475187d bellard
#endif
3376 e8af50a3 bellard
                        }
3377 e8af50a3 bellard
                        break;
3378 e9ebed4d blueswir1
                    case 0x33: /* wrtbr, UA2005 wrhpr */
3379 e8af50a3 bellard
                        {
3380 e9ebed4d blueswir1
#ifndef TARGET_SPARC64
3381 0f8a249a blueswir1
                            if (!supervisor(dc))
3382 0f8a249a blueswir1
                                goto priv_insn;
3383 6ae20372 blueswir1
                            tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3384 6ae20372 blueswir1
                            tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState, tbr));
3385 e9ebed4d blueswir1
#else
3386 e9ebed4d blueswir1
                            if (!hypervisor(dc))
3387 e9ebed4d blueswir1
                                goto priv_insn;
3388 6ae20372 blueswir1
                            tcg_gen_xor_tl(cpu_dst, cpu_dst, cpu_src2);
3389 e9ebed4d blueswir1
                            switch (rd) {
3390 e9ebed4d blueswir1
                            case 0: // hpstate
3391 e9ebed4d blueswir1
                                // XXX gen_op_wrhpstate();
3392 6ae20372 blueswir1
                                save_state(dc, cpu_cond);
3393 e9ebed4d blueswir1
                                gen_op_next_insn();
3394 57fec1fe bellard
                                tcg_gen_exit_tb(0);
3395 e9ebed4d blueswir1
                                dc->is_br = 1;
3396 e9ebed4d blueswir1
                                break;
3397 e9ebed4d blueswir1
                            case 1: // htstate
3398 e9ebed4d blueswir1
                                // XXX gen_op_wrhtstate();
3399 e9ebed4d blueswir1
                                break;
3400 e9ebed4d blueswir1
                            case 3: // hintp
3401 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3402 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, hintp));
3403 e9ebed4d blueswir1
                                break;
3404 e9ebed4d blueswir1
                            case 5: // htba
3405 6ae20372 blueswir1
                                tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
3406 2f5680ee blueswir1
                                tcg_gen_st_i32(cpu_tmp32, cpu_env, offsetof(CPUSPARCState, htba));
3407 e9ebed4d blueswir1
                                break;
3408 e9ebed4d blueswir1
                            case 31: // hstick_cmpr
3409 ccd4a219 blueswir1
                                {
3410 ccd4a219 blueswir1
                                    TCGv r_tickptr;
3411 ccd4a219 blueswir1
3412 6ae20372 blueswir1
                                    tcg_gen_st_tl(cpu_dst, cpu_env, offsetof(CPUSPARCState,
3413 ccd4a219 blueswir1
                                                                 hstick_cmpr));
3414 ccd4a219 blueswir1
                                    r_tickptr = tcg_temp_new(TCG_TYPE_PTR);
3415 ccd4a219 blueswir1
                                    tcg_gen_ld_ptr(r_tickptr, cpu_env,
3416 ccd4a219 blueswir1
                                                   offsetof(CPUState, hstick));
3417 ccd4a219 blueswir1
                                    tcg_gen_helper_0_2(helper_tick_set_limit,
3418 6ae20372 blueswir1
                                                       r_tickptr, cpu_dst);
3419 0425bee5 blueswir1
                                    tcg_gen_discard_ptr(r_tickptr);
3420 ccd4a219 blueswir1
                                }
3421 e9ebed4d blueswir1
                                break;
3422 e9ebed4d blueswir1
                            case 6: // hver readonly
3423 e9ebed4d blueswir1
                            default:
3424 e9ebed4d blueswir1
                                goto illegal_insn;
3425 e9ebed4d blueswir1
                            }
3426 e9ebed4d blueswir1
#endif
3427 e8af50a3 bellard
                        }
3428 e8af50a3 bellard
                        break;
3429 e8af50a3 bellard
#endif
3430 3475187d bellard
#ifdef TARGET_SPARC64
3431 0f8a249a blueswir1
                    case 0x2c: /* V9 movcc */
3432 0f8a249a blueswir1
                        {
3433 0f8a249a blueswir1
                            int cc = GET_FIELD_SP(insn, 11, 12);
3434 0f8a249a blueswir1
                            int cond = GET_FIELD_SP(insn, 14, 17);
3435 748b9d8e blueswir1
                            TCGv r_cond;
3436 00f219bf blueswir1
                            int l1;
3437 00f219bf blueswir1
3438 748b9d8e blueswir1
                            r_cond = tcg_temp_new(TCG_TYPE_TL);
3439 0f8a249a blueswir1
                            if (insn & (1 << 18)) {
3440 0f8a249a blueswir1
                                if (cc == 0)
3441 748b9d8e blueswir1
                                    gen_cond(r_cond, 0, cond);
3442 0f8a249a blueswir1
                                else if (cc == 2)
3443 748b9d8e blueswir1
                                    gen_cond(r_cond, 1, cond);
3444 0f8a249a blueswir1
                                else
3445 0f8a249a blueswir1
                                    goto illegal_insn;
3446 0f8a249a blueswir1
                            } else {
3447 748b9d8e blueswir1
                                gen_fcond(r_cond, cc, cond);
3448 0f8a249a blueswir1
                            }
3449 00f219bf blueswir1
3450 00f219bf blueswir1
                            l1 = gen_new_label();
3451 00f219bf blueswir1
3452 748b9d8e blueswir1
                            tcg_gen_brcond_tl(TCG_COND_EQ, r_cond,
3453 748b9d8e blueswir1
                                              tcg_const_tl(0), l1);
3454 00f219bf blueswir1
                            if (IS_IMM) {       /* immediate */
3455 00f219bf blueswir1
                                rs2 = GET_FIELD_SPs(insn, 0, 10);
3456 6ae20372 blueswir1
                                tcg_gen_movi_tl(cpu_dst, (int)rs2);
3457 00f219bf blueswir1
                            } else {
3458 00f219bf blueswir1
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3459 6ae20372 blueswir1
                                gen_movl_reg_TN(rs2, cpu_dst);
3460 00f219bf blueswir1
                            }
3461 6ae20372 blueswir1
                            gen_movl_TN_reg(rd, cpu_dst);
3462 00f219bf blueswir1
                            gen_set_label(l1);
3463 0425bee5 blueswir1
                            tcg_gen_discard_tl(r_cond);
3464 0f8a249a blueswir1
                            break;
3465 0f8a249a blueswir1
                        }
3466 0f8a249a blueswir1
                    case 0x2d: /* V9 sdivx */
3467 6ae20372 blueswir1
                        gen_op_sdivx(cpu_dst, cpu_src1, cpu_src2);
3468 6ae20372 blueswir1
                        gen_movl_TN_reg(rd, cpu_dst);
3469 0f8a249a blueswir1
                        break;
3470 0f8a249a blueswir1
                    case 0x2e: /* V9 popc */
3471 0f8a249a blueswir1
                        {
3472 0f8a249a blueswir1
                            if (IS_IMM) {       /* immediate */
3473 0f8a249a blueswir1
                                rs2 = GET_FIELD_SPs(insn, 0, 12);
3474 6ae20372 blueswir1
                                tcg_gen_movi_tl(cpu_src2, (int)rs2);
3475 0f8a249a blueswir1
                                // XXX optimize: popc(constant)
3476 0f8a249a blueswir1
                            }
3477 0f8a249a blueswir1
                            else {
3478 0f8a249a blueswir1
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3479 6ae20372 blueswir1
                                gen_movl_reg_TN(rs2, cpu_src2);
3480 0f8a249a blueswir1
                            }
3481 6ae20372 blueswir1
                            tcg_gen_helper_1_1(helper_popc, cpu_dst,
3482 6ae20372 blueswir1
                                               cpu_src2);
3483 6ae20372 blueswir1
                            gen_movl_TN_reg(rd, cpu_dst);
3484 0f8a249a blueswir1
                        }
3485 0f8a249a blueswir1
                    case 0x2f: /* V9 movr */
3486 0f8a249a blueswir1
                        {
3487 0f8a249a blueswir1
                            int cond = GET_FIELD_SP(insn, 10, 12);
3488 00f219bf blueswir1
                            int l1;
3489 00f219bf blueswir1
3490 9322a4bf blueswir1
                            cpu_src1 = get_src1(insn, cpu_src1);
3491 00f219bf blueswir1
3492 00f219bf blueswir1
                            l1 = gen_new_label();
3493 00f219bf blueswir1
3494 6ae20372 blueswir1
                            tcg_gen_brcond_tl(gen_tcg_cond_reg[cond], cpu_src1,
3495 0425bee5 blueswir1
                                              tcg_const_tl(0), l1);
3496 0f8a249a blueswir1
                            if (IS_IMM) {       /* immediate */
3497 0f8a249a blueswir1
                                rs2 = GET_FIELD_SPs(insn, 0, 9);
3498 6ae20372 blueswir1
                                tcg_gen_movi_tl(cpu_dst, (int)rs2);
3499 00f219bf blueswir1
                            } else {
3500 0f8a249a blueswir1
                                rs2 = GET_FIELD_SP(insn, 0, 4);
3501 6ae20372 blueswir1
                                gen_movl_reg_TN(rs2, cpu_dst);
3502 0f8a249a blueswir1
                            }
3503 6ae20372 blueswir1
                            gen_movl_TN_reg(rd, cpu_dst);
3504 00f219bf blueswir1
                            gen_set_label(l1);
3505 0f8a249a blueswir1
                            break;
3506 0f8a249a blueswir1
                        }
3507 0f8a249a blueswir1
#endif
3508 0f8a249a blueswir1
                    default:
3509 0f8a249a blueswir1
                        goto illegal_insn;
3510 0f8a249a blueswir1
                    }
3511 0f8a249a blueswir1
                }
3512 3299908c blueswir1
            } else if (xop == 0x36) { /* UltraSparc shutdown, VIS, V8 CPop1 */
3513 3299908c blueswir1
#ifdef TARGET_SPARC64
3514 3299908c blueswir1
                int opf = GET_FIELD_SP(insn, 5, 13);
3515 3299908c blueswir1
                rs1 = GET_FIELD(insn, 13, 17);
3516 3299908c blueswir1
                rs2 = GET_FIELD(insn, 27, 31);
3517 6ae20372 blueswir1
                if (gen_trap_ifnofpu(dc, cpu_cond))
3518 e9ebed4d blueswir1
                    goto jmp_insn;
3519 3299908c blueswir1
3520 3299908c blueswir1
                switch (opf) {
3521 e9ebed4d blueswir1
                case 0x000: /* VIS I edge8cc */
3522 e9ebed4d blueswir1
                case 0x001: /* VIS II edge8n */
3523 e9ebed4d blueswir1
                case 0x002: /* VIS I edge8lcc */
3524 e9ebed4d blueswir1
                case 0x003: /* VIS II edge8ln */
3525 e9ebed4d blueswir1
                case 0x004: /* VIS I edge16cc */
3526 e9ebed4d blueswir1
                case 0x005: /* VIS II edge16n */
3527 e9ebed4d blueswir1
                case 0x006: /* VIS I edge16lcc */
3528 e9ebed4d blueswir1
                case 0x007: /* VIS II edge16ln */
3529 e9ebed4d blueswir1
                case 0x008: /* VIS I edge32cc */
3530 e9ebed4d blueswir1
                case 0x009: /* VIS II edge32n */
3531 e9ebed4d blueswir1
                case 0x00a: /* VIS I edge32lcc */
3532 e9ebed4d blueswir1
                case 0x00b: /* VIS II edge32ln */
3533 e9ebed4d blueswir1
                    // XXX
3534 e9ebed4d blueswir1
                    goto illegal_insn;
3535 e9ebed4d blueswir1
                case 0x010: /* VIS I array8 */
3536 9322a4bf blueswir1
                    cpu_src1 = get_src1(insn, cpu_src1);
3537 6ae20372 blueswir1
                    gen_movl_reg_TN(rs2, cpu_src2);
3538 6ae20372 blueswir1
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3539 6ae20372 blueswir1
                                       cpu_src2);
3540 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
3541 e9ebed4d blueswir1
                    break;
3542 e9ebed4d blueswir1
                case 0x012: /* VIS I array16 */
3543 9322a4bf blueswir1
                    cpu_src1 = get_src1(insn, cpu_src1);
3544 6ae20372 blueswir1
                    gen_movl_reg_TN(rs2, cpu_src2);
3545 6ae20372 blueswir1
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3546 6ae20372 blueswir1
                                       cpu_src2);
3547 6ae20372 blueswir1
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 1);
3548 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
3549 e9ebed4d blueswir1
                    break;
3550 e9ebed4d blueswir1
                case 0x014: /* VIS I array32 */
3551 9322a4bf blueswir1
                    cpu_src1 = get_src1(insn, cpu_src1);
3552 6ae20372 blueswir1
                    gen_movl_reg_TN(rs2, cpu_src2);
3553 6ae20372 blueswir1
                    tcg_gen_helper_1_2(helper_array8, cpu_dst, cpu_src1,
3554 6ae20372 blueswir1
                                       cpu_src2);
3555 6ae20372 blueswir1
                    tcg_gen_shli_i64(cpu_dst, cpu_dst, 2);
3556 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
3557 e9ebed4d blueswir1
                    break;
3558 3299908c blueswir1
                case 0x018: /* VIS I alignaddr */
3559 9322a4bf blueswir1
                    cpu_src1 = get_src1(insn, cpu_src1);
3560 6ae20372 blueswir1
                    gen_movl_reg_TN(rs2, cpu_src2);
3561 6ae20372 blueswir1
                    tcg_gen_helper_1_2(helper_alignaddr, cpu_dst, cpu_src1,
3562 6ae20372 blueswir1
                                       cpu_src2);
3563 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
3564 3299908c blueswir1
                    break;
3565 e9ebed4d blueswir1
                case 0x019: /* VIS II bmask */
3566 3299908c blueswir1
                case 0x01a: /* VIS I alignaddrl */
3567 3299908c blueswir1
                    // XXX
3568 e9ebed4d blueswir1
                    goto illegal_insn;
3569 e9ebed4d blueswir1
                case 0x020: /* VIS I fcmple16 */
3570 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3571 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3572 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fcmple16);
3573 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3574 e9ebed4d blueswir1
                    break;
3575 e9ebed4d blueswir1
                case 0x022: /* VIS I fcmpne16 */
3576 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3577 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3578 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fcmpne16);
3579 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3580 3299908c blueswir1
                    break;
3581 e9ebed4d blueswir1
                case 0x024: /* VIS I fcmple32 */
3582 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3583 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3584 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fcmple32);
3585 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3586 e9ebed4d blueswir1
                    break;
3587 e9ebed4d blueswir1
                case 0x026: /* VIS I fcmpne32 */
3588 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3589 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3590 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fcmpne32);
3591 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3592 e9ebed4d blueswir1
                    break;
3593 e9ebed4d blueswir1
                case 0x028: /* VIS I fcmpgt16 */
3594 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3595 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3596 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fcmpgt16);
3597 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3598 e9ebed4d blueswir1
                    break;
3599 e9ebed4d blueswir1
                case 0x02a: /* VIS I fcmpeq16 */
3600 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3601 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3602 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fcmpeq16);
3603 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3604 e9ebed4d blueswir1
                    break;
3605 e9ebed4d blueswir1
                case 0x02c: /* VIS I fcmpgt32 */
3606 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3607 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3608 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fcmpgt32);
3609 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3610 e9ebed4d blueswir1
                    break;
3611 e9ebed4d blueswir1
                case 0x02e: /* VIS I fcmpeq32 */
3612 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3613 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3614 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fcmpeq32);
3615 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3616 e9ebed4d blueswir1
                    break;
3617 e9ebed4d blueswir1
                case 0x031: /* VIS I fmul8x16 */
3618 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3619 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3620 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fmul8x16);
3621 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3622 e9ebed4d blueswir1
                    break;
3623 e9ebed4d blueswir1
                case 0x033: /* VIS I fmul8x16au */
3624 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3625 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3626 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fmul8x16au);
3627 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3628 e9ebed4d blueswir1
                    break;
3629 e9ebed4d blueswir1
                case 0x035: /* VIS I fmul8x16al */
3630 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3631 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3632 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fmul8x16al);
3633 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3634 e9ebed4d blueswir1
                    break;
3635 e9ebed4d blueswir1
                case 0x036: /* VIS I fmul8sux16 */
3636 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3637 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3638 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fmul8sux16);
3639 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3640 e9ebed4d blueswir1
                    break;
3641 e9ebed4d blueswir1
                case 0x037: /* VIS I fmul8ulx16 */
3642 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3643 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3644 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fmul8ulx16);
3645 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3646 e9ebed4d blueswir1
                    break;
3647 e9ebed4d blueswir1
                case 0x038: /* VIS I fmuld8sux16 */
3648 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3649 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3650 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fmuld8sux16);
3651 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3652 e9ebed4d blueswir1
                    break;
3653 e9ebed4d blueswir1
                case 0x039: /* VIS I fmuld8ulx16 */
3654 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3655 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3656 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fmuld8ulx16);
3657 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3658 e9ebed4d blueswir1
                    break;
3659 e9ebed4d blueswir1
                case 0x03a: /* VIS I fpack32 */
3660 e9ebed4d blueswir1
                case 0x03b: /* VIS I fpack16 */
3661 e9ebed4d blueswir1
                case 0x03d: /* VIS I fpackfix */
3662 e9ebed4d blueswir1
                case 0x03e: /* VIS I pdist */
3663 e9ebed4d blueswir1
                    // XXX
3664 e9ebed4d blueswir1
                    goto illegal_insn;
3665 3299908c blueswir1
                case 0x048: /* VIS I faligndata */
3666 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3667 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3668 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_faligndata);
3669 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3670 3299908c blueswir1
                    break;
3671 e9ebed4d blueswir1
                case 0x04b: /* VIS I fpmerge */
3672 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3673 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3674 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fpmerge);
3675 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3676 e9ebed4d blueswir1
                    break;
3677 e9ebed4d blueswir1
                case 0x04c: /* VIS II bshuffle */
3678 e9ebed4d blueswir1
                    // XXX
3679 e9ebed4d blueswir1
                    goto illegal_insn;
3680 e9ebed4d blueswir1
                case 0x04d: /* VIS I fexpand */
3681 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3682 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3683 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fexpand);
3684 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3685 e9ebed4d blueswir1
                    break;
3686 e9ebed4d blueswir1
                case 0x050: /* VIS I fpadd16 */
3687 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3688 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3689 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fpadd16);
3690 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3691 e9ebed4d blueswir1
                    break;
3692 e9ebed4d blueswir1
                case 0x051: /* VIS I fpadd16s */
3693 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3694 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3695 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fpadd16s);
3696 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3697 e9ebed4d blueswir1
                    break;
3698 e9ebed4d blueswir1
                case 0x052: /* VIS I fpadd32 */
3699 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3700 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3701 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fpadd32);
3702 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3703 e9ebed4d blueswir1
                    break;
3704 e9ebed4d blueswir1
                case 0x053: /* VIS I fpadd32s */
3705 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3706 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3707 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fpadd32s);
3708 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3709 e9ebed4d blueswir1
                    break;
3710 e9ebed4d blueswir1
                case 0x054: /* VIS I fpsub16 */
3711 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3712 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3713 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fpsub16);
3714 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3715 e9ebed4d blueswir1
                    break;
3716 e9ebed4d blueswir1
                case 0x055: /* VIS I fpsub16s */
3717 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3718 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3719 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fpsub16s);
3720 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3721 e9ebed4d blueswir1
                    break;
3722 e9ebed4d blueswir1
                case 0x056: /* VIS I fpsub32 */
3723 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3724 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3725 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fpadd32);
3726 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3727 e9ebed4d blueswir1
                    break;
3728 e9ebed4d blueswir1
                case 0x057: /* VIS I fpsub32s */
3729 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3730 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3731 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fpsub32s);
3732 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3733 e9ebed4d blueswir1
                    break;
3734 3299908c blueswir1
                case 0x060: /* VIS I fzero */
3735 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_movl_DT0_0);
3736 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3737 3299908c blueswir1
                    break;
3738 3299908c blueswir1
                case 0x061: /* VIS I fzeros */
3739 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_movl_FT0_0);
3740 3299908c blueswir1
                    gen_op_store_FT0_fpr(rd);
3741 3299908c blueswir1
                    break;
3742 e9ebed4d blueswir1
                case 0x062: /* VIS I fnor */
3743 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3744 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3745 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fnor);
3746 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3747 e9ebed4d blueswir1
                    break;
3748 e9ebed4d blueswir1
                case 0x063: /* VIS I fnors */
3749 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3750 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3751 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fnors);
3752 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3753 e9ebed4d blueswir1
                    break;
3754 e9ebed4d blueswir1
                case 0x064: /* VIS I fandnot2 */
3755 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3756 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3757 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fandnot);
3758 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3759 e9ebed4d blueswir1
                    break;
3760 e9ebed4d blueswir1
                case 0x065: /* VIS I fandnot2s */
3761 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs1);
3762 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs2);
3763 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fandnots);
3764 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3765 e9ebed4d blueswir1
                    break;
3766 e9ebed4d blueswir1
                case 0x066: /* VIS I fnot2 */
3767 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3768 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fnot);
3769 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3770 e9ebed4d blueswir1
                    break;
3771 e9ebed4d blueswir1
                case 0x067: /* VIS I fnot2s */
3772 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3773 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fnot);
3774 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3775 e9ebed4d blueswir1
                    break;
3776 e9ebed4d blueswir1
                case 0x068: /* VIS I fandnot1 */
3777 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3778 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3779 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fandnot);
3780 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3781 e9ebed4d blueswir1
                    break;
3782 e9ebed4d blueswir1
                case 0x069: /* VIS I fandnot1s */
3783 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3784 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3785 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fandnots);
3786 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3787 e9ebed4d blueswir1
                    break;
3788 e9ebed4d blueswir1
                case 0x06a: /* VIS I fnot1 */
3789 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3790 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fnot);
3791 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3792 e9ebed4d blueswir1
                    break;
3793 e9ebed4d blueswir1
                case 0x06b: /* VIS I fnot1s */
3794 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs1);
3795 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fnot);
3796 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3797 e9ebed4d blueswir1
                    break;
3798 e9ebed4d blueswir1
                case 0x06c: /* VIS I fxor */
3799 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3800 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3801 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fxor);
3802 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3803 e9ebed4d blueswir1
                    break;
3804 e9ebed4d blueswir1
                case 0x06d: /* VIS I fxors */
3805 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3806 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3807 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fxors);
3808 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3809 e9ebed4d blueswir1
                    break;
3810 e9ebed4d blueswir1
                case 0x06e: /* VIS I fnand */
3811 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3812 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3813 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fnand);
3814 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3815 e9ebed4d blueswir1
                    break;
3816 e9ebed4d blueswir1
                case 0x06f: /* VIS I fnands */
3817 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3818 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3819 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fnands);
3820 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3821 e9ebed4d blueswir1
                    break;
3822 e9ebed4d blueswir1
                case 0x070: /* VIS I fand */
3823 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3824 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3825 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fand);
3826 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3827 e9ebed4d blueswir1
                    break;
3828 e9ebed4d blueswir1
                case 0x071: /* VIS I fands */
3829 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3830 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3831 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fands);
3832 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3833 e9ebed4d blueswir1
                    break;
3834 e9ebed4d blueswir1
                case 0x072: /* VIS I fxnor */
3835 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3836 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3837 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fxnor);
3838 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3839 e9ebed4d blueswir1
                    break;
3840 e9ebed4d blueswir1
                case 0x073: /* VIS I fxnors */
3841 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3842 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3843 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fxnors);
3844 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3845 e9ebed4d blueswir1
                    break;
3846 3299908c blueswir1
                case 0x074: /* VIS I fsrc1 */
3847 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3848 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3849 3299908c blueswir1
                    break;
3850 3299908c blueswir1
                case 0x075: /* VIS I fsrc1s */
3851 3299908c blueswir1
                    gen_op_load_fpr_FT0(rs1);
3852 3299908c blueswir1
                    gen_op_store_FT0_fpr(rd);
3853 3299908c blueswir1
                    break;
3854 e9ebed4d blueswir1
                case 0x076: /* VIS I fornot2 */
3855 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs1));
3856 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3857 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fornot);
3858 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3859 e9ebed4d blueswir1
                    break;
3860 e9ebed4d blueswir1
                case 0x077: /* VIS I fornot2s */
3861 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs1);
3862 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs2);
3863 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fornots);
3864 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3865 e9ebed4d blueswir1
                    break;
3866 3299908c blueswir1
                case 0x078: /* VIS I fsrc2 */
3867 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs2));
3868 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3869 3299908c blueswir1
                    break;
3870 3299908c blueswir1
                case 0x079: /* VIS I fsrc2s */
3871 3299908c blueswir1
                    gen_op_load_fpr_FT0(rs2);
3872 3299908c blueswir1
                    gen_op_store_FT0_fpr(rd);
3873 3299908c blueswir1
                    break;
3874 e9ebed4d blueswir1
                case 0x07a: /* VIS I fornot1 */
3875 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3876 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3877 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fornot);
3878 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3879 e9ebed4d blueswir1
                    break;
3880 e9ebed4d blueswir1
                case 0x07b: /* VIS I fornot1s */
3881 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3882 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3883 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fornots);
3884 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3885 e9ebed4d blueswir1
                    break;
3886 e9ebed4d blueswir1
                case 0x07c: /* VIS I for */
3887 2382dc6b blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rs1));
3888 2382dc6b blueswir1
                    gen_op_load_fpr_DT1(DFPREG(rs2));
3889 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_for);
3890 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3891 e9ebed4d blueswir1
                    break;
3892 e9ebed4d blueswir1
                case 0x07d: /* VIS I fors */
3893 e9ebed4d blueswir1
                    gen_op_load_fpr_FT0(rs1);
3894 e9ebed4d blueswir1
                    gen_op_load_fpr_FT1(rs2);
3895 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_fors);
3896 e9ebed4d blueswir1
                    gen_op_store_FT0_fpr(rd);
3897 e9ebed4d blueswir1
                    break;
3898 3299908c blueswir1
                case 0x07e: /* VIS I fone */
3899 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_movl_DT0_1);
3900 2382dc6b blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
3901 3299908c blueswir1
                    break;
3902 3299908c blueswir1
                case 0x07f: /* VIS I fones */
3903 44e7757c blueswir1
                    tcg_gen_helper_0_0(helper_movl_FT0_1);
3904 3299908c blueswir1
                    gen_op_store_FT0_fpr(rd);
3905 3299908c blueswir1
                    break;
3906 e9ebed4d blueswir1
                case 0x080: /* VIS I shutdown */
3907 e9ebed4d blueswir1
                case 0x081: /* VIS II siam */
3908 e9ebed4d blueswir1
                    // XXX
3909 e9ebed4d blueswir1
                    goto illegal_insn;
3910 3299908c blueswir1
                default:
3911 3299908c blueswir1
                    goto illegal_insn;
3912 3299908c blueswir1
                }
3913 3299908c blueswir1
#else
3914 0f8a249a blueswir1
                goto ncp_insn;
3915 3299908c blueswir1
#endif
3916 3299908c blueswir1
            } else if (xop == 0x37) { /* V8 CPop2, V9 impdep2 */
3917 fcc72045 blueswir1
#ifdef TARGET_SPARC64
3918 0f8a249a blueswir1
                goto illegal_insn;
3919 fcc72045 blueswir1
#else
3920 0f8a249a blueswir1
                goto ncp_insn;
3921 fcc72045 blueswir1
#endif
3922 3475187d bellard
#ifdef TARGET_SPARC64
3923 0f8a249a blueswir1
            } else if (xop == 0x39) { /* V9 return */
3924 6ae20372 blueswir1
                save_state(dc, cpu_cond);
3925 9322a4bf blueswir1
                cpu_src1 = get_src1(insn, cpu_src1);
3926 0f8a249a blueswir1
                if (IS_IMM) {   /* immediate */
3927 0f8a249a blueswir1
                    rs2 = GET_FIELDs(insn, 19, 31);
3928 6ae20372 blueswir1
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3929 0f8a249a blueswir1
                } else {                /* register */
3930 3475187d bellard
                    rs2 = GET_FIELD(insn, 27, 31);
3931 3475187d bellard
#if defined(OPTIM)
3932 0f8a249a blueswir1
                    if (rs2) {
3933 3475187d bellard
#endif
3934 6ae20372 blueswir1
                        gen_movl_reg_TN(rs2, cpu_src2);
3935 6ae20372 blueswir1
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3936 3475187d bellard
#if defined(OPTIM)
3937 0f8a249a blueswir1
                    }
3938 3475187d bellard
#endif
3939 3475187d bellard
                }
3940 72a9747b blueswir1
                tcg_gen_helper_0_0(helper_restore);
3941 6ae20372 blueswir1
                gen_mov_pc_npc(dc, cpu_cond);
3942 6ae20372 blueswir1
                tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3943 6ae20372 blueswir1
                tcg_gen_mov_tl(cpu_npc, cpu_dst);
3944 0f8a249a blueswir1
                dc->npc = DYNAMIC_PC;
3945 0f8a249a blueswir1
                goto jmp_insn;
3946 3475187d bellard
#endif
3947 0f8a249a blueswir1
            } else {
3948 9322a4bf blueswir1
                cpu_src1 = get_src1(insn, cpu_src1);
3949 0f8a249a blueswir1
                if (IS_IMM) {   /* immediate */
3950 0f8a249a blueswir1
                    rs2 = GET_FIELDs(insn, 19, 31);
3951 6ae20372 blueswir1
                    tcg_gen_addi_tl(cpu_dst, cpu_src1, (int)rs2);
3952 0f8a249a blueswir1
                } else {                /* register */
3953 e80cfcfc bellard
                    rs2 = GET_FIELD(insn, 27, 31);
3954 e80cfcfc bellard
#if defined(OPTIM)
3955 0f8a249a blueswir1
                    if (rs2) {
3956 e80cfcfc bellard
#endif
3957 6ae20372 blueswir1
                        gen_movl_reg_TN(rs2, cpu_src2);
3958 6ae20372 blueswir1
                        tcg_gen_add_tl(cpu_dst, cpu_src1, cpu_src2);
3959 e80cfcfc bellard
#if defined(OPTIM)
3960 0f8a249a blueswir1
                    }
3961 e8af50a3 bellard
#endif
3962 cf495bcf bellard
                }
3963 0f8a249a blueswir1
                switch (xop) {
3964 0f8a249a blueswir1
                case 0x38:      /* jmpl */
3965 0f8a249a blueswir1
                    {
3966 0f8a249a blueswir1
                        if (rd != 0) {
3967 32b6c812 blueswir1
                            tcg_gen_movi_tl(cpu_tmp0, dc->pc);
3968 32b6c812 blueswir1
                            gen_movl_TN_reg(rd, cpu_tmp0);
3969 0f8a249a blueswir1
                        }
3970 6ae20372 blueswir1
                        gen_mov_pc_npc(dc, cpu_cond);
3971 6ae20372 blueswir1
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3972 6ae20372 blueswir1
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
3973 0f8a249a blueswir1
                        dc->npc = DYNAMIC_PC;
3974 0f8a249a blueswir1
                    }
3975 0f8a249a blueswir1
                    goto jmp_insn;
3976 3475187d bellard
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
3977 0f8a249a blueswir1
                case 0x39:      /* rett, V9 return */
3978 0f8a249a blueswir1
                    {
3979 0f8a249a blueswir1
                        if (!supervisor(dc))
3980 0f8a249a blueswir1
                            goto priv_insn;
3981 6ae20372 blueswir1
                        gen_mov_pc_npc(dc, cpu_cond);
3982 6ae20372 blueswir1
                        tcg_gen_helper_0_2(helper_check_align, cpu_dst, tcg_const_i32(3));
3983 6ae20372 blueswir1
                        tcg_gen_mov_tl(cpu_npc, cpu_dst);
3984 0f8a249a blueswir1
                        dc->npc = DYNAMIC_PC;
3985 1a2fb1c0 blueswir1
                        tcg_gen_helper_0_0(helper_rett);
3986 0f8a249a blueswir1
                    }
3987 0f8a249a blueswir1
                    goto jmp_insn;
3988 0f8a249a blueswir1
#endif
3989 0f8a249a blueswir1
                case 0x3b: /* flush */
3990 6ae20372 blueswir1
                    tcg_gen_helper_0_1(helper_flush, cpu_dst);
3991 0f8a249a blueswir1
                    break;
3992 0f8a249a blueswir1
                case 0x3c:      /* save */
3993 6ae20372 blueswir1
                    save_state(dc, cpu_cond);
3994 72a9747b blueswir1
                    tcg_gen_helper_0_0(helper_save);
3995 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
3996 0f8a249a blueswir1
                    break;
3997 0f8a249a blueswir1
                case 0x3d:      /* restore */
3998 6ae20372 blueswir1
                    save_state(dc, cpu_cond);
3999 72a9747b blueswir1
                    tcg_gen_helper_0_0(helper_restore);
4000 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_dst);
4001 0f8a249a blueswir1
                    break;
4002 3475187d bellard
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
4003 0f8a249a blueswir1
                case 0x3e:      /* V9 done/retry */
4004 0f8a249a blueswir1
                    {
4005 0f8a249a blueswir1
                        switch (rd) {
4006 0f8a249a blueswir1
                        case 0:
4007 0f8a249a blueswir1
                            if (!supervisor(dc))
4008 0f8a249a blueswir1
                                goto priv_insn;
4009 0f8a249a blueswir1
                            dc->npc = DYNAMIC_PC;
4010 0f8a249a blueswir1
                            dc->pc = DYNAMIC_PC;
4011 1a2fb1c0 blueswir1
                            tcg_gen_helper_0_0(helper_done);
4012 0f8a249a blueswir1
                            goto jmp_insn;
4013 0f8a249a blueswir1
                        case 1:
4014 0f8a249a blueswir1
                            if (!supervisor(dc))
4015 0f8a249a blueswir1
                                goto priv_insn;
4016 0f8a249a blueswir1
                            dc->npc = DYNAMIC_PC;
4017 0f8a249a blueswir1
                            dc->pc = DYNAMIC_PC;
4018 1a2fb1c0 blueswir1
                            tcg_gen_helper_0_0(helper_retry);
4019 0f8a249a blueswir1
                            goto jmp_insn;
4020 0f8a249a blueswir1
                        default:
4021 0f8a249a blueswir1
                            goto illegal_insn;
4022 0f8a249a blueswir1
                        }
4023 0f8a249a blueswir1
                    }
4024 0f8a249a blueswir1
                    break;
4025 0f8a249a blueswir1
#endif
4026 0f8a249a blueswir1
                default:
4027 0f8a249a blueswir1
                    goto illegal_insn;
4028 0f8a249a blueswir1
                }
4029 cf495bcf bellard
            }
4030 0f8a249a blueswir1
            break;
4031 0f8a249a blueswir1
        }
4032 0f8a249a blueswir1
        break;
4033 0f8a249a blueswir1
    case 3:                     /* load/store instructions */
4034 0f8a249a blueswir1
        {
4035 0f8a249a blueswir1
            unsigned int xop = GET_FIELD(insn, 7, 12);
4036 9322a4bf blueswir1
4037 6ae20372 blueswir1
            save_state(dc, cpu_cond);
4038 9322a4bf blueswir1
            cpu_src1 = get_src1(insn, cpu_src1);
4039 81ad8ba2 blueswir1
            if (xop == 0x3c || xop == 0x3e)
4040 81ad8ba2 blueswir1
            {
4041 81ad8ba2 blueswir1
                rs2 = GET_FIELD(insn, 27, 31);
4042 6ae20372 blueswir1
                gen_movl_reg_TN(rs2, cpu_src2);
4043 81ad8ba2 blueswir1
            }
4044 81ad8ba2 blueswir1
            else if (IS_IMM) {       /* immediate */
4045 0f8a249a blueswir1
                rs2 = GET_FIELDs(insn, 19, 31);
4046 6ae20372 blueswir1
                tcg_gen_addi_tl(cpu_addr, cpu_src1, (int)rs2);
4047 0f8a249a blueswir1
            } else {            /* register */
4048 0f8a249a blueswir1
                rs2 = GET_FIELD(insn, 27, 31);
4049 e80cfcfc bellard
#if defined(OPTIM)
4050 0f8a249a blueswir1
                if (rs2 != 0) {
4051 e80cfcfc bellard
#endif
4052 6ae20372 blueswir1
                    gen_movl_reg_TN(rs2, cpu_src2);
4053 6ae20372 blueswir1
                    tcg_gen_add_tl(cpu_addr, cpu_src1, cpu_src2);
4054 e80cfcfc bellard
#if defined(OPTIM)
4055 0f8a249a blueswir1
                }
4056 e80cfcfc bellard
#endif
4057 0f8a249a blueswir1
            }
4058 2f2ecb83 blueswir1
            if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) ||
4059 2f2ecb83 blueswir1
                (xop > 0x17 && xop <= 0x1d ) ||
4060 2f2ecb83 blueswir1
                (xop > 0x2c && xop <= 0x33) || xop == 0x1f || xop == 0x3d) {
4061 0f8a249a blueswir1
                switch (xop) {
4062 1a2fb1c0 blueswir1
                case 0x0:       /* load unsigned word */
4063 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4064 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4065 6ae20372 blueswir1
                    tcg_gen_qemu_ld32u(cpu_val, cpu_addr, dc->mem_idx);
4066 0f8a249a blueswir1
                    break;
4067 0f8a249a blueswir1
                case 0x1:       /* load unsigned byte */
4068 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4069 6ae20372 blueswir1
                    tcg_gen_qemu_ld8u(cpu_val, cpu_addr, dc->mem_idx);
4070 0f8a249a blueswir1
                    break;
4071 0f8a249a blueswir1
                case 0x2:       /* load unsigned halfword */
4072 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4073 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4074 6ae20372 blueswir1
                    tcg_gen_qemu_ld16u(cpu_val, cpu_addr, dc->mem_idx);
4075 0f8a249a blueswir1
                    break;
4076 0f8a249a blueswir1
                case 0x3:       /* load double word */
4077 0f8a249a blueswir1
                    if (rd & 1)
4078 d4218d99 blueswir1
                        goto illegal_insn;
4079 1a2fb1c0 blueswir1
                    else {
4080 6ae20372 blueswir1
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4081 6ae20372 blueswir1
                        ABI32_MASK(cpu_addr);
4082 6ae20372 blueswir1
                        tcg_gen_qemu_ld64(cpu_tmp64, cpu_addr, dc->mem_idx);
4083 32b6c812 blueswir1
                        tcg_gen_trunc_i64_tl(cpu_tmp0, cpu_tmp64);
4084 32b6c812 blueswir1
                        tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, 0xffffffffULL);
4085 32b6c812 blueswir1
                        gen_movl_TN_reg(rd + 1, cpu_tmp0);
4086 8911f501 blueswir1
                        tcg_gen_shri_i64(cpu_tmp64, cpu_tmp64, 32);
4087 6ae20372 blueswir1
                        tcg_gen_trunc_i64_tl(cpu_val, cpu_tmp64);
4088 6ae20372 blueswir1
                        tcg_gen_andi_tl(cpu_val, cpu_val, 0xffffffffULL);
4089 1a2fb1c0 blueswir1
                    }
4090 0f8a249a blueswir1
                    break;
4091 0f8a249a blueswir1
                case 0x9:       /* load signed byte */
4092 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4093 6ae20372 blueswir1
                    tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4094 0f8a249a blueswir1
                    break;
4095 0f8a249a blueswir1
                case 0xa:       /* load signed halfword */
4096 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4097 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4098 6ae20372 blueswir1
                    tcg_gen_qemu_ld16s(cpu_val, cpu_addr, dc->mem_idx);
4099 0f8a249a blueswir1
                    break;
4100 0f8a249a blueswir1
                case 0xd:       /* ldstub -- XXX: should be atomically */
4101 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4102 6ae20372 blueswir1
                    tcg_gen_qemu_ld8s(cpu_val, cpu_addr, dc->mem_idx);
4103 6ae20372 blueswir1
                    tcg_gen_qemu_st8(tcg_const_tl(0xff), cpu_addr, dc->mem_idx);
4104 0f8a249a blueswir1
                    break;
4105 0f8a249a blueswir1
                case 0x0f:      /* swap register with memory. Also atomically */
4106 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4107 6ae20372 blueswir1
                    gen_movl_reg_TN(rd, cpu_val);
4108 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4109 6ae20372 blueswir1
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4110 6ae20372 blueswir1
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4111 6ae20372 blueswir1
                    tcg_gen_extu_i32_tl(cpu_val, cpu_tmp32);
4112 0f8a249a blueswir1
                    break;
4113 3475187d bellard
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4114 0f8a249a blueswir1
                case 0x10:      /* load word alternate */
4115 3475187d bellard
#ifndef TARGET_SPARC64
4116 0f8a249a blueswir1
                    if (IS_IMM)
4117 0f8a249a blueswir1
                        goto illegal_insn;
4118 0f8a249a blueswir1
                    if (!supervisor(dc))
4119 0f8a249a blueswir1
                        goto priv_insn;
4120 6ea4a6c8 blueswir1
#endif
4121 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4122 6ae20372 blueswir1
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 0);
4123 0f8a249a blueswir1
                    break;
4124 0f8a249a blueswir1
                case 0x11:      /* load unsigned byte alternate */
4125 3475187d bellard
#ifndef TARGET_SPARC64
4126 0f8a249a blueswir1
                    if (IS_IMM)
4127 0f8a249a blueswir1
                        goto illegal_insn;
4128 0f8a249a blueswir1
                    if (!supervisor(dc))
4129 0f8a249a blueswir1
                        goto priv_insn;
4130 0f8a249a blueswir1
#endif
4131 6ae20372 blueswir1
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 0);
4132 0f8a249a blueswir1
                    break;
4133 0f8a249a blueswir1
                case 0x12:      /* load unsigned halfword alternate */
4134 3475187d bellard
#ifndef TARGET_SPARC64
4135 0f8a249a blueswir1
                    if (IS_IMM)
4136 0f8a249a blueswir1
                        goto illegal_insn;
4137 0f8a249a blueswir1
                    if (!supervisor(dc))
4138 0f8a249a blueswir1
                        goto priv_insn;
4139 6ea4a6c8 blueswir1
#endif
4140 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4141 6ae20372 blueswir1
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 0);
4142 0f8a249a blueswir1
                    break;
4143 0f8a249a blueswir1
                case 0x13:      /* load double word alternate */
4144 3475187d bellard
#ifndef TARGET_SPARC64
4145 0f8a249a blueswir1
                    if (IS_IMM)
4146 0f8a249a blueswir1
                        goto illegal_insn;
4147 0f8a249a blueswir1
                    if (!supervisor(dc))
4148 0f8a249a blueswir1
                        goto priv_insn;
4149 3475187d bellard
#endif
4150 0f8a249a blueswir1
                    if (rd & 1)
4151 d4218d99 blueswir1
                        goto illegal_insn;
4152 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4153 6ae20372 blueswir1
                    gen_ldda_asi(cpu_tmp0, cpu_val, cpu_addr, insn);
4154 32b6c812 blueswir1
                    gen_movl_TN_reg(rd + 1, cpu_tmp0);
4155 0f8a249a blueswir1
                    break;
4156 0f8a249a blueswir1
                case 0x19:      /* load signed byte alternate */
4157 3475187d bellard
#ifndef TARGET_SPARC64
4158 0f8a249a blueswir1
                    if (IS_IMM)
4159 0f8a249a blueswir1
                        goto illegal_insn;
4160 0f8a249a blueswir1
                    if (!supervisor(dc))
4161 0f8a249a blueswir1
                        goto priv_insn;
4162 0f8a249a blueswir1
#endif
4163 6ae20372 blueswir1
                    gen_ld_asi(cpu_val, cpu_addr, insn, 1, 1);
4164 0f8a249a blueswir1
                    break;
4165 0f8a249a blueswir1
                case 0x1a:      /* load signed halfword alternate */
4166 3475187d bellard
#ifndef TARGET_SPARC64
4167 0f8a249a blueswir1
                    if (IS_IMM)
4168 0f8a249a blueswir1
                        goto illegal_insn;
4169 0f8a249a blueswir1
                    if (!supervisor(dc))
4170 0f8a249a blueswir1
                        goto priv_insn;
4171 6ea4a6c8 blueswir1
#endif
4172 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4173 6ae20372 blueswir1
                    gen_ld_asi(cpu_val, cpu_addr, insn, 2, 1);
4174 0f8a249a blueswir1
                    break;
4175 0f8a249a blueswir1
                case 0x1d:      /* ldstuba -- XXX: should be atomically */
4176 3475187d bellard
#ifndef TARGET_SPARC64
4177 0f8a249a blueswir1
                    if (IS_IMM)
4178 0f8a249a blueswir1
                        goto illegal_insn;
4179 0f8a249a blueswir1
                    if (!supervisor(dc))
4180 0f8a249a blueswir1
                        goto priv_insn;
4181 0f8a249a blueswir1
#endif
4182 6ae20372 blueswir1
                    gen_ldstub_asi(cpu_val, cpu_addr, insn);
4183 0f8a249a blueswir1
                    break;
4184 0f8a249a blueswir1
                case 0x1f:      /* swap reg with alt. memory. Also atomically */
4185 3475187d bellard
#ifndef TARGET_SPARC64
4186 0f8a249a blueswir1
                    if (IS_IMM)
4187 0f8a249a blueswir1
                        goto illegal_insn;
4188 0f8a249a blueswir1
                    if (!supervisor(dc))
4189 0f8a249a blueswir1
                        goto priv_insn;
4190 6ea4a6c8 blueswir1
#endif
4191 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4192 6ae20372 blueswir1
                    gen_movl_reg_TN(rd, cpu_val);
4193 6ae20372 blueswir1
                    gen_swap_asi(cpu_val, cpu_addr, insn);
4194 0f8a249a blueswir1
                    break;
4195 3475187d bellard
4196 3475187d bellard
#ifndef TARGET_SPARC64
4197 0f8a249a blueswir1
                case 0x30: /* ldc */
4198 0f8a249a blueswir1
                case 0x31: /* ldcsr */
4199 0f8a249a blueswir1
                case 0x33: /* lddc */
4200 0f8a249a blueswir1
                    goto ncp_insn;
4201 3475187d bellard
#endif
4202 3475187d bellard
#endif
4203 3475187d bellard
#ifdef TARGET_SPARC64
4204 0f8a249a blueswir1
                case 0x08: /* V9 ldsw */
4205 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4206 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4207 6ae20372 blueswir1
                    tcg_gen_qemu_ld32s(cpu_val, cpu_addr, dc->mem_idx);
4208 0f8a249a blueswir1
                    break;
4209 0f8a249a blueswir1
                case 0x0b: /* V9 ldx */
4210 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4211 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4212 6ae20372 blueswir1
                    tcg_gen_qemu_ld64(cpu_val, cpu_addr, dc->mem_idx);
4213 0f8a249a blueswir1
                    break;
4214 0f8a249a blueswir1
                case 0x18: /* V9 ldswa */
4215 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4216 6ae20372 blueswir1
                    gen_ld_asi(cpu_val, cpu_addr, insn, 4, 1);
4217 0f8a249a blueswir1
                    break;
4218 0f8a249a blueswir1
                case 0x1b: /* V9 ldxa */
4219 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4220 6ae20372 blueswir1
                    gen_ld_asi(cpu_val, cpu_addr, insn, 8, 0);
4221 0f8a249a blueswir1
                    break;
4222 0f8a249a blueswir1
                case 0x2d: /* V9 prefetch, no effect */
4223 0f8a249a blueswir1
                    goto skip_move;
4224 0f8a249a blueswir1
                case 0x30: /* V9 ldfa */
4225 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4226 6ae20372 blueswir1
                    gen_ldf_asi(cpu_addr, insn, 4, rd);
4227 81ad8ba2 blueswir1
                    goto skip_move;
4228 0f8a249a blueswir1
                case 0x33: /* V9 lddfa */
4229 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4230 6ae20372 blueswir1
                    gen_ldf_asi(cpu_addr, insn, 8, DFPREG(rd));
4231 81ad8ba2 blueswir1
                    goto skip_move;
4232 0f8a249a blueswir1
                case 0x3d: /* V9 prefetcha, no effect */
4233 0f8a249a blueswir1
                    goto skip_move;
4234 0f8a249a blueswir1
                case 0x32: /* V9 ldqfa */
4235 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
4236 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4237 6ae20372 blueswir1
                    gen_ldf_asi(cpu_addr, insn, 16, QFPREG(rd));
4238 1f587329 blueswir1
                    goto skip_move;
4239 1f587329 blueswir1
#else
4240 0f8a249a blueswir1
                    goto nfpu_insn;
4241 0f8a249a blueswir1
#endif
4242 1f587329 blueswir1
#endif
4243 0f8a249a blueswir1
                default:
4244 0f8a249a blueswir1
                    goto illegal_insn;
4245 0f8a249a blueswir1
                }
4246 6ae20372 blueswir1
                gen_movl_TN_reg(rd, cpu_val);
4247 3475187d bellard
#ifdef TARGET_SPARC64
4248 0f8a249a blueswir1
            skip_move: ;
4249 3475187d bellard
#endif
4250 0f8a249a blueswir1
            } else if (xop >= 0x20 && xop < 0x24) {
4251 6ae20372 blueswir1
                if (gen_trap_ifnofpu(dc, cpu_cond))
4252 a80dde08 bellard
                    goto jmp_insn;
4253 0f8a249a blueswir1
                switch (xop) {
4254 0f8a249a blueswir1
                case 0x20:      /* load fpreg */
4255 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4256 6ae20372 blueswir1
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4257 ce8536e2 blueswir1
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4258 ce8536e2 blueswir1
                                   offsetof(CPUState, fpr[rd]));
4259 0f8a249a blueswir1
                    break;
4260 0f8a249a blueswir1
                case 0x21:      /* load fsr */
4261 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4262 6ae20372 blueswir1
                    tcg_gen_qemu_ld32u(cpu_tmp32, cpu_addr, dc->mem_idx);
4263 ce8536e2 blueswir1
                    tcg_gen_st_i32(cpu_tmp32, cpu_env,
4264 ce8536e2 blueswir1
                                   offsetof(CPUState, ft0));
4265 7e8c2b6c blueswir1
                    tcg_gen_helper_0_0(helper_ldfsr);
4266 0f8a249a blueswir1
                    break;
4267 0f8a249a blueswir1
                case 0x22:      /* load quad fpreg */
4268 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
4269 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4270 1f587329 blueswir1
                    gen_op_ldst(ldqf);
4271 1f587329 blueswir1
                    gen_op_store_QT0_fpr(QFPREG(rd));
4272 1f587329 blueswir1
                    break;
4273 1f587329 blueswir1
#else
4274 0f8a249a blueswir1
                    goto nfpu_insn;
4275 1f587329 blueswir1
#endif
4276 0f8a249a blueswir1
                case 0x23:      /* load double fpreg */
4277 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4278 0f8a249a blueswir1
                    gen_op_ldst(lddf);
4279 0f8a249a blueswir1
                    gen_op_store_DT0_fpr(DFPREG(rd));
4280 0f8a249a blueswir1
                    break;
4281 0f8a249a blueswir1
                default:
4282 0f8a249a blueswir1
                    goto illegal_insn;
4283 0f8a249a blueswir1
                }
4284 0f8a249a blueswir1
            } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
4285 0f8a249a blueswir1
                       xop == 0xe || xop == 0x1e) {
4286 6ae20372 blueswir1
                gen_movl_reg_TN(rd, cpu_val);
4287 0f8a249a blueswir1
                switch (xop) {
4288 1a2fb1c0 blueswir1
                case 0x4: /* store word */
4289 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4290 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4291 6ae20372 blueswir1
                    tcg_gen_qemu_st32(cpu_val, cpu_addr, dc->mem_idx);
4292 0f8a249a blueswir1
                    break;
4293 1a2fb1c0 blueswir1
                case 0x5: /* store byte */
4294 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4295 6ae20372 blueswir1
                    tcg_gen_qemu_st8(cpu_val, cpu_addr, dc->mem_idx);
4296 0f8a249a blueswir1
                    break;
4297 1a2fb1c0 blueswir1
                case 0x6: /* store halfword */
4298 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4299 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4300 6ae20372 blueswir1
                    tcg_gen_qemu_st16(cpu_val, cpu_addr, dc->mem_idx);
4301 0f8a249a blueswir1
                    break;
4302 1a2fb1c0 blueswir1
                case 0x7: /* store double word */
4303 0f8a249a blueswir1
                    if (rd & 1)
4304 d4218d99 blueswir1
                        goto illegal_insn;
4305 b25deda7 blueswir1
#ifndef __i386__
4306 1a2fb1c0 blueswir1
                    else {
4307 8911f501 blueswir1
                        TCGv r_low;
4308 1a2fb1c0 blueswir1
4309 6ae20372 blueswir1
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4310 1a2fb1c0 blueswir1
                        r_low = tcg_temp_new(TCG_TYPE_I32);
4311 1a2fb1c0 blueswir1
                        gen_movl_reg_TN(rd + 1, r_low);
4312 6ae20372 blueswir1
                        tcg_gen_helper_1_2(helper_pack64, cpu_tmp64, cpu_val,
4313 1a2fb1c0 blueswir1
                                           r_low);
4314 6ae20372 blueswir1
                        tcg_gen_qemu_st64(cpu_tmp64, cpu_addr, dc->mem_idx);
4315 1a2fb1c0 blueswir1
                    }
4316 b25deda7 blueswir1
#else /* __i386__ */
4317 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4318 6ae20372 blueswir1
                    flush_cond(dc, cpu_cond);
4319 6ae20372 blueswir1
                    gen_movl_reg_TN(rd + 1, cpu_cond);
4320 b25deda7 blueswir1
                    gen_op_ldst(std);
4321 b25deda7 blueswir1
#endif /* __i386__ */
4322 0f8a249a blueswir1
                    break;
4323 3475187d bellard
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
4324 1a2fb1c0 blueswir1
                case 0x14: /* store word alternate */
4325 3475187d bellard
#ifndef TARGET_SPARC64
4326 0f8a249a blueswir1
                    if (IS_IMM)
4327 0f8a249a blueswir1
                        goto illegal_insn;
4328 0f8a249a blueswir1
                    if (!supervisor(dc))
4329 0f8a249a blueswir1
                        goto priv_insn;
4330 3475187d bellard
#endif
4331 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4332 6ae20372 blueswir1
                    gen_st_asi(cpu_val, cpu_addr, insn, 4);
4333 d39c0b99 bellard
                    break;
4334 1a2fb1c0 blueswir1
                case 0x15: /* store byte alternate */
4335 3475187d bellard
#ifndef TARGET_SPARC64
4336 0f8a249a blueswir1
                    if (IS_IMM)
4337 0f8a249a blueswir1
                        goto illegal_insn;
4338 0f8a249a blueswir1
                    if (!supervisor(dc))
4339 0f8a249a blueswir1
                        goto priv_insn;
4340 3475187d bellard
#endif
4341 6ae20372 blueswir1
                    gen_st_asi(cpu_val, cpu_addr, insn, 1);
4342 d39c0b99 bellard
                    break;
4343 1a2fb1c0 blueswir1
                case 0x16: /* store halfword alternate */
4344 3475187d bellard
#ifndef TARGET_SPARC64
4345 0f8a249a blueswir1
                    if (IS_IMM)
4346 0f8a249a blueswir1
                        goto illegal_insn;
4347 0f8a249a blueswir1
                    if (!supervisor(dc))
4348 0f8a249a blueswir1
                        goto priv_insn;
4349 3475187d bellard
#endif
4350 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(1));
4351 6ae20372 blueswir1
                    gen_st_asi(cpu_val, cpu_addr, insn, 2);
4352 d39c0b99 bellard
                    break;
4353 1a2fb1c0 blueswir1
                case 0x17: /* store double word alternate */
4354 3475187d bellard
#ifndef TARGET_SPARC64
4355 0f8a249a blueswir1
                    if (IS_IMM)
4356 0f8a249a blueswir1
                        goto illegal_insn;
4357 0f8a249a blueswir1
                    if (!supervisor(dc))
4358 0f8a249a blueswir1
                        goto priv_insn;
4359 3475187d bellard
#endif
4360 0f8a249a blueswir1
                    if (rd & 1)
4361 d4218d99 blueswir1
                        goto illegal_insn;
4362 1a2fb1c0 blueswir1
                    else {
4363 6ae20372 blueswir1
                        tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4364 6ae20372 blueswir1
                        gen_stda_asi(cpu_val, cpu_addr, insn, rd);
4365 1a2fb1c0 blueswir1
                    }
4366 d39c0b99 bellard
                    break;
4367 e80cfcfc bellard
#endif
4368 3475187d bellard
#ifdef TARGET_SPARC64
4369 0f8a249a blueswir1
                case 0x0e: /* V9 stx */
4370 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4371 6ae20372 blueswir1
                    ABI32_MASK(cpu_addr);
4372 6ae20372 blueswir1
                    tcg_gen_qemu_st64(cpu_val, cpu_addr, dc->mem_idx);
4373 0f8a249a blueswir1
                    break;
4374 0f8a249a blueswir1
                case 0x1e: /* V9 stxa */
4375 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4376 6ae20372 blueswir1
                    gen_st_asi(cpu_val, cpu_addr, insn, 8);
4377 0f8a249a blueswir1
                    break;
4378 3475187d bellard
#endif
4379 0f8a249a blueswir1
                default:
4380 0f8a249a blueswir1
                    goto illegal_insn;
4381 0f8a249a blueswir1
                }
4382 0f8a249a blueswir1
            } else if (xop > 0x23 && xop < 0x28) {
4383 6ae20372 blueswir1
                if (gen_trap_ifnofpu(dc, cpu_cond))
4384 a80dde08 bellard
                    goto jmp_insn;
4385 0f8a249a blueswir1
                switch (xop) {
4386 ce8536e2 blueswir1
                case 0x24: /* store fpreg */
4387 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4388 ce8536e2 blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4389 ce8536e2 blueswir1
                                   offsetof(CPUState, fpr[rd]));
4390 6ae20372 blueswir1
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4391 0f8a249a blueswir1
                    break;
4392 0f8a249a blueswir1
                case 0x25: /* stfsr, V9 stxfsr */
4393 6ea4a6c8 blueswir1
#ifdef CONFIG_USER_ONLY
4394 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4395 6ea4a6c8 blueswir1
#endif
4396 bb5529bb blueswir1
                    tcg_gen_helper_0_0(helper_stfsr);
4397 ce8536e2 blueswir1
                    tcg_gen_ld_i32(cpu_tmp32, cpu_env,
4398 ce8536e2 blueswir1
                                   offsetof(CPUState, ft0));
4399 6ae20372 blueswir1
                    tcg_gen_qemu_st32(cpu_tmp32, cpu_addr, dc->mem_idx);
4400 0f8a249a blueswir1
                    break;
4401 1f587329 blueswir1
                case 0x26:
4402 1f587329 blueswir1
#ifdef TARGET_SPARC64
4403 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
4404 1f587329 blueswir1
                    /* V9 stqf, store quad fpreg */
4405 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4406 1f587329 blueswir1
                    gen_op_load_fpr_QT0(QFPREG(rd));
4407 1f587329 blueswir1
                    gen_op_ldst(stqf);
4408 1f587329 blueswir1
                    break;
4409 1f587329 blueswir1
#else
4410 1f587329 blueswir1
                    goto nfpu_insn;
4411 1f587329 blueswir1
#endif
4412 1f587329 blueswir1
#else /* !TARGET_SPARC64 */
4413 1f587329 blueswir1
                    /* stdfq, store floating point queue */
4414 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
4415 1f587329 blueswir1
                    goto illegal_insn;
4416 1f587329 blueswir1
#else
4417 0f8a249a blueswir1
                    if (!supervisor(dc))
4418 0f8a249a blueswir1
                        goto priv_insn;
4419 6ae20372 blueswir1
                    if (gen_trap_ifnofpu(dc, cpu_cond))
4420 0f8a249a blueswir1
                        goto jmp_insn;
4421 0f8a249a blueswir1
                    goto nfq_insn;
4422 0f8a249a blueswir1
#endif
4423 1f587329 blueswir1
#endif
4424 0f8a249a blueswir1
                case 0x27:
4425 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4426 3475187d bellard
                    gen_op_load_fpr_DT0(DFPREG(rd));
4427 0f8a249a blueswir1
                    gen_op_ldst(stdf);
4428 0f8a249a blueswir1
                    break;
4429 0f8a249a blueswir1
                default:
4430 0f8a249a blueswir1
                    goto illegal_insn;
4431 0f8a249a blueswir1
                }
4432 0f8a249a blueswir1
            } else if (xop > 0x33 && xop < 0x3f) {
4433 0f8a249a blueswir1
                switch (xop) {
4434 a4d17f19 blueswir1
#ifdef TARGET_SPARC64
4435 0f8a249a blueswir1
                case 0x34: /* V9 stfa */
4436 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4437 3391c818 blueswir1
                    gen_op_load_fpr_FT0(rd);
4438 6ae20372 blueswir1
                    gen_stf_asi(cpu_addr, insn, 4, rd);
4439 0f8a249a blueswir1
                    break;
4440 1f587329 blueswir1
                case 0x36: /* V9 stqfa */
4441 1f587329 blueswir1
#if defined(CONFIG_USER_ONLY)
4442 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4443 1f587329 blueswir1
                    gen_op_load_fpr_QT0(QFPREG(rd));
4444 6ae20372 blueswir1
                    gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd));
4445 1f587329 blueswir1
                    break;
4446 1f587329 blueswir1
#else
4447 1f587329 blueswir1
                    goto nfpu_insn;
4448 1f587329 blueswir1
#endif
4449 0f8a249a blueswir1
                case 0x37: /* V9 stdfa */
4450 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4451 3391c818 blueswir1
                    gen_op_load_fpr_DT0(DFPREG(rd));
4452 6ae20372 blueswir1
                    gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
4453 0f8a249a blueswir1
                    break;
4454 0f8a249a blueswir1
                case 0x3c: /* V9 casa */
4455 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(3));
4456 6ae20372 blueswir1
                    gen_cas_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4457 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_val);
4458 0f8a249a blueswir1
                    break;
4459 0f8a249a blueswir1
                case 0x3e: /* V9 casxa */
4460 6ae20372 blueswir1
                    tcg_gen_helper_0_2(helper_check_align, cpu_addr, tcg_const_i32(7));
4461 6ae20372 blueswir1
                    gen_casx_asi(cpu_val, cpu_addr, cpu_val, insn, rd);
4462 6ae20372 blueswir1
                    gen_movl_TN_reg(rd, cpu_val);
4463 0f8a249a blueswir1
                    break;
4464 a4d17f19 blueswir1
#else
4465 0f8a249a blueswir1
                case 0x34: /* stc */
4466 0f8a249a blueswir1
                case 0x35: /* stcsr */
4467 0f8a249a blueswir1
                case 0x36: /* stdcq */
4468 0f8a249a blueswir1
                case 0x37: /* stdc */
4469 0f8a249a blueswir1
                    goto ncp_insn;
4470 0f8a249a blueswir1
#endif
4471 0f8a249a blueswir1
                default:
4472 0f8a249a blueswir1
                    goto illegal_insn;
4473 0f8a249a blueswir1
                }
4474 e8af50a3 bellard
            }
4475 0f8a249a blueswir1
            else
4476 0f8a249a blueswir1
                goto illegal_insn;
4477 0f8a249a blueswir1
        }
4478 0f8a249a blueswir1
        break;
4479 cf495bcf bellard
    }
4480 cf495bcf bellard
    /* default case for non jump instructions */
4481 72cbca10 bellard
    if (dc->npc == DYNAMIC_PC) {
4482 0f8a249a blueswir1
        dc->pc = DYNAMIC_PC;
4483 0f8a249a blueswir1
        gen_op_next_insn();
4484 72cbca10 bellard
    } else if (dc->npc == JUMP_PC) {
4485 72cbca10 bellard
        /* we can do a static jump */
4486 6ae20372 blueswir1
        gen_branch2(dc, dc->jump_pc[0], dc->jump_pc[1], cpu_cond);
4487 72cbca10 bellard
        dc->is_br = 1;
4488 72cbca10 bellard
    } else {
4489 0f8a249a blueswir1
        dc->pc = dc->npc;
4490 0f8a249a blueswir1
        dc->npc = dc->npc + 4;
4491 cf495bcf bellard
    }
4492 e80cfcfc bellard
 jmp_insn:
4493 cf495bcf bellard
    return;
4494 cf495bcf bellard
 illegal_insn:
4495 6ae20372 blueswir1
    save_state(dc, cpu_cond);
4496 2f5680ee blueswir1
    tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_ILL_INSN));
4497 cf495bcf bellard
    dc->is_br = 1;
4498 e8af50a3 bellard
    return;
4499 e80cfcfc bellard
#if !defined(CONFIG_USER_ONLY)
4500 e8af50a3 bellard
 priv_insn:
4501 6ae20372 blueswir1
    save_state(dc, cpu_cond);
4502 2f5680ee blueswir1
    tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_PRIV_INSN));
4503 e8af50a3 bellard
    dc->is_br = 1;
4504 e80cfcfc bellard
    return;
4505 e80cfcfc bellard
 nfpu_insn:
4506 6ae20372 blueswir1
    save_state(dc, cpu_cond);
4507 e80cfcfc bellard
    gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
4508 e80cfcfc bellard
    dc->is_br = 1;
4509 fcc72045 blueswir1
    return;
4510 1f587329 blueswir1
#ifndef TARGET_SPARC64
4511 9143e598 blueswir1
 nfq_insn:
4512 6ae20372 blueswir1
    save_state(dc, cpu_cond);
4513 9143e598 blueswir1
    gen_op_fpexception_im(FSR_FTT_SEQ_ERROR);
4514 9143e598 blueswir1
    dc->is_br = 1;
4515 9143e598 blueswir1
    return;
4516 9143e598 blueswir1
#endif
4517 1f587329 blueswir1
#endif
4518 fcc72045 blueswir1
#ifndef TARGET_SPARC64
4519 fcc72045 blueswir1
 ncp_insn:
4520 6ae20372 blueswir1
    save_state(dc, cpu_cond);
4521 2f5680ee blueswir1
    tcg_gen_helper_0_1(raise_exception, tcg_const_i32(TT_NCP_INSN));
4522 fcc72045 blueswir1
    dc->is_br = 1;
4523 fcc72045 blueswir1
    return;
4524 fcc72045 blueswir1
#endif
4525 7a3f1944 bellard
}
4526 7a3f1944 bellard
4527 1a2fb1c0 blueswir1
static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
4528 1a2fb1c0 blueswir1
{
4529 1a2fb1c0 blueswir1
}
4530 1a2fb1c0 blueswir1
4531 cf495bcf bellard
static inline int gen_intermediate_code_internal(TranslationBlock * tb,
4532 0f8a249a blueswir1
                                                 int spc, CPUSPARCState *env)
4533 7a3f1944 bellard
{
4534 72cbca10 bellard
    target_ulong pc_start, last_pc;
4535 cf495bcf bellard
    uint16_t *gen_opc_end;
4536 cf495bcf bellard
    DisasContext dc1, *dc = &dc1;
4537 e8af50a3 bellard
    int j, lj = -1;
4538 cf495bcf bellard
4539 cf495bcf bellard
    memset(dc, 0, sizeof(DisasContext));
4540 cf495bcf bellard
    dc->tb = tb;
4541 72cbca10 bellard
    pc_start = tb->pc;
4542 cf495bcf bellard
    dc->pc = pc_start;
4543 e80cfcfc bellard
    last_pc = dc->pc;
4544 72cbca10 bellard
    dc->npc = (target_ulong) tb->cs_base;
4545 6f27aba6 blueswir1
    dc->mem_idx = cpu_mmu_index(env);
4546 6f27aba6 blueswir1
    dc->fpu_enabled = cpu_fpu_enabled(env);
4547 cf495bcf bellard
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4548 cf495bcf bellard
4549 1a2fb1c0 blueswir1
    cpu_tmp0 = tcg_temp_new(TCG_TYPE_TL);
4550 8911f501 blueswir1
    cpu_tmp32 = tcg_temp_new(TCG_TYPE_I32);
4551 8911f501 blueswir1
    cpu_tmp64 = tcg_temp_new(TCG_TYPE_I64);
4552 1a2fb1c0 blueswir1
4553 6ae20372 blueswir1
    cpu_cond = cpu_T[2];
4554 6ae20372 blueswir1
4555 cf495bcf bellard
    do {
4556 e8af50a3 bellard
        if (env->nb_breakpoints > 0) {
4557 e8af50a3 bellard
            for(j = 0; j < env->nb_breakpoints; j++) {
4558 e8af50a3 bellard
                if (env->breakpoints[j] == dc->pc) {
4559 0f8a249a blueswir1
                    if (dc->pc != pc_start)
4560 6ae20372 blueswir1
                        save_state(dc, cpu_cond);
4561 1a2fb1c0 blueswir1
                    tcg_gen_helper_0_0(helper_debug);
4562 57fec1fe bellard
                    tcg_gen_exit_tb(0);
4563 0f8a249a blueswir1
                    dc->is_br = 1;
4564 e80cfcfc bellard
                    goto exit_gen_loop;
4565 e8af50a3 bellard
                }
4566 e8af50a3 bellard
            }
4567 e8af50a3 bellard
        }
4568 e8af50a3 bellard
        if (spc) {
4569 e8af50a3 bellard
            if (loglevel > 0)
4570 e8af50a3 bellard
                fprintf(logfile, "Search PC...\n");
4571 e8af50a3 bellard
            j = gen_opc_ptr - gen_opc_buf;
4572 e8af50a3 bellard
            if (lj < j) {
4573 e8af50a3 bellard
                lj++;
4574 e8af50a3 bellard
                while (lj < j)
4575 e8af50a3 bellard
                    gen_opc_instr_start[lj++] = 0;
4576 e8af50a3 bellard
                gen_opc_pc[lj] = dc->pc;
4577 e8af50a3 bellard
                gen_opc_npc[lj] = dc->npc;
4578 e8af50a3 bellard
                gen_opc_instr_start[lj] = 1;
4579 e8af50a3 bellard
            }
4580 e8af50a3 bellard
        }
4581 0f8a249a blueswir1
        last_pc = dc->pc;
4582 0f8a249a blueswir1
        disas_sparc_insn(dc);
4583 0f8a249a blueswir1
4584 0f8a249a blueswir1
        if (dc->is_br)
4585 0f8a249a blueswir1
            break;
4586 0f8a249a blueswir1
        /* if the next PC is different, we abort now */
4587 0f8a249a blueswir1
        if (dc->pc != (last_pc + 4))
4588 0f8a249a blueswir1
            break;
4589 d39c0b99 bellard
        /* if we reach a page boundary, we stop generation so that the
4590 d39c0b99 bellard
           PC of a TT_TFAULT exception is always in the right page */
4591 d39c0b99 bellard
        if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
4592 d39c0b99 bellard
            break;
4593 e80cfcfc bellard
        /* if single step mode, we generate only one instruction and
4594 e80cfcfc bellard
           generate an exception */
4595 e80cfcfc bellard
        if (env->singlestep_enabled) {
4596 2f5680ee blueswir1
            tcg_gen_movi_tl(cpu_pc, dc->pc);
4597 57fec1fe bellard
            tcg_gen_exit_tb(0);
4598 e80cfcfc bellard
            break;
4599 e80cfcfc bellard
        }
4600 cf495bcf bellard
    } while ((gen_opc_ptr < gen_opc_end) &&
4601 0f8a249a blueswir1
             (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
4602 e80cfcfc bellard
4603 e80cfcfc bellard
 exit_gen_loop:
4604 72cbca10 bellard
    if (!dc->is_br) {
4605 5fafdf24 ths
        if (dc->pc != DYNAMIC_PC &&
4606 72cbca10 bellard
            (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
4607 72cbca10 bellard
            /* static PC and NPC: we can use direct chaining */
4608 2f5680ee blueswir1
            gen_goto_tb(dc, 0, dc->pc, dc->npc);
4609 72cbca10 bellard
        } else {
4610 72cbca10 bellard
            if (dc->pc != DYNAMIC_PC)
4611 2f5680ee blueswir1
                tcg_gen_movi_tl(cpu_pc, dc->pc);
4612 6ae20372 blueswir1
            save_npc(dc, cpu_cond);
4613 57fec1fe bellard
            tcg_gen_exit_tb(0);
4614 72cbca10 bellard
        }
4615 72cbca10 bellard
    }
4616 cf495bcf bellard
    *gen_opc_ptr = INDEX_op_end;
4617 e8af50a3 bellard
    if (spc) {
4618 e8af50a3 bellard
        j = gen_opc_ptr - gen_opc_buf;
4619 e8af50a3 bellard
        lj++;
4620 e8af50a3 bellard
        while (lj <= j)
4621 e8af50a3 bellard
            gen_opc_instr_start[lj++] = 0;
4622 e8af50a3 bellard
#if 0
4623 e8af50a3 bellard
        if (loglevel > 0) {
4624 e8af50a3 bellard
            page_dump(logfile);
4625 e8af50a3 bellard
        }
4626 e8af50a3 bellard
#endif
4627 c3278b7b bellard
        gen_opc_jump_pc[0] = dc->jump_pc[0];
4628 c3278b7b bellard
        gen_opc_jump_pc[1] = dc->jump_pc[1];
4629 e8af50a3 bellard
    } else {
4630 e80cfcfc bellard
        tb->size = last_pc + 4 - pc_start;
4631 e8af50a3 bellard
    }
4632 7a3f1944 bellard
#ifdef DEBUG_DISAS
4633 e19e89a5 bellard
    if (loglevel & CPU_LOG_TB_IN_ASM) {
4634 0f8a249a blueswir1
        fprintf(logfile, "--------------\n");
4635 0f8a249a blueswir1
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4636 0f8a249a blueswir1
        target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
4637 0f8a249a blueswir1
        fprintf(logfile, "\n");
4638 cf495bcf bellard
    }
4639 7a3f1944 bellard
#endif
4640 cf495bcf bellard
    return 0;
4641 7a3f1944 bellard
}
4642 7a3f1944 bellard
4643 cf495bcf bellard
int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
4644 7a3f1944 bellard
{
4645 e8af50a3 bellard
    return gen_intermediate_code_internal(tb, 0, env);
4646 7a3f1944 bellard
}
4647 7a3f1944 bellard
4648 cf495bcf bellard
int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
4649 7a3f1944 bellard
{
4650 e8af50a3 bellard
    return gen_intermediate_code_internal(tb, 1, env);
4651 7a3f1944 bellard
}
4652 7a3f1944 bellard
4653 c48fcb47 blueswir1
void gen_intermediate_code_init(CPUSPARCState *env)
4654 e80cfcfc bellard
{
4655 f5069b26 blueswir1
    unsigned int i;
4656 c48fcb47 blueswir1
    static int inited;
4657 f5069b26 blueswir1
    static const char * const gregnames[8] = {
4658 f5069b26 blueswir1
        NULL, // g0 not used
4659 f5069b26 blueswir1
        "g1",
4660 f5069b26 blueswir1
        "g2",
4661 f5069b26 blueswir1
        "g3",
4662 f5069b26 blueswir1
        "g4",
4663 f5069b26 blueswir1
        "g5",
4664 f5069b26 blueswir1
        "g6",
4665 f5069b26 blueswir1
        "g7",
4666 f5069b26 blueswir1
    };
4667 aaed909a bellard
4668 1a2fb1c0 blueswir1
    /* init various static tables */
4669 1a2fb1c0 blueswir1
    if (!inited) {
4670 1a2fb1c0 blueswir1
        inited = 1;
4671 1a2fb1c0 blueswir1
4672 1a2fb1c0 blueswir1
        tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
4673 1a2fb1c0 blueswir1
        cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
4674 db4a4ea4 blueswir1
        cpu_regwptr = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
4675 db4a4ea4 blueswir1
                                         offsetof(CPUState, regwptr),
4676 db4a4ea4 blueswir1
                                         "regwptr");
4677 1a2fb1c0 blueswir1
        //#if TARGET_LONG_BITS > HOST_LONG_BITS
4678 1a2fb1c0 blueswir1
#ifdef TARGET_SPARC64
4679 1a2fb1c0 blueswir1
        cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
4680 1a2fb1c0 blueswir1
                                      TCG_AREG0, offsetof(CPUState, t0), "T0");
4681 1a2fb1c0 blueswir1
        cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
4682 1a2fb1c0 blueswir1
                                      TCG_AREG0, offsetof(CPUState, t1), "T1");
4683 1a2fb1c0 blueswir1
        cpu_T[2] = tcg_global_mem_new(TCG_TYPE_TL,
4684 1a2fb1c0 blueswir1
                                      TCG_AREG0, offsetof(CPUState, t2), "T2");
4685 dc99a3f2 blueswir1
        cpu_xcc = tcg_global_mem_new(TCG_TYPE_I32,
4686 dc99a3f2 blueswir1
                                     TCG_AREG0, offsetof(CPUState, xcc),
4687 dc99a3f2 blueswir1
                                     "xcc");
4688 1a2fb1c0 blueswir1
#else
4689 1a2fb1c0 blueswir1
        cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
4690 1a2fb1c0 blueswir1
        cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
4691 1a2fb1c0 blueswir1
        cpu_T[2] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG3, "T2");
4692 1a2fb1c0 blueswir1
#endif
4693 dc99a3f2 blueswir1
        cpu_cc_src = tcg_global_mem_new(TCG_TYPE_TL,
4694 dc99a3f2 blueswir1
                                        TCG_AREG0, offsetof(CPUState, cc_src),
4695 dc99a3f2 blueswir1
                                        "cc_src");
4696 d9bdab86 blueswir1
        cpu_cc_src2 = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4697 d9bdab86 blueswir1
                                         offsetof(CPUState, cc_src2),
4698 d9bdab86 blueswir1
                                         "cc_src2");
4699 dc99a3f2 blueswir1
        cpu_cc_dst = tcg_global_mem_new(TCG_TYPE_TL,
4700 dc99a3f2 blueswir1
                                        TCG_AREG0, offsetof(CPUState, cc_dst),
4701 dc99a3f2 blueswir1
                                        "cc_dst");
4702 dc99a3f2 blueswir1
        cpu_psr = tcg_global_mem_new(TCG_TYPE_I32,
4703 dc99a3f2 blueswir1
                                     TCG_AREG0, offsetof(CPUState, psr),
4704 dc99a3f2 blueswir1
                                     "psr");
4705 87e92502 blueswir1
        cpu_fsr = tcg_global_mem_new(TCG_TYPE_TL,
4706 87e92502 blueswir1
                                     TCG_AREG0, offsetof(CPUState, fsr),
4707 87e92502 blueswir1
                                     "fsr");
4708 48d5c82b blueswir1
        cpu_pc = tcg_global_mem_new(TCG_TYPE_TL,
4709 48d5c82b blueswir1
                                    TCG_AREG0, offsetof(CPUState, pc),
4710 48d5c82b blueswir1
                                    "pc");
4711 48d5c82b blueswir1
        cpu_npc = tcg_global_mem_new(TCG_TYPE_TL,
4712 48d5c82b blueswir1
                                    TCG_AREG0, offsetof(CPUState, npc),
4713 48d5c82b blueswir1
                                    "npc");
4714 f5069b26 blueswir1
        for (i = 1; i < 8; i++)
4715 f5069b26 blueswir1
            cpu_gregs[i] = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
4716 f5069b26 blueswir1
                                              offsetof(CPUState, gregs[i]),
4717 f5069b26 blueswir1
                                              gregnames[i]);
4718 1a2fb1c0 blueswir1
    }
4719 658138bc bellard
}