Revision 9349b4f9 tcg/s390/tcg-target.c

b/tcg/s390/tcg-target.c
1439 1439
    tgen64_andi_tmp(s, arg1, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
1440 1440

  
1441 1441
    if (is_store) {
1442
        ofs = offsetof(CPUState, tlb_table[mem_index][0].addr_write);
1442
        ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_write);
1443 1443
    } else {
1444
        ofs = offsetof(CPUState, tlb_table[mem_index][0].addr_read);
1444
        ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addr_read);
1445 1445
    }
1446 1446
    assert(ofs < 0x80000);
1447 1447

  
......
1515 1515
    *(label1_ptr + 1) = ((unsigned long)s->code_ptr -
1516 1516
                         (unsigned long)label1_ptr) >> 1;
1517 1517

  
1518
    ofs = offsetof(CPUState, tlb_table[mem_index][0].addend);
1518
    ofs = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1519 1519
    assert(ofs < 0x80000);
1520 1520

  
1521 1521
    tcg_out_mem(s, 0, RXY_AG, arg0, arg1, TCG_AREG0, ofs);
......
2293 2293
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
2294 2294

  
2295 2295
    tcg_add_target_add_op_defs(s390_op_defs);
2296
    tcg_set_frame(s, TCG_AREG0, offsetof(CPUState, temp_buf),
2296
    tcg_set_frame(s, TCG_AREG0, offsetof(CPUArchState, temp_buf),
2297 2297
                  CPU_TEMP_BUF_NLONGS * sizeof(long));
2298 2298
}
2299 2299

  

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