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1 | e8af50a3 | bellard | /*
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2 | e8af50a3 | bellard | * sparc helpers
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3 | 5fafdf24 | ths | *
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4 | 83469015 | bellard | * Copyright (c) 2003-2005 Fabrice Bellard
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5 | e8af50a3 | bellard | *
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6 | e8af50a3 | bellard | * This library is free software; you can redistribute it and/or
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7 | e8af50a3 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | e8af50a3 | bellard | * License as published by the Free Software Foundation; either
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9 | e8af50a3 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | e8af50a3 | bellard | *
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11 | e8af50a3 | bellard | * This library is distributed in the hope that it will be useful,
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12 | e8af50a3 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | e8af50a3 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | e8af50a3 | bellard | * Lesser General Public License for more details.
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15 | e8af50a3 | bellard | *
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16 | e8af50a3 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | e8af50a3 | bellard | * License along with this library; if not, write to the Free Software
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18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
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19 | e8af50a3 | bellard | */
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20 | ee5bbe38 | bellard | #include <stdarg.h> |
21 | ee5bbe38 | bellard | #include <stdlib.h> |
22 | ee5bbe38 | bellard | #include <stdio.h> |
23 | ee5bbe38 | bellard | #include <string.h> |
24 | ee5bbe38 | bellard | #include <inttypes.h> |
25 | ee5bbe38 | bellard | #include <signal.h> |
26 | ee5bbe38 | bellard | #include <assert.h> |
27 | ee5bbe38 | bellard | |
28 | ee5bbe38 | bellard | #include "cpu.h" |
29 | ee5bbe38 | bellard | #include "exec-all.h" |
30 | ca10f867 | aurel32 | #include "qemu-common.h" |
31 | e8af50a3 | bellard | |
32 | e80cfcfc | bellard | //#define DEBUG_MMU
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33 | 64a88d5d | blueswir1 | //#define DEBUG_FEATURES
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34 | e8af50a3 | bellard | |
35 | 22548760 | blueswir1 | static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); |
36 | c48fcb47 | blueswir1 | |
37 | e8af50a3 | bellard | /* Sparc MMU emulation */
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38 | e8af50a3 | bellard | |
39 | e8af50a3 | bellard | /* thread support */
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40 | e8af50a3 | bellard | |
41 | 797d5db0 | blueswir1 | static spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
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42 | e8af50a3 | bellard | |
43 | e8af50a3 | bellard | void cpu_lock(void) |
44 | e8af50a3 | bellard | { |
45 | e8af50a3 | bellard | spin_lock(&global_cpu_lock); |
46 | e8af50a3 | bellard | } |
47 | e8af50a3 | bellard | |
48 | e8af50a3 | bellard | void cpu_unlock(void) |
49 | e8af50a3 | bellard | { |
50 | e8af50a3 | bellard | spin_unlock(&global_cpu_lock); |
51 | e8af50a3 | bellard | } |
52 | e8af50a3 | bellard | |
53 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
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54 | 9d893301 | bellard | |
55 | 22548760 | blueswir1 | int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw, |
56 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
57 | 9d893301 | bellard | { |
58 | 878d3096 | bellard | if (rw & 2) |
59 | 22548760 | blueswir1 | env1->exception_index = TT_TFAULT; |
60 | 878d3096 | bellard | else
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61 | 22548760 | blueswir1 | env1->exception_index = TT_DFAULT; |
62 | 9d893301 | bellard | return 1; |
63 | 9d893301 | bellard | } |
64 | 9d893301 | bellard | |
65 | 9d893301 | bellard | #else
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66 | e8af50a3 | bellard | |
67 | 3475187d | bellard | #ifndef TARGET_SPARC64
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68 | 83469015 | bellard | /*
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69 | 83469015 | bellard | * Sparc V8 Reference MMU (SRMMU)
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70 | 83469015 | bellard | */
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71 | e8af50a3 | bellard | static const int access_table[8][8] = { |
72 | a764a566 | blueswir1 | { 0, 0, 0, 0, 8, 0, 12, 12 }, |
73 | a764a566 | blueswir1 | { 0, 0, 0, 0, 8, 0, 0, 0 }, |
74 | a764a566 | blueswir1 | { 8, 8, 0, 0, 0, 8, 12, 12 }, |
75 | a764a566 | blueswir1 | { 8, 8, 0, 0, 0, 8, 0, 0 }, |
76 | a764a566 | blueswir1 | { 8, 0, 8, 0, 8, 8, 12, 12 }, |
77 | a764a566 | blueswir1 | { 8, 0, 8, 0, 8, 0, 8, 0 }, |
78 | a764a566 | blueswir1 | { 8, 8, 8, 0, 8, 8, 12, 12 }, |
79 | a764a566 | blueswir1 | { 8, 8, 8, 0, 8, 8, 8, 0 } |
80 | e8af50a3 | bellard | }; |
81 | e8af50a3 | bellard | |
82 | 227671c9 | bellard | static const int perm_table[2][8] = { |
83 | 227671c9 | bellard | { |
84 | 227671c9 | bellard | PAGE_READ, |
85 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
86 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
87 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
88 | 227671c9 | bellard | PAGE_EXEC, |
89 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
90 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
91 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC |
92 | 227671c9 | bellard | }, |
93 | 227671c9 | bellard | { |
94 | 227671c9 | bellard | PAGE_READ, |
95 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE, |
96 | 227671c9 | bellard | PAGE_READ | PAGE_EXEC, |
97 | 227671c9 | bellard | PAGE_READ | PAGE_WRITE | PAGE_EXEC, |
98 | 227671c9 | bellard | PAGE_EXEC, |
99 | 227671c9 | bellard | PAGE_READ, |
100 | 227671c9 | bellard | 0,
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101 | 227671c9 | bellard | 0,
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102 | 227671c9 | bellard | } |
103 | e8af50a3 | bellard | }; |
104 | e8af50a3 | bellard | |
105 | c48fcb47 | blueswir1 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
106 | c48fcb47 | blueswir1 | int *prot, int *access_index, |
107 | c48fcb47 | blueswir1 | target_ulong address, int rw, int mmu_idx) |
108 | e8af50a3 | bellard | { |
109 | e80cfcfc | bellard | int access_perms = 0; |
110 | e80cfcfc | bellard | target_phys_addr_t pde_ptr; |
111 | af7bf89b | bellard | uint32_t pde; |
112 | af7bf89b | bellard | target_ulong virt_addr; |
113 | 6ebbf390 | j_mayer | int error_code = 0, is_dirty, is_user; |
114 | e80cfcfc | bellard | unsigned long page_offset; |
115 | e8af50a3 | bellard | |
116 | 6ebbf390 | j_mayer | is_user = mmu_idx == MMU_USER_IDX; |
117 | e8af50a3 | bellard | virt_addr = address & TARGET_PAGE_MASK; |
118 | 40ce0a9a | blueswir1 | |
119 | e8af50a3 | bellard | if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
120 | 40ce0a9a | blueswir1 | // Boot mode: instruction fetches are taken from PROM
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121 | 5578ceab | blueswir1 | if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) { |
122 | 58a770f3 | blueswir1 | *physical = env->prom_addr | (address & 0x7ffffULL);
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123 | 40ce0a9a | blueswir1 | *prot = PAGE_READ | PAGE_EXEC; |
124 | 40ce0a9a | blueswir1 | return 0; |
125 | 40ce0a9a | blueswir1 | } |
126 | 0f8a249a | blueswir1 | *physical = address; |
127 | 227671c9 | bellard | *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
128 | e80cfcfc | bellard | return 0; |
129 | e8af50a3 | bellard | } |
130 | e8af50a3 | bellard | |
131 | 7483750d | bellard | *access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
132 | 5dcb6b91 | blueswir1 | *physical = 0xffffffffffff0000ULL;
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133 | 7483750d | bellard | |
134 | e8af50a3 | bellard | /* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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135 | e8af50a3 | bellard | /* Context base + context number */
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136 | 3deaeab7 | blueswir1 | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
137 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
138 | e8af50a3 | bellard | |
139 | e8af50a3 | bellard | /* Ctx pde */
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140 | e8af50a3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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141 | e80cfcfc | bellard | default:
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142 | e8af50a3 | bellard | case 0: /* Invalid */ |
143 | 0f8a249a | blueswir1 | return 1 << 2; |
144 | e80cfcfc | bellard | case 2: /* L0 PTE, maybe should not happen? */ |
145 | e8af50a3 | bellard | case 3: /* Reserved */ |
146 | 7483750d | bellard | return 4 << 2; |
147 | e80cfcfc | bellard | case 1: /* L0 PDE */ |
148 | 0f8a249a | blueswir1 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
149 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
150 | e8af50a3 | bellard | |
151 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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152 | 0f8a249a | blueswir1 | default:
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153 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
154 | 0f8a249a | blueswir1 | return (1 << 8) | (1 << 2); |
155 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
156 | 0f8a249a | blueswir1 | return (1 << 8) | (4 << 2); |
157 | 0f8a249a | blueswir1 | case 1: /* L1 PDE */ |
158 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
159 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
160 | e8af50a3 | bellard | |
161 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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162 | 0f8a249a | blueswir1 | default:
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163 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
164 | 0f8a249a | blueswir1 | return (2 << 8) | (1 << 2); |
165 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
166 | 0f8a249a | blueswir1 | return (2 << 8) | (4 << 2); |
167 | 0f8a249a | blueswir1 | case 1: /* L2 PDE */ |
168 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
169 | 49be8030 | bellard | pde = ldl_phys(pde_ptr); |
170 | e8af50a3 | bellard | |
171 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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172 | 0f8a249a | blueswir1 | default:
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173 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
174 | 0f8a249a | blueswir1 | return (3 << 8) | (1 << 2); |
175 | 0f8a249a | blueswir1 | case 1: /* PDE, should not happen */ |
176 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
177 | 0f8a249a | blueswir1 | return (3 << 8) | (4 << 2); |
178 | 0f8a249a | blueswir1 | case 2: /* L3 PTE */ |
179 | 0f8a249a | blueswir1 | virt_addr = address & TARGET_PAGE_MASK; |
180 | 77f193da | blueswir1 | page_offset = (address & TARGET_PAGE_MASK) & |
181 | 77f193da | blueswir1 | (TARGET_PAGE_SIZE - 1);
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182 | 0f8a249a | blueswir1 | } |
183 | 0f8a249a | blueswir1 | break;
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184 | 0f8a249a | blueswir1 | case 2: /* L2 PTE */ |
185 | 0f8a249a | blueswir1 | virt_addr = address & ~0x3ffff;
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186 | 0f8a249a | blueswir1 | page_offset = address & 0x3ffff;
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187 | 0f8a249a | blueswir1 | } |
188 | 0f8a249a | blueswir1 | break;
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189 | 0f8a249a | blueswir1 | case 2: /* L1 PTE */ |
190 | 0f8a249a | blueswir1 | virt_addr = address & ~0xffffff;
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191 | 0f8a249a | blueswir1 | page_offset = address & 0xffffff;
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192 | 0f8a249a | blueswir1 | } |
193 | e8af50a3 | bellard | } |
194 | e8af50a3 | bellard | |
195 | e8af50a3 | bellard | /* update page modified and dirty bits */
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196 | b769d8fe | bellard | is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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197 | e8af50a3 | bellard | if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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198 | 0f8a249a | blueswir1 | pde |= PG_ACCESSED_MASK; |
199 | 0f8a249a | blueswir1 | if (is_dirty)
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200 | 0f8a249a | blueswir1 | pde |= PG_MODIFIED_MASK; |
201 | 49be8030 | bellard | stl_phys_notdirty(pde_ptr, pde); |
202 | e8af50a3 | bellard | } |
203 | e8af50a3 | bellard | /* check access */
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204 | e8af50a3 | bellard | access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
205 | e80cfcfc | bellard | error_code = access_table[*access_index][access_perms]; |
206 | d8e3326c | bellard | if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) |
207 | 0f8a249a | blueswir1 | return error_code;
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208 | e8af50a3 | bellard | |
209 | e8af50a3 | bellard | /* the page can be put in the TLB */
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210 | 227671c9 | bellard | *prot = perm_table[is_user][access_perms]; |
211 | 227671c9 | bellard | if (!(pde & PG_MODIFIED_MASK)) {
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212 | e8af50a3 | bellard | /* only set write access if already dirty... otherwise wait
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213 | e8af50a3 | bellard | for dirty access */
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214 | 227671c9 | bellard | *prot &= ~PAGE_WRITE; |
215 | e8af50a3 | bellard | } |
216 | e8af50a3 | bellard | |
217 | e8af50a3 | bellard | /* Even if large ptes, we map only one 4KB page in the cache to
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218 | e8af50a3 | bellard | avoid filling it too fast */
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219 | 5dcb6b91 | blueswir1 | *physical = ((target_phys_addr_t)(pde & PTE_ADDR_MASK) << 4) + page_offset;
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220 | 6f7e9aec | bellard | return error_code;
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221 | e80cfcfc | bellard | } |
222 | e80cfcfc | bellard | |
223 | e80cfcfc | bellard | /* Perform address translation */
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224 | af7bf89b | bellard | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
225 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
226 | e80cfcfc | bellard | { |
227 | af7bf89b | bellard | target_phys_addr_t paddr; |
228 | 5dcb6b91 | blueswir1 | target_ulong vaddr; |
229 | e80cfcfc | bellard | int error_code = 0, prot, ret = 0, access_index; |
230 | e8af50a3 | bellard | |
231 | 77f193da | blueswir1 | error_code = get_physical_address(env, &paddr, &prot, &access_index, |
232 | 77f193da | blueswir1 | address, rw, mmu_idx); |
233 | e80cfcfc | bellard | if (error_code == 0) { |
234 | 0f8a249a | blueswir1 | vaddr = address & TARGET_PAGE_MASK; |
235 | 0f8a249a | blueswir1 | paddr &= TARGET_PAGE_MASK; |
236 | 9e61bde5 | bellard | #ifdef DEBUG_MMU
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237 | 0f8a249a | blueswir1 | printf("Translate at " TARGET_FMT_lx " -> " TARGET_FMT_plx ", vaddr " |
238 | 5dcb6b91 | blueswir1 | TARGET_FMT_lx "\n", address, paddr, vaddr);
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239 | 9e61bde5 | bellard | #endif
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240 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
241 | 0f8a249a | blueswir1 | return ret;
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242 | e80cfcfc | bellard | } |
243 | e8af50a3 | bellard | |
244 | e8af50a3 | bellard | if (env->mmuregs[3]) /* Fault status register */ |
245 | 0f8a249a | blueswir1 | env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
246 | 7483750d | bellard | env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
247 | e8af50a3 | bellard | env->mmuregs[4] = address; /* Fault address register */ |
248 | e8af50a3 | bellard | |
249 | 878d3096 | bellard | if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
250 | 6f7e9aec | bellard | // No fault mode: if a mapping is available, just override
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251 | 6f7e9aec | bellard | // permissions. If no mapping is available, redirect accesses to
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252 | 6f7e9aec | bellard | // neverland. Fake/overridden mappings will be flushed when
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253 | 6f7e9aec | bellard | // switching to normal mode.
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254 | 0f8a249a | blueswir1 | vaddr = address & TARGET_PAGE_MASK; |
255 | 227671c9 | bellard | prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; |
256 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
257 | 0f8a249a | blueswir1 | return ret;
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258 | 7483750d | bellard | } else {
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259 | 7483750d | bellard | if (rw & 2) |
260 | 7483750d | bellard | env->exception_index = TT_TFAULT; |
261 | 7483750d | bellard | else
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262 | 7483750d | bellard | env->exception_index = TT_DFAULT; |
263 | 7483750d | bellard | return 1; |
264 | 878d3096 | bellard | } |
265 | e8af50a3 | bellard | } |
266 | 24741ef3 | bellard | |
267 | 24741ef3 | bellard | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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268 | 24741ef3 | bellard | { |
269 | 24741ef3 | bellard | target_phys_addr_t pde_ptr; |
270 | 24741ef3 | bellard | uint32_t pde; |
271 | 24741ef3 | bellard | |
272 | 24741ef3 | bellard | /* Context base + context number */
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273 | 5dcb6b91 | blueswir1 | pde_ptr = (target_phys_addr_t)(env->mmuregs[1] << 4) + |
274 | 5dcb6b91 | blueswir1 | (env->mmuregs[2] << 2); |
275 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
276 | 24741ef3 | bellard | |
277 | 24741ef3 | bellard | switch (pde & PTE_ENTRYTYPE_MASK) {
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278 | 24741ef3 | bellard | default:
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279 | 24741ef3 | bellard | case 0: /* Invalid */ |
280 | 24741ef3 | bellard | case 2: /* PTE, maybe should not happen? */ |
281 | 24741ef3 | bellard | case 3: /* Reserved */ |
282 | 0f8a249a | blueswir1 | return 0; |
283 | 24741ef3 | bellard | case 1: /* L1 PDE */ |
284 | 0f8a249a | blueswir1 | if (mmulev == 3) |
285 | 0f8a249a | blueswir1 | return pde;
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286 | 0f8a249a | blueswir1 | pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
287 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
288 | 24741ef3 | bellard | |
289 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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290 | 0f8a249a | blueswir1 | default:
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291 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
292 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
293 | 0f8a249a | blueswir1 | return 0; |
294 | 0f8a249a | blueswir1 | case 2: /* L1 PTE */ |
295 | 0f8a249a | blueswir1 | return pde;
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296 | 0f8a249a | blueswir1 | case 1: /* L2 PDE */ |
297 | 0f8a249a | blueswir1 | if (mmulev == 2) |
298 | 0f8a249a | blueswir1 | return pde;
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299 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
300 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
301 | 24741ef3 | bellard | |
302 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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303 | 0f8a249a | blueswir1 | default:
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304 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
305 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
306 | 0f8a249a | blueswir1 | return 0; |
307 | 0f8a249a | blueswir1 | case 2: /* L2 PTE */ |
308 | 0f8a249a | blueswir1 | return pde;
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309 | 0f8a249a | blueswir1 | case 1: /* L3 PDE */ |
310 | 0f8a249a | blueswir1 | if (mmulev == 1) |
311 | 0f8a249a | blueswir1 | return pde;
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312 | 0f8a249a | blueswir1 | pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
313 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
314 | 24741ef3 | bellard | |
315 | 0f8a249a | blueswir1 | switch (pde & PTE_ENTRYTYPE_MASK) {
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316 | 0f8a249a | blueswir1 | default:
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317 | 0f8a249a | blueswir1 | case 0: /* Invalid */ |
318 | 0f8a249a | blueswir1 | case 1: /* PDE, should not happen */ |
319 | 0f8a249a | blueswir1 | case 3: /* Reserved */ |
320 | 0f8a249a | blueswir1 | return 0; |
321 | 0f8a249a | blueswir1 | case 2: /* L3 PTE */ |
322 | 0f8a249a | blueswir1 | return pde;
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323 | 0f8a249a | blueswir1 | } |
324 | 0f8a249a | blueswir1 | } |
325 | 0f8a249a | blueswir1 | } |
326 | 24741ef3 | bellard | } |
327 | 24741ef3 | bellard | return 0; |
328 | 24741ef3 | bellard | } |
329 | 24741ef3 | bellard | |
330 | 24741ef3 | bellard | #ifdef DEBUG_MMU
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331 | 24741ef3 | bellard | void dump_mmu(CPUState *env)
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332 | 24741ef3 | bellard | { |
333 | 5dcb6b91 | blueswir1 | target_ulong va, va1, va2; |
334 | 5dcb6b91 | blueswir1 | unsigned int n, m, o; |
335 | 5dcb6b91 | blueswir1 | target_phys_addr_t pde_ptr, pa; |
336 | 24741ef3 | bellard | uint32_t pde; |
337 | 24741ef3 | bellard | |
338 | 24741ef3 | bellard | printf("MMU dump:\n");
|
339 | 24741ef3 | bellard | pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
340 | 24741ef3 | bellard | pde = ldl_phys(pde_ptr); |
341 | 5dcb6b91 | blueswir1 | printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", |
342 | 5dcb6b91 | blueswir1 | (target_phys_addr_t)env->mmuregs[1] << 4, env->mmuregs[2]); |
343 | 24741ef3 | bellard | for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
344 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va, 2);
|
345 | 0f8a249a | blueswir1 | if (pde) {
|
346 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va); |
347 | 0f8a249a | blueswir1 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
348 | 5dcb6b91 | blueswir1 | " PDE: " TARGET_FMT_lx "\n", va, pa, pde); |
349 | 0f8a249a | blueswir1 | for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
350 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va1, 1);
|
351 | 0f8a249a | blueswir1 | if (pde) {
|
352 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va1); |
353 | 0f8a249a | blueswir1 | printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_plx |
354 | 5dcb6b91 | blueswir1 | " PDE: " TARGET_FMT_lx "\n", va1, pa, pde); |
355 | 0f8a249a | blueswir1 | for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
356 | 0f8a249a | blueswir1 | pde = mmu_probe(env, va2, 0);
|
357 | 0f8a249a | blueswir1 | if (pde) {
|
358 | 0f8a249a | blueswir1 | pa = cpu_get_phys_page_debug(env, va2); |
359 | 0f8a249a | blueswir1 | printf(" VA: " TARGET_FMT_lx ", PA: " |
360 | 5dcb6b91 | blueswir1 | TARGET_FMT_plx " PTE: " TARGET_FMT_lx "\n", |
361 | 5dcb6b91 | blueswir1 | va2, pa, pde); |
362 | 0f8a249a | blueswir1 | } |
363 | 0f8a249a | blueswir1 | } |
364 | 0f8a249a | blueswir1 | } |
365 | 0f8a249a | blueswir1 | } |
366 | 0f8a249a | blueswir1 | } |
367 | 24741ef3 | bellard | } |
368 | 24741ef3 | bellard | printf("MMU dump ends\n");
|
369 | 24741ef3 | bellard | } |
370 | 24741ef3 | bellard | #endif /* DEBUG_MMU */ |
371 | 24741ef3 | bellard | |
372 | 24741ef3 | bellard | #else /* !TARGET_SPARC64 */ |
373 | 83469015 | bellard | /*
|
374 | 83469015 | bellard | * UltraSparc IIi I/DMMUs
|
375 | 83469015 | bellard | */
|
376 | 77f193da | blueswir1 | static int get_physical_address_data(CPUState *env, |
377 | 77f193da | blueswir1 | target_phys_addr_t *physical, int *prot,
|
378 | 22548760 | blueswir1 | target_ulong address, int rw, int is_user) |
379 | 3475187d | bellard | { |
380 | 3475187d | bellard | target_ulong mask; |
381 | 3475187d | bellard | unsigned int i; |
382 | 3475187d | bellard | |
383 | 3475187d | bellard | if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
384 | 0f8a249a | blueswir1 | *physical = address; |
385 | 0f8a249a | blueswir1 | *prot = PAGE_READ | PAGE_WRITE; |
386 | 3475187d | bellard | return 0; |
387 | 3475187d | bellard | } |
388 | 3475187d | bellard | |
389 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
390 | 0f8a249a | blueswir1 | switch ((env->dtlb_tte[i] >> 61) & 3) { |
391 | 0f8a249a | blueswir1 | default:
|
392 | 0f8a249a | blueswir1 | case 0x0: // 8k |
393 | 0f8a249a | blueswir1 | mask = 0xffffffffffffe000ULL;
|
394 | 0f8a249a | blueswir1 | break;
|
395 | 0f8a249a | blueswir1 | case 0x1: // 64k |
396 | 0f8a249a | blueswir1 | mask = 0xffffffffffff0000ULL;
|
397 | 0f8a249a | blueswir1 | break;
|
398 | 0f8a249a | blueswir1 | case 0x2: // 512k |
399 | 0f8a249a | blueswir1 | mask = 0xfffffffffff80000ULL;
|
400 | 0f8a249a | blueswir1 | break;
|
401 | 0f8a249a | blueswir1 | case 0x3: // 4M |
402 | 0f8a249a | blueswir1 | mask = 0xffffffffffc00000ULL;
|
403 | 0f8a249a | blueswir1 | break;
|
404 | 0f8a249a | blueswir1 | } |
405 | afdf8109 | blueswir1 | // ctx match, vaddr match, valid?
|
406 | 0f8a249a | blueswir1 | if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
407 | afdf8109 | blueswir1 | (address & mask) == (env->dtlb_tag[i] & ~0x1fffULL) &&
|
408 | afdf8109 | blueswir1 | (env->dtlb_tte[i] & 0x8000000000000000ULL)) {
|
409 | afdf8109 | blueswir1 | // access ok?
|
410 | afdf8109 | blueswir1 | if (((env->dtlb_tte[i] & 0x4) && is_user) || |
411 | 0f8a249a | blueswir1 | (!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { |
412 | 0f8a249a | blueswir1 | if (env->dmmuregs[3]) /* Fault status register */ |
413 | 77f193da | blueswir1 | env->dmmuregs[3] = 2; /* overflow (not read before |
414 | 77f193da | blueswir1 | another fault) */
|
415 | 0f8a249a | blueswir1 | env->dmmuregs[3] |= (is_user << 3) | ((rw == 1) << 2) | 1; |
416 | 0f8a249a | blueswir1 | env->dmmuregs[4] = address; /* Fault address register */ |
417 | 0f8a249a | blueswir1 | env->exception_index = TT_DFAULT; |
418 | 83469015 | bellard | #ifdef DEBUG_MMU
|
419 | 0f8a249a | blueswir1 | printf("DFAULT at 0x%" PRIx64 "\n", address); |
420 | 83469015 | bellard | #endif
|
421 | 0f8a249a | blueswir1 | return 1; |
422 | 0f8a249a | blueswir1 | } |
423 | 77f193da | blueswir1 | *physical = (env->dtlb_tte[i] & mask & 0x1fffffff000ULL) +
|
424 | 77f193da | blueswir1 | (address & ~mask & 0x1fffffff000ULL);
|
425 | 0f8a249a | blueswir1 | *prot = PAGE_READ; |
426 | 0f8a249a | blueswir1 | if (env->dtlb_tte[i] & 0x2) |
427 | 0f8a249a | blueswir1 | *prot |= PAGE_WRITE; |
428 | 0f8a249a | blueswir1 | return 0; |
429 | 0f8a249a | blueswir1 | } |
430 | 3475187d | bellard | } |
431 | 83469015 | bellard | #ifdef DEBUG_MMU
|
432 | 26a76461 | bellard | printf("DMISS at 0x%" PRIx64 "\n", address); |
433 | 83469015 | bellard | #endif
|
434 | f617a9a6 | blueswir1 | env->dmmuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff); |
435 | 83469015 | bellard | env->exception_index = TT_DMISS; |
436 | 3475187d | bellard | return 1; |
437 | 3475187d | bellard | } |
438 | 3475187d | bellard | |
439 | 77f193da | blueswir1 | static int get_physical_address_code(CPUState *env, |
440 | 77f193da | blueswir1 | target_phys_addr_t *physical, int *prot,
|
441 | 22548760 | blueswir1 | target_ulong address, int is_user)
|
442 | 3475187d | bellard | { |
443 | 3475187d | bellard | target_ulong mask; |
444 | 3475187d | bellard | unsigned int i; |
445 | 3475187d | bellard | |
446 | 3475187d | bellard | if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ |
447 | 0f8a249a | blueswir1 | *physical = address; |
448 | 0f8a249a | blueswir1 | *prot = PAGE_EXEC; |
449 | 3475187d | bellard | return 0; |
450 | 3475187d | bellard | } |
451 | 83469015 | bellard | |
452 | 3475187d | bellard | for (i = 0; i < 64; i++) { |
453 | 0f8a249a | blueswir1 | switch ((env->itlb_tte[i] >> 61) & 3) { |
454 | 0f8a249a | blueswir1 | default:
|
455 | 0f8a249a | blueswir1 | case 0x0: // 8k |
456 | 0f8a249a | blueswir1 | mask = 0xffffffffffffe000ULL;
|
457 | 0f8a249a | blueswir1 | break;
|
458 | 0f8a249a | blueswir1 | case 0x1: // 64k |
459 | 0f8a249a | blueswir1 | mask = 0xffffffffffff0000ULL;
|
460 | 0f8a249a | blueswir1 | break;
|
461 | 0f8a249a | blueswir1 | case 0x2: // 512k |
462 | 0f8a249a | blueswir1 | mask = 0xfffffffffff80000ULL;
|
463 | 0f8a249a | blueswir1 | break;
|
464 | 0f8a249a | blueswir1 | case 0x3: // 4M |
465 | 0f8a249a | blueswir1 | mask = 0xffffffffffc00000ULL;
|
466 | 0f8a249a | blueswir1 | break;
|
467 | 0f8a249a | blueswir1 | } |
468 | afdf8109 | blueswir1 | // ctx match, vaddr match, valid?
|
469 | 0f8a249a | blueswir1 | if (env->dmmuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
470 | afdf8109 | blueswir1 | (address & mask) == (env->itlb_tag[i] & ~0x1fffULL) &&
|
471 | afdf8109 | blueswir1 | (env->itlb_tte[i] & 0x8000000000000000ULL)) {
|
472 | afdf8109 | blueswir1 | // access ok?
|
473 | afdf8109 | blueswir1 | if ((env->itlb_tte[i] & 0x4) && is_user) { |
474 | 0f8a249a | blueswir1 | if (env->immuregs[3]) /* Fault status register */ |
475 | 77f193da | blueswir1 | env->immuregs[3] = 2; /* overflow (not read before |
476 | 77f193da | blueswir1 | another fault) */
|
477 | 0f8a249a | blueswir1 | env->immuregs[3] |= (is_user << 3) | 1; |
478 | 0f8a249a | blueswir1 | env->exception_index = TT_TFAULT; |
479 | 83469015 | bellard | #ifdef DEBUG_MMU
|
480 | 0f8a249a | blueswir1 | printf("TFAULT at 0x%" PRIx64 "\n", address); |
481 | 83469015 | bellard | #endif
|
482 | 0f8a249a | blueswir1 | return 1; |
483 | 0f8a249a | blueswir1 | } |
484 | 77f193da | blueswir1 | *physical = (env->itlb_tte[i] & mask & 0x1fffffff000ULL) +
|
485 | 77f193da | blueswir1 | (address & ~mask & 0x1fffffff000ULL);
|
486 | 0f8a249a | blueswir1 | *prot = PAGE_EXEC; |
487 | 0f8a249a | blueswir1 | return 0; |
488 | 0f8a249a | blueswir1 | } |
489 | 3475187d | bellard | } |
490 | 83469015 | bellard | #ifdef DEBUG_MMU
|
491 | 26a76461 | bellard | printf("TMISS at 0x%" PRIx64 "\n", address); |
492 | 83469015 | bellard | #endif
|
493 | f617a9a6 | blueswir1 | env->immuregs[6] = (address & ~0x1fffULL) | (env->dmmuregs[1] & 0x1fff); |
494 | 83469015 | bellard | env->exception_index = TT_TMISS; |
495 | 3475187d | bellard | return 1; |
496 | 3475187d | bellard | } |
497 | 3475187d | bellard | |
498 | c48fcb47 | blueswir1 | static int get_physical_address(CPUState *env, target_phys_addr_t *physical, |
499 | c48fcb47 | blueswir1 | int *prot, int *access_index, |
500 | c48fcb47 | blueswir1 | target_ulong address, int rw, int mmu_idx) |
501 | 3475187d | bellard | { |
502 | 6ebbf390 | j_mayer | int is_user = mmu_idx == MMU_USER_IDX;
|
503 | 6ebbf390 | j_mayer | |
504 | 3475187d | bellard | if (rw == 2) |
505 | 22548760 | blueswir1 | return get_physical_address_code(env, physical, prot, address,
|
506 | 22548760 | blueswir1 | is_user); |
507 | 3475187d | bellard | else
|
508 | 22548760 | blueswir1 | return get_physical_address_data(env, physical, prot, address, rw,
|
509 | 22548760 | blueswir1 | is_user); |
510 | 3475187d | bellard | } |
511 | 3475187d | bellard | |
512 | 3475187d | bellard | /* Perform address translation */
|
513 | 3475187d | bellard | int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
514 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu) |
515 | 3475187d | bellard | { |
516 | 83469015 | bellard | target_ulong virt_addr, vaddr; |
517 | 3475187d | bellard | target_phys_addr_t paddr; |
518 | 3475187d | bellard | int error_code = 0, prot, ret = 0, access_index; |
519 | 3475187d | bellard | |
520 | 77f193da | blueswir1 | error_code = get_physical_address(env, &paddr, &prot, &access_index, |
521 | 77f193da | blueswir1 | address, rw, mmu_idx); |
522 | 3475187d | bellard | if (error_code == 0) { |
523 | 0f8a249a | blueswir1 | virt_addr = address & TARGET_PAGE_MASK; |
524 | 77f193da | blueswir1 | vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & |
525 | 77f193da | blueswir1 | (TARGET_PAGE_SIZE - 1));
|
526 | 83469015 | bellard | #ifdef DEBUG_MMU
|
527 | 77f193da | blueswir1 | printf("Translate at 0x%" PRIx64 " -> 0x%" PRIx64 ", vaddr 0x%" PRIx64 |
528 | 77f193da | blueswir1 | "\n", address, paddr, vaddr);
|
529 | 83469015 | bellard | #endif
|
530 | 6ebbf390 | j_mayer | ret = tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu); |
531 | 0f8a249a | blueswir1 | return ret;
|
532 | 3475187d | bellard | } |
533 | 3475187d | bellard | // XXX
|
534 | 3475187d | bellard | return 1; |
535 | 3475187d | bellard | } |
536 | 3475187d | bellard | |
537 | 83469015 | bellard | #ifdef DEBUG_MMU
|
538 | 83469015 | bellard | void dump_mmu(CPUState *env)
|
539 | 83469015 | bellard | { |
540 | 83469015 | bellard | unsigned int i; |
541 | 83469015 | bellard | const char *mask; |
542 | 83469015 | bellard | |
543 | 77f193da | blueswir1 | printf("MMU contexts: Primary: %" PRId64 ", Secondary: %" PRId64 "\n", |
544 | 77f193da | blueswir1 | env->dmmuregs[1], env->dmmuregs[2]); |
545 | 83469015 | bellard | if ((env->lsu & DMMU_E) == 0) { |
546 | 0f8a249a | blueswir1 | printf("DMMU disabled\n");
|
547 | 83469015 | bellard | } else {
|
548 | 0f8a249a | blueswir1 | printf("DMMU dump:\n");
|
549 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
550 | 0f8a249a | blueswir1 | switch ((env->dtlb_tte[i] >> 61) & 3) { |
551 | 0f8a249a | blueswir1 | default:
|
552 | 0f8a249a | blueswir1 | case 0x0: |
553 | 0f8a249a | blueswir1 | mask = " 8k";
|
554 | 0f8a249a | blueswir1 | break;
|
555 | 0f8a249a | blueswir1 | case 0x1: |
556 | 0f8a249a | blueswir1 | mask = " 64k";
|
557 | 0f8a249a | blueswir1 | break;
|
558 | 0f8a249a | blueswir1 | case 0x2: |
559 | 0f8a249a | blueswir1 | mask = "512k";
|
560 | 0f8a249a | blueswir1 | break;
|
561 | 0f8a249a | blueswir1 | case 0x3: |
562 | 0f8a249a | blueswir1 | mask = " 4M";
|
563 | 0f8a249a | blueswir1 | break;
|
564 | 0f8a249a | blueswir1 | } |
565 | 0f8a249a | blueswir1 | if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { |
566 | 77f193da | blueswir1 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx |
567 | 77f193da | blueswir1 | ", %s, %s, %s, %s, ctx %" PRId64 "\n", |
568 | 0f8a249a | blueswir1 | env->dtlb_tag[i] & ~0x1fffULL,
|
569 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x1ffffffe000ULL,
|
570 | 0f8a249a | blueswir1 | mask, |
571 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x4? "priv": "user", |
572 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x2? "RW": "RO", |
573 | 0f8a249a | blueswir1 | env->dtlb_tte[i] & 0x40? "locked": "unlocked", |
574 | 0f8a249a | blueswir1 | env->dtlb_tag[i] & 0x1fffULL);
|
575 | 0f8a249a | blueswir1 | } |
576 | 0f8a249a | blueswir1 | } |
577 | 83469015 | bellard | } |
578 | 83469015 | bellard | if ((env->lsu & IMMU_E) == 0) { |
579 | 0f8a249a | blueswir1 | printf("IMMU disabled\n");
|
580 | 83469015 | bellard | } else {
|
581 | 0f8a249a | blueswir1 | printf("IMMU dump:\n");
|
582 | 0f8a249a | blueswir1 | for (i = 0; i < 64; i++) { |
583 | 0f8a249a | blueswir1 | switch ((env->itlb_tte[i] >> 61) & 3) { |
584 | 0f8a249a | blueswir1 | default:
|
585 | 0f8a249a | blueswir1 | case 0x0: |
586 | 0f8a249a | blueswir1 | mask = " 8k";
|
587 | 0f8a249a | blueswir1 | break;
|
588 | 0f8a249a | blueswir1 | case 0x1: |
589 | 0f8a249a | blueswir1 | mask = " 64k";
|
590 | 0f8a249a | blueswir1 | break;
|
591 | 0f8a249a | blueswir1 | case 0x2: |
592 | 0f8a249a | blueswir1 | mask = "512k";
|
593 | 0f8a249a | blueswir1 | break;
|
594 | 0f8a249a | blueswir1 | case 0x3: |
595 | 0f8a249a | blueswir1 | mask = " 4M";
|
596 | 0f8a249a | blueswir1 | break;
|
597 | 0f8a249a | blueswir1 | } |
598 | 0f8a249a | blueswir1 | if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { |
599 | 77f193da | blueswir1 | printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx |
600 | 77f193da | blueswir1 | ", %s, %s, %s, ctx %" PRId64 "\n", |
601 | 0f8a249a | blueswir1 | env->itlb_tag[i] & ~0x1fffULL,
|
602 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x1ffffffe000ULL,
|
603 | 0f8a249a | blueswir1 | mask, |
604 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x4? "priv": "user", |
605 | 0f8a249a | blueswir1 | env->itlb_tte[i] & 0x40? "locked": "unlocked", |
606 | 0f8a249a | blueswir1 | env->itlb_tag[i] & 0x1fffULL);
|
607 | 0f8a249a | blueswir1 | } |
608 | 0f8a249a | blueswir1 | } |
609 | 83469015 | bellard | } |
610 | 83469015 | bellard | } |
611 | 24741ef3 | bellard | #endif /* DEBUG_MMU */ |
612 | 24741ef3 | bellard | |
613 | 24741ef3 | bellard | #endif /* TARGET_SPARC64 */ |
614 | 24741ef3 | bellard | #endif /* !CONFIG_USER_ONLY */ |
615 | 24741ef3 | bellard | |
616 | c48fcb47 | blueswir1 | |
617 | c48fcb47 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
618 | c48fcb47 | blueswir1 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
619 | c48fcb47 | blueswir1 | { |
620 | c48fcb47 | blueswir1 | return addr;
|
621 | c48fcb47 | blueswir1 | } |
622 | c48fcb47 | blueswir1 | |
623 | c48fcb47 | blueswir1 | #else
|
624 | c48fcb47 | blueswir1 | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr) |
625 | c48fcb47 | blueswir1 | { |
626 | c48fcb47 | blueswir1 | target_phys_addr_t phys_addr; |
627 | c48fcb47 | blueswir1 | int prot, access_index;
|
628 | c48fcb47 | blueswir1 | |
629 | c48fcb47 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, |
630 | c48fcb47 | blueswir1 | MMU_KERNEL_IDX) != 0)
|
631 | c48fcb47 | blueswir1 | if (get_physical_address(env, &phys_addr, &prot, &access_index, addr,
|
632 | c48fcb47 | blueswir1 | 0, MMU_KERNEL_IDX) != 0) |
633 | c48fcb47 | blueswir1 | return -1; |
634 | c48fcb47 | blueswir1 | if (cpu_get_physical_page_desc(phys_addr) == IO_MEM_UNASSIGNED)
|
635 | c48fcb47 | blueswir1 | return -1; |
636 | c48fcb47 | blueswir1 | return phys_addr;
|
637 | c48fcb47 | blueswir1 | } |
638 | c48fcb47 | blueswir1 | #endif
|
639 | c48fcb47 | blueswir1 | |
640 | c48fcb47 | blueswir1 | void cpu_reset(CPUSPARCState *env)
|
641 | c48fcb47 | blueswir1 | { |
642 | eca1bdf4 | aliguori | if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
643 | eca1bdf4 | aliguori | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
644 | eca1bdf4 | aliguori | log_cpu_state(env, 0);
|
645 | eca1bdf4 | aliguori | } |
646 | eca1bdf4 | aliguori | |
647 | c48fcb47 | blueswir1 | tlb_flush(env, 1);
|
648 | c48fcb47 | blueswir1 | env->cwp = 0;
|
649 | c48fcb47 | blueswir1 | env->wim = 1;
|
650 | c48fcb47 | blueswir1 | env->regwptr = env->regbase + (env->cwp * 16);
|
651 | c48fcb47 | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
652 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
653 | 1a14026e | blueswir1 | env->cleanwin = env->nwindows - 2;
|
654 | 1a14026e | blueswir1 | env->cansave = env->nwindows - 2;
|
655 | c48fcb47 | blueswir1 | env->pstate = PS_RMO | PS_PEF | PS_IE; |
656 | c48fcb47 | blueswir1 | env->asi = 0x82; // Primary no-fault |
657 | c48fcb47 | blueswir1 | #endif
|
658 | c48fcb47 | blueswir1 | #else
|
659 | c48fcb47 | blueswir1 | env->psret = 0;
|
660 | c48fcb47 | blueswir1 | env->psrs = 1;
|
661 | c48fcb47 | blueswir1 | env->psrps = 1;
|
662 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
663 | c48fcb47 | blueswir1 | env->pstate = PS_PRIV; |
664 | c48fcb47 | blueswir1 | env->hpstate = HS_PRIV; |
665 | c19148bd | blueswir1 | env->tsptr = &env->ts[env->tl & MAXTL_MASK]; |
666 | 415fc906 | blueswir1 | env->lsu = 0;
|
667 | c48fcb47 | blueswir1 | #else
|
668 | c48fcb47 | blueswir1 | env->mmuregs[0] &= ~(MMU_E | MMU_NF);
|
669 | 5578ceab | blueswir1 | env->mmuregs[0] |= env->def->mmu_bm;
|
670 | c48fcb47 | blueswir1 | #endif
|
671 | e87231d4 | blueswir1 | env->pc = 0;
|
672 | c48fcb47 | blueswir1 | env->npc = env->pc + 4;
|
673 | c48fcb47 | blueswir1 | #endif
|
674 | c48fcb47 | blueswir1 | } |
675 | c48fcb47 | blueswir1 | |
676 | 64a88d5d | blueswir1 | static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) |
677 | c48fcb47 | blueswir1 | { |
678 | 64a88d5d | blueswir1 | sparc_def_t def1, *def = &def1; |
679 | c48fcb47 | blueswir1 | |
680 | 64a88d5d | blueswir1 | if (cpu_sparc_find_by_name(def, cpu_model) < 0) |
681 | 64a88d5d | blueswir1 | return -1; |
682 | c48fcb47 | blueswir1 | |
683 | 5578ceab | blueswir1 | env->def = qemu_mallocz(sizeof(*def));
|
684 | 5578ceab | blueswir1 | memcpy(env->def, def, sizeof(*def));
|
685 | 5578ceab | blueswir1 | #if defined(CONFIG_USER_ONLY)
|
686 | 5578ceab | blueswir1 | if ((env->def->features & CPU_FEATURE_FLOAT))
|
687 | 5578ceab | blueswir1 | env->def->features |= CPU_FEATURE_FLOAT128; |
688 | 5578ceab | blueswir1 | #endif
|
689 | c48fcb47 | blueswir1 | env->cpu_model_str = cpu_model; |
690 | c48fcb47 | blueswir1 | env->version = def->iu_version; |
691 | c48fcb47 | blueswir1 | env->fsr = def->fpu_version; |
692 | 1a14026e | blueswir1 | env->nwindows = def->nwindows; |
693 | c48fcb47 | blueswir1 | #if !defined(TARGET_SPARC64)
|
694 | c48fcb47 | blueswir1 | env->mmuregs[0] |= def->mmu_version;
|
695 | c48fcb47 | blueswir1 | cpu_sparc_set_id(env, 0);
|
696 | 963262de | blueswir1 | env->mxccregs[7] |= def->mxcc_version;
|
697 | 1a14026e | blueswir1 | #else
|
698 | fb79ceb9 | blueswir1 | env->mmu_version = def->mmu_version; |
699 | c19148bd | blueswir1 | env->maxtl = def->maxtl; |
700 | c19148bd | blueswir1 | env->version |= def->maxtl << 8;
|
701 | 1a14026e | blueswir1 | env->version |= def->nwindows - 1;
|
702 | c48fcb47 | blueswir1 | #endif
|
703 | 64a88d5d | blueswir1 | return 0; |
704 | 64a88d5d | blueswir1 | } |
705 | 64a88d5d | blueswir1 | |
706 | 64a88d5d | blueswir1 | static void cpu_sparc_close(CPUSPARCState *env) |
707 | 64a88d5d | blueswir1 | { |
708 | 5578ceab | blueswir1 | free(env->def); |
709 | 64a88d5d | blueswir1 | free(env); |
710 | 64a88d5d | blueswir1 | } |
711 | 64a88d5d | blueswir1 | |
712 | 64a88d5d | blueswir1 | CPUSPARCState *cpu_sparc_init(const char *cpu_model) |
713 | 64a88d5d | blueswir1 | { |
714 | 64a88d5d | blueswir1 | CPUSPARCState *env; |
715 | 64a88d5d | blueswir1 | |
716 | 64a88d5d | blueswir1 | env = qemu_mallocz(sizeof(CPUSPARCState));
|
717 | 64a88d5d | blueswir1 | cpu_exec_init(env); |
718 | c48fcb47 | blueswir1 | |
719 | c48fcb47 | blueswir1 | gen_intermediate_code_init(env); |
720 | c48fcb47 | blueswir1 | |
721 | 64a88d5d | blueswir1 | if (cpu_sparc_register(env, cpu_model) < 0) { |
722 | 64a88d5d | blueswir1 | cpu_sparc_close(env); |
723 | 64a88d5d | blueswir1 | return NULL; |
724 | 64a88d5d | blueswir1 | } |
725 | c48fcb47 | blueswir1 | cpu_reset(env); |
726 | c48fcb47 | blueswir1 | |
727 | c48fcb47 | blueswir1 | return env;
|
728 | c48fcb47 | blueswir1 | } |
729 | c48fcb47 | blueswir1 | |
730 | c48fcb47 | blueswir1 | void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) |
731 | c48fcb47 | blueswir1 | { |
732 | c48fcb47 | blueswir1 | #if !defined(TARGET_SPARC64)
|
733 | c48fcb47 | blueswir1 | env->mxccregs[7] = ((cpu + 8) & 0xf) << 24; |
734 | c48fcb47 | blueswir1 | #endif
|
735 | c48fcb47 | blueswir1 | } |
736 | c48fcb47 | blueswir1 | |
737 | c48fcb47 | blueswir1 | static const sparc_def_t sparc_defs[] = { |
738 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
739 | c48fcb47 | blueswir1 | { |
740 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64",
|
741 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)), |
742 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
743 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
744 | 1a14026e | blueswir1 | .nwindows = 4,
|
745 | c19148bd | blueswir1 | .maxtl = 4,
|
746 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
747 | c48fcb47 | blueswir1 | }, |
748 | c48fcb47 | blueswir1 | { |
749 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 III",
|
750 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)), |
751 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
752 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
753 | 1a14026e | blueswir1 | .nwindows = 5,
|
754 | c19148bd | blueswir1 | .maxtl = 4,
|
755 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
756 | c48fcb47 | blueswir1 | }, |
757 | c48fcb47 | blueswir1 | { |
758 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 IV",
|
759 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)), |
760 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
761 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
762 | 1a14026e | blueswir1 | .nwindows = 8,
|
763 | c19148bd | blueswir1 | .maxtl = 5,
|
764 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
765 | c48fcb47 | blueswir1 | }, |
766 | c48fcb47 | blueswir1 | { |
767 | c48fcb47 | blueswir1 | .name = "Fujitsu Sparc64 V",
|
768 | c19148bd | blueswir1 | .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)), |
769 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
770 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
771 | 1a14026e | blueswir1 | .nwindows = 8,
|
772 | c19148bd | blueswir1 | .maxtl = 5,
|
773 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
774 | c48fcb47 | blueswir1 | }, |
775 | c48fcb47 | blueswir1 | { |
776 | c48fcb47 | blueswir1 | .name = "TI UltraSparc I",
|
777 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
778 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
779 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
780 | 1a14026e | blueswir1 | .nwindows = 8,
|
781 | c19148bd | blueswir1 | .maxtl = 5,
|
782 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
783 | c48fcb47 | blueswir1 | }, |
784 | c48fcb47 | blueswir1 | { |
785 | c48fcb47 | blueswir1 | .name = "TI UltraSparc II",
|
786 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)), |
787 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
788 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
789 | 1a14026e | blueswir1 | .nwindows = 8,
|
790 | c19148bd | blueswir1 | .maxtl = 5,
|
791 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
792 | c48fcb47 | blueswir1 | }, |
793 | c48fcb47 | blueswir1 | { |
794 | c48fcb47 | blueswir1 | .name = "TI UltraSparc IIi",
|
795 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)), |
796 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
797 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
798 | 1a14026e | blueswir1 | .nwindows = 8,
|
799 | c19148bd | blueswir1 | .maxtl = 5,
|
800 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
801 | c48fcb47 | blueswir1 | }, |
802 | c48fcb47 | blueswir1 | { |
803 | c48fcb47 | blueswir1 | .name = "TI UltraSparc IIe",
|
804 | c19148bd | blueswir1 | .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)), |
805 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
806 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
807 | 1a14026e | blueswir1 | .nwindows = 8,
|
808 | c19148bd | blueswir1 | .maxtl = 5,
|
809 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
810 | c48fcb47 | blueswir1 | }, |
811 | c48fcb47 | blueswir1 | { |
812 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc III",
|
813 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)), |
814 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
815 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
816 | 1a14026e | blueswir1 | .nwindows = 8,
|
817 | c19148bd | blueswir1 | .maxtl = 5,
|
818 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
819 | c48fcb47 | blueswir1 | }, |
820 | c48fcb47 | blueswir1 | { |
821 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc III Cu",
|
822 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)), |
823 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
824 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_3, |
825 | 1a14026e | blueswir1 | .nwindows = 8,
|
826 | c19148bd | blueswir1 | .maxtl = 5,
|
827 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
828 | c48fcb47 | blueswir1 | }, |
829 | c48fcb47 | blueswir1 | { |
830 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IIIi",
|
831 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)), |
832 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
833 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
834 | 1a14026e | blueswir1 | .nwindows = 8,
|
835 | c19148bd | blueswir1 | .maxtl = 5,
|
836 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
837 | c48fcb47 | blueswir1 | }, |
838 | c48fcb47 | blueswir1 | { |
839 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IV",
|
840 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)), |
841 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
842 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_4, |
843 | 1a14026e | blueswir1 | .nwindows = 8,
|
844 | c19148bd | blueswir1 | .maxtl = 5,
|
845 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
846 | c48fcb47 | blueswir1 | }, |
847 | c48fcb47 | blueswir1 | { |
848 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IV+",
|
849 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)), |
850 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
851 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
852 | 1a14026e | blueswir1 | .nwindows = 8,
|
853 | c19148bd | blueswir1 | .maxtl = 5,
|
854 | fb79ceb9 | blueswir1 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT, |
855 | c48fcb47 | blueswir1 | }, |
856 | c48fcb47 | blueswir1 | { |
857 | c48fcb47 | blueswir1 | .name = "Sun UltraSparc IIIi+",
|
858 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)), |
859 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
860 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_3, |
861 | 1a14026e | blueswir1 | .nwindows = 8,
|
862 | c19148bd | blueswir1 | .maxtl = 5,
|
863 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
864 | c48fcb47 | blueswir1 | }, |
865 | c48fcb47 | blueswir1 | { |
866 | c7ba218d | blueswir1 | .name = "Sun UltraSparc T1",
|
867 | c7ba218d | blueswir1 | // defined in sparc_ifu_fdp.v and ctu.h
|
868 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)), |
869 | c7ba218d | blueswir1 | .fpu_version = 0x00000000,
|
870 | c7ba218d | blueswir1 | .mmu_version = mmu_sun4v, |
871 | c7ba218d | blueswir1 | .nwindows = 8,
|
872 | c19148bd | blueswir1 | .maxtl = 6,
|
873 | c7ba218d | blueswir1 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
874 | c7ba218d | blueswir1 | | CPU_FEATURE_GL, |
875 | c7ba218d | blueswir1 | }, |
876 | c7ba218d | blueswir1 | { |
877 | c7ba218d | blueswir1 | .name = "Sun UltraSparc T2",
|
878 | c7ba218d | blueswir1 | // defined in tlu_asi_ctl.v and n2_revid_cust.v
|
879 | c19148bd | blueswir1 | .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)), |
880 | c7ba218d | blueswir1 | .fpu_version = 0x00000000,
|
881 | c7ba218d | blueswir1 | .mmu_version = mmu_sun4v, |
882 | c7ba218d | blueswir1 | .nwindows = 8,
|
883 | c19148bd | blueswir1 | .maxtl = 6,
|
884 | c7ba218d | blueswir1 | .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT |
885 | c7ba218d | blueswir1 | | CPU_FEATURE_GL, |
886 | c7ba218d | blueswir1 | }, |
887 | c7ba218d | blueswir1 | { |
888 | c48fcb47 | blueswir1 | .name = "NEC UltraSparc I",
|
889 | c19148bd | blueswir1 | .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)), |
890 | c48fcb47 | blueswir1 | .fpu_version = 0x00000000,
|
891 | fb79ceb9 | blueswir1 | .mmu_version = mmu_us_12, |
892 | 1a14026e | blueswir1 | .nwindows = 8,
|
893 | c19148bd | blueswir1 | .maxtl = 5,
|
894 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
895 | c48fcb47 | blueswir1 | }, |
896 | c48fcb47 | blueswir1 | #else
|
897 | c48fcb47 | blueswir1 | { |
898 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86900",
|
899 | c48fcb47 | blueswir1 | .iu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
900 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
901 | c48fcb47 | blueswir1 | .mmu_version = 0x00 << 24, /* Impl 0, ver 0 */ |
902 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
903 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
904 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
905 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
906 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
907 | 1a14026e | blueswir1 | .nwindows = 7,
|
908 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_FSMULD, |
909 | c48fcb47 | blueswir1 | }, |
910 | c48fcb47 | blueswir1 | { |
911 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86904",
|
912 | c48fcb47 | blueswir1 | .iu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
913 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
914 | c48fcb47 | blueswir1 | .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */ |
915 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
916 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
917 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
918 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
919 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
920 | 1a14026e | blueswir1 | .nwindows = 8,
|
921 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
922 | c48fcb47 | blueswir1 | }, |
923 | c48fcb47 | blueswir1 | { |
924 | c48fcb47 | blueswir1 | .name = "Fujitsu MB86907",
|
925 | c48fcb47 | blueswir1 | .iu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
926 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
927 | c48fcb47 | blueswir1 | .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */ |
928 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
929 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
930 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
931 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
932 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
933 | 1a14026e | blueswir1 | .nwindows = 8,
|
934 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
935 | c48fcb47 | blueswir1 | }, |
936 | c48fcb47 | blueswir1 | { |
937 | c48fcb47 | blueswir1 | .name = "LSI L64811",
|
938 | c48fcb47 | blueswir1 | .iu_version = 0x10 << 24, /* Impl 1, ver 0 */ |
939 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, /* FPU version 1 (LSI L64814) */ |
940 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
941 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
942 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
943 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
944 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
945 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
946 | 1a14026e | blueswir1 | .nwindows = 8,
|
947 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
948 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
949 | c48fcb47 | blueswir1 | }, |
950 | c48fcb47 | blueswir1 | { |
951 | c48fcb47 | blueswir1 | .name = "Cypress CY7C601",
|
952 | c48fcb47 | blueswir1 | .iu_version = 0x11 << 24, /* Impl 1, ver 1 */ |
953 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
954 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
955 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
956 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
957 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
958 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
959 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
960 | 1a14026e | blueswir1 | .nwindows = 8,
|
961 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
962 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
963 | c48fcb47 | blueswir1 | }, |
964 | c48fcb47 | blueswir1 | { |
965 | c48fcb47 | blueswir1 | .name = "Cypress CY7C611",
|
966 | c48fcb47 | blueswir1 | .iu_version = 0x13 << 24, /* Impl 1, ver 3 */ |
967 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Cypress CY7C602) */ |
968 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
969 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
970 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
971 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
972 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
973 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
974 | 1a14026e | blueswir1 | .nwindows = 8,
|
975 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
976 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
977 | c48fcb47 | blueswir1 | }, |
978 | c48fcb47 | blueswir1 | { |
979 | c48fcb47 | blueswir1 | .name = "TI MicroSparc I",
|
980 | c48fcb47 | blueswir1 | .iu_version = 0x41000000,
|
981 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
982 | c48fcb47 | blueswir1 | .mmu_version = 0x41000000,
|
983 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
984 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
985 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
986 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
987 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x0000003f,
|
988 | 1a14026e | blueswir1 | .nwindows = 7,
|
989 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_MUL | |
990 | e30b4678 | blueswir1 | CPU_FEATURE_DIV | CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | |
991 | e30b4678 | blueswir1 | CPU_FEATURE_FMUL, |
992 | c48fcb47 | blueswir1 | }, |
993 | c48fcb47 | blueswir1 | { |
994 | c48fcb47 | blueswir1 | .name = "TI MicroSparc II",
|
995 | c48fcb47 | blueswir1 | .iu_version = 0x42000000,
|
996 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
997 | c48fcb47 | blueswir1 | .mmu_version = 0x02000000,
|
998 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
999 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
1000 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
1001 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016fff,
|
1002 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
1003 | 1a14026e | blueswir1 | .nwindows = 8,
|
1004 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1005 | c48fcb47 | blueswir1 | }, |
1006 | c48fcb47 | blueswir1 | { |
1007 | c48fcb47 | blueswir1 | .name = "TI MicroSparc IIep",
|
1008 | c48fcb47 | blueswir1 | .iu_version = 0x42000000,
|
1009 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, |
1010 | c48fcb47 | blueswir1 | .mmu_version = 0x04000000,
|
1011 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1012 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x00ffffc0,
|
1013 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x000000ff,
|
1014 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0x00016bff,
|
1015 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0x00ffffff,
|
1016 | 1a14026e | blueswir1 | .nwindows = 8,
|
1017 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1018 | c48fcb47 | blueswir1 | }, |
1019 | c48fcb47 | blueswir1 | { |
1020 | b5154bde | blueswir1 | .name = "TI SuperSparc 40", // STP1020NPGA |
1021 | 963262de | blueswir1 | .iu_version = 0x41000000, // SuperSPARC 2.x |
1022 | b5154bde | blueswir1 | .fpu_version = 0 << 17, |
1023 | 963262de | blueswir1 | .mmu_version = 0x00000800, // SuperSPARC 2.x, no MXCC |
1024 | b5154bde | blueswir1 | .mmu_bm = 0x00002000,
|
1025 | b5154bde | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1026 | b5154bde | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1027 | b5154bde | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1028 | b5154bde | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1029 | 1a14026e | blueswir1 | .nwindows = 8,
|
1030 | b5154bde | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1031 | b5154bde | blueswir1 | }, |
1032 | b5154bde | blueswir1 | { |
1033 | b5154bde | blueswir1 | .name = "TI SuperSparc 50", // STP1020PGA |
1034 | 963262de | blueswir1 | .iu_version = 0x40000000, // SuperSPARC 3.x |
1035 | b5154bde | blueswir1 | .fpu_version = 0 << 17, |
1036 | 963262de | blueswir1 | .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC |
1037 | b5154bde | blueswir1 | .mmu_bm = 0x00002000,
|
1038 | b5154bde | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1039 | b5154bde | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1040 | b5154bde | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1041 | b5154bde | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1042 | 1a14026e | blueswir1 | .nwindows = 8,
|
1043 | b5154bde | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1044 | b5154bde | blueswir1 | }, |
1045 | b5154bde | blueswir1 | { |
1046 | c48fcb47 | blueswir1 | .name = "TI SuperSparc 51",
|
1047 | 963262de | blueswir1 | .iu_version = 0x40000000, // SuperSPARC 3.x |
1048 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
1049 | 963262de | blueswir1 | .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC |
1050 | c48fcb47 | blueswir1 | .mmu_bm = 0x00002000,
|
1051 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1052 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1053 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1054 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1055 | 963262de | blueswir1 | .mxcc_version = 0x00000104,
|
1056 | 1a14026e | blueswir1 | .nwindows = 8,
|
1057 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1058 | c48fcb47 | blueswir1 | }, |
1059 | c48fcb47 | blueswir1 | { |
1060 | b5154bde | blueswir1 | .name = "TI SuperSparc 60", // STP1020APGA |
1061 | 963262de | blueswir1 | .iu_version = 0x40000000, // SuperSPARC 3.x |
1062 | b5154bde | blueswir1 | .fpu_version = 0 << 17, |
1063 | 963262de | blueswir1 | .mmu_version = 0x01000800, // SuperSPARC 3.x, no MXCC |
1064 | b5154bde | blueswir1 | .mmu_bm = 0x00002000,
|
1065 | b5154bde | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1066 | b5154bde | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1067 | b5154bde | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1068 | b5154bde | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1069 | 1a14026e | blueswir1 | .nwindows = 8,
|
1070 | b5154bde | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1071 | b5154bde | blueswir1 | }, |
1072 | b5154bde | blueswir1 | { |
1073 | c48fcb47 | blueswir1 | .name = "TI SuperSparc 61",
|
1074 | 963262de | blueswir1 | .iu_version = 0x44000000, // SuperSPARC 3.x |
1075 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
1076 | 963262de | blueswir1 | .mmu_version = 0x01000000, // SuperSPARC 3.x, MXCC |
1077 | 963262de | blueswir1 | .mmu_bm = 0x00002000,
|
1078 | 963262de | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1079 | 963262de | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1080 | 963262de | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1081 | 963262de | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1082 | 963262de | blueswir1 | .mxcc_version = 0x00000104,
|
1083 | 963262de | blueswir1 | .nwindows = 8,
|
1084 | 963262de | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1085 | 963262de | blueswir1 | }, |
1086 | 963262de | blueswir1 | { |
1087 | 963262de | blueswir1 | .name = "TI SuperSparc II",
|
1088 | 963262de | blueswir1 | .iu_version = 0x40000000, // SuperSPARC II 1.x |
1089 | 963262de | blueswir1 | .fpu_version = 0 << 17, |
1090 | 963262de | blueswir1 | .mmu_version = 0x08000000, // SuperSPARC II 1.x, MXCC |
1091 | c48fcb47 | blueswir1 | .mmu_bm = 0x00002000,
|
1092 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0xffffffc0,
|
1093 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000ffff,
|
1094 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1095 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1096 | 963262de | blueswir1 | .mxcc_version = 0x00000104,
|
1097 | 1a14026e | blueswir1 | .nwindows = 8,
|
1098 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1099 | c48fcb47 | blueswir1 | }, |
1100 | c48fcb47 | blueswir1 | { |
1101 | c48fcb47 | blueswir1 | .name = "Ross RT625",
|
1102 | c48fcb47 | blueswir1 | .iu_version = 0x1e000000,
|
1103 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, |
1104 | c48fcb47 | blueswir1 | .mmu_version = 0x1e000000,
|
1105 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1106 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1107 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1108 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1109 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1110 | 1a14026e | blueswir1 | .nwindows = 8,
|
1111 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1112 | c48fcb47 | blueswir1 | }, |
1113 | c48fcb47 | blueswir1 | { |
1114 | c48fcb47 | blueswir1 | .name = "Ross RT620",
|
1115 | c48fcb47 | blueswir1 | .iu_version = 0x1f000000,
|
1116 | c48fcb47 | blueswir1 | .fpu_version = 1 << 17, |
1117 | c48fcb47 | blueswir1 | .mmu_version = 0x1f000000,
|
1118 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1119 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1120 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1121 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1122 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1123 | 1a14026e | blueswir1 | .nwindows = 8,
|
1124 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1125 | c48fcb47 | blueswir1 | }, |
1126 | c48fcb47 | blueswir1 | { |
1127 | c48fcb47 | blueswir1 | .name = "BIT B5010",
|
1128 | c48fcb47 | blueswir1 | .iu_version = 0x20000000,
|
1129 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, /* B5010/B5110/B5120/B5210 */ |
1130 | c48fcb47 | blueswir1 | .mmu_version = 0x20000000,
|
1131 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1132 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1133 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1134 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1135 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1136 | 1a14026e | blueswir1 | .nwindows = 8,
|
1137 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | CPU_FEATURE_FSQRT | |
1138 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
1139 | c48fcb47 | blueswir1 | }, |
1140 | c48fcb47 | blueswir1 | { |
1141 | c48fcb47 | blueswir1 | .name = "Matsushita MN10501",
|
1142 | c48fcb47 | blueswir1 | .iu_version = 0x50000000,
|
1143 | c48fcb47 | blueswir1 | .fpu_version = 0 << 17, |
1144 | c48fcb47 | blueswir1 | .mmu_version = 0x50000000,
|
1145 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1146 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1147 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1148 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1149 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1150 | 1a14026e | blueswir1 | .nwindows = 8,
|
1151 | e30b4678 | blueswir1 | .features = CPU_FEATURE_FLOAT | CPU_FEATURE_MUL | CPU_FEATURE_FSQRT | |
1152 | e30b4678 | blueswir1 | CPU_FEATURE_FSMULD, |
1153 | c48fcb47 | blueswir1 | }, |
1154 | c48fcb47 | blueswir1 | { |
1155 | c48fcb47 | blueswir1 | .name = "Weitek W8601",
|
1156 | c48fcb47 | blueswir1 | .iu_version = 0x90 << 24, /* Impl 9, ver 0 */ |
1157 | c48fcb47 | blueswir1 | .fpu_version = 3 << 17, /* FPU version 3 (Weitek WTL3170/2) */ |
1158 | c48fcb47 | blueswir1 | .mmu_version = 0x10 << 24, |
1159 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1160 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1161 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1162 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1163 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1164 | 1a14026e | blueswir1 | .nwindows = 8,
|
1165 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1166 | c48fcb47 | blueswir1 | }, |
1167 | c48fcb47 | blueswir1 | { |
1168 | c48fcb47 | blueswir1 | .name = "LEON2",
|
1169 | c48fcb47 | blueswir1 | .iu_version = 0xf2000000,
|
1170 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1171 | c48fcb47 | blueswir1 | .mmu_version = 0xf2000000,
|
1172 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1173 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1174 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1175 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1176 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1177 | 1a14026e | blueswir1 | .nwindows = 8,
|
1178 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1179 | c48fcb47 | blueswir1 | }, |
1180 | c48fcb47 | blueswir1 | { |
1181 | c48fcb47 | blueswir1 | .name = "LEON3",
|
1182 | c48fcb47 | blueswir1 | .iu_version = 0xf3000000,
|
1183 | c48fcb47 | blueswir1 | .fpu_version = 4 << 17, /* FPU version 4 (Meiko) */ |
1184 | c48fcb47 | blueswir1 | .mmu_version = 0xf3000000,
|
1185 | c48fcb47 | blueswir1 | .mmu_bm = 0x00004000,
|
1186 | c48fcb47 | blueswir1 | .mmu_ctpr_mask = 0x007ffff0,
|
1187 | c48fcb47 | blueswir1 | .mmu_cxr_mask = 0x0000003f,
|
1188 | c48fcb47 | blueswir1 | .mmu_sfsr_mask = 0xffffffff,
|
1189 | c48fcb47 | blueswir1 | .mmu_trcr_mask = 0xffffffff,
|
1190 | 1a14026e | blueswir1 | .nwindows = 8,
|
1191 | 64a88d5d | blueswir1 | .features = CPU_DEFAULT_FEATURES, |
1192 | c48fcb47 | blueswir1 | }, |
1193 | c48fcb47 | blueswir1 | #endif
|
1194 | c48fcb47 | blueswir1 | }; |
1195 | c48fcb47 | blueswir1 | |
1196 | 64a88d5d | blueswir1 | static const char * const feature_name[] = { |
1197 | 64a88d5d | blueswir1 | "float",
|
1198 | 64a88d5d | blueswir1 | "float128",
|
1199 | 64a88d5d | blueswir1 | "swap",
|
1200 | 64a88d5d | blueswir1 | "mul",
|
1201 | 64a88d5d | blueswir1 | "div",
|
1202 | 64a88d5d | blueswir1 | "flush",
|
1203 | 64a88d5d | blueswir1 | "fsqrt",
|
1204 | 64a88d5d | blueswir1 | "fmul",
|
1205 | 64a88d5d | blueswir1 | "vis1",
|
1206 | 64a88d5d | blueswir1 | "vis2",
|
1207 | e30b4678 | blueswir1 | "fsmuld",
|
1208 | fb79ceb9 | blueswir1 | "hypv",
|
1209 | fb79ceb9 | blueswir1 | "cmt",
|
1210 | fb79ceb9 | blueswir1 | "gl",
|
1211 | 64a88d5d | blueswir1 | }; |
1212 | 64a88d5d | blueswir1 | |
1213 | 64a88d5d | blueswir1 | static void print_features(FILE *f, |
1214 | 64a88d5d | blueswir1 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
1215 | 64a88d5d | blueswir1 | uint32_t features, const char *prefix) |
1216 | c48fcb47 | blueswir1 | { |
1217 | c48fcb47 | blueswir1 | unsigned int i; |
1218 | c48fcb47 | blueswir1 | |
1219 | 64a88d5d | blueswir1 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1220 | 64a88d5d | blueswir1 | if (feature_name[i] && (features & (1 << i))) { |
1221 | 64a88d5d | blueswir1 | if (prefix)
|
1222 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "%s", prefix);
|
1223 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "%s ", feature_name[i]);
|
1224 | 64a88d5d | blueswir1 | } |
1225 | 64a88d5d | blueswir1 | } |
1226 | 64a88d5d | blueswir1 | |
1227 | 64a88d5d | blueswir1 | static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features) |
1228 | 64a88d5d | blueswir1 | { |
1229 | 64a88d5d | blueswir1 | unsigned int i; |
1230 | 64a88d5d | blueswir1 | |
1231 | 64a88d5d | blueswir1 | for (i = 0; i < ARRAY_SIZE(feature_name); i++) |
1232 | 64a88d5d | blueswir1 | if (feature_name[i] && !strcmp(flagname, feature_name[i])) {
|
1233 | 64a88d5d | blueswir1 | *features |= 1 << i;
|
1234 | 64a88d5d | blueswir1 | return;
|
1235 | 64a88d5d | blueswir1 | } |
1236 | 64a88d5d | blueswir1 | fprintf(stderr, "CPU feature %s not found\n", flagname);
|
1237 | 64a88d5d | blueswir1 | } |
1238 | 64a88d5d | blueswir1 | |
1239 | 22548760 | blueswir1 | static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model) |
1240 | 64a88d5d | blueswir1 | { |
1241 | 64a88d5d | blueswir1 | unsigned int i; |
1242 | 64a88d5d | blueswir1 | const sparc_def_t *def = NULL; |
1243 | 64a88d5d | blueswir1 | char *s = strdup(cpu_model);
|
1244 | 64a88d5d | blueswir1 | char *featurestr, *name = strtok(s, ","); |
1245 | 64a88d5d | blueswir1 | uint32_t plus_features = 0;
|
1246 | 64a88d5d | blueswir1 | uint32_t minus_features = 0;
|
1247 | 64a88d5d | blueswir1 | long long iu_version; |
1248 | 1a14026e | blueswir1 | uint32_t fpu_version, mmu_version, nwindows; |
1249 | 64a88d5d | blueswir1 | |
1250 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
1251 | c48fcb47 | blueswir1 | if (strcasecmp(name, sparc_defs[i].name) == 0) { |
1252 | 64a88d5d | blueswir1 | def = &sparc_defs[i]; |
1253 | c48fcb47 | blueswir1 | } |
1254 | c48fcb47 | blueswir1 | } |
1255 | 64a88d5d | blueswir1 | if (!def)
|
1256 | 64a88d5d | blueswir1 | goto error;
|
1257 | 64a88d5d | blueswir1 | memcpy(cpu_def, def, sizeof(*def));
|
1258 | 64a88d5d | blueswir1 | |
1259 | 64a88d5d | blueswir1 | featurestr = strtok(NULL, ","); |
1260 | 64a88d5d | blueswir1 | while (featurestr) {
|
1261 | 64a88d5d | blueswir1 | char *val;
|
1262 | 64a88d5d | blueswir1 | |
1263 | 64a88d5d | blueswir1 | if (featurestr[0] == '+') { |
1264 | 64a88d5d | blueswir1 | add_flagname_to_bitmaps(featurestr + 1, &plus_features);
|
1265 | 64a88d5d | blueswir1 | } else if (featurestr[0] == '-') { |
1266 | 64a88d5d | blueswir1 | add_flagname_to_bitmaps(featurestr + 1, &minus_features);
|
1267 | 64a88d5d | blueswir1 | } else if ((val = strchr(featurestr, '='))) { |
1268 | 64a88d5d | blueswir1 | *val = 0; val++;
|
1269 | 64a88d5d | blueswir1 | if (!strcmp(featurestr, "iu_version")) { |
1270 | 64a88d5d | blueswir1 | char *err;
|
1271 | 64a88d5d | blueswir1 | |
1272 | 64a88d5d | blueswir1 | iu_version = strtoll(val, &err, 0);
|
1273 | 64a88d5d | blueswir1 | if (!*val || *err) {
|
1274 | 64a88d5d | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1275 | 64a88d5d | blueswir1 | goto error;
|
1276 | 64a88d5d | blueswir1 | } |
1277 | 64a88d5d | blueswir1 | cpu_def->iu_version = iu_version; |
1278 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1279 | 64a88d5d | blueswir1 | fprintf(stderr, "iu_version %llx\n", iu_version);
|
1280 | 64a88d5d | blueswir1 | #endif
|
1281 | 64a88d5d | blueswir1 | } else if (!strcmp(featurestr, "fpu_version")) { |
1282 | 64a88d5d | blueswir1 | char *err;
|
1283 | 64a88d5d | blueswir1 | |
1284 | 64a88d5d | blueswir1 | fpu_version = strtol(val, &err, 0);
|
1285 | 64a88d5d | blueswir1 | if (!*val || *err) {
|
1286 | 64a88d5d | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1287 | 64a88d5d | blueswir1 | goto error;
|
1288 | 64a88d5d | blueswir1 | } |
1289 | 64a88d5d | blueswir1 | cpu_def->fpu_version = fpu_version; |
1290 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1291 | 64a88d5d | blueswir1 | fprintf(stderr, "fpu_version %llx\n", fpu_version);
|
1292 | 64a88d5d | blueswir1 | #endif
|
1293 | 64a88d5d | blueswir1 | } else if (!strcmp(featurestr, "mmu_version")) { |
1294 | 64a88d5d | blueswir1 | char *err;
|
1295 | 64a88d5d | blueswir1 | |
1296 | 64a88d5d | blueswir1 | mmu_version = strtol(val, &err, 0);
|
1297 | 64a88d5d | blueswir1 | if (!*val || *err) {
|
1298 | 64a88d5d | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1299 | 64a88d5d | blueswir1 | goto error;
|
1300 | 64a88d5d | blueswir1 | } |
1301 | 64a88d5d | blueswir1 | cpu_def->mmu_version = mmu_version; |
1302 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1303 | 64a88d5d | blueswir1 | fprintf(stderr, "mmu_version %llx\n", mmu_version);
|
1304 | 64a88d5d | blueswir1 | #endif
|
1305 | 1a14026e | blueswir1 | } else if (!strcmp(featurestr, "nwindows")) { |
1306 | 1a14026e | blueswir1 | char *err;
|
1307 | 1a14026e | blueswir1 | |
1308 | 1a14026e | blueswir1 | nwindows = strtol(val, &err, 0);
|
1309 | 1a14026e | blueswir1 | if (!*val || *err || nwindows > MAX_NWINDOWS ||
|
1310 | 1a14026e | blueswir1 | nwindows < MIN_NWINDOWS) { |
1311 | 1a14026e | blueswir1 | fprintf(stderr, "bad numerical value %s\n", val);
|
1312 | 1a14026e | blueswir1 | goto error;
|
1313 | 1a14026e | blueswir1 | } |
1314 | 1a14026e | blueswir1 | cpu_def->nwindows = nwindows; |
1315 | 1a14026e | blueswir1 | #ifdef DEBUG_FEATURES
|
1316 | 1a14026e | blueswir1 | fprintf(stderr, "nwindows %d\n", nwindows);
|
1317 | 1a14026e | blueswir1 | #endif
|
1318 | 64a88d5d | blueswir1 | } else {
|
1319 | 64a88d5d | blueswir1 | fprintf(stderr, "unrecognized feature %s\n", featurestr);
|
1320 | 64a88d5d | blueswir1 | goto error;
|
1321 | 64a88d5d | blueswir1 | } |
1322 | 64a88d5d | blueswir1 | } else {
|
1323 | 77f193da | blueswir1 | fprintf(stderr, "feature string `%s' not in format "
|
1324 | 77f193da | blueswir1 | "(+feature|-feature|feature=xyz)\n", featurestr);
|
1325 | 64a88d5d | blueswir1 | goto error;
|
1326 | 64a88d5d | blueswir1 | } |
1327 | 64a88d5d | blueswir1 | featurestr = strtok(NULL, ","); |
1328 | 64a88d5d | blueswir1 | } |
1329 | 64a88d5d | blueswir1 | cpu_def->features |= plus_features; |
1330 | 64a88d5d | blueswir1 | cpu_def->features &= ~minus_features; |
1331 | 64a88d5d | blueswir1 | #ifdef DEBUG_FEATURES
|
1332 | 64a88d5d | blueswir1 | print_features(stderr, fprintf, cpu_def->features, NULL);
|
1333 | 64a88d5d | blueswir1 | #endif
|
1334 | 64a88d5d | blueswir1 | free(s); |
1335 | 64a88d5d | blueswir1 | return 0; |
1336 | 64a88d5d | blueswir1 | |
1337 | 64a88d5d | blueswir1 | error:
|
1338 | 64a88d5d | blueswir1 | free(s); |
1339 | 64a88d5d | blueswir1 | return -1; |
1340 | c48fcb47 | blueswir1 | } |
1341 | c48fcb47 | blueswir1 | |
1342 | 77f193da | blueswir1 | void sparc_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)) |
1343 | c48fcb47 | blueswir1 | { |
1344 | c48fcb47 | blueswir1 | unsigned int i; |
1345 | c48fcb47 | blueswir1 | |
1346 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) { |
1347 | 1a14026e | blueswir1 | (*cpu_fprintf)(f, "Sparc %16s IU " TARGET_FMT_lx " FPU %08x MMU %08x NWINS %d ", |
1348 | c48fcb47 | blueswir1 | sparc_defs[i].name, |
1349 | c48fcb47 | blueswir1 | sparc_defs[i].iu_version, |
1350 | c48fcb47 | blueswir1 | sparc_defs[i].fpu_version, |
1351 | 1a14026e | blueswir1 | sparc_defs[i].mmu_version, |
1352 | 1a14026e | blueswir1 | sparc_defs[i].nwindows); |
1353 | 77f193da | blueswir1 | print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES & |
1354 | 77f193da | blueswir1 | ~sparc_defs[i].features, "-");
|
1355 | 77f193da | blueswir1 | print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES & |
1356 | 77f193da | blueswir1 | sparc_defs[i].features, "+");
|
1357 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "\n");
|
1358 | c48fcb47 | blueswir1 | } |
1359 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "Default CPU feature flags (use '-' to remove): ");
|
1360 | f76981b1 | blueswir1 | print_features(f, cpu_fprintf, CPU_DEFAULT_FEATURES, NULL);
|
1361 | 64a88d5d | blueswir1 | (*cpu_fprintf)(f, "\n");
|
1362 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "Available CPU feature flags (use '+' to add): ");
|
1363 | f76981b1 | blueswir1 | print_features(f, cpu_fprintf, ~CPU_DEFAULT_FEATURES, NULL);
|
1364 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "\n");
|
1365 | f76981b1 | blueswir1 | (*cpu_fprintf)(f, "Numerical features (use '=' to set): iu_version "
|
1366 | f76981b1 | blueswir1 | "fpu_version mmu_version nwindows\n");
|
1367 | c48fcb47 | blueswir1 | } |
1368 | c48fcb47 | blueswir1 | |
1369 | c48fcb47 | blueswir1 | void cpu_dump_state(CPUState *env, FILE *f,
|
1370 | c48fcb47 | blueswir1 | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
1371 | c48fcb47 | blueswir1 | int flags)
|
1372 | c48fcb47 | blueswir1 | { |
1373 | c48fcb47 | blueswir1 | int i, x;
|
1374 | c48fcb47 | blueswir1 | |
1375 | 77f193da | blueswir1 | cpu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc, |
1376 | 77f193da | blueswir1 | env->npc); |
1377 | c48fcb47 | blueswir1 | cpu_fprintf(f, "General Registers:\n");
|
1378 | c48fcb47 | blueswir1 | for (i = 0; i < 4; i++) |
1379 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1380 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1381 | c48fcb47 | blueswir1 | for (; i < 8; i++) |
1382 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]); |
1383 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\nCurrent Register Window:\n");
|
1384 | c48fcb47 | blueswir1 | for (x = 0; x < 3; x++) { |
1385 | c48fcb47 | blueswir1 | for (i = 0; i < 4; i++) |
1386 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1387 | c48fcb47 | blueswir1 | (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i, |
1388 | c48fcb47 | blueswir1 | env->regwptr[i + x * 8]);
|
1389 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1390 | c48fcb47 | blueswir1 | for (; i < 8; i++) |
1391 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t", |
1392 | c48fcb47 | blueswir1 | (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i, |
1393 | c48fcb47 | blueswir1 | env->regwptr[i + x * 8]);
|
1394 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1395 | c48fcb47 | blueswir1 | } |
1396 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\nFloating Point Registers:\n");
|
1397 | c48fcb47 | blueswir1 | for (i = 0; i < 32; i++) { |
1398 | c48fcb47 | blueswir1 | if ((i & 3) == 0) |
1399 | c48fcb47 | blueswir1 | cpu_fprintf(f, "%%f%02d:", i);
|
1400 | a37ee56c | blueswir1 | cpu_fprintf(f, " %016f", *(float *)&env->fpr[i]); |
1401 | c48fcb47 | blueswir1 | if ((i & 3) == 3) |
1402 | c48fcb47 | blueswir1 | cpu_fprintf(f, "\n");
|
1403 | c48fcb47 | blueswir1 | } |
1404 | c48fcb47 | blueswir1 | #ifdef TARGET_SPARC64
|
1405 | c48fcb47 | blueswir1 | cpu_fprintf(f, "pstate: 0x%08x ccr: 0x%02x asi: 0x%02x tl: %d fprs: %d\n",
|
1406 | c48fcb47 | blueswir1 | env->pstate, GET_CCR(env), env->asi, env->tl, env->fprs); |
1407 | 77f193da | blueswir1 | cpu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate %d "
|
1408 | 77f193da | blueswir1 | "cleanwin %d cwp %d\n",
|
1409 | c48fcb47 | blueswir1 | env->cansave, env->canrestore, env->otherwin, env->wstate, |
1410 | 1a14026e | blueswir1 | env->cleanwin, env->nwindows - 1 - env->cwp);
|
1411 | c48fcb47 | blueswir1 | #else
|
1412 | d78f3995 | blueswir1 | |
1413 | d78f3995 | blueswir1 | #define GET_FLAG(a,b) ((env->psr & a)?b:'-') |
1414 | d78f3995 | blueswir1 | |
1415 | 77f193da | blueswir1 | cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n",
|
1416 | 77f193da | blueswir1 | GET_PSR(env), GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'), |
1417 | 77f193da | blueswir1 | GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'), |
1418 | 77f193da | blueswir1 | env->psrs?'S':'-', env->psrps?'P':'-', |
1419 | 77f193da | blueswir1 | env->psret?'E':'-', env->wim); |
1420 | c48fcb47 | blueswir1 | #endif
|
1421 | 3a3b925d | blueswir1 | cpu_fprintf(f, "fsr: 0x%08x\n", env->fsr);
|
1422 | c48fcb47 | blueswir1 | } |