root / hw / etraxfs_timer.c @ 94a943ef
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1 | 83fa1010 | ths | /*
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2 | e62b5b13 | edgar_igl | * QEMU ETRAX Timers
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3 | 83fa1010 | ths | *
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4 | 83fa1010 | ths | * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
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5 | 83fa1010 | ths | *
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6 | 83fa1010 | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 83fa1010 | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | 83fa1010 | ths | * in the Software without restriction, including without limitation the rights
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9 | 83fa1010 | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 83fa1010 | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | 83fa1010 | ths | * furnished to do so, subject to the following conditions:
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12 | 83fa1010 | ths | *
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13 | 83fa1010 | ths | * The above copyright notice and this permission notice shall be included in
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14 | 83fa1010 | ths | * all copies or substantial portions of the Software.
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15 | 83fa1010 | ths | *
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16 | 83fa1010 | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 83fa1010 | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 83fa1010 | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 83fa1010 | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 83fa1010 | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 83fa1010 | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 83fa1010 | ths | * THE SOFTWARE.
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23 | 83fa1010 | ths | */
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24 | 3b1fd90e | Edgar E. Iglesias | #include "sysbus.h" |
25 | 5439779e | edgar_igl | #include "sysemu.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | 83fa1010 | ths | |
28 | bbaf29c7 | edgar_igl | #define D(x)
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29 | bbaf29c7 | edgar_igl | |
30 | ca87d03b | edgar_igl | #define RW_TMR0_DIV 0x00 |
31 | ca87d03b | edgar_igl | #define R_TMR0_DATA 0x04 |
32 | ca87d03b | edgar_igl | #define RW_TMR0_CTRL 0x08 |
33 | ca87d03b | edgar_igl | #define RW_TMR1_DIV 0x10 |
34 | ca87d03b | edgar_igl | #define R_TMR1_DATA 0x14 |
35 | ca87d03b | edgar_igl | #define RW_TMR1_CTRL 0x18 |
36 | ca87d03b | edgar_igl | #define R_TIME 0x38 |
37 | ca87d03b | edgar_igl | #define RW_WD_CTRL 0x40 |
38 | 5439779e | edgar_igl | #define R_WD_STAT 0x44 |
39 | ca87d03b | edgar_igl | #define RW_INTR_MASK 0x48 |
40 | ca87d03b | edgar_igl | #define RW_ACK_INTR 0x4c |
41 | ca87d03b | edgar_igl | #define R_INTR 0x50 |
42 | ca87d03b | edgar_igl | #define R_MASKED_INTR 0x54 |
43 | 83fa1010 | ths | |
44 | 3b1fd90e | Edgar E. Iglesias | struct etrax_timer {
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45 | 3b1fd90e | Edgar E. Iglesias | SysBusDevice busdev; |
46 | 3b1fd90e | Edgar E. Iglesias | qemu_irq irq; |
47 | 3b1fd90e | Edgar E. Iglesias | qemu_irq nmi; |
48 | 84ceea57 | Edgar E. Iglesias | |
49 | 84ceea57 | Edgar E. Iglesias | QEMUBH *bh_t0; |
50 | 84ceea57 | Edgar E. Iglesias | QEMUBH *bh_t1; |
51 | 84ceea57 | Edgar E. Iglesias | QEMUBH *bh_wd; |
52 | 84ceea57 | Edgar E. Iglesias | ptimer_state *ptimer_t0; |
53 | 84ceea57 | Edgar E. Iglesias | ptimer_state *ptimer_t1; |
54 | 84ceea57 | Edgar E. Iglesias | ptimer_state *ptimer_wd; |
55 | 84ceea57 | Edgar E. Iglesias | |
56 | 84ceea57 | Edgar E. Iglesias | int wd_hits;
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57 | 84ceea57 | Edgar E. Iglesias | |
58 | 84ceea57 | Edgar E. Iglesias | /* Control registers. */
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59 | 84ceea57 | Edgar E. Iglesias | uint32_t rw_tmr0_div; |
60 | 84ceea57 | Edgar E. Iglesias | uint32_t r_tmr0_data; |
61 | 84ceea57 | Edgar E. Iglesias | uint32_t rw_tmr0_ctrl; |
62 | 84ceea57 | Edgar E. Iglesias | |
63 | 84ceea57 | Edgar E. Iglesias | uint32_t rw_tmr1_div; |
64 | 84ceea57 | Edgar E. Iglesias | uint32_t r_tmr1_data; |
65 | 84ceea57 | Edgar E. Iglesias | uint32_t rw_tmr1_ctrl; |
66 | 84ceea57 | Edgar E. Iglesias | |
67 | 84ceea57 | Edgar E. Iglesias | uint32_t rw_wd_ctrl; |
68 | 84ceea57 | Edgar E. Iglesias | |
69 | 84ceea57 | Edgar E. Iglesias | uint32_t rw_intr_mask; |
70 | 84ceea57 | Edgar E. Iglesias | uint32_t rw_ack_intr; |
71 | 84ceea57 | Edgar E. Iglesias | uint32_t r_intr; |
72 | 84ceea57 | Edgar E. Iglesias | uint32_t r_masked_intr; |
73 | 83fa1010 | ths | }; |
74 | 83fa1010 | ths | |
75 | 83fa1010 | ths | static uint32_t timer_readl (void *opaque, target_phys_addr_t addr) |
76 | 83fa1010 | ths | { |
77 | 3b1fd90e | Edgar E. Iglesias | struct etrax_timer *t = opaque;
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78 | 84ceea57 | Edgar E. Iglesias | uint32_t r = 0;
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79 | 84ceea57 | Edgar E. Iglesias | |
80 | 84ceea57 | Edgar E. Iglesias | switch (addr) {
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81 | 84ceea57 | Edgar E. Iglesias | case R_TMR0_DATA:
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82 | 84ceea57 | Edgar E. Iglesias | r = ptimer_get_count(t->ptimer_t0); |
83 | 84ceea57 | Edgar E. Iglesias | break;
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84 | 84ceea57 | Edgar E. Iglesias | case R_TMR1_DATA:
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85 | 84ceea57 | Edgar E. Iglesias | r = ptimer_get_count(t->ptimer_t1); |
86 | 84ceea57 | Edgar E. Iglesias | break;
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87 | 84ceea57 | Edgar E. Iglesias | case R_TIME:
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88 | 84ceea57 | Edgar E. Iglesias | r = qemu_get_clock(vm_clock) / 10;
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89 | 84ceea57 | Edgar E. Iglesias | break;
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90 | 84ceea57 | Edgar E. Iglesias | case RW_INTR_MASK:
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91 | 84ceea57 | Edgar E. Iglesias | r = t->rw_intr_mask; |
92 | 84ceea57 | Edgar E. Iglesias | break;
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93 | 84ceea57 | Edgar E. Iglesias | case R_MASKED_INTR:
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94 | 84ceea57 | Edgar E. Iglesias | r = t->r_intr & t->rw_intr_mask; |
95 | 84ceea57 | Edgar E. Iglesias | break;
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96 | 84ceea57 | Edgar E. Iglesias | default:
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97 | 84ceea57 | Edgar E. Iglesias | D(printf ("%s %x\n", __func__, addr));
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98 | 84ceea57 | Edgar E. Iglesias | break;
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99 | 84ceea57 | Edgar E. Iglesias | } |
100 | 84ceea57 | Edgar E. Iglesias | return r;
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101 | 83fa1010 | ths | } |
102 | 83fa1010 | ths | |
103 | f0b86b14 | edgar_igl | #define TIMER_SLOWDOWN 1 |
104 | 3b1fd90e | Edgar E. Iglesias | static void update_ctrl(struct etrax_timer *t, int tnum) |
105 | 83fa1010 | ths | { |
106 | 84ceea57 | Edgar E. Iglesias | unsigned int op; |
107 | 84ceea57 | Edgar E. Iglesias | unsigned int freq; |
108 | 84ceea57 | Edgar E. Iglesias | unsigned int freq_hz; |
109 | 84ceea57 | Edgar E. Iglesias | unsigned int div; |
110 | 84ceea57 | Edgar E. Iglesias | uint32_t ctrl; |
111 | 84ceea57 | Edgar E. Iglesias | |
112 | 84ceea57 | Edgar E. Iglesias | ptimer_state *timer; |
113 | 84ceea57 | Edgar E. Iglesias | |
114 | 84ceea57 | Edgar E. Iglesias | if (tnum == 0) { |
115 | 84ceea57 | Edgar E. Iglesias | ctrl = t->rw_tmr0_ctrl; |
116 | 84ceea57 | Edgar E. Iglesias | div = t->rw_tmr0_div; |
117 | 84ceea57 | Edgar E. Iglesias | timer = t->ptimer_t0; |
118 | 84ceea57 | Edgar E. Iglesias | } else {
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119 | 84ceea57 | Edgar E. Iglesias | ctrl = t->rw_tmr1_ctrl; |
120 | 84ceea57 | Edgar E. Iglesias | div = t->rw_tmr1_div; |
121 | 84ceea57 | Edgar E. Iglesias | timer = t->ptimer_t1; |
122 | 84ceea57 | Edgar E. Iglesias | } |
123 | 84ceea57 | Edgar E. Iglesias | |
124 | 84ceea57 | Edgar E. Iglesias | |
125 | 84ceea57 | Edgar E. Iglesias | op = ctrl & 3;
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126 | 84ceea57 | Edgar E. Iglesias | freq = ctrl >> 2;
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127 | 84ceea57 | Edgar E. Iglesias | freq_hz = 32000000;
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128 | 84ceea57 | Edgar E. Iglesias | |
129 | 84ceea57 | Edgar E. Iglesias | switch (freq)
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130 | 84ceea57 | Edgar E. Iglesias | { |
131 | 84ceea57 | Edgar E. Iglesias | case 0: |
132 | 84ceea57 | Edgar E. Iglesias | case 1: |
133 | 84ceea57 | Edgar E. Iglesias | D(printf ("extern or disabled timer clock?\n"));
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134 | 84ceea57 | Edgar E. Iglesias | break;
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135 | 84ceea57 | Edgar E. Iglesias | case 4: freq_hz = 29493000; break; |
136 | 84ceea57 | Edgar E. Iglesias | case 5: freq_hz = 32000000; break; |
137 | 84ceea57 | Edgar E. Iglesias | case 6: freq_hz = 32768000; break; |
138 | 84ceea57 | Edgar E. Iglesias | case 7: freq_hz = 100000000; break; |
139 | 84ceea57 | Edgar E. Iglesias | default:
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140 | 84ceea57 | Edgar E. Iglesias | abort(); |
141 | 84ceea57 | Edgar E. Iglesias | break;
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142 | 84ceea57 | Edgar E. Iglesias | } |
143 | 84ceea57 | Edgar E. Iglesias | |
144 | 84ceea57 | Edgar E. Iglesias | D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
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145 | 84ceea57 | Edgar E. Iglesias | div = div * TIMER_SLOWDOWN; |
146 | 84ceea57 | Edgar E. Iglesias | div /= 1000;
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147 | 84ceea57 | Edgar E. Iglesias | freq_hz /= 1000;
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148 | 84ceea57 | Edgar E. Iglesias | ptimer_set_freq(timer, freq_hz); |
149 | 84ceea57 | Edgar E. Iglesias | ptimer_set_limit(timer, div, 0);
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150 | 84ceea57 | Edgar E. Iglesias | |
151 | 84ceea57 | Edgar E. Iglesias | switch (op)
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152 | 84ceea57 | Edgar E. Iglesias | { |
153 | 84ceea57 | Edgar E. Iglesias | case 0: |
154 | 84ceea57 | Edgar E. Iglesias | /* Load. */
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155 | 84ceea57 | Edgar E. Iglesias | ptimer_set_limit(timer, div, 1);
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156 | 84ceea57 | Edgar E. Iglesias | break;
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157 | 84ceea57 | Edgar E. Iglesias | case 1: |
158 | 84ceea57 | Edgar E. Iglesias | /* Hold. */
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159 | 84ceea57 | Edgar E. Iglesias | ptimer_stop(timer); |
160 | 84ceea57 | Edgar E. Iglesias | break;
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161 | 84ceea57 | Edgar E. Iglesias | case 2: |
162 | 84ceea57 | Edgar E. Iglesias | /* Run. */
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163 | 84ceea57 | Edgar E. Iglesias | ptimer_run(timer, 0);
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164 | 84ceea57 | Edgar E. Iglesias | break;
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165 | 84ceea57 | Edgar E. Iglesias | default:
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166 | 84ceea57 | Edgar E. Iglesias | abort(); |
167 | 84ceea57 | Edgar E. Iglesias | break;
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168 | 84ceea57 | Edgar E. Iglesias | } |
169 | 83fa1010 | ths | } |
170 | 83fa1010 | ths | |
171 | 3b1fd90e | Edgar E. Iglesias | static void timer_update_irq(struct etrax_timer *t) |
172 | 83fa1010 | ths | { |
173 | 84ceea57 | Edgar E. Iglesias | t->r_intr &= ~(t->rw_ack_intr); |
174 | 84ceea57 | Edgar E. Iglesias | t->r_masked_intr = t->r_intr & t->rw_intr_mask; |
175 | 60237223 | edgar_igl | |
176 | 84ceea57 | Edgar E. Iglesias | D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
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177 | 3b1fd90e | Edgar E. Iglesias | qemu_set_irq(t->irq, !!t->r_masked_intr); |
178 | 83fa1010 | ths | } |
179 | 83fa1010 | ths | |
180 | 5439779e | edgar_igl | static void timer0_hit(void *opaque) |
181 | 60237223 | edgar_igl | { |
182 | 3b1fd90e | Edgar E. Iglesias | struct etrax_timer *t = opaque;
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183 | 84ceea57 | Edgar E. Iglesias | t->r_intr |= 1;
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184 | 84ceea57 | Edgar E. Iglesias | timer_update_irq(t); |
185 | 60237223 | edgar_igl | } |
186 | 60237223 | edgar_igl | |
187 | 5439779e | edgar_igl | static void timer1_hit(void *opaque) |
188 | 5439779e | edgar_igl | { |
189 | 3b1fd90e | Edgar E. Iglesias | struct etrax_timer *t = opaque;
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190 | 84ceea57 | Edgar E. Iglesias | t->r_intr |= 2;
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191 | 84ceea57 | Edgar E. Iglesias | timer_update_irq(t); |
192 | 5439779e | edgar_igl | } |
193 | 5439779e | edgar_igl | |
194 | 5439779e | edgar_igl | static void watchdog_hit(void *opaque) |
195 | 5439779e | edgar_igl | { |
196 | 3b1fd90e | Edgar E. Iglesias | struct etrax_timer *t = opaque;
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197 | 84ceea57 | Edgar E. Iglesias | if (t->wd_hits == 0) { |
198 | 84ceea57 | Edgar E. Iglesias | /* real hw gives a single tick before reseting but we are
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199 | 84ceea57 | Edgar E. Iglesias | a bit friendlier to compensate for our slower execution. */
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200 | 84ceea57 | Edgar E. Iglesias | ptimer_set_count(t->ptimer_wd, 10);
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201 | 84ceea57 | Edgar E. Iglesias | ptimer_run(t->ptimer_wd, 1);
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202 | 3b1fd90e | Edgar E. Iglesias | qemu_irq_raise(t->nmi); |
203 | 84ceea57 | Edgar E. Iglesias | } |
204 | 84ceea57 | Edgar E. Iglesias | else
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205 | 84ceea57 | Edgar E. Iglesias | qemu_system_reset_request(); |
206 | 84ceea57 | Edgar E. Iglesias | |
207 | 84ceea57 | Edgar E. Iglesias | t->wd_hits++; |
208 | 5439779e | edgar_igl | } |
209 | 5439779e | edgar_igl | |
210 | 3b1fd90e | Edgar E. Iglesias | static inline void timer_watchdog_update(struct etrax_timer *t, uint32_t value) |
211 | 5439779e | edgar_igl | { |
212 | 84ceea57 | Edgar E. Iglesias | unsigned int wd_en = t->rw_wd_ctrl & (1 << 8); |
213 | 84ceea57 | Edgar E. Iglesias | unsigned int wd_key = t->rw_wd_ctrl >> 9; |
214 | 84ceea57 | Edgar E. Iglesias | unsigned int wd_cnt = t->rw_wd_ctrl & 511; |
215 | 84ceea57 | Edgar E. Iglesias | unsigned int new_key = value >> 9 & ((1 << 7) - 1); |
216 | 84ceea57 | Edgar E. Iglesias | unsigned int new_cmd = (value >> 8) & 1; |
217 | 5439779e | edgar_igl | |
218 | 84ceea57 | Edgar E. Iglesias | /* If the watchdog is enabled, they written key must match the
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219 | 84ceea57 | Edgar E. Iglesias | complement of the previous. */
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220 | 84ceea57 | Edgar E. Iglesias | wd_key = ~wd_key & ((1 << 7) - 1); |
221 | 5439779e | edgar_igl | |
222 | 84ceea57 | Edgar E. Iglesias | if (wd_en && wd_key != new_key)
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223 | 84ceea57 | Edgar E. Iglesias | return;
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224 | 5439779e | edgar_igl | |
225 | 84ceea57 | Edgar E. Iglesias | D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
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226 | 84ceea57 | Edgar E. Iglesias | wd_en, new_key, wd_key, new_cmd, wd_cnt)); |
227 | 5439779e | edgar_igl | |
228 | 84ceea57 | Edgar E. Iglesias | if (t->wd_hits)
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229 | 3b1fd90e | Edgar E. Iglesias | qemu_irq_lower(t->nmi); |
230 | 5ef98b47 | edgar_igl | |
231 | 84ceea57 | Edgar E. Iglesias | t->wd_hits = 0;
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232 | 5ef98b47 | edgar_igl | |
233 | 84ceea57 | Edgar E. Iglesias | ptimer_set_freq(t->ptimer_wd, 760);
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234 | 84ceea57 | Edgar E. Iglesias | if (wd_cnt == 0) |
235 | 84ceea57 | Edgar E. Iglesias | wd_cnt = 256;
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236 | 84ceea57 | Edgar E. Iglesias | ptimer_set_count(t->ptimer_wd, wd_cnt); |
237 | 84ceea57 | Edgar E. Iglesias | if (new_cmd)
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238 | 84ceea57 | Edgar E. Iglesias | ptimer_run(t->ptimer_wd, 1);
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239 | 84ceea57 | Edgar E. Iglesias | else
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240 | 84ceea57 | Edgar E. Iglesias | ptimer_stop(t->ptimer_wd); |
241 | 5439779e | edgar_igl | |
242 | 84ceea57 | Edgar E. Iglesias | t->rw_wd_ctrl = value; |
243 | 5439779e | edgar_igl | } |
244 | 5439779e | edgar_igl | |
245 | 83fa1010 | ths | static void |
246 | 83fa1010 | ths | timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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247 | 83fa1010 | ths | { |
248 | 3b1fd90e | Edgar E. Iglesias | struct etrax_timer *t = opaque;
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249 | 84ceea57 | Edgar E. Iglesias | |
250 | 84ceea57 | Edgar E. Iglesias | switch (addr)
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251 | 84ceea57 | Edgar E. Iglesias | { |
252 | 84ceea57 | Edgar E. Iglesias | case RW_TMR0_DIV:
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253 | 84ceea57 | Edgar E. Iglesias | t->rw_tmr0_div = value; |
254 | 84ceea57 | Edgar E. Iglesias | break;
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255 | 84ceea57 | Edgar E. Iglesias | case RW_TMR0_CTRL:
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256 | 84ceea57 | Edgar E. Iglesias | D(printf ("RW_TMR0_CTRL=%x\n", value));
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257 | 84ceea57 | Edgar E. Iglesias | t->rw_tmr0_ctrl = value; |
258 | 84ceea57 | Edgar E. Iglesias | update_ctrl(t, 0);
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259 | 84ceea57 | Edgar E. Iglesias | break;
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260 | 84ceea57 | Edgar E. Iglesias | case RW_TMR1_DIV:
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261 | 84ceea57 | Edgar E. Iglesias | t->rw_tmr1_div = value; |
262 | 84ceea57 | Edgar E. Iglesias | break;
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263 | 84ceea57 | Edgar E. Iglesias | case RW_TMR1_CTRL:
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264 | 84ceea57 | Edgar E. Iglesias | D(printf ("RW_TMR1_CTRL=%x\n", value));
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265 | 84ceea57 | Edgar E. Iglesias | t->rw_tmr1_ctrl = value; |
266 | 84ceea57 | Edgar E. Iglesias | update_ctrl(t, 1);
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267 | 84ceea57 | Edgar E. Iglesias | break;
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268 | 84ceea57 | Edgar E. Iglesias | case RW_INTR_MASK:
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269 | 84ceea57 | Edgar E. Iglesias | D(printf ("RW_INTR_MASK=%x\n", value));
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270 | 84ceea57 | Edgar E. Iglesias | t->rw_intr_mask = value; |
271 | 84ceea57 | Edgar E. Iglesias | timer_update_irq(t); |
272 | 84ceea57 | Edgar E. Iglesias | break;
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273 | 84ceea57 | Edgar E. Iglesias | case RW_WD_CTRL:
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274 | 84ceea57 | Edgar E. Iglesias | timer_watchdog_update(t, value); |
275 | 84ceea57 | Edgar E. Iglesias | break;
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276 | 84ceea57 | Edgar E. Iglesias | case RW_ACK_INTR:
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277 | 84ceea57 | Edgar E. Iglesias | t->rw_ack_intr = value; |
278 | 84ceea57 | Edgar E. Iglesias | timer_update_irq(t); |
279 | 84ceea57 | Edgar E. Iglesias | t->rw_ack_intr = 0;
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280 | 84ceea57 | Edgar E. Iglesias | break;
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281 | 84ceea57 | Edgar E. Iglesias | default:
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282 | 84ceea57 | Edgar E. Iglesias | printf ("%s " TARGET_FMT_plx " %x\n", |
283 | 84ceea57 | Edgar E. Iglesias | __func__, addr, value); |
284 | 84ceea57 | Edgar E. Iglesias | break;
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285 | 84ceea57 | Edgar E. Iglesias | } |
286 | 83fa1010 | ths | } |
287 | 83fa1010 | ths | |
288 | d60efc6b | Blue Swirl | static CPUReadMemoryFunc * const timer_read[] = { |
289 | 84ceea57 | Edgar E. Iglesias | NULL, NULL, |
290 | 84ceea57 | Edgar E. Iglesias | &timer_readl, |
291 | 83fa1010 | ths | }; |
292 | 83fa1010 | ths | |
293 | d60efc6b | Blue Swirl | static CPUWriteMemoryFunc * const timer_write[] = { |
294 | 84ceea57 | Edgar E. Iglesias | NULL, NULL, |
295 | 84ceea57 | Edgar E. Iglesias | &timer_writel, |
296 | 83fa1010 | ths | }; |
297 | 83fa1010 | ths | |
298 | 5439779e | edgar_igl | static void etraxfs_timer_reset(void *opaque) |
299 | 5439779e | edgar_igl | { |
300 | 3b1fd90e | Edgar E. Iglesias | struct etrax_timer *t = opaque;
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301 | 84ceea57 | Edgar E. Iglesias | |
302 | 84ceea57 | Edgar E. Iglesias | ptimer_stop(t->ptimer_t0); |
303 | 84ceea57 | Edgar E. Iglesias | ptimer_stop(t->ptimer_t1); |
304 | 84ceea57 | Edgar E. Iglesias | ptimer_stop(t->ptimer_wd); |
305 | 84ceea57 | Edgar E. Iglesias | t->rw_wd_ctrl = 0;
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306 | 84ceea57 | Edgar E. Iglesias | t->r_intr = 0;
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307 | 84ceea57 | Edgar E. Iglesias | t->rw_intr_mask = 0;
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308 | 3b1fd90e | Edgar E. Iglesias | qemu_irq_lower(t->irq); |
309 | 5439779e | edgar_igl | } |
310 | 5439779e | edgar_igl | |
311 | 81a322d4 | Gerd Hoffmann | static int etraxfs_timer_init(SysBusDevice *dev) |
312 | 83fa1010 | ths | { |
313 | 3b1fd90e | Edgar E. Iglesias | struct etrax_timer *t = FROM_SYSBUS(typeof (*t), dev);
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314 | 84ceea57 | Edgar E. Iglesias | int timer_regs;
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315 | 83fa1010 | ths | |
316 | 84ceea57 | Edgar E. Iglesias | t->bh_t0 = qemu_bh_new(timer0_hit, t); |
317 | 84ceea57 | Edgar E. Iglesias | t->bh_t1 = qemu_bh_new(timer1_hit, t); |
318 | 84ceea57 | Edgar E. Iglesias | t->bh_wd = qemu_bh_new(watchdog_hit, t); |
319 | 84ceea57 | Edgar E. Iglesias | t->ptimer_t0 = ptimer_init(t->bh_t0); |
320 | 84ceea57 | Edgar E. Iglesias | t->ptimer_t1 = ptimer_init(t->bh_t1); |
321 | 84ceea57 | Edgar E. Iglesias | t->ptimer_wd = ptimer_init(t->bh_wd); |
322 | 3b1fd90e | Edgar E. Iglesias | |
323 | 3b1fd90e | Edgar E. Iglesias | sysbus_init_irq(dev, &t->irq); |
324 | 3b1fd90e | Edgar E. Iglesias | sysbus_init_irq(dev, &t->nmi); |
325 | 83fa1010 | ths | |
326 | 1eed09cb | Avi Kivity | timer_regs = cpu_register_io_memory(timer_read, timer_write, t); |
327 | 3b1fd90e | Edgar E. Iglesias | sysbus_init_mmio(dev, 0x5c, timer_regs);
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328 | 5439779e | edgar_igl | |
329 | a08d4367 | Jan Kiszka | qemu_register_reset(etraxfs_timer_reset, t); |
330 | 81a322d4 | Gerd Hoffmann | return 0; |
331 | 83fa1010 | ths | } |
332 | 3b1fd90e | Edgar E. Iglesias | |
333 | 3b1fd90e | Edgar E. Iglesias | static void etraxfs_timer_register(void) |
334 | 3b1fd90e | Edgar E. Iglesias | { |
335 | 3b1fd90e | Edgar E. Iglesias | sysbus_register_dev("etraxfs,timer", sizeof (struct etrax_timer), |
336 | 3b1fd90e | Edgar E. Iglesias | etraxfs_timer_init); |
337 | 3b1fd90e | Edgar E. Iglesias | } |
338 | 3b1fd90e | Edgar E. Iglesias | |
339 | 3b1fd90e | Edgar E. Iglesias | device_init(etraxfs_timer_register) |