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1 | d4e8164f | bellard | /*
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2 | d4e8164f | bellard | * internal execution defines for qemu
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3 | d4e8164f | bellard | *
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4 | d4e8164f | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | d4e8164f | bellard | *
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6 | d4e8164f | bellard | * This library is free software; you can redistribute it and/or
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7 | d4e8164f | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | d4e8164f | bellard | * License as published by the Free Software Foundation; either
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9 | d4e8164f | bellard | * version 2 of the License, or (at your option) any later version.
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10 | d4e8164f | bellard | *
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11 | d4e8164f | bellard | * This library is distributed in the hope that it will be useful,
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12 | d4e8164f | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | d4e8164f | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | d4e8164f | bellard | * Lesser General Public License for more details.
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15 | d4e8164f | bellard | *
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16 | d4e8164f | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | d4e8164f | bellard | * License along with this library; if not, write to the Free Software
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18 | d4e8164f | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | d4e8164f | bellard | */
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20 | d4e8164f | bellard | |
21 | b346ff46 | bellard | /* allow to see translation results - the slowdown should be negligible, so we leave it */
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22 | b346ff46 | bellard | #define DEBUG_DISAS
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23 | b346ff46 | bellard | |
24 | 33417e70 | bellard | #ifndef glue
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25 | 33417e70 | bellard | #define xglue(x, y) x ## y |
26 | 33417e70 | bellard | #define glue(x, y) xglue(x, y)
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27 | 33417e70 | bellard | #define stringify(s) tostring(s)
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28 | 33417e70 | bellard | #define tostring(s) #s |
29 | 33417e70 | bellard | #endif
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30 | 33417e70 | bellard | |
31 | c98baaac | bellard | #if __GNUC__ < 3 |
32 | 33417e70 | bellard | #define __builtin_expect(x, n) (x)
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33 | 33417e70 | bellard | #endif
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34 | 33417e70 | bellard | |
35 | e2222c39 | bellard | #ifdef __i386__
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36 | e2222c39 | bellard | #define REGPARM(n) __attribute((regparm(n)))
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37 | e2222c39 | bellard | #else
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38 | e2222c39 | bellard | #define REGPARM(n)
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39 | e2222c39 | bellard | #endif
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40 | e2222c39 | bellard | |
41 | b346ff46 | bellard | /* is_jmp field values */
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42 | b346ff46 | bellard | #define DISAS_NEXT 0 /* next instruction can be analyzed */ |
43 | b346ff46 | bellard | #define DISAS_JUMP 1 /* only pc was modified dynamically */ |
44 | b346ff46 | bellard | #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ |
45 | b346ff46 | bellard | #define DISAS_TB_JUMP 3 /* only pc was modified statically */ |
46 | b346ff46 | bellard | |
47 | b346ff46 | bellard | struct TranslationBlock;
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48 | b346ff46 | bellard | |
49 | b346ff46 | bellard | /* XXX: make safe guess about sizes */
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50 | b346ff46 | bellard | #define MAX_OP_PER_INSTR 32 |
51 | b346ff46 | bellard | #define OPC_BUF_SIZE 512 |
52 | b346ff46 | bellard | #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
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53 | b346ff46 | bellard | |
54 | b346ff46 | bellard | #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3) |
55 | b346ff46 | bellard | |
56 | b346ff46 | bellard | extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
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57 | b346ff46 | bellard | extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
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58 | c27004ec | bellard | extern long gen_labels[OPC_BUF_SIZE]; |
59 | c27004ec | bellard | extern int nb_gen_labels; |
60 | c27004ec | bellard | extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
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61 | c27004ec | bellard | extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
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62 | 66e85a21 | bellard | extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
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63 | b346ff46 | bellard | extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
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64 | c3278b7b | bellard | extern target_ulong gen_opc_jump_pc[2]; |
65 | 30d6cb84 | bellard | extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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66 | b346ff46 | bellard | |
67 | 9886cc16 | bellard | typedef void (GenOpFunc)(void); |
68 | 9886cc16 | bellard | typedef void (GenOpFunc1)(long); |
69 | 9886cc16 | bellard | typedef void (GenOpFunc2)(long, long); |
70 | 9886cc16 | bellard | typedef void (GenOpFunc3)(long, long, long); |
71 | 9886cc16 | bellard | |
72 | b346ff46 | bellard | #if defined(TARGET_I386)
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73 | b346ff46 | bellard | |
74 | 33417e70 | bellard | void optimize_flags_init(void); |
75 | d4e8164f | bellard | |
76 | b346ff46 | bellard | #endif
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77 | b346ff46 | bellard | |
78 | b346ff46 | bellard | extern FILE *logfile;
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79 | b346ff46 | bellard | extern int loglevel; |
80 | b346ff46 | bellard | |
81 | 4c3a88a2 | bellard | int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb); |
82 | 4c3a88a2 | bellard | int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb); |
83 | b346ff46 | bellard | void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); |
84 | 4c3a88a2 | bellard | int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, |
85 | b346ff46 | bellard | int max_code_size, int *gen_code_size_ptr); |
86 | 66e85a21 | bellard | int cpu_restore_state(struct TranslationBlock *tb, |
87 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
88 | 58fe2f10 | bellard | void *puc);
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89 | 58fe2f10 | bellard | int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, |
90 | 58fe2f10 | bellard | int max_code_size, int *gen_code_size_ptr); |
91 | 58fe2f10 | bellard | int cpu_restore_state_copy(struct TranslationBlock *tb, |
92 | 58fe2f10 | bellard | CPUState *env, unsigned long searched_pc, |
93 | 58fe2f10 | bellard | void *puc);
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94 | 2e12669a | bellard | void cpu_resume_from_signal(CPUState *env1, void *puc); |
95 | 6a00d601 | bellard | void cpu_exec_init(CPUState *env);
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96 | 53a5960a | pbrook | int page_unprotect(target_ulong address, unsigned long pc, void *puc); |
97 | 2e12669a | bellard | void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
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98 | 2e12669a | bellard | int is_cpu_write_access);
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99 | 4390df51 | bellard | void tb_invalidate_page_range(target_ulong start, target_ulong end);
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100 | 2e12669a | bellard | void tlb_flush_page(CPUState *env, target_ulong addr);
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101 | ee8b7021 | bellard | void tlb_flush(CPUState *env, int flush_global); |
102 | 84b7b8e7 | bellard | int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
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103 | 84b7b8e7 | bellard | target_phys_addr_t paddr, int prot,
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104 | 84b7b8e7 | bellard | int is_user, int is_softmmu); |
105 | 84b7b8e7 | bellard | static inline int tlb_set_page(CPUState *env, target_ulong vaddr, |
106 | 84b7b8e7 | bellard | target_phys_addr_t paddr, int prot,
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107 | 84b7b8e7 | bellard | int is_user, int is_softmmu) |
108 | 84b7b8e7 | bellard | { |
109 | 84b7b8e7 | bellard | if (prot & PAGE_READ)
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110 | 84b7b8e7 | bellard | prot |= PAGE_EXEC; |
111 | 84b7b8e7 | bellard | return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu);
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112 | 84b7b8e7 | bellard | } |
113 | d4e8164f | bellard | |
114 | d4e8164f | bellard | #define CODE_GEN_MAX_SIZE 65536 |
115 | d4e8164f | bellard | #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ |
116 | d4e8164f | bellard | |
117 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_BITS 15 |
118 | 4390df51 | bellard | #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) |
119 | 4390df51 | bellard | |
120 | d4e8164f | bellard | /* maximum total translate dcode allocated */
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121 | 4390df51 | bellard | |
122 | 4390df51 | bellard | /* NOTE: the translated code area cannot be too big because on some
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123 | c4c7e3e6 | bellard | archs the range of "fast" function calls is limited. Here is a
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124 | 4390df51 | bellard | summary of the ranges:
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125 | 4390df51 | bellard | |
126 | 4390df51 | bellard | i386 : signed 32 bits
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127 | 4390df51 | bellard | arm : signed 26 bits
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128 | 4390df51 | bellard | ppc : signed 24 bits
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129 | 4390df51 | bellard | sparc : signed 32 bits
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130 | 4390df51 | bellard | alpha : signed 23 bits
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131 | 4390df51 | bellard | */
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132 | 4390df51 | bellard | |
133 | 4390df51 | bellard | #if defined(__alpha__)
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134 | 4390df51 | bellard | #define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) |
135 | b8076a74 | bellard | #elif defined(__ia64)
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136 | b8076a74 | bellard | #define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ |
137 | 4390df51 | bellard | #elif defined(__powerpc__)
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138 | c4c7e3e6 | bellard | #define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) |
139 | 4390df51 | bellard | #else
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140 | c98baaac | bellard | #define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) |
141 | 4390df51 | bellard | #endif
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142 | 4390df51 | bellard | |
143 | d4e8164f | bellard | //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
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144 | d4e8164f | bellard | |
145 | 4390df51 | bellard | /* estimated block size for TB allocation */
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146 | 4390df51 | bellard | /* XXX: use a per code average code fragment size and modulate it
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147 | 4390df51 | bellard | according to the host CPU */
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148 | 4390df51 | bellard | #if defined(CONFIG_SOFTMMU)
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149 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 128 |
150 | 4390df51 | bellard | #else
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151 | 4390df51 | bellard | #define CODE_GEN_AVG_BLOCK_SIZE 64 |
152 | 4390df51 | bellard | #endif
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153 | 4390df51 | bellard | |
154 | 4390df51 | bellard | #define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
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155 | 4390df51 | bellard | |
156 | 4390df51 | bellard | #if defined(__powerpc__)
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157 | 4390df51 | bellard | #define USE_DIRECT_JUMP
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158 | 4390df51 | bellard | #endif
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159 | 67b915a5 | bellard | #if defined(__i386__) && !defined(_WIN32)
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160 | d4e8164f | bellard | #define USE_DIRECT_JUMP
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161 | d4e8164f | bellard | #endif
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162 | d4e8164f | bellard | |
163 | d4e8164f | bellard | typedef struct TranslationBlock { |
164 | 2e12669a | bellard | target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
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165 | 2e12669a | bellard | target_ulong cs_base; /* CS base for this block */
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166 | d4e8164f | bellard | unsigned int flags; /* flags defining in which context the code was generated */ |
167 | d4e8164f | bellard | uint16_t size; /* size of target code for this block (1 <=
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168 | d4e8164f | bellard | size <= TARGET_PAGE_SIZE) */
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169 | 58fe2f10 | bellard | uint16_t cflags; /* compile flags */
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170 | bf088061 | bellard | #define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ |
171 | bf088061 | bellard | #define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ |
172 | bf088061 | bellard | #define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ |
173 | 2e12669a | bellard | #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ |
174 | 58fe2f10 | bellard | |
175 | d4e8164f | bellard | uint8_t *tc_ptr; /* pointer to the translated code */
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176 | 4390df51 | bellard | /* next matching tb for physical address. */
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177 | 4390df51 | bellard | struct TranslationBlock *phys_hash_next;
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178 | 4390df51 | bellard | /* first and second physical page containing code. The lower bit
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179 | 4390df51 | bellard | of the pointer tells the index in page_next[] */
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180 | 4390df51 | bellard | struct TranslationBlock *page_next[2]; |
181 | 4390df51 | bellard | target_ulong page_addr[2];
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182 | 4390df51 | bellard | |
183 | d4e8164f | bellard | /* the following data are used to directly call another TB from
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184 | d4e8164f | bellard | the code of this one. */
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185 | d4e8164f | bellard | uint16_t tb_next_offset[2]; /* offset of original jump target */ |
186 | d4e8164f | bellard | #ifdef USE_DIRECT_JUMP
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187 | 4cbb86e1 | bellard | uint16_t tb_jmp_offset[4]; /* offset of jump instruction */ |
188 | d4e8164f | bellard | #else
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189 | 95f7652d | bellard | uint32_t tb_next[2]; /* address of jump generated code */ |
190 | d4e8164f | bellard | #endif
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191 | d4e8164f | bellard | /* list of TBs jumping to this one. This is a circular list using
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192 | d4e8164f | bellard | the two least significant bits of the pointers to tell what is
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193 | d4e8164f | bellard | the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
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194 | d4e8164f | bellard | jmp_first */
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195 | d4e8164f | bellard | struct TranslationBlock *jmp_next[2]; |
196 | d4e8164f | bellard | struct TranslationBlock *jmp_first;
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197 | d4e8164f | bellard | } TranslationBlock; |
198 | d4e8164f | bellard | |
199 | 8a40a180 | bellard | static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) |
200 | d4e8164f | bellard | { |
201 | 8a40a180 | bellard | return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1); |
202 | d4e8164f | bellard | } |
203 | d4e8164f | bellard | |
204 | 4390df51 | bellard | static inline unsigned int tb_phys_hash_func(unsigned long pc) |
205 | 4390df51 | bellard | { |
206 | 4390df51 | bellard | return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); |
207 | 4390df51 | bellard | } |
208 | 4390df51 | bellard | |
209 | c27004ec | bellard | TranslationBlock *tb_alloc(target_ulong pc); |
210 | 0124311e | bellard | void tb_flush(CPUState *env);
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211 | 4390df51 | bellard | void tb_link_phys(TranslationBlock *tb,
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212 | 4390df51 | bellard | target_ulong phys_pc, target_ulong phys_page2); |
213 | d4e8164f | bellard | |
214 | 4390df51 | bellard | extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
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215 | d4e8164f | bellard | |
216 | d4e8164f | bellard | extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
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217 | d4e8164f | bellard | extern uint8_t *code_gen_ptr;
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218 | d4e8164f | bellard | |
219 | 4390df51 | bellard | #if defined(USE_DIRECT_JUMP)
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220 | 4390df51 | bellard | |
221 | 4390df51 | bellard | #if defined(__powerpc__)
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222 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
223 | d4e8164f | bellard | { |
224 | d4e8164f | bellard | uint32_t val, *ptr; |
225 | d4e8164f | bellard | |
226 | d4e8164f | bellard | /* patch the branch destination */
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227 | 4cbb86e1 | bellard | ptr = (uint32_t *)jmp_addr; |
228 | d4e8164f | bellard | val = *ptr; |
229 | 4cbb86e1 | bellard | val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc); |
230 | d4e8164f | bellard | *ptr = val; |
231 | d4e8164f | bellard | /* flush icache */
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232 | d4e8164f | bellard | asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory"); |
233 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
234 | d4e8164f | bellard | asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory"); |
235 | d4e8164f | bellard | asm volatile ("sync" : : : "memory"); |
236 | d4e8164f | bellard | asm volatile ("isync" : : : "memory"); |
237 | d4e8164f | bellard | } |
238 | 4390df51 | bellard | #elif defined(__i386__)
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239 | 4390df51 | bellard | static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) |
240 | 4390df51 | bellard | { |
241 | 4390df51 | bellard | /* patch the branch destination */
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242 | 4390df51 | bellard | *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
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243 | 4390df51 | bellard | /* no need to flush icache explicitely */
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244 | 4390df51 | bellard | } |
245 | 4390df51 | bellard | #endif
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246 | d4e8164f | bellard | |
247 | 4cbb86e1 | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
248 | 4cbb86e1 | bellard | int n, unsigned long addr) |
249 | 4cbb86e1 | bellard | { |
250 | 4cbb86e1 | bellard | unsigned long offset; |
251 | 4cbb86e1 | bellard | |
252 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n]; |
253 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
254 | 4cbb86e1 | bellard | offset = tb->tb_jmp_offset[n + 2];
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255 | 4cbb86e1 | bellard | if (offset != 0xffff) |
256 | 4cbb86e1 | bellard | tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr); |
257 | 4cbb86e1 | bellard | } |
258 | 4cbb86e1 | bellard | |
259 | d4e8164f | bellard | #else
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260 | d4e8164f | bellard | |
261 | d4e8164f | bellard | /* set the jump target */
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262 | d4e8164f | bellard | static inline void tb_set_jmp_target(TranslationBlock *tb, |
263 | d4e8164f | bellard | int n, unsigned long addr) |
264 | d4e8164f | bellard | { |
265 | 95f7652d | bellard | tb->tb_next[n] = addr; |
266 | d4e8164f | bellard | } |
267 | d4e8164f | bellard | |
268 | d4e8164f | bellard | #endif
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269 | d4e8164f | bellard | |
270 | d4e8164f | bellard | static inline void tb_add_jump(TranslationBlock *tb, int n, |
271 | d4e8164f | bellard | TranslationBlock *tb_next) |
272 | d4e8164f | bellard | { |
273 | cf25629d | bellard | /* NOTE: this test is only needed for thread safety */
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274 | cf25629d | bellard | if (!tb->jmp_next[n]) {
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275 | cf25629d | bellard | /* patch the native jump address */
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276 | cf25629d | bellard | tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr); |
277 | cf25629d | bellard | |
278 | cf25629d | bellard | /* add in TB jmp circular list */
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279 | cf25629d | bellard | tb->jmp_next[n] = tb_next->jmp_first; |
280 | cf25629d | bellard | tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
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281 | cf25629d | bellard | } |
282 | d4e8164f | bellard | } |
283 | d4e8164f | bellard | |
284 | a513fe19 | bellard | TranslationBlock *tb_find_pc(unsigned long pc_ptr); |
285 | a513fe19 | bellard | |
286 | d4e8164f | bellard | #ifndef offsetof
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287 | d4e8164f | bellard | #define offsetof(type, field) ((size_t) &((type *)0)->field) |
288 | d4e8164f | bellard | #endif
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289 | d4e8164f | bellard | |
290 | d549f7d9 | bellard | #if defined(_WIN32)
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291 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
292 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".section .text\n" |
293 | d549f7d9 | bellard | #elif defined(__APPLE__)
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294 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".data\n" |
295 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".text\n" |
296 | d549f7d9 | bellard | #else
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297 | d549f7d9 | bellard | #define ASM_DATA_SECTION ".section \".data\"\n" |
298 | d549f7d9 | bellard | #define ASM_PREVIOUS_SECTION ".previous\n" |
299 | d549f7d9 | bellard | #endif
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300 | d549f7d9 | bellard | |
301 | 75913b72 | bellard | #define ASM_OP_LABEL_NAME(n, opname) \
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302 | 75913b72 | bellard | ASM_NAME(__op_label) #n "." ASM_NAME(opname) |
303 | 75913b72 | bellard | |
304 | b346ff46 | bellard | #if defined(__powerpc__)
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305 | b346ff46 | bellard | |
306 | 4390df51 | bellard | /* we patch the jump instruction directly */
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307 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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308 | b346ff46 | bellard | do {\
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309 | d549f7d9 | bellard | asm volatile (ASM_DATA_SECTION\ |
310 | 75913b72 | bellard | ASM_OP_LABEL_NAME(n, opname) ":\n"\
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311 | 9257a9e4 | bellard | ".long 1f\n"\
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312 | d549f7d9 | bellard | ASM_PREVIOUS_SECTION \ |
313 | d549f7d9 | bellard | "b " ASM_NAME(__op_jmp) #n "\n"\ |
314 | 9257a9e4 | bellard | "1:\n");\
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315 | 4390df51 | bellard | } while (0) |
316 | 4390df51 | bellard | |
317 | 4390df51 | bellard | #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
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318 | 4390df51 | bellard | |
319 | 4390df51 | bellard | /* we patch the jump instruction directly */
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320 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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321 | c27004ec | bellard | do {\
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322 | c27004ec | bellard | asm volatile (".section .data\n"\ |
323 | 75913b72 | bellard | ASM_OP_LABEL_NAME(n, opname) ":\n"\
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324 | c27004ec | bellard | ".long 1f\n"\
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325 | c27004ec | bellard | ASM_PREVIOUS_SECTION \ |
326 | c27004ec | bellard | "jmp " ASM_NAME(__op_jmp) #n "\n"\ |
327 | c27004ec | bellard | "1:\n");\
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328 | c27004ec | bellard | } while (0) |
329 | c27004ec | bellard | |
330 | b346ff46 | bellard | #else
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331 | b346ff46 | bellard | |
332 | b346ff46 | bellard | /* jump to next block operations (more portable code, does not need
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333 | b346ff46 | bellard | cache flushing, but slower because of indirect jump) */
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334 | ae063a68 | bellard | #define GOTO_TB(opname, tbparam, n)\
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335 | b346ff46 | bellard | do {\
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336 | 2f62b397 | bellard | static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ |
337 | 75913b72 | bellard | static void __attribute__((unused)) *__op_label ## n \ |
338 | 75913b72 | bellard | __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ |
339 | b346ff46 | bellard | goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ |
340 | ae063a68 | bellard | label ## n: ;\ |
341 | ae063a68 | bellard | dummy_label ## n: ;\ |
342 | b346ff46 | bellard | } while (0) |
343 | b346ff46 | bellard | |
344 | ae063a68 | bellard | #endif
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345 | ae063a68 | bellard | |
346 | 33417e70 | bellard | extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; |
347 | 33417e70 | bellard | extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; |
348 | a4193c8a | bellard | extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; |
349 | 33417e70 | bellard | |
350 | d4e8164f | bellard | #ifdef __powerpc__
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351 | d4e8164f | bellard | static inline int testandset (int *p) |
352 | d4e8164f | bellard | { |
353 | d4e8164f | bellard | int ret;
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354 | d4e8164f | bellard | __asm__ __volatile__ ( |
355 | 02e1ec9b | bellard | "0: lwarx %0,0,%1\n"
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356 | 02e1ec9b | bellard | " xor. %0,%3,%0\n"
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357 | 02e1ec9b | bellard | " bne 1f\n"
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358 | 02e1ec9b | bellard | " stwcx. %2,0,%1\n"
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359 | 02e1ec9b | bellard | " bne- 0b\n"
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360 | d4e8164f | bellard | "1: "
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361 | d4e8164f | bellard | : "=&r" (ret)
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362 | d4e8164f | bellard | : "r" (p), "r" (1), "r" (0) |
363 | d4e8164f | bellard | : "cr0", "memory"); |
364 | d4e8164f | bellard | return ret;
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365 | d4e8164f | bellard | } |
366 | d4e8164f | bellard | #endif
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367 | d4e8164f | bellard | |
368 | d4e8164f | bellard | #ifdef __i386__
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369 | d4e8164f | bellard | static inline int testandset (int *p) |
370 | d4e8164f | bellard | { |
371 | 4955a2cd | bellard | long int readval = 0; |
372 | d4e8164f | bellard | |
373 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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374 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
375 | 4955a2cd | bellard | : "r" (1) |
376 | 4955a2cd | bellard | : "cc");
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377 | 4955a2cd | bellard | return readval;
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378 | d4e8164f | bellard | } |
379 | d4e8164f | bellard | #endif
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380 | d4e8164f | bellard | |
381 | bc51c5c9 | bellard | #ifdef __x86_64__
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382 | bc51c5c9 | bellard | static inline int testandset (int *p) |
383 | bc51c5c9 | bellard | { |
384 | 4955a2cd | bellard | long int readval = 0; |
385 | bc51c5c9 | bellard | |
386 | 4955a2cd | bellard | __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
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387 | 4955a2cd | bellard | : "+m" (*p), "+a" (readval) |
388 | 4955a2cd | bellard | : "r" (1) |
389 | 4955a2cd | bellard | : "cc");
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390 | 4955a2cd | bellard | return readval;
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391 | bc51c5c9 | bellard | } |
392 | bc51c5c9 | bellard | #endif
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393 | bc51c5c9 | bellard | |
394 | d4e8164f | bellard | #ifdef __s390__
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395 | d4e8164f | bellard | static inline int testandset (int *p) |
396 | d4e8164f | bellard | { |
397 | d4e8164f | bellard | int ret;
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398 | d4e8164f | bellard | |
399 | d4e8164f | bellard | __asm__ __volatile__ ("0: cs %0,%1,0(%2)\n"
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400 | d4e8164f | bellard | " jl 0b"
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401 | d4e8164f | bellard | : "=&d" (ret)
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402 | d4e8164f | bellard | : "r" (1), "a" (p), "0" (*p) |
403 | d4e8164f | bellard | : "cc", "memory" ); |
404 | d4e8164f | bellard | return ret;
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405 | d4e8164f | bellard | } |
406 | d4e8164f | bellard | #endif
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407 | d4e8164f | bellard | |
408 | d4e8164f | bellard | #ifdef __alpha__
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409 | 2f87c607 | bellard | static inline int testandset (int *p) |
410 | d4e8164f | bellard | { |
411 | d4e8164f | bellard | int ret;
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412 | d4e8164f | bellard | unsigned long one; |
413 | d4e8164f | bellard | |
414 | d4e8164f | bellard | __asm__ __volatile__ ("0: mov 1,%2\n"
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415 | d4e8164f | bellard | " ldl_l %0,%1\n"
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416 | d4e8164f | bellard | " stl_c %2,%1\n"
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417 | d4e8164f | bellard | " beq %2,1f\n"
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418 | d4e8164f | bellard | ".subsection 2\n"
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419 | d4e8164f | bellard | "1: br 0b\n"
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420 | d4e8164f | bellard | ".previous"
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421 | d4e8164f | bellard | : "=r" (ret), "=m" (*p), "=r" (one) |
422 | d4e8164f | bellard | : "m" (*p));
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423 | d4e8164f | bellard | return ret;
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424 | d4e8164f | bellard | } |
425 | d4e8164f | bellard | #endif
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426 | d4e8164f | bellard | |
427 | d4e8164f | bellard | #ifdef __sparc__
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428 | d4e8164f | bellard | static inline int testandset (int *p) |
429 | d4e8164f | bellard | { |
430 | d4e8164f | bellard | int ret;
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431 | d4e8164f | bellard | |
432 | d4e8164f | bellard | __asm__ __volatile__("ldstub [%1], %0"
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433 | d4e8164f | bellard | : "=r" (ret)
|
434 | d4e8164f | bellard | : "r" (p)
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435 | d4e8164f | bellard | : "memory");
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436 | d4e8164f | bellard | |
437 | d4e8164f | bellard | return (ret ? 1 : 0); |
438 | d4e8164f | bellard | } |
439 | d4e8164f | bellard | #endif
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440 | d4e8164f | bellard | |
441 | a95c6790 | bellard | #ifdef __arm__
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442 | a95c6790 | bellard | static inline int testandset (int *spinlock) |
443 | a95c6790 | bellard | { |
444 | a95c6790 | bellard | register unsigned int ret; |
445 | a95c6790 | bellard | __asm__ __volatile__("swp %0, %1, [%2]"
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446 | a95c6790 | bellard | : "=r"(ret)
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447 | a95c6790 | bellard | : "0"(1), "r"(spinlock)); |
448 | a95c6790 | bellard | |
449 | a95c6790 | bellard | return ret;
|
450 | a95c6790 | bellard | } |
451 | a95c6790 | bellard | #endif
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452 | a95c6790 | bellard | |
453 | 38e584a0 | bellard | #ifdef __mc68000
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454 | 38e584a0 | bellard | static inline int testandset (int *p) |
455 | 38e584a0 | bellard | { |
456 | 38e584a0 | bellard | char ret;
|
457 | 38e584a0 | bellard | __asm__ __volatile__("tas %1; sne %0"
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458 | 38e584a0 | bellard | : "=r" (ret)
|
459 | 38e584a0 | bellard | : "m" (p)
|
460 | 38e584a0 | bellard | : "cc","memory"); |
461 | 4955a2cd | bellard | return ret;
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462 | 38e584a0 | bellard | } |
463 | 38e584a0 | bellard | #endif
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464 | 38e584a0 | bellard | |
465 | b8076a74 | bellard | #ifdef __ia64
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466 | b8076a74 | bellard | #include <ia64intrin.h> |
467 | b8076a74 | bellard | |
468 | b8076a74 | bellard | static inline int testandset (int *p) |
469 | b8076a74 | bellard | { |
470 | b8076a74 | bellard | return __sync_lock_test_and_set (p, 1); |
471 | b8076a74 | bellard | } |
472 | b8076a74 | bellard | #endif
|
473 | b8076a74 | bellard | |
474 | d4e8164f | bellard | typedef int spinlock_t; |
475 | d4e8164f | bellard | |
476 | d4e8164f | bellard | #define SPIN_LOCK_UNLOCKED 0 |
477 | d4e8164f | bellard | |
478 | aebcb60e | bellard | #if defined(CONFIG_USER_ONLY)
|
479 | d4e8164f | bellard | static inline void spin_lock(spinlock_t *lock) |
480 | d4e8164f | bellard | { |
481 | d4e8164f | bellard | while (testandset(lock));
|
482 | d4e8164f | bellard | } |
483 | d4e8164f | bellard | |
484 | d4e8164f | bellard | static inline void spin_unlock(spinlock_t *lock) |
485 | d4e8164f | bellard | { |
486 | d4e8164f | bellard | *lock = 0;
|
487 | d4e8164f | bellard | } |
488 | d4e8164f | bellard | |
489 | d4e8164f | bellard | static inline int spin_trylock(spinlock_t *lock) |
490 | d4e8164f | bellard | { |
491 | d4e8164f | bellard | return !testandset(lock);
|
492 | d4e8164f | bellard | } |
493 | 3c1cf9fa | bellard | #else
|
494 | 3c1cf9fa | bellard | static inline void spin_lock(spinlock_t *lock) |
495 | 3c1cf9fa | bellard | { |
496 | 3c1cf9fa | bellard | } |
497 | 3c1cf9fa | bellard | |
498 | 3c1cf9fa | bellard | static inline void spin_unlock(spinlock_t *lock) |
499 | 3c1cf9fa | bellard | { |
500 | 3c1cf9fa | bellard | } |
501 | 3c1cf9fa | bellard | |
502 | 3c1cf9fa | bellard | static inline int spin_trylock(spinlock_t *lock) |
503 | 3c1cf9fa | bellard | { |
504 | 3c1cf9fa | bellard | return 1; |
505 | 3c1cf9fa | bellard | } |
506 | 3c1cf9fa | bellard | #endif
|
507 | d4e8164f | bellard | |
508 | d4e8164f | bellard | extern spinlock_t tb_lock;
|
509 | d4e8164f | bellard | |
510 | 36bdbe54 | bellard | extern int tb_invalidated_flag; |
511 | 6e59c1db | bellard | |
512 | e95c8d51 | bellard | #if !defined(CONFIG_USER_ONLY)
|
513 | 6e59c1db | bellard | |
514 | c27004ec | bellard | void tlb_fill(target_ulong addr, int is_write, int is_user, |
515 | 6e59c1db | bellard | void *retaddr);
|
516 | 6e59c1db | bellard | |
517 | 6e59c1db | bellard | #define ACCESS_TYPE 3 |
518 | 6e59c1db | bellard | #define MEMSUFFIX _code
|
519 | 6e59c1db | bellard | #define env cpu_single_env
|
520 | 6e59c1db | bellard | |
521 | 6e59c1db | bellard | #define DATA_SIZE 1 |
522 | 6e59c1db | bellard | #include "softmmu_header.h" |
523 | 6e59c1db | bellard | |
524 | 6e59c1db | bellard | #define DATA_SIZE 2 |
525 | 6e59c1db | bellard | #include "softmmu_header.h" |
526 | 6e59c1db | bellard | |
527 | 6e59c1db | bellard | #define DATA_SIZE 4 |
528 | 6e59c1db | bellard | #include "softmmu_header.h" |
529 | 6e59c1db | bellard | |
530 | c27004ec | bellard | #define DATA_SIZE 8 |
531 | c27004ec | bellard | #include "softmmu_header.h" |
532 | c27004ec | bellard | |
533 | 6e59c1db | bellard | #undef ACCESS_TYPE
|
534 | 6e59c1db | bellard | #undef MEMSUFFIX
|
535 | 6e59c1db | bellard | #undef env
|
536 | 6e59c1db | bellard | |
537 | 6e59c1db | bellard | #endif
|
538 | 4390df51 | bellard | |
539 | 4390df51 | bellard | #if defined(CONFIG_USER_ONLY)
|
540 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
541 | 4390df51 | bellard | { |
542 | 4390df51 | bellard | return addr;
|
543 | 4390df51 | bellard | } |
544 | 4390df51 | bellard | #else
|
545 | 4390df51 | bellard | /* NOTE: this function can trigger an exception */
|
546 | 1ccde1cb | bellard | /* NOTE2: the returned address is not exactly the physical address: it
|
547 | 1ccde1cb | bellard | is the offset relative to phys_ram_base */
|
548 | 4390df51 | bellard | static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) |
549 | 4390df51 | bellard | { |
550 | c27004ec | bellard | int is_user, index, pd;
|
551 | 4390df51 | bellard | |
552 | 4390df51 | bellard | index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
|
553 | 3f5dcc34 | bellard | #if defined(TARGET_I386)
|
554 | 4390df51 | bellard | is_user = ((env->hflags & HF_CPL_MASK) == 3);
|
555 | 3f5dcc34 | bellard | #elif defined (TARGET_PPC)
|
556 | 3f5dcc34 | bellard | is_user = msr_pr; |
557 | 6af0bf9c | bellard | #elif defined (TARGET_MIPS)
|
558 | 6af0bf9c | bellard | is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM); |
559 | e95c8d51 | bellard | #elif defined (TARGET_SPARC)
|
560 | e95c8d51 | bellard | is_user = (env->psrs == 0);
|
561 | b5ff1b31 | bellard | #elif defined (TARGET_ARM)
|
562 | b5ff1b31 | bellard | is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR); |
563 | 3f5dcc34 | bellard | #else
|
564 | b5ff1b31 | bellard | #error unimplemented CPU
|
565 | 3f5dcc34 | bellard | #endif
|
566 | 84b7b8e7 | bellard | if (__builtin_expect(env->tlb_table[is_user][index].addr_code !=
|
567 | 4390df51 | bellard | (addr & TARGET_PAGE_MASK), 0)) {
|
568 | c27004ec | bellard | ldub_code(addr); |
569 | c27004ec | bellard | } |
570 | 84b7b8e7 | bellard | pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK; |
571 | c27004ec | bellard | if (pd > IO_MEM_ROM) {
|
572 | c27004ec | bellard | cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr);
|
573 | 4390df51 | bellard | } |
574 | 84b7b8e7 | bellard | return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base; |
575 | 4390df51 | bellard | } |
576 | 4390df51 | bellard | #endif
|
577 | 9df217a3 | bellard | |
578 | 9df217a3 | bellard | |
579 | 9df217a3 | bellard | #ifdef USE_KQEMU
|
580 | f32fc648 | bellard | #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) |
581 | f32fc648 | bellard | |
582 | 9df217a3 | bellard | int kqemu_init(CPUState *env);
|
583 | 9df217a3 | bellard | int kqemu_cpu_exec(CPUState *env);
|
584 | 9df217a3 | bellard | void kqemu_flush_page(CPUState *env, target_ulong addr);
|
585 | 9df217a3 | bellard | void kqemu_flush(CPUState *env, int global); |
586 | 4b7df22f | bellard | void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
|
587 | f32fc648 | bellard | void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
|
588 | a332e112 | bellard | void kqemu_cpu_interrupt(CPUState *env);
|
589 | f32fc648 | bellard | void kqemu_record_dump(void); |
590 | 9df217a3 | bellard | |
591 | 9df217a3 | bellard | static inline int kqemu_is_ok(CPUState *env) |
592 | 9df217a3 | bellard | { |
593 | 9df217a3 | bellard | return(env->kqemu_enabled &&
|
594 | 9df217a3 | bellard | (env->cr[0] & CR0_PE_MASK) &&
|
595 | f32fc648 | bellard | !(env->hflags & HF_INHIBIT_IRQ_MASK) && |
596 | 9df217a3 | bellard | (env->eflags & IF_MASK) && |
597 | f32fc648 | bellard | !(env->eflags & VM_MASK) && |
598 | f32fc648 | bellard | (env->kqemu_enabled == 2 ||
|
599 | f32fc648 | bellard | ((env->hflags & HF_CPL_MASK) == 3 &&
|
600 | f32fc648 | bellard | (env->eflags & IOPL_MASK) != IOPL_MASK))); |
601 | 9df217a3 | bellard | } |
602 | 9df217a3 | bellard | |
603 | 9df217a3 | bellard | #endif |