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1 | 79aceca5 | bellard | /*
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2 | 3fc6c082 | bellard | * PowerPC emulation cpu definitions for qemu.
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3 | 79aceca5 | bellard | *
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4 | 3fc6c082 | bellard | * Copyright (c) 2003-2005 Jocelyn Mayer
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5 | 79aceca5 | bellard | *
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6 | 79aceca5 | bellard | * This library is free software; you can redistribute it and/or
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7 | 79aceca5 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 79aceca5 | bellard | * License as published by the Free Software Foundation; either
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9 | 79aceca5 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 79aceca5 | bellard | *
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11 | 79aceca5 | bellard | * This library is distributed in the hope that it will be useful,
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12 | 79aceca5 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 79aceca5 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 79aceca5 | bellard | * Lesser General Public License for more details.
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15 | 79aceca5 | bellard | *
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16 | 79aceca5 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 79aceca5 | bellard | * License along with this library; if not, write to the Free Software
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18 | 79aceca5 | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 79aceca5 | bellard | */
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20 | 79aceca5 | bellard | #if !defined (__CPU_PPC_H__)
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21 | 79aceca5 | bellard | #define __CPU_PPC_H__
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22 | 79aceca5 | bellard | |
23 | 3fc6c082 | bellard | #include "config.h" |
24 | 3fc6c082 | bellard | |
25 | 3cf1e035 | bellard | #define TARGET_LONG_BITS 32 |
26 | 3cf1e035 | bellard | |
27 | 79aceca5 | bellard | #include "cpu-defs.h" |
28 | 79aceca5 | bellard | |
29 | 79aceca5 | bellard | #include <setjmp.h> |
30 | 79aceca5 | bellard | |
31 | 4ecc3190 | bellard | #include "softfloat.h" |
32 | 4ecc3190 | bellard | |
33 | 1fddef4b | bellard | #define TARGET_HAS_ICE 1 |
34 | 1fddef4b | bellard | |
35 | fdabc366 | bellard | /* XXX: this should be tunable: PowerPC 601 & 64 bits PowerPC
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36 | fdabc366 | bellard | * have different cache line sizes
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37 | fdabc366 | bellard | */
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38 | fdabc366 | bellard | #define ICACHE_LINE_SIZE 32 |
39 | fdabc366 | bellard | #define DCACHE_LINE_SIZE 32 |
40 | fdabc366 | bellard | |
41 | fdabc366 | bellard | /* XXX: put this in a common place */
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42 | fdabc366 | bellard | #define likely(x) __builtin_expect(!!(x), 1) |
43 | fdabc366 | bellard | |
44 | 3fc6c082 | bellard | /*****************************************************************************/
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45 | 3fc6c082 | bellard | /* PVR definitions for most known PowerPC */
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46 | 3fc6c082 | bellard | enum {
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47 | 3fc6c082 | bellard | /* PowerPC 401 cores */
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48 | 3fc6c082 | bellard | CPU_PPC_401A1 = 0x00210000,
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49 | 3fc6c082 | bellard | CPU_PPC_401B2 = 0x00220000,
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50 | 3fc6c082 | bellard | CPU_PPC_401C2 = 0x00230000,
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51 | 3fc6c082 | bellard | CPU_PPC_401D2 = 0x00240000,
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52 | 3fc6c082 | bellard | CPU_PPC_401E2 = 0x00250000,
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53 | 3fc6c082 | bellard | CPU_PPC_401F2 = 0x00260000,
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54 | 3fc6c082 | bellard | CPU_PPC_401G2 = 0x00270000,
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55 | 3fc6c082 | bellard | CPU_PPC_IOP480 = 0x40100000,
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56 | 3fc6c082 | bellard | /* PowerPC 403 cores */
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57 | 3fc6c082 | bellard | CPU_PPC_403GA = 0x00200000,
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58 | 3fc6c082 | bellard | CPU_PPC_403GB = 0x00200100,
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59 | 3fc6c082 | bellard | CPU_PPC_403GC = 0x00200200,
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60 | 3fc6c082 | bellard | CPU_PPC_403GCX = 0x00201400,
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61 | 3fc6c082 | bellard | /* PowerPC 405 cores */
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62 | 3fc6c082 | bellard | CPU_PPC_405 = 0x40110000,
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63 | 3fc6c082 | bellard | CPU_PPC_405EP = 0x51210000,
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64 | 3fc6c082 | bellard | CPU_PPC_405GPR = 0x50910000,
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65 | 3fc6c082 | bellard | CPU_PPC_405D2 = 0x20010000,
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66 | 3fc6c082 | bellard | CPU_PPC_405D4 = 0x41810000,
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67 | 3fc6c082 | bellard | CPU_PPC_NPE405H = 0x41410000,
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68 | 3fc6c082 | bellard | CPU_PPC_NPE405L = 0x41610000,
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69 | 3fc6c082 | bellard | #if 0
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70 | 3fc6c082 | bellard | CPU_PPC_STB02 = xxx,
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71 | 3fc6c082 | bellard | #endif
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72 | 3fc6c082 | bellard | CPU_PPC_STB03 = 0x40310000,
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73 | 3fc6c082 | bellard | #if 0
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74 | 3fc6c082 | bellard | CPU_PPC_STB04 = xxx,
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75 | 3fc6c082 | bellard | #endif
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76 | 3fc6c082 | bellard | CPU_PPC_STB25 = 0x51510000,
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77 | 3fc6c082 | bellard | #if 0
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78 | 3fc6c082 | bellard | CPU_PPC_STB130 = xxx,
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79 | 3fc6c082 | bellard | #endif
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80 | 3fc6c082 | bellard | /* PowerPC 440 cores */
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81 | 3fc6c082 | bellard | CPU_PPC_440EP = 0x42220000,
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82 | 3fc6c082 | bellard | CPU_PPC_440GP = 0x40120400,
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83 | 3fc6c082 | bellard | CPU_PPC_440GX = 0x51B20000,
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84 | 3fc6c082 | bellard | /* PowerPC MPC 8xx cores */
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85 | 3fc6c082 | bellard | CPU_PPC_8540 = 0x80200000,
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86 | 3fc6c082 | bellard | CPU_PPC_8xx = 0x00500000,
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87 | 3fc6c082 | bellard | CPU_PPC_8240 = 0x00810100,
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88 | 3fc6c082 | bellard | CPU_PPC_8245 = 0x00811014,
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89 | 3fc6c082 | bellard | /* PowerPC 6xx cores */
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90 | 3fc6c082 | bellard | CPU_PPC_601 = 0x00010000,
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91 | 3fc6c082 | bellard | CPU_PPC_602 = 0x00050000,
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92 | 3fc6c082 | bellard | CPU_PPC_603 = 0x00030000,
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93 | 3fc6c082 | bellard | CPU_PPC_603E = 0x00060000,
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94 | 3fc6c082 | bellard | CPU_PPC_603EV = 0x00070000,
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95 | 3fc6c082 | bellard | CPU_PPC_603R = 0x00071000,
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96 | 3fc6c082 | bellard | CPU_PPC_G2 = 0x80810000,
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97 | 3fc6c082 | bellard | CPU_PPC_G2LE = 0x80820000,
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98 | 3fc6c082 | bellard | CPU_PPC_604 = 0x00040000,
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99 | 3fc6c082 | bellard | CPU_PPC_604E = 0x00090000,
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100 | 3fc6c082 | bellard | CPU_PPC_604R = 0x000a0000,
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101 | 3fc6c082 | bellard | /* PowerPC 74x/75x cores (aka G3) */
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102 | 3fc6c082 | bellard | CPU_PPC_74x = 0x00080000,
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103 | 3fc6c082 | bellard | CPU_PPC_755 = 0x00083000,
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104 | 3fc6c082 | bellard | CPU_PPC_74xP = 0x10080000,
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105 | 3fc6c082 | bellard | CPU_PPC_750CXE22 = 0x00082202,
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106 | 3fc6c082 | bellard | CPU_PPC_750CXE24 = 0x00082214,
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107 | 3fc6c082 | bellard | CPU_PPC_750CXE24b = 0x00083214,
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108 | 3fc6c082 | bellard | CPU_PPC_750CXE31 = 0x00083211,
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109 | 3fc6c082 | bellard | CPU_PPC_750CXE31b = 0x00083311,
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110 | 3fc6c082 | bellard | #define CPU_PPC_750CXE CPU_PPC_750CXE31b
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111 | 3fc6c082 | bellard | CPU_PPC_750FX = 0x70000000,
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112 | 3fc6c082 | bellard | CPU_PPC_750GX = 0x70020000,
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113 | 3fc6c082 | bellard | /* PowerPC 74xx cores (aka G4) */
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114 | 3fc6c082 | bellard | CPU_PPC_7400 = 0x000C0000,
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115 | 3fc6c082 | bellard | CPU_PPC_7410 = 0x800C0000,
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116 | 3fc6c082 | bellard | CPU_PPC_7441 = 0x80000200,
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117 | 3fc6c082 | bellard | CPU_PPC_7450 = 0x80000000,
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118 | 3fc6c082 | bellard | CPU_PPC_7451 = 0x80000203,
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119 | 3fc6c082 | bellard | CPU_PPC_7455 = 0x80010000,
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120 | 3fc6c082 | bellard | CPU_PPC_7457 = 0x80020000,
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121 | 3fc6c082 | bellard | CPU_PPC_7457A = 0x80030000,
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122 | 3fc6c082 | bellard | /* 64 bits PowerPC */
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123 | 3fc6c082 | bellard | CPU_PPC_620 = 0x00140000,
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124 | 3fc6c082 | bellard | CPU_PPC_630 = 0x00400000,
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125 | 3fc6c082 | bellard | CPU_PPC_631 = 0x00410000,
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126 | 3fc6c082 | bellard | CPU_PPC_POWER4 = 0x00350000,
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127 | 3fc6c082 | bellard | CPU_PPC_POWER4P = 0x00380000,
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128 | 3fc6c082 | bellard | CPU_PPC_POWER5 = 0x003A0000,
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129 | 3fc6c082 | bellard | CPU_PPC_POWER5P = 0x003B0000,
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130 | 3fc6c082 | bellard | CPU_PPC_970 = 0x00390000,
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131 | 3fc6c082 | bellard | CPU_PPC_970FX = 0x003C0000,
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132 | 3fc6c082 | bellard | CPU_PPC_RS64 = 0x00330000,
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133 | 3fc6c082 | bellard | CPU_PPC_RS64II = 0x00340000,
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134 | 3fc6c082 | bellard | CPU_PPC_RS64III = 0x00360000,
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135 | 3fc6c082 | bellard | CPU_PPC_RS64IV = 0x00370000,
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136 | 3fc6c082 | bellard | /* Original POWER */
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137 | 3fc6c082 | bellard | /* XXX: should be POWER (RIOS), RSC3308, RSC4608,
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138 | 3fc6c082 | bellard | * POWER2 (RIOS2) & RSC2 (P2SC) here
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139 | 3fc6c082 | bellard | */
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140 | 3fc6c082 | bellard | #if 0
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141 | 3fc6c082 | bellard | CPU_POWER = xxx,
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142 | 3fc6c082 | bellard | #endif
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143 | 3fc6c082 | bellard | #if 0
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144 | 3fc6c082 | bellard | CPU_POWER2 = xxx,
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145 | 3fc6c082 | bellard | #endif
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146 | 3fc6c082 | bellard | }; |
147 | 3fc6c082 | bellard | |
148 | 3fc6c082 | bellard | /* System version register (used on MPC 8xx) */
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149 | 3fc6c082 | bellard | enum {
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150 | 3fc6c082 | bellard | PPC_SVR_8540 = 0x80300000,
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151 | 3fc6c082 | bellard | PPC_SVR_8541E = 0x807A0000,
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152 | 3fc6c082 | bellard | PPC_SVR_8555E = 0x80790000,
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153 | 3fc6c082 | bellard | PPC_SVR_8560 = 0x80700000,
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154 | 3fc6c082 | bellard | }; |
155 | 3fc6c082 | bellard | |
156 | 3fc6c082 | bellard | /*****************************************************************************/
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157 | 9a64fbe4 | bellard | /* Instruction types */
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158 | 9a64fbe4 | bellard | enum {
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159 | 3fc6c082 | bellard | PPC_NONE = 0x00000000,
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160 | 3fc6c082 | bellard | /* integer operations instructions */
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161 | 3fc6c082 | bellard | /* flow control instructions */
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162 | 3fc6c082 | bellard | /* virtual memory instructions */
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163 | 3fc6c082 | bellard | /* ld/st with reservation instructions */
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164 | 3fc6c082 | bellard | /* cache control instructions */
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165 | 3fc6c082 | bellard | /* spr/msr access instructions */
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166 | 3fc6c082 | bellard | PPC_INSNS_BASE = 0x00000001,
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167 | 3fc6c082 | bellard | #define PPC_INTEGER PPC_INSNS_BASE
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168 | 3fc6c082 | bellard | #define PPC_FLOW PPC_INSNS_BASE
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169 | 3fc6c082 | bellard | #define PPC_MEM PPC_INSNS_BASE
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170 | 3fc6c082 | bellard | #define PPC_RES PPC_INSNS_BASE
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171 | 3fc6c082 | bellard | #define PPC_CACHE PPC_INSNS_BASE
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172 | 3fc6c082 | bellard | #define PPC_MISC PPC_INSNS_BASE
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173 | 3fc6c082 | bellard | /* floating point operations instructions */
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174 | 3fc6c082 | bellard | PPC_FLOAT = 0x00000002,
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175 | 3fc6c082 | bellard | /* more floating point operations instructions */
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176 | 3fc6c082 | bellard | PPC_FLOAT_EXT = 0x00000004,
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177 | 3fc6c082 | bellard | /* external control instructions */
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178 | 3fc6c082 | bellard | PPC_EXTERN = 0x00000008,
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179 | 3fc6c082 | bellard | /* segment register access instructions */
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180 | 3fc6c082 | bellard | PPC_SEGMENT = 0x00000010,
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181 | 3fc6c082 | bellard | /* Optional cache control instructions */
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182 | 3fc6c082 | bellard | PPC_CACHE_OPT = 0x00000020,
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183 | 3fc6c082 | bellard | /* Optional floating point op instructions */
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184 | 3fc6c082 | bellard | PPC_FLOAT_OPT = 0x00000040,
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185 | 3fc6c082 | bellard | /* Optional memory control instructions */
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186 | 3fc6c082 | bellard | PPC_MEM_TLBIA = 0x00000080,
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187 | 3fc6c082 | bellard | PPC_MEM_TLBIE = 0x00000100,
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188 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC = 0x00000200,
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189 | 3fc6c082 | bellard | /* eieio & sync */
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190 | 3fc6c082 | bellard | PPC_MEM_SYNC = 0x00000400,
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191 | 3fc6c082 | bellard | /* PowerPC 6xx TLB management instructions */
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192 | 3fc6c082 | bellard | PPC_6xx_TLB = 0x00000800,
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193 | 3fc6c082 | bellard | /* Altivec support */
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194 | 3fc6c082 | bellard | PPC_ALTIVEC = 0x00001000,
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195 | 3fc6c082 | bellard | /* Time base support */
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196 | 3fc6c082 | bellard | PPC_TB = 0x00002000,
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197 | 3fc6c082 | bellard | /* Embedded PowerPC dedicated instructions */
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198 | 3fc6c082 | bellard | PPC_4xx_COMMON = 0x00004000,
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199 | 3fc6c082 | bellard | /* PowerPC 40x exception model */
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200 | 3fc6c082 | bellard | PPC_40x_EXCP = 0x00008000,
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201 | 3fc6c082 | bellard | /* PowerPC 40x specific instructions */
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202 | 3fc6c082 | bellard | PPC_40x_SPEC = 0x00010000,
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203 | 3fc6c082 | bellard | /* PowerPC 405 Mac instructions */
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204 | 3fc6c082 | bellard | PPC_405_MAC = 0x00020000,
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205 | 3fc6c082 | bellard | /* PowerPC 440 specific instructions */
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206 | 3fc6c082 | bellard | PPC_440_SPEC = 0x00040000,
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207 | 3fc6c082 | bellard | /* Specific extensions */
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208 | 3fc6c082 | bellard | /* Power-to-PowerPC bridge (601) */
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209 | 3fc6c082 | bellard | PPC_POWER_BR = 0x00080000,
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210 | 3fc6c082 | bellard | /* PowerPC 602 specific */
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211 | 3fc6c082 | bellard | PPC_602_SPEC = 0x00100000,
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212 | 3fc6c082 | bellard | /* Deprecated instructions */
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213 | 3fc6c082 | bellard | /* Original POWER instruction set */
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214 | 3fc6c082 | bellard | PPC_POWER = 0x00200000,
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215 | 3fc6c082 | bellard | /* POWER2 instruction set extension */
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216 | 3fc6c082 | bellard | PPC_POWER2 = 0x00400000,
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217 | 3fc6c082 | bellard | /* Power RTC support */
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218 | 3fc6c082 | bellard | PPC_POWER_RTC = 0x00800000,
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219 | 3fc6c082 | bellard | /* 64 bits PowerPC instructions */
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220 | 3fc6c082 | bellard | /* 64 bits PowerPC instruction set */
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221 | 3fc6c082 | bellard | PPC_64B = 0x01000000,
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222 | 3fc6c082 | bellard | /* 64 bits hypervisor extensions */
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223 | 3fc6c082 | bellard | PPC_64H = 0x02000000,
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224 | 3fc6c082 | bellard | /* 64 bits PowerPC "bridge" features */
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225 | 3fc6c082 | bellard | PPC_64_BRIDGE = 0x04000000,
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226 | 9a64fbe4 | bellard | }; |
227 | 79aceca5 | bellard | |
228 | 3fc6c082 | bellard | /* CPU run-time flags (MMU and exception model) */
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229 | 3fc6c082 | bellard | enum {
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230 | 3fc6c082 | bellard | /* MMU model */
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231 | 3fc6c082 | bellard | #define PPC_FLAGS_MMU_MASK (0x0000000F) |
232 | 3fc6c082 | bellard | /* Standard 32 bits PowerPC MMU */
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233 | 3fc6c082 | bellard | PPC_FLAGS_MMU_32B = 0x00000000,
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234 | 3fc6c082 | bellard | /* Standard 64 bits PowerPC MMU */
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235 | 3fc6c082 | bellard | PPC_FLAGS_MMU_64B = 0x00000001,
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236 | 3fc6c082 | bellard | /* PowerPC 601 MMU */
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237 | 3fc6c082 | bellard | PPC_FLAGS_MMU_601 = 0x00000002,
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238 | 3fc6c082 | bellard | /* PowerPC 6xx MMU with software TLB */
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239 | 3fc6c082 | bellard | PPC_FLAGS_MMU_SOFT_6xx = 0x00000003,
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240 | 3fc6c082 | bellard | /* PowerPC 4xx MMU with software TLB */
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241 | 3fc6c082 | bellard | PPC_FLAGS_MMU_SOFT_4xx = 0x00000004,
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242 | 3fc6c082 | bellard | /* PowerPC 403 MMU */
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243 | 3fc6c082 | bellard | PPC_FLAGS_MMU_403 = 0x00000005,
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244 | 3fc6c082 | bellard | /* Exception model */
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245 | 3fc6c082 | bellard | #define PPC_FLAGS_EXCP_MASK (0x000000F0) |
246 | 3fc6c082 | bellard | /* Standard PowerPC exception model */
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247 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_STD = 0x00000000,
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248 | 3fc6c082 | bellard | /* PowerPC 40x exception model */
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249 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_40x = 0x00000010,
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250 | 3fc6c082 | bellard | /* PowerPC 601 exception model */
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251 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_601 = 0x00000020,
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252 | 3fc6c082 | bellard | /* PowerPC 602 exception model */
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253 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_602 = 0x00000030,
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254 | 3fc6c082 | bellard | /* PowerPC 603 exception model */
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255 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_603 = 0x00000040,
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256 | 3fc6c082 | bellard | /* PowerPC 604 exception model */
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257 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_604 = 0x00000050,
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258 | 3fc6c082 | bellard | /* PowerPC 7x0 exception model */
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259 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_7x0 = 0x00000060,
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260 | 3fc6c082 | bellard | /* PowerPC 7x5 exception model */
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261 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_7x5 = 0x00000070,
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262 | 3fc6c082 | bellard | /* PowerPC 74xx exception model */
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263 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_74xx = 0x00000080,
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264 | 3fc6c082 | bellard | /* PowerPC 970 exception model */
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265 | 3fc6c082 | bellard | PPC_FLAGS_EXCP_970 = 0x00000090,
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266 | 3fc6c082 | bellard | }; |
267 | 3fc6c082 | bellard | |
268 | 3fc6c082 | bellard | #define PPC_MMU(env) (env->flags & PPC_FLAGS_MMU_MASK)
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269 | 3fc6c082 | bellard | #define PPC_EXCP(env) (env->flags & PPC_FLAGS_EXCP_MASK)
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270 | 3fc6c082 | bellard | |
271 | 3fc6c082 | bellard | /*****************************************************************************/
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272 | 3fc6c082 | bellard | /* Supported instruction set definitions */
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273 | 3fc6c082 | bellard | /* This generates an empty opcode table... */
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274 | 3fc6c082 | bellard | #define PPC_INSNS_TODO (PPC_NONE)
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275 | 3fc6c082 | bellard | #define PPC_FLAGS_TODO (0x00000000) |
276 | 3fc6c082 | bellard | |
277 | 3fc6c082 | bellard | /* PowerPC 40x instruction set */
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278 | 3fc6c082 | bellard | #define PPC_INSNS_4xx (PPC_INSNS_BASE | PPC_MEM_TLBSYNC | PPC_4xx_COMMON)
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279 | 3fc6c082 | bellard | /* PowerPC 401 */
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280 | 3fc6c082 | bellard | #define PPC_INSNS_401 (PPC_INSNS_TODO)
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281 | 3fc6c082 | bellard | #define PPC_FLAGS_401 (PPC_FLAGS_TODO)
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282 | 3fc6c082 | bellard | /* PowerPC 403 */
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283 | 3fc6c082 | bellard | #define PPC_INSNS_403 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_MEM_TLBIA | \
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284 | 3fc6c082 | bellard | PPC_40x_EXCP | PPC_40x_SPEC) |
285 | 3fc6c082 | bellard | #define PPC_FLAGS_403 (PPC_FLAGS_MMU_403 | PPC_FLAGS_EXCP_40x)
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286 | 3fc6c082 | bellard | /* PowerPC 405 */
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287 | 3fc6c082 | bellard | #define PPC_INSNS_405 (PPC_INSNS_4xx | PPC_MEM_SYNC | PPC_CACHE_OPT | \
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288 | 3fc6c082 | bellard | PPC_MEM_TLBIA | PPC_TB | PPC_40x_SPEC | PPC_40x_EXCP | \ |
289 | 3fc6c082 | bellard | PPC_405_MAC) |
290 | 3fc6c082 | bellard | #define PPC_FLAGS_405 (PPC_FLAGS_MMU_SOFT_4xx | PPC_FLAGS_EXCP_40x)
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291 | 3fc6c082 | bellard | /* PowerPC 440 */
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292 | 3fc6c082 | bellard | #define PPC_INSNS_440 (PPC_INSNS_4xx | PPC_CACHE_OPT | PPC_405_MAC | \
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293 | 3fc6c082 | bellard | PPC_440_SPEC) |
294 | 3fc6c082 | bellard | #define PPC_FLAGS_440 (PPC_FLAGS_TODO)
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295 | 3fc6c082 | bellard | /* Non-embedded PowerPC */
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296 | 3fc6c082 | bellard | #define PPC_INSNS_COMMON (PPC_INSNS_BASE | PPC_FLOAT | PPC_MEM_SYNC | \
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297 | 3fc6c082 | bellard | PPC_SEGMENT | PPC_MEM_TLBIE) |
298 | 3fc6c082 | bellard | /* PowerPC 601 */
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299 | 3fc6c082 | bellard | #define PPC_INSNS_601 (PPC_INSNS_COMMON | PPC_EXTERN | PPC_POWER_BR)
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300 | 3fc6c082 | bellard | #define PPC_FLAGS_601 (PPC_FLAGS_MMU_601 | PPC_FLAGS_EXCP_601)
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301 | 3fc6c082 | bellard | /* PowerPC 602 */
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302 | 3fc6c082 | bellard | #define PPC_INSNS_602 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
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303 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_TB) |
304 | 3fc6c082 | bellard | #define PPC_FLAGS_602 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_602)
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305 | 3fc6c082 | bellard | /* PowerPC 603 */
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306 | 3fc6c082 | bellard | #define PPC_INSNS_603 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
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307 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) |
308 | 3fc6c082 | bellard | #define PPC_FLAGS_603 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
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309 | 3fc6c082 | bellard | /* PowerPC G2 */
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310 | 3fc6c082 | bellard | #define PPC_INSNS_G2 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_6xx_TLB | \
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311 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_EXTERN | PPC_TB) |
312 | 3fc6c082 | bellard | #define PPC_FLAGS_G2 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_603)
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313 | 3fc6c082 | bellard | /* PowerPC 604 */
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314 | 3fc6c082 | bellard | #define PPC_INSNS_604 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
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315 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_TB) |
316 | 3fc6c082 | bellard | #define PPC_FLAGS_604 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_604)
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317 | 3fc6c082 | bellard | /* PowerPC 740/750 (aka G3) */
|
318 | 3fc6c082 | bellard | #define PPC_INSNS_7x0 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
|
319 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_TB) |
320 | 3fc6c082 | bellard | #define PPC_FLAGS_7x0 (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_7x0)
|
321 | 3fc6c082 | bellard | /* PowerPC 745/755 */
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322 | 3fc6c082 | bellard | #define PPC_INSNS_7x5 (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_EXTERN | \
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323 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_TB | PPC_6xx_TLB) |
324 | 3fc6c082 | bellard | #define PPC_FLAGS_7x5 (PPC_FLAGS_MMU_SOFT_6xx | PPC_FLAGS_EXCP_7x5)
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325 | 3fc6c082 | bellard | /* PowerPC 74xx (aka G4) */
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326 | 3fc6c082 | bellard | #define PPC_INSNS_74xx (PPC_INSNS_COMMON | PPC_FLOAT_EXT | PPC_ALTIVEC | \
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327 | 3fc6c082 | bellard | PPC_MEM_TLBSYNC | PPC_TB) |
328 | 3fc6c082 | bellard | #define PPC_FLAGS_74xx (PPC_FLAGS_MMU_32B | PPC_FLAGS_EXCP_74xx)
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329 | 3fc6c082 | bellard | |
330 | 3fc6c082 | bellard | /* Default PowerPC will be 604/970 */
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331 | 3fc6c082 | bellard | #define PPC_INSNS_PPC32 PPC_INSNS_604
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332 | 3fc6c082 | bellard | #define PPC_FLAGS_PPC32 PPC_FLAGS_604
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333 | 3fc6c082 | bellard | #if 0
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334 | 3fc6c082 | bellard | #define PPC_INSNS_PPC64 PPC_INSNS_970
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335 | 3fc6c082 | bellard | #define PPC_FLAGS_PPC64 PPC_FLAGS_970
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336 | 3fc6c082 | bellard | #endif
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337 | 3fc6c082 | bellard | #define PPC_INSNS_DEFAULT PPC_INSNS_604
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338 | 3fc6c082 | bellard | #define PPC_FLAGS_DEFAULT PPC_FLAGS_604
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339 | 3fc6c082 | bellard | typedef struct ppc_def_t ppc_def_t; |
340 | 79aceca5 | bellard | |
341 | 3fc6c082 | bellard | /*****************************************************************************/
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342 | 3fc6c082 | bellard | /* Types used to describe some PowerPC registers */
|
343 | 3fc6c082 | bellard | typedef struct CPUPPCState CPUPPCState; |
344 | 3fc6c082 | bellard | typedef struct opc_handler_t opc_handler_t; |
345 | 9fddaa0c | bellard | typedef struct ppc_tb_t ppc_tb_t; |
346 | 3fc6c082 | bellard | typedef struct ppc_spr_t ppc_spr_t; |
347 | 3fc6c082 | bellard | typedef struct ppc_dcr_t ppc_dcr_t; |
348 | 3fc6c082 | bellard | typedef struct ppc_avr_t ppc_avr_t; |
349 | 3fc6c082 | bellard | |
350 | 3fc6c082 | bellard | /* SPR access micro-ops generations callbacks */
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351 | 3fc6c082 | bellard | struct ppc_spr_t {
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352 | 3fc6c082 | bellard | void (*uea_read)(void *opaque, int spr_num); |
353 | 3fc6c082 | bellard | void (*uea_write)(void *opaque, int spr_num); |
354 | 3fc6c082 | bellard | void (*oea_read)(void *opaque, int spr_num); |
355 | 3fc6c082 | bellard | void (*oea_write)(void *opaque, int spr_num); |
356 | 3fc6c082 | bellard | const unsigned char *name; |
357 | 3fc6c082 | bellard | }; |
358 | 3fc6c082 | bellard | |
359 | 3fc6c082 | bellard | /* Altivec registers (128 bits) */
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360 | 3fc6c082 | bellard | struct ppc_avr_t {
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361 | 3fc6c082 | bellard | uint32_t u[4];
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362 | 3fc6c082 | bellard | }; |
363 | 9fddaa0c | bellard | |
364 | 3fc6c082 | bellard | /* Software TLB cache */
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365 | 3fc6c082 | bellard | typedef struct ppc_tlb_t ppc_tlb_t; |
366 | 3fc6c082 | bellard | struct ppc_tlb_t {
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367 | 3fc6c082 | bellard | /* Physical page number */
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368 | 3fc6c082 | bellard | target_phys_addr_t RPN; |
369 | 3fc6c082 | bellard | /* Virtual page number */
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370 | 3fc6c082 | bellard | target_ulong VPN; |
371 | 3fc6c082 | bellard | /* Page size */
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372 | 3fc6c082 | bellard | target_ulong size; |
373 | 3fc6c082 | bellard | /* Protection bits */
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374 | 3fc6c082 | bellard | int prot;
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375 | 3fc6c082 | bellard | int is_user;
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376 | 3fc6c082 | bellard | uint32_t private; |
377 | 3fc6c082 | bellard | uint32_t flags; |
378 | 3fc6c082 | bellard | }; |
379 | 3fc6c082 | bellard | |
380 | 3fc6c082 | bellard | /*****************************************************************************/
|
381 | 3fc6c082 | bellard | /* Machine state register bits definition */
|
382 | 3fc6c082 | bellard | #define MSR_SF 63 /* Sixty-four-bit mode */ |
383 | 3fc6c082 | bellard | #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
384 | 3fc6c082 | bellard | #define MSR_HV 60 /* hypervisor state */ |
385 | 3fc6c082 | bellard | #define MSR_VR 25 /* altivec available */ |
386 | 3fc6c082 | bellard | #define MSR_AP 23 /* Access privilege state on 602 */ |
387 | 3fc6c082 | bellard | #define MSR_SA 22 /* Supervisor access mode on 602 */ |
388 | 3fc6c082 | bellard | #define MSR_KEY 19 /* key bit on 603e */ |
389 | 3fc6c082 | bellard | #define MSR_POW 18 /* Power management */ |
390 | 3fc6c082 | bellard | #define MSR_WE 18 /* Wait state enable on embedded PowerPC */ |
391 | 3fc6c082 | bellard | #define MSR_TGPR 17 /* TGPR usage on 602/603 */ |
392 | 3fc6c082 | bellard | #define MSR_TLB 17 /* TLB on ? */ |
393 | 3fc6c082 | bellard | #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC */ |
394 | 3fc6c082 | bellard | #define MSR_ILE 16 /* Interrupt little-endian mode */ |
395 | 3fc6c082 | bellard | #define MSR_EE 15 /* External interrupt enable */ |
396 | 3fc6c082 | bellard | #define MSR_PR 14 /* Problem state */ |
397 | 3fc6c082 | bellard | #define MSR_FP 13 /* Floating point available */ |
398 | 3fc6c082 | bellard | #define MSR_ME 12 /* Machine check interrupt enable */ |
399 | 3fc6c082 | bellard | #define MSR_FE0 11 /* Floating point exception mode 0 */ |
400 | 3fc6c082 | bellard | #define MSR_SE 10 /* Single-step trace enable */ |
401 | 3fc6c082 | bellard | #define MSR_DWE 10 /* Debug wait enable on 405 */ |
402 | 3fc6c082 | bellard | #define MSR_BE 9 /* Branch trace enable */ |
403 | 3fc6c082 | bellard | #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC */ |
404 | 3fc6c082 | bellard | #define MSR_FE1 8 /* Floating point exception mode 1 */ |
405 | 3fc6c082 | bellard | #define MSR_AL 7 /* AL bit on POWER */ |
406 | 3fc6c082 | bellard | #define MSR_IP 6 /* Interrupt prefix */ |
407 | 3fc6c082 | bellard | #define MSR_IR 5 /* Instruction relocate */ |
408 | 3fc6c082 | bellard | #define MSR_IS 5 /* Instruction address space on embedded PowerPC */ |
409 | 3fc6c082 | bellard | #define MSR_DR 4 /* Data relocate */ |
410 | 3fc6c082 | bellard | #define MSR_DS 4 /* Data address space on embedded PowerPC */ |
411 | 3fc6c082 | bellard | #define MSR_PE 3 /* Protection enable on 403 */ |
412 | 3fc6c082 | bellard | #define MSR_EP 3 /* Exception prefix on 601 */ |
413 | 3fc6c082 | bellard | #define MSR_PX 2 /* Protection exclusive on 403 */ |
414 | 3fc6c082 | bellard | #define MSR_PMM 2 /* Performance monitor mark on POWER */ |
415 | 3fc6c082 | bellard | #define MSR_RI 1 /* Recoverable interrupt */ |
416 | 3fc6c082 | bellard | #define MSR_LE 0 /* Little-endian mode */ |
417 | 3fc6c082 | bellard | #define msr_sf env->msr[MSR_SF]
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418 | 3fc6c082 | bellard | #define msr_isf env->msr[MSR_ISF]
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419 | 3fc6c082 | bellard | #define msr_hv env->msr[MSR_HV]
|
420 | 3fc6c082 | bellard | #define msr_vr env->msr[MSR_VR]
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421 | 3fc6c082 | bellard | #define msr_ap env->msr[MSR_AP]
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422 | 3fc6c082 | bellard | #define msr_sa env->msr[MSR_SA]
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423 | 3fc6c082 | bellard | #define msr_key env->msr[MSR_KEY]
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424 | 79aceca5 | bellard | #define msr_pow env->msr[MSR_POW]
|
425 | 3fc6c082 | bellard | #define msr_we env->msr[MSR_WE]
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426 | 3fc6c082 | bellard | #define msr_tgpr env->msr[MSR_TGPR]
|
427 | 3fc6c082 | bellard | #define msr_tlb env->msr[MSR_TLB]
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428 | 3fc6c082 | bellard | #define msr_ce env->msr[MSR_CE]
|
429 | 79aceca5 | bellard | #define msr_ile env->msr[MSR_ILE]
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430 | 79aceca5 | bellard | #define msr_ee env->msr[MSR_EE]
|
431 | 79aceca5 | bellard | #define msr_pr env->msr[MSR_PR]
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432 | 79aceca5 | bellard | #define msr_fp env->msr[MSR_FP]
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433 | 79aceca5 | bellard | #define msr_me env->msr[MSR_ME]
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434 | 79aceca5 | bellard | #define msr_fe0 env->msr[MSR_FE0]
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435 | 79aceca5 | bellard | #define msr_se env->msr[MSR_SE]
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436 | 3fc6c082 | bellard | #define msr_dwe env->msr[MSR_DWE]
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437 | 79aceca5 | bellard | #define msr_be env->msr[MSR_BE]
|
438 | 3fc6c082 | bellard | #define msr_de env->msr[MSR_DE]
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439 | 79aceca5 | bellard | #define msr_fe1 env->msr[MSR_FE1]
|
440 | 3fc6c082 | bellard | #define msr_al env->msr[MSR_AL]
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441 | 79aceca5 | bellard | #define msr_ip env->msr[MSR_IP]
|
442 | 79aceca5 | bellard | #define msr_ir env->msr[MSR_IR]
|
443 | 3fc6c082 | bellard | #define msr_is env->msr[MSR_IS]
|
444 | 79aceca5 | bellard | #define msr_dr env->msr[MSR_DR]
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445 | 3fc6c082 | bellard | #define msr_ds env->msr[MSR_DS]
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446 | 3fc6c082 | bellard | #define msr_pe env->msr[MSR_PE]
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447 | 3fc6c082 | bellard | #define msr_ep env->msr[MSR_EP]
|
448 | 3fc6c082 | bellard | #define msr_px env->msr[MSR_PX]
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449 | 3fc6c082 | bellard | #define msr_pmm env->msr[MSR_PMM]
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450 | 79aceca5 | bellard | #define msr_ri env->msr[MSR_RI]
|
451 | 79aceca5 | bellard | #define msr_le env->msr[MSR_LE]
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452 | 79aceca5 | bellard | |
453 | 3fc6c082 | bellard | /*****************************************************************************/
|
454 | 3fc6c082 | bellard | /* The whole PowerPC CPU context */
|
455 | 3fc6c082 | bellard | struct CPUPPCState {
|
456 | 3fc6c082 | bellard | /* First are the most commonly used resources
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457 | 3fc6c082 | bellard | * during translated code execution
|
458 | 3fc6c082 | bellard | */
|
459 | 3fc6c082 | bellard | #if TARGET_LONG_BITS > HOST_LONG_BITS
|
460 | 3fc6c082 | bellard | /* temporary fixed-point registers
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461 | 3fc6c082 | bellard | * used to emulate 64 bits target on 32 bits hosts
|
462 | 3fc6c082 | bellard | */
|
463 | 3fc6c082 | bellard | target_ulong t0, t1, t2; |
464 | 3fc6c082 | bellard | #endif
|
465 | 79aceca5 | bellard | /* general purpose registers */
|
466 | 3fc6c082 | bellard | target_ulong gpr[32];
|
467 | 3fc6c082 | bellard | /* LR */
|
468 | 3fc6c082 | bellard | target_ulong lr; |
469 | 3fc6c082 | bellard | /* CTR */
|
470 | 3fc6c082 | bellard | target_ulong ctr; |
471 | 3fc6c082 | bellard | /* condition register */
|
472 | 3fc6c082 | bellard | uint8_t crf[8];
|
473 | 79aceca5 | bellard | /* XER */
|
474 | 3fc6c082 | bellard | /* XXX: We use only 5 fields, but we want to keep the structure aligned */
|
475 | 3fc6c082 | bellard | uint8_t xer[8];
|
476 | 79aceca5 | bellard | /* Reservation address */
|
477 | 3fc6c082 | bellard | target_ulong reserve; |
478 | 3fc6c082 | bellard | |
479 | 3fc6c082 | bellard | /* Those ones are used in supervisor mode only */
|
480 | 79aceca5 | bellard | /* machine state register */
|
481 | 3fc6c082 | bellard | uint8_t msr[64];
|
482 | 3fc6c082 | bellard | /* temporary general purpose registers */
|
483 | 3fc6c082 | bellard | target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */ |
484 | 3fc6c082 | bellard | |
485 | 3fc6c082 | bellard | /* Floating point execution context */
|
486 | fb0eaffc | bellard | /* temporary float registers */
|
487 | 4ecc3190 | bellard | float64 ft0; |
488 | 4ecc3190 | bellard | float64 ft1; |
489 | 4ecc3190 | bellard | float64 ft2; |
490 | 4ecc3190 | bellard | float_status fp_status; |
491 | 3fc6c082 | bellard | /* floating point registers */
|
492 | 3fc6c082 | bellard | float64 fpr[32];
|
493 | 3fc6c082 | bellard | /* floating point status and control register */
|
494 | 3fc6c082 | bellard | uint8_t fpscr[8];
|
495 | 4ecc3190 | bellard | |
496 | a316d335 | bellard | CPU_COMMON |
497 | a316d335 | bellard | |
498 | 50443c98 | bellard | int halted; /* TRUE if the CPU is in suspend state */ |
499 | 50443c98 | bellard | |
500 | ac9eb073 | bellard | int access_type; /* when a memory exception occurs, the access |
501 | ac9eb073 | bellard | type is stored here */
|
502 | a541f297 | bellard | |
503 | 3fc6c082 | bellard | /* MMU context */
|
504 | 3fc6c082 | bellard | /* Address space register */
|
505 | 3fc6c082 | bellard | target_ulong asr; |
506 | 3fc6c082 | bellard | /* segment registers */
|
507 | 3fc6c082 | bellard | target_ulong sdr1; |
508 | 3fc6c082 | bellard | target_ulong sr[16];
|
509 | 3fc6c082 | bellard | /* BATs */
|
510 | 3fc6c082 | bellard | int nb_BATs;
|
511 | 3fc6c082 | bellard | target_ulong DBAT[2][8]; |
512 | 3fc6c082 | bellard | target_ulong IBAT[2][8]; |
513 | 9fddaa0c | bellard | |
514 | 3fc6c082 | bellard | /* Other registers */
|
515 | 3fc6c082 | bellard | /* Special purpose registers */
|
516 | 3fc6c082 | bellard | target_ulong spr[1024];
|
517 | 3fc6c082 | bellard | /* Altivec registers */
|
518 | 3fc6c082 | bellard | ppc_avr_t avr[32];
|
519 | 3fc6c082 | bellard | uint32_t vscr; |
520 | 3fc6c082 | bellard | |
521 | 3fc6c082 | bellard | /* Internal devices resources */
|
522 | 9fddaa0c | bellard | /* Time base and decrementer */
|
523 | 9fddaa0c | bellard | ppc_tb_t *tb_env; |
524 | 3fc6c082 | bellard | /* Device control registers */
|
525 | 3fc6c082 | bellard | int (*dcr_read)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong *val); |
526 | 3fc6c082 | bellard | int (*dcr_write)(ppc_dcr_t *dcr_env, int dcr_num, target_ulong val); |
527 | 3fc6c082 | bellard | ppc_dcr_t *dcr_env; |
528 | 3fc6c082 | bellard | |
529 | 3fc6c082 | bellard | /* PowerPC TLB registers (for 4xx and 60x software driven TLBs) */
|
530 | 3fc6c082 | bellard | int nb_tlb;
|
531 | 3fc6c082 | bellard | int nb_ways, last_way;
|
532 | 3fc6c082 | bellard | ppc_tlb_t tlb[128];
|
533 | 3fc6c082 | bellard | /* Callbacks for specific checks on some implementations */
|
534 | 3fc6c082 | bellard | int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot, |
535 | 3fc6c082 | bellard | target_ulong vaddr, int rw, int acc_type, |
536 | 3fc6c082 | bellard | int is_user);
|
537 | 3fc6c082 | bellard | /* 403 dedicated access protection registers */
|
538 | 3fc6c082 | bellard | target_ulong pb[4];
|
539 | 3fc6c082 | bellard | |
540 | 3fc6c082 | bellard | /* Those resources are used during exception processing */
|
541 | 3fc6c082 | bellard | /* CPU model definition */
|
542 | 3fc6c082 | bellard | uint64_t msr_mask; |
543 | 3fc6c082 | bellard | uint32_t flags; |
544 | 3fc6c082 | bellard | |
545 | 3fc6c082 | bellard | int exception_index;
|
546 | 3fc6c082 | bellard | int error_code;
|
547 | 3fc6c082 | bellard | int interrupt_request;
|
548 | 3fc6c082 | bellard | |
549 | 3fc6c082 | bellard | /* Those resources are used only during code translation */
|
550 | 3fc6c082 | bellard | /* Next instruction pointer */
|
551 | 3fc6c082 | bellard | target_ulong nip; |
552 | 3fc6c082 | bellard | /* SPR translation callbacks */
|
553 | 3fc6c082 | bellard | ppc_spr_t spr_cb[1024];
|
554 | 3fc6c082 | bellard | /* opcode handlers */
|
555 | 3fc6c082 | bellard | opc_handler_t *opcodes[0x40];
|
556 | 3fc6c082 | bellard | |
557 | 3fc6c082 | bellard | /* Those resources are used only in Qemu core */
|
558 | 3fc6c082 | bellard | jmp_buf jmp_env; |
559 | 3fc6c082 | bellard | int user_mode_only; /* user mode only simulation */ |
560 | 3fc6c082 | bellard | uint32_t hflags; |
561 | 3fc6c082 | bellard | |
562 | 9fddaa0c | bellard | /* Power management */
|
563 | 9fddaa0c | bellard | int power_mode;
|
564 | a541f297 | bellard | |
565 | 6d506e6d | bellard | /* temporary hack to handle OSI calls (only used if non NULL) */
|
566 | 6d506e6d | bellard | int (*osi_call)(struct CPUPPCState *env); |
567 | 3fc6c082 | bellard | }; |
568 | 79aceca5 | bellard | |
569 | 3fc6c082 | bellard | /*****************************************************************************/
|
570 | 79aceca5 | bellard | CPUPPCState *cpu_ppc_init(void);
|
571 | 79aceca5 | bellard | int cpu_ppc_exec(CPUPPCState *s);
|
572 | 79aceca5 | bellard | void cpu_ppc_close(CPUPPCState *s);
|
573 | 79aceca5 | bellard | /* you can call this signal handler from your SIGBUS and SIGSEGV
|
574 | 79aceca5 | bellard | signal handlers to inform the virtual CPU of exceptions. non zero
|
575 | 79aceca5 | bellard | is returned if the signal was handled by the virtual CPU. */
|
576 | 79aceca5 | bellard | struct siginfo;
|
577 | 79aceca5 | bellard | int cpu_ppc_signal_handler(int host_signum, struct siginfo *info, |
578 | 79aceca5 | bellard | void *puc);
|
579 | 79aceca5 | bellard | |
580 | a541f297 | bellard | void do_interrupt (CPUPPCState *env);
|
581 | 9a64fbe4 | bellard | void cpu_loop_exit(void); |
582 | a541f297 | bellard | |
583 | 9a64fbe4 | bellard | void dump_stack (CPUPPCState *env);
|
584 | a541f297 | bellard | |
585 | 3fc6c082 | bellard | target_ulong do_load_ibatu (CPUPPCState *env, int nr);
|
586 | 3fc6c082 | bellard | target_ulong do_load_ibatl (CPUPPCState *env, int nr);
|
587 | 3fc6c082 | bellard | void do_store_ibatu (CPUPPCState *env, int nr, target_ulong value); |
588 | 3fc6c082 | bellard | void do_store_ibatl (CPUPPCState *env, int nr, target_ulong value); |
589 | 3fc6c082 | bellard | target_ulong do_load_dbatu (CPUPPCState *env, int nr);
|
590 | 3fc6c082 | bellard | target_ulong do_load_dbatl (CPUPPCState *env, int nr);
|
591 | 3fc6c082 | bellard | void do_store_dbatu (CPUPPCState *env, int nr, target_ulong value); |
592 | 3fc6c082 | bellard | void do_store_dbatl (CPUPPCState *env, int nr, target_ulong value); |
593 | 3fc6c082 | bellard | |
594 | 3fc6c082 | bellard | target_ulong do_load_nip (CPUPPCState *env); |
595 | 3fc6c082 | bellard | void do_store_nip (CPUPPCState *env, target_ulong value);
|
596 | 3fc6c082 | bellard | target_ulong do_load_sdr1 (CPUPPCState *env); |
597 | 3fc6c082 | bellard | void do_store_sdr1 (CPUPPCState *env, target_ulong value);
|
598 | 3fc6c082 | bellard | target_ulong do_load_asr (CPUPPCState *env); |
599 | 3fc6c082 | bellard | void do_store_asr (CPUPPCState *env, target_ulong value);
|
600 | 3fc6c082 | bellard | target_ulong do_load_sr (CPUPPCState *env, int srnum);
|
601 | 3fc6c082 | bellard | void do_store_sr (CPUPPCState *env, int srnum, target_ulong value); |
602 | 3fc6c082 | bellard | uint32_t do_load_cr (CPUPPCState *env); |
603 | 3fc6c082 | bellard | void do_store_cr (CPUPPCState *env, uint32_t value, uint32_t mask);
|
604 | 3fc6c082 | bellard | uint32_t do_load_xer (CPUPPCState *env); |
605 | 3fc6c082 | bellard | void do_store_xer (CPUPPCState *env, uint32_t value);
|
606 | 3fc6c082 | bellard | target_ulong do_load_msr (CPUPPCState *env); |
607 | 3fc6c082 | bellard | void do_store_msr (CPUPPCState *env, target_ulong value);
|
608 | 3fc6c082 | bellard | float64 do_load_fpscr (CPUPPCState *env); |
609 | 3fc6c082 | bellard | void do_store_fpscr (CPUPPCState *env, float64 f, uint32_t mask);
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610 | 3fc6c082 | bellard | |
611 | 3fc6c082 | bellard | void do_compute_hflags (CPUPPCState *env);
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612 | a541f297 | bellard | |
613 | 3fc6c082 | bellard | int ppc_find_by_name (const unsigned char *name, ppc_def_t **def); |
614 | 3fc6c082 | bellard | int ppc_find_by_pvr (uint32_t apvr, ppc_def_t **def);
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615 | 3fc6c082 | bellard | void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
616 | 3fc6c082 | bellard | int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def);
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617 | 85c4adf6 | bellard | |
618 | 9fddaa0c | bellard | /* Time-base and decrementer management */
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619 | 9fddaa0c | bellard | #ifndef NO_CPU_IO_DEFS
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620 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbl (CPUPPCState *env); |
621 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_tbu (CPUPPCState *env); |
622 | 9fddaa0c | bellard | void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
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623 | 9fddaa0c | bellard | void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
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624 | 9fddaa0c | bellard | uint32_t cpu_ppc_load_decr (CPUPPCState *env); |
625 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
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626 | 9fddaa0c | bellard | #endif
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627 | 79aceca5 | bellard | |
628 | 79aceca5 | bellard | #define TARGET_PAGE_BITS 12 |
629 | 79aceca5 | bellard | #include "cpu-all.h" |
630 | 79aceca5 | bellard | |
631 | 3fc6c082 | bellard | /*****************************************************************************/
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632 | 3fc6c082 | bellard | /* Registers definitions */
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633 | 79aceca5 | bellard | #define ugpr(n) (env->gpr[n])
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634 | 79aceca5 | bellard | |
635 | 79aceca5 | bellard | #define XER_SO 31 |
636 | 79aceca5 | bellard | #define XER_OV 30 |
637 | 79aceca5 | bellard | #define XER_CA 29 |
638 | 3fc6c082 | bellard | #define XER_CMP 8 |
639 | 79aceca5 | bellard | #define XER_BC 0 |
640 | 3fc6c082 | bellard | #define xer_so env->xer[4] |
641 | 3fc6c082 | bellard | #define xer_ov env->xer[6] |
642 | 3fc6c082 | bellard | #define xer_ca env->xer[2] |
643 | 3fc6c082 | bellard | #define xer_cmp env->xer[1] |
644 | 9a64fbe4 | bellard | #define xer_bc env->xer[0] |
645 | 79aceca5 | bellard | |
646 | 3fc6c082 | bellard | /* SPR definitions */
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647 | 3fc6c082 | bellard | #define SPR_MQ (0x000) |
648 | 3fc6c082 | bellard | #define SPR_XER (0x001) |
649 | 3fc6c082 | bellard | #define SPR_601_VRTCU (0x004) |
650 | 3fc6c082 | bellard | #define SPR_601_VRTCL (0x005) |
651 | 3fc6c082 | bellard | #define SPR_601_UDECR (0x006) |
652 | 3fc6c082 | bellard | #define SPR_LR (0x008) |
653 | 3fc6c082 | bellard | #define SPR_CTR (0x009) |
654 | 3fc6c082 | bellard | #define SPR_DSISR (0x012) |
655 | 3fc6c082 | bellard | #define SPR_DAR (0x013) |
656 | 3fc6c082 | bellard | #define SPR_601_RTCU (0x014) |
657 | 3fc6c082 | bellard | #define SPR_601_RTCL (0x015) |
658 | 3fc6c082 | bellard | #define SPR_DECR (0x016) |
659 | 3fc6c082 | bellard | #define SPR_SDR1 (0x019) |
660 | 3fc6c082 | bellard | #define SPR_SRR0 (0x01A) |
661 | 3fc6c082 | bellard | #define SPR_SRR1 (0x01B) |
662 | 3fc6c082 | bellard | #define SPR_440_PID (0x030) |
663 | 3fc6c082 | bellard | #define SPR_440_DECAR (0x036) |
664 | 3fc6c082 | bellard | #define SPR_CSRR0 (0x03A) |
665 | 3fc6c082 | bellard | #define SPR_CSRR1 (0x03B) |
666 | 3fc6c082 | bellard | #define SPR_440_DEAR (0x03D) |
667 | 3fc6c082 | bellard | #define SPR_440_ESR (0x03E) |
668 | 3fc6c082 | bellard | #define SPR_440_IVPR (0x03F) |
669 | 3fc6c082 | bellard | #define SPR_8xx_EIE (0x050) |
670 | 3fc6c082 | bellard | #define SPR_8xx_EID (0x051) |
671 | 3fc6c082 | bellard | #define SPR_8xx_NRE (0x052) |
672 | 3fc6c082 | bellard | #define SPR_58x_CMPA (0x090) |
673 | 3fc6c082 | bellard | #define SPR_58x_CMPB (0x091) |
674 | 3fc6c082 | bellard | #define SPR_58x_CMPC (0x092) |
675 | 3fc6c082 | bellard | #define SPR_58x_CMPD (0x093) |
676 | 3fc6c082 | bellard | #define SPR_58x_ICR (0x094) |
677 | 3fc6c082 | bellard | #define SPR_58x_DER (0x094) |
678 | 3fc6c082 | bellard | #define SPR_58x_COUNTA (0x096) |
679 | 3fc6c082 | bellard | #define SPR_58x_COUNTB (0x097) |
680 | 3fc6c082 | bellard | #define SPR_58x_CMPE (0x098) |
681 | 3fc6c082 | bellard | #define SPR_58x_CMPF (0x099) |
682 | 3fc6c082 | bellard | #define SPR_58x_CMPG (0x09A) |
683 | 3fc6c082 | bellard | #define SPR_58x_CMPH (0x09B) |
684 | 3fc6c082 | bellard | #define SPR_58x_LCTRL1 (0x09C) |
685 | 3fc6c082 | bellard | #define SPR_58x_LCTRL2 (0x09D) |
686 | 3fc6c082 | bellard | #define SPR_58x_ICTRL (0x09E) |
687 | 3fc6c082 | bellard | #define SPR_58x_BAR (0x09F) |
688 | 3fc6c082 | bellard | #define SPR_VRSAVE (0x100) |
689 | 3fc6c082 | bellard | #define SPR_USPRG0 (0x100) |
690 | 3fc6c082 | bellard | #define SPR_USPRG4 (0x104) |
691 | 3fc6c082 | bellard | #define SPR_USPRG5 (0x105) |
692 | 3fc6c082 | bellard | #define SPR_USPRG6 (0x106) |
693 | 3fc6c082 | bellard | #define SPR_USPRG7 (0x107) |
694 | 3fc6c082 | bellard | #define SPR_VTBL (0x10C) |
695 | 3fc6c082 | bellard | #define SPR_VTBU (0x10D) |
696 | 3fc6c082 | bellard | #define SPR_SPRG0 (0x110) |
697 | 3fc6c082 | bellard | #define SPR_SPRG1 (0x111) |
698 | 3fc6c082 | bellard | #define SPR_SPRG2 (0x112) |
699 | 3fc6c082 | bellard | #define SPR_SPRG3 (0x113) |
700 | 3fc6c082 | bellard | #define SPR_SPRG4 (0x114) |
701 | 3fc6c082 | bellard | #define SPR_SCOMC (0x114) |
702 | 3fc6c082 | bellard | #define SPR_SPRG5 (0x115) |
703 | 3fc6c082 | bellard | #define SPR_SCOMD (0x115) |
704 | 3fc6c082 | bellard | #define SPR_SPRG6 (0x116) |
705 | 3fc6c082 | bellard | #define SPR_SPRG7 (0x117) |
706 | 3fc6c082 | bellard | #define SPR_ASR (0x118) |
707 | 3fc6c082 | bellard | #define SPR_EAR (0x11A) |
708 | 3fc6c082 | bellard | #define SPR_TBL (0x11C) |
709 | 3fc6c082 | bellard | #define SPR_TBU (0x11D) |
710 | 3fc6c082 | bellard | #define SPR_SVR (0x11E) |
711 | 3fc6c082 | bellard | #define SPR_440_PIR (0x11E) |
712 | 3fc6c082 | bellard | #define SPR_PVR (0x11F) |
713 | 3fc6c082 | bellard | #define SPR_HSPRG0 (0x130) |
714 | 3fc6c082 | bellard | #define SPR_440_DBSR (0x130) |
715 | 3fc6c082 | bellard | #define SPR_HSPRG1 (0x131) |
716 | 3fc6c082 | bellard | #define SPR_440_DBCR0 (0x134) |
717 | 3fc6c082 | bellard | #define SPR_IBCR (0x135) |
718 | 3fc6c082 | bellard | #define SPR_440_DBCR1 (0x135) |
719 | 3fc6c082 | bellard | #define SPR_DBCR (0x136) |
720 | 3fc6c082 | bellard | #define SPR_HDEC (0x136) |
721 | 3fc6c082 | bellard | #define SPR_440_DBCR2 (0x136) |
722 | 3fc6c082 | bellard | #define SPR_HIOR (0x137) |
723 | 3fc6c082 | bellard | #define SPR_MBAR (0x137) |
724 | 3fc6c082 | bellard | #define SPR_RMOR (0x138) |
725 | 3fc6c082 | bellard | #define SPR_440_IAC1 (0x138) |
726 | 3fc6c082 | bellard | #define SPR_HRMOR (0x139) |
727 | 3fc6c082 | bellard | #define SPR_440_IAC2 (0x139) |
728 | 3fc6c082 | bellard | #define SPR_HSSR0 (0x13A) |
729 | 3fc6c082 | bellard | #define SPR_440_IAC3 (0x13A) |
730 | 3fc6c082 | bellard | #define SPR_HSSR1 (0x13B) |
731 | 3fc6c082 | bellard | #define SPR_440_IAC4 (0x13B) |
732 | 3fc6c082 | bellard | #define SPR_LPCR (0x13C) |
733 | 3fc6c082 | bellard | #define SPR_440_DAC1 (0x13C) |
734 | 3fc6c082 | bellard | #define SPR_LPIDR (0x13D) |
735 | 3fc6c082 | bellard | #define SPR_DABR2 (0x13D) |
736 | 3fc6c082 | bellard | #define SPR_440_DAC2 (0x13D) |
737 | 3fc6c082 | bellard | #define SPR_440_DVC1 (0x13E) |
738 | 3fc6c082 | bellard | #define SPR_440_DVC2 (0x13F) |
739 | 3fc6c082 | bellard | #define SPR_440_TSR (0x150) |
740 | 3fc6c082 | bellard | #define SPR_440_TCR (0x154) |
741 | 3fc6c082 | bellard | #define SPR_440_IVOR0 (0x190) |
742 | 3fc6c082 | bellard | #define SPR_440_IVOR1 (0x191) |
743 | 3fc6c082 | bellard | #define SPR_440_IVOR2 (0x192) |
744 | 3fc6c082 | bellard | #define SPR_440_IVOR3 (0x193) |
745 | 3fc6c082 | bellard | #define SPR_440_IVOR4 (0x194) |
746 | 3fc6c082 | bellard | #define SPR_440_IVOR5 (0x195) |
747 | 3fc6c082 | bellard | #define SPR_440_IVOR6 (0x196) |
748 | 3fc6c082 | bellard | #define SPR_440_IVOR7 (0x197) |
749 | 3fc6c082 | bellard | #define SPR_440_IVOR8 (0x198) |
750 | 3fc6c082 | bellard | #define SPR_440_IVOR9 (0x199) |
751 | 3fc6c082 | bellard | #define SPR_440_IVOR10 (0x19A) |
752 | 3fc6c082 | bellard | #define SPR_440_IVOR11 (0x19B) |
753 | 3fc6c082 | bellard | #define SPR_440_IVOR12 (0x19C) |
754 | 3fc6c082 | bellard | #define SPR_440_IVOR13 (0x19D) |
755 | 3fc6c082 | bellard | #define SPR_440_IVOR14 (0x19E) |
756 | 3fc6c082 | bellard | #define SPR_440_IVOR15 (0x19F) |
757 | 3fc6c082 | bellard | #define SPR_IBAT0U (0x210) |
758 | 3fc6c082 | bellard | #define SPR_IBAT0L (0x211) |
759 | 3fc6c082 | bellard | #define SPR_IBAT1U (0x212) |
760 | 3fc6c082 | bellard | #define SPR_IBAT1L (0x213) |
761 | 3fc6c082 | bellard | #define SPR_IBAT2U (0x214) |
762 | 3fc6c082 | bellard | #define SPR_IBAT2L (0x215) |
763 | 3fc6c082 | bellard | #define SPR_IBAT3U (0x216) |
764 | 3fc6c082 | bellard | #define SPR_IBAT3L (0x217) |
765 | 3fc6c082 | bellard | #define SPR_DBAT0U (0x218) |
766 | 3fc6c082 | bellard | #define SPR_DBAT0L (0x219) |
767 | 3fc6c082 | bellard | #define SPR_DBAT1U (0x21A) |
768 | 3fc6c082 | bellard | #define SPR_DBAT1L (0x21B) |
769 | 3fc6c082 | bellard | #define SPR_DBAT2U (0x21C) |
770 | 3fc6c082 | bellard | #define SPR_DBAT2L (0x21D) |
771 | 3fc6c082 | bellard | #define SPR_DBAT3U (0x21E) |
772 | 3fc6c082 | bellard | #define SPR_DBAT3L (0x21F) |
773 | 3fc6c082 | bellard | #define SPR_IBAT4U (0x230) |
774 | 3fc6c082 | bellard | #define SPR_IBAT4L (0x231) |
775 | 3fc6c082 | bellard | #define SPR_IBAT5U (0x232) |
776 | 3fc6c082 | bellard | #define SPR_IBAT5L (0x233) |
777 | 3fc6c082 | bellard | #define SPR_IBAT6U (0x234) |
778 | 3fc6c082 | bellard | #define SPR_IBAT6L (0x235) |
779 | 3fc6c082 | bellard | #define SPR_IBAT7U (0x236) |
780 | 3fc6c082 | bellard | #define SPR_IBAT7L (0x237) |
781 | 3fc6c082 | bellard | #define SPR_DBAT4U (0x238) |
782 | 3fc6c082 | bellard | #define SPR_DBAT4L (0x239) |
783 | 3fc6c082 | bellard | #define SPR_DBAT5U (0x23A) |
784 | 3fc6c082 | bellard | #define SPR_DBAT5L (0x23B) |
785 | 3fc6c082 | bellard | #define SPR_DBAT6U (0x23C) |
786 | 3fc6c082 | bellard | #define SPR_DBAT6L (0x23D) |
787 | 3fc6c082 | bellard | #define SPR_DBAT7U (0x23E) |
788 | 3fc6c082 | bellard | #define SPR_DBAT7L (0x23F) |
789 | 3fc6c082 | bellard | #define SPR_440_INV0 (0x370) |
790 | 3fc6c082 | bellard | #define SPR_440_INV1 (0x371) |
791 | 3fc6c082 | bellard | #define SPR_440_INV2 (0x372) |
792 | 3fc6c082 | bellard | #define SPR_440_INV3 (0x373) |
793 | 3fc6c082 | bellard | #define SPR_440_IVT0 (0x374) |
794 | 3fc6c082 | bellard | #define SPR_440_IVT1 (0x375) |
795 | 3fc6c082 | bellard | #define SPR_440_IVT2 (0x376) |
796 | 3fc6c082 | bellard | #define SPR_440_IVT3 (0x377) |
797 | 3fc6c082 | bellard | #define SPR_440_DNV0 (0x390) |
798 | 3fc6c082 | bellard | #define SPR_440_DNV1 (0x391) |
799 | 3fc6c082 | bellard | #define SPR_440_DNV2 (0x392) |
800 | 3fc6c082 | bellard | #define SPR_440_DNV3 (0x393) |
801 | 3fc6c082 | bellard | #define SPR_440_DVT0 (0x394) |
802 | 3fc6c082 | bellard | #define SPR_440_DVT1 (0x395) |
803 | 3fc6c082 | bellard | #define SPR_440_DVT2 (0x396) |
804 | 3fc6c082 | bellard | #define SPR_440_DVT3 (0x397) |
805 | 3fc6c082 | bellard | #define SPR_440_DVLIM (0x398) |
806 | 3fc6c082 | bellard | #define SPR_440_IVLIM (0x399) |
807 | 3fc6c082 | bellard | #define SPR_440_RSTCFG (0x39B) |
808 | 3fc6c082 | bellard | #define SPR_440_DCBTRL (0x39C) |
809 | 3fc6c082 | bellard | #define SPR_440_DCBTRH (0x39D) |
810 | 3fc6c082 | bellard | #define SPR_440_ICBTRL (0x39E) |
811 | 3fc6c082 | bellard | #define SPR_440_ICBTRH (0x39F) |
812 | 3fc6c082 | bellard | #define SPR_UMMCR0 (0x3A8) |
813 | 3fc6c082 | bellard | #define SPR_UPMC1 (0x3A9) |
814 | 3fc6c082 | bellard | #define SPR_UPMC2 (0x3AA) |
815 | 3fc6c082 | bellard | #define SPR_USIA (0x3AB) |
816 | 3fc6c082 | bellard | #define SPR_UMMCR1 (0x3AC) |
817 | 3fc6c082 | bellard | #define SPR_UPMC3 (0x3AD) |
818 | 3fc6c082 | bellard | #define SPR_UPMC4 (0x3AE) |
819 | 3fc6c082 | bellard | #define SPR_USDA (0x3AF) |
820 | 3fc6c082 | bellard | #define SPR_40x_ZPR (0x3B0) |
821 | 3fc6c082 | bellard | #define SPR_40x_PID (0x3B1) |
822 | 3fc6c082 | bellard | #define SPR_440_MMUCR (0x3B2) |
823 | 3fc6c082 | bellard | #define SPR_4xx_CCR0 (0x3B3) |
824 | 3fc6c082 | bellard | #define SPR_405_IAC3 (0x3B4) |
825 | 3fc6c082 | bellard | #define SPR_405_IAC4 (0x3B5) |
826 | 3fc6c082 | bellard | #define SPR_405_DVC1 (0x3B6) |
827 | 3fc6c082 | bellard | #define SPR_405_DVC2 (0x3B7) |
828 | 3fc6c082 | bellard | #define SPR_MMCR0 (0x3B8) |
829 | 3fc6c082 | bellard | #define SPR_PMC1 (0x3B9) |
830 | 3fc6c082 | bellard | #define SPR_40x_SGR (0x3B9) |
831 | 3fc6c082 | bellard | #define SPR_PMC2 (0x3BA) |
832 | 3fc6c082 | bellard | #define SPR_40x_DCWR (0x3BA) |
833 | 3fc6c082 | bellard | #define SPR_SIA (0x3BB) |
834 | 3fc6c082 | bellard | #define SPR_405_SLER (0x3BB) |
835 | 3fc6c082 | bellard | #define SPR_MMCR1 (0x3BC) |
836 | 3fc6c082 | bellard | #define SPR_405_SU0R (0x3BC) |
837 | 3fc6c082 | bellard | #define SPR_PMC3 (0x3BD) |
838 | 3fc6c082 | bellard | #define SPR_405_DBCR1 (0x3BD) |
839 | 3fc6c082 | bellard | #define SPR_PMC4 (0x3BE) |
840 | 3fc6c082 | bellard | #define SPR_SDA (0x3BF) |
841 | 3fc6c082 | bellard | #define SPR_403_VTBL (0x3CC) |
842 | 3fc6c082 | bellard | #define SPR_403_VTBU (0x3CD) |
843 | 3fc6c082 | bellard | #define SPR_DMISS (0x3D0) |
844 | 3fc6c082 | bellard | #define SPR_DCMP (0x3D1) |
845 | 3fc6c082 | bellard | #define SPR_DHASH1 (0x3D2) |
846 | 3fc6c082 | bellard | #define SPR_DHASH2 (0x3D3) |
847 | 3fc6c082 | bellard | #define SPR_4xx_ICDBDR (0x3D3) |
848 | 3fc6c082 | bellard | #define SPR_IMISS (0x3D4) |
849 | 3fc6c082 | bellard | #define SPR_40x_ESR (0x3D4) |
850 | 3fc6c082 | bellard | #define SPR_ICMP (0x3D5) |
851 | 3fc6c082 | bellard | #define SPR_40x_DEAR (0x3D5) |
852 | 3fc6c082 | bellard | #define SPR_RPA (0x3D6) |
853 | 3fc6c082 | bellard | #define SPR_40x_EVPR (0x3D6) |
854 | 3fc6c082 | bellard | #define SPR_403_CDBCR (0x3D7) |
855 | 3fc6c082 | bellard | #define SPR_TCR (0x3D8) |
856 | 3fc6c082 | bellard | #define SPR_40x_TSR (0x3D8) |
857 | 3fc6c082 | bellard | #define SPR_IBR (0x3DA) |
858 | 3fc6c082 | bellard | #define SPR_40x_TCR (0x3DA) |
859 | 3fc6c082 | bellard | #define SPR_ESASR (0x3DB) |
860 | 3fc6c082 | bellard | #define SPR_40x_PIT (0x3DB) |
861 | 3fc6c082 | bellard | #define SPR_403_TBL (0x3DC) |
862 | 3fc6c082 | bellard | #define SPR_403_TBU (0x3DD) |
863 | 3fc6c082 | bellard | #define SPR_SEBR (0x3DE) |
864 | 3fc6c082 | bellard | #define SPR_40x_SRR2 (0x3DE) |
865 | 3fc6c082 | bellard | #define SPR_SER (0x3DF) |
866 | 3fc6c082 | bellard | #define SPR_40x_SRR3 (0x3DF) |
867 | 3fc6c082 | bellard | #define SPR_HID0 (0x3F0) |
868 | 3fc6c082 | bellard | #define SPR_40x_DBSR (0x3F0) |
869 | 3fc6c082 | bellard | #define SPR_HID1 (0x3F1) |
870 | 3fc6c082 | bellard | #define SPR_IABR (0x3F2) |
871 | 3fc6c082 | bellard | #define SPR_40x_DBCR0 (0x3F2) |
872 | 3fc6c082 | bellard | #define SPR_601_HID2 (0x3F2) |
873 | 3fc6c082 | bellard | #define SPR_HID2 (0x3F3) |
874 | 3fc6c082 | bellard | #define SPR_440_DBDR (0x3F3) |
875 | 3fc6c082 | bellard | #define SPR_40x_IAC1 (0x3F4) |
876 | 3fc6c082 | bellard | #define SPR_DABR (0x3F5) |
877 | 3fc6c082 | bellard | #define DABR_MASK (~(target_ulong)0x7) |
878 | 3fc6c082 | bellard | #define SPR_40x_IAC2 (0x3F5) |
879 | 3fc6c082 | bellard | #define SPR_601_HID5 (0x3F5) |
880 | 3fc6c082 | bellard | #define SPR_40x_DAC1 (0x3F6) |
881 | 3fc6c082 | bellard | #define SPR_40x_DAC2 (0x3F7) |
882 | 3fc6c082 | bellard | #define SPR_L2PM (0x3F8) |
883 | 3fc6c082 | bellard | #define SPR_750_HID2 (0x3F8) |
884 | 3fc6c082 | bellard | #define SPR_L2CR (0x3F9) |
885 | 3fc6c082 | bellard | #define SPR_IABR2 (0x3FA) |
886 | 3fc6c082 | bellard | #define SPR_40x_DCCR (0x3FA) |
887 | 3fc6c082 | bellard | #define SPR_ICTC (0x3FB) |
888 | 3fc6c082 | bellard | #define SPR_40x_ICCR (0x3FB) |
889 | 3fc6c082 | bellard | #define SPR_THRM1 (0x3FC) |
890 | 3fc6c082 | bellard | #define SPR_403_PBL1 (0x3FC) |
891 | 3fc6c082 | bellard | #define SPR_SP (0x3FD) |
892 | 3fc6c082 | bellard | #define SPR_THRM2 (0x3FD) |
893 | 3fc6c082 | bellard | #define SPR_403_PBU1 (0x3FD) |
894 | 3fc6c082 | bellard | #define SPR_LT (0x3FE) |
895 | 3fc6c082 | bellard | #define SPR_THRM3 (0x3FE) |
896 | 3fc6c082 | bellard | #define SPR_FPECR (0x3FE) |
897 | 3fc6c082 | bellard | #define SPR_403_PBL2 (0x3FE) |
898 | 3fc6c082 | bellard | #define SPR_PIR (0x3FF) |
899 | 3fc6c082 | bellard | #define SPR_403_PBU2 (0x3FF) |
900 | 3fc6c082 | bellard | #define SPR_601_HID15 (0x3FF) |
901 | 79aceca5 | bellard | |
902 | 9a64fbe4 | bellard | /* Memory access type :
|
903 | 9a64fbe4 | bellard | * may be needed for precise access rights control and precise exceptions.
|
904 | 9a64fbe4 | bellard | */
|
905 | 79aceca5 | bellard | enum {
|
906 | 9a64fbe4 | bellard | /* 1 bit to define user level / supervisor access */
|
907 | 9a64fbe4 | bellard | ACCESS_USER = 0x00,
|
908 | 9a64fbe4 | bellard | ACCESS_SUPER = 0x01,
|
909 | 9a64fbe4 | bellard | /* Type of instruction that generated the access */
|
910 | 9a64fbe4 | bellard | ACCESS_CODE = 0x10, /* Code fetch access */ |
911 | 9a64fbe4 | bellard | ACCESS_INT = 0x20, /* Integer load/store access */ |
912 | 9a64fbe4 | bellard | ACCESS_FLOAT = 0x30, /* floating point load/store access */ |
913 | 9a64fbe4 | bellard | ACCESS_RES = 0x40, /* load/store with reservation */ |
914 | 9a64fbe4 | bellard | ACCESS_EXT = 0x50, /* external access */ |
915 | 9a64fbe4 | bellard | ACCESS_CACHE = 0x60, /* Cache manipulation */ |
916 | 9a64fbe4 | bellard | }; |
917 | 9a64fbe4 | bellard | |
918 | 9a64fbe4 | bellard | /*****************************************************************************/
|
919 | 9a64fbe4 | bellard | /* Exceptions */
|
920 | 2be0071f | bellard | #define EXCP_NONE -1 |
921 | 2be0071f | bellard | /* PowerPC hardware exceptions : exception vectors defined in PowerPC book 3 */
|
922 | 2be0071f | bellard | #define EXCP_RESET 0x0100 /* System reset */ |
923 | 2be0071f | bellard | #define EXCP_MACHINE_CHECK 0x0200 /* Machine check exception */ |
924 | 2be0071f | bellard | #define EXCP_DSI 0x0300 /* Data storage exception */ |
925 | 2be0071f | bellard | #define EXCP_DSEG 0x0380 /* Data segment exception */ |
926 | 2be0071f | bellard | #define EXCP_ISI 0x0400 /* Instruction storage exception */ |
927 | 2be0071f | bellard | #define EXCP_ISEG 0x0480 /* Instruction segment exception */ |
928 | 2be0071f | bellard | #define EXCP_EXTERNAL 0x0500 /* External interruption */ |
929 | 2be0071f | bellard | #define EXCP_ALIGN 0x0600 /* Alignment exception */ |
930 | 2be0071f | bellard | #define EXCP_PROGRAM 0x0700 /* Program exception */ |
931 | 2be0071f | bellard | #define EXCP_NO_FP 0x0800 /* Floating point unavailable exception */ |
932 | 2be0071f | bellard | #define EXCP_DECR 0x0900 /* Decrementer exception */ |
933 | 2be0071f | bellard | #define EXCP_HDECR 0x0980 /* Hypervisor decrementer exception */ |
934 | 2be0071f | bellard | #define EXCP_SYSCALL 0x0C00 /* System call */ |
935 | 2be0071f | bellard | #define EXCP_TRACE 0x0D00 /* Trace exception */ |
936 | 2be0071f | bellard | #define EXCP_PERF 0x0F00 /* Performance monitor exception */ |
937 | 2be0071f | bellard | /* Exceptions defined in PowerPC 32 bits programming environment manual */
|
938 | 2be0071f | bellard | #define EXCP_FP_ASSIST 0x0E00 /* Floating-point assist */ |
939 | 2be0071f | bellard | /* Implementation specific exceptions */
|
940 | 2be0071f | bellard | /* 40x exceptions */
|
941 | 2be0071f | bellard | #define EXCP_40x_PIT 0x1000 /* Programmable interval timer interrupt */ |
942 | 2be0071f | bellard | #define EXCP_40x_FIT 0x1010 /* Fixed interval timer interrupt */ |
943 | 2be0071f | bellard | #define EXCP_40x_WATCHDOG 0x1020 /* Watchdog timer exception */ |
944 | 2be0071f | bellard | #define EXCP_40x_DTLBMISS 0x1100 /* Data TLB miss exception */ |
945 | 2be0071f | bellard | #define EXCP_40x_ITLBMISS 0x1200 /* Instruction TLB miss exception */ |
946 | 2be0071f | bellard | #define EXCP_40x_DEBUG 0x2000 /* Debug exception */ |
947 | 2be0071f | bellard | /* 405 specific exceptions */
|
948 | 2be0071f | bellard | #define EXCP_405_APU 0x0F20 /* APU unavailable exception */ |
949 | 2be0071f | bellard | /* TLB assist exceptions (602/603) */
|
950 | 2be0071f | bellard | #define EXCP_I_TLBMISS 0x1000 /* Instruction TLB miss */ |
951 | 2be0071f | bellard | #define EXCP_DL_TLBMISS 0x1100 /* Data load TLB miss */ |
952 | 2be0071f | bellard | #define EXCP_DS_TLBMISS 0x1200 /* Data store TLB miss */ |
953 | 2be0071f | bellard | /* Breakpoint exceptions (602/603/604/620/740/745/750/755...) */
|
954 | 2be0071f | bellard | #define EXCP_IABR 0x1300 /* Instruction address breakpoint */ |
955 | 2be0071f | bellard | #define EXCP_SMI 0x1400 /* System management interrupt */ |
956 | 2be0071f | bellard | /* Altivec related exceptions */
|
957 | 2be0071f | bellard | #define EXCP_VPU 0x0F20 /* VPU unavailable exception */ |
958 | 2be0071f | bellard | /* 601 specific exceptions */
|
959 | 2be0071f | bellard | #define EXCP_601_IO 0x0600 /* IO error exception */ |
960 | 2be0071f | bellard | #define EXCP_601_RUNM 0x2000 /* Run mode exception */ |
961 | 2be0071f | bellard | /* 602 specific exceptions */
|
962 | 2be0071f | bellard | #define EXCP_602_WATCHDOG 0x1500 /* Watchdog exception */ |
963 | 2be0071f | bellard | #define EXCP_602_EMUL 0x1600 /* Emulation trap exception */ |
964 | 2be0071f | bellard | /* G2 specific exceptions */
|
965 | 2be0071f | bellard | #define EXCP_G2_CRIT 0x0A00 /* Critical interrupt */ |
966 | 2be0071f | bellard | /* MPC740/745/750 & IBM 750 specific exceptions */
|
967 | 2be0071f | bellard | #define EXCP_THRM 0x1700 /* Thermal management interrupt */ |
968 | 2be0071f | bellard | /* 74xx specific exceptions */
|
969 | 2be0071f | bellard | #define EXCP_74xx_VPUA 0x1600 /* VPU assist exception */ |
970 | 2be0071f | bellard | /* 970FX specific exceptions */
|
971 | 2be0071f | bellard | #define EXCP_970_SOFTP 0x1500 /* Soft patch exception */ |
972 | 2be0071f | bellard | #define EXCP_970_MAINT 0x1600 /* Maintenance exception */ |
973 | 2be0071f | bellard | #define EXCP_970_THRM 0x1800 /* Thermal exception */ |
974 | 2be0071f | bellard | #define EXCP_970_VPUA 0x1700 /* VPU assist exception */ |
975 | 2be0071f | bellard | /* End of exception vectors area */
|
976 | 2be0071f | bellard | #define EXCP_PPC_MAX 0x4000 |
977 | 2be0071f | bellard | /* Qemu exceptions: special cases we want to stop translation */
|
978 | 2be0071f | bellard | #define EXCP_MTMSR 0x11000 /* mtmsr instruction: */ |
979 | 9a64fbe4 | bellard | /* may change privilege level */
|
980 | 2be0071f | bellard | #define EXCP_BRANCH 0x11001 /* branch instruction */ |
981 | 2be0071f | bellard | #define EXCP_SYSCALL_USER 0x12000 /* System call in user mode only */ |
982 | 2be0071f | bellard | #define EXCP_INTERRUPT_CRITICAL 0x13000 /* critical IRQ */ |
983 | 2be0071f | bellard | |
984 | 9a64fbe4 | bellard | /* Error codes */
|
985 | 9a64fbe4 | bellard | enum {
|
986 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_ALIGN */
|
987 | 9a64fbe4 | bellard | EXCP_ALIGN_FP = 0x01, /* FP alignment exception */ |
988 | 9a64fbe4 | bellard | EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */ |
989 | 9a64fbe4 | bellard | EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */ |
990 | 9a64fbe4 | bellard | EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */ |
991 | 9a64fbe4 | bellard | EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */ |
992 | 9a64fbe4 | bellard | EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */ |
993 | 9a64fbe4 | bellard | /* Exception subtypes for EXCP_PROGRAM */
|
994 | 79aceca5 | bellard | /* FP exceptions */
|
995 | 9a64fbe4 | bellard | EXCP_FP = 0x10,
|
996 | 9a64fbe4 | bellard | EXCP_FP_OX = 0x01, /* FP overflow */ |
997 | 9a64fbe4 | bellard | EXCP_FP_UX = 0x02, /* FP underflow */ |
998 | 9a64fbe4 | bellard | EXCP_FP_ZX = 0x03, /* FP divide by zero */ |
999 | 9a64fbe4 | bellard | EXCP_FP_XX = 0x04, /* FP inexact */ |
1000 | 9a64fbe4 | bellard | EXCP_FP_VXNAN = 0x05, /* FP invalid SNaN op */ |
1001 | 9a64fbe4 | bellard | EXCP_FP_VXISI = 0x06, /* FP invalid infinite substraction */ |
1002 | 9a64fbe4 | bellard | EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */ |
1003 | 9a64fbe4 | bellard | EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */ |
1004 | 9a64fbe4 | bellard | EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */ |
1005 | 9a64fbe4 | bellard | EXCP_FP_VXVC = 0x0A, /* FP invalid compare */ |
1006 | 9a64fbe4 | bellard | EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */ |
1007 | 9a64fbe4 | bellard | EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */ |
1008 | 9a64fbe4 | bellard | EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */ |
1009 | 79aceca5 | bellard | /* Invalid instruction */
|
1010 | 9a64fbe4 | bellard | EXCP_INVAL = 0x20,
|
1011 | 9a64fbe4 | bellard | EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */ |
1012 | 9a64fbe4 | bellard | EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */ |
1013 | 9a64fbe4 | bellard | EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */ |
1014 | 9a64fbe4 | bellard | EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */ |
1015 | 79aceca5 | bellard | /* Privileged instruction */
|
1016 | 9a64fbe4 | bellard | EXCP_PRIV = 0x30,
|
1017 | 9a64fbe4 | bellard | EXCP_PRIV_OPC = 0x01,
|
1018 | 9a64fbe4 | bellard | EXCP_PRIV_REG = 0x02,
|
1019 | 79aceca5 | bellard | /* Trap */
|
1020 | 9a64fbe4 | bellard | EXCP_TRAP = 0x40,
|
1021 | 79aceca5 | bellard | }; |
1022 | 79aceca5 | bellard | |
1023 | 9a64fbe4 | bellard | /*****************************************************************************/
|
1024 | 9a64fbe4 | bellard | |
1025 | 79aceca5 | bellard | #endif /* !defined (__CPU_PPC_H__) */ |